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| author | Li Zhijian <lizhijian@fujitsu.com> | 2025-02-03 16:19:05 +0000 |
|---|---|---|
| committer | Michael S. Tsirkin <mst@redhat.com> | 2025-02-21 07:18:42 -0500 |
| commit | 0401c4328f4d18be540fd432c2bbacce4531d14f (patch) | |
| tree | 29ee2b130085a95e80de2a95d179da945086fd6f | |
| parent | 8f90a54cfafe8c93a71930a96a63ccbd074f4142 (diff) | |
| download | qemu-0401c4328f4d18be540fd432c2bbacce4531d14f.zip qemu-0401c4328f4d18be540fd432c2bbacce4531d14f.tar.gz qemu-0401c4328f4d18be540fd432c2bbacce4531d14f.tar.bz2 | |
hw/mem/cxl_type3: Add paired msix_uninit_exclusive_bar() call
msix_uninit_exclusive_bar() should be paired with msix_init_exclusive_bar()
Ensure proper resource cleanup by adding the missing
`msix_uninit_exclusive_bar()` call for the Type3 CXL device.
Signed-off-by: Li Zhijian <lizhijian@fujitsu.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20250203161908.145406-3-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
| -rw-r--r-- | hw/mem/cxl_type3.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c index ebc0ec5..4775aab 100644 --- a/hw/mem/cxl_type3.c +++ b/hw/mem/cxl_type3.c @@ -944,6 +944,7 @@ static void ct3_realize(PCIDevice *pci_dev, Error **errp) err_release_cdat: cxl_doe_cdat_release(cxl_cstate); err_free_special_ops: + msix_uninit_exclusive_bar(pci_dev); g_free(regs->special_ops); err_address_space_free: if (ct3d->dc.host_dc) { @@ -967,6 +968,7 @@ static void ct3_exit(PCIDevice *pci_dev) pcie_aer_exit(pci_dev); cxl_doe_cdat_release(cxl_cstate); + msix_uninit_exclusive_bar(pci_dev); g_free(regs->special_ops); if (ct3d->dc.host_dc) { cxl_destroy_dc_regions(ct3d); |