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author | David Hildenbrand <david@redhat.com> | 2019-08-23 12:07:41 +0200 |
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committer | Richard Henderson <richard.henderson@linaro.org> | 2019-09-03 08:34:18 -0700 |
commit | 03a981893c99faba84bb373976796ad7dce0aecc (patch) | |
tree | 6249147b5a39409cd3ded6ff91d745764afb9c92 | |
parent | 50b107c5d617eaf93301cef20221312e7a986701 (diff) | |
download | qemu-03a981893c99faba84bb373976796ad7dce0aecc.zip qemu-03a981893c99faba84bb373976796ad7dce0aecc.tar.gz qemu-03a981893c99faba84bb373976796ad7dce0aecc.tar.bz2 |
tcg: Check for watchpoints in probe_write()
Let size > 0 indicate a promise to write to those bytes.
Check for write watchpoints in the probed range.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
Message-Id: <20190823100741.9621-10-david@redhat.com>
[rth: Recompute index after tlb_fill; check TLB_WATCHPOINT.]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-rw-r--r-- | accel/tcg/cputlb.c | 15 |
1 files changed, 13 insertions, 2 deletions
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 9a9a626..010c4c6 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1086,13 +1086,24 @@ void probe_write(CPUArchState *env, target_ulong addr, int size, int mmu_idx, { uintptr_t index = tlb_index(env, mmu_idx, addr); CPUTLBEntry *entry = tlb_entry(env, mmu_idx, addr); + target_ulong tlb_addr = tlb_addr_write(entry); - if (!tlb_hit(tlb_addr_write(entry), addr)) { - /* TLB entry is for a different page */ + if (unlikely(!tlb_hit(tlb_addr, addr))) { if (!VICTIM_TLB_HIT(addr_write, addr)) { tlb_fill(env_cpu(env), addr, size, MMU_DATA_STORE, mmu_idx, retaddr); + /* TLB resize via tlb_fill may have moved the entry. */ + index = tlb_index(env, mmu_idx, addr); + entry = tlb_entry(env, mmu_idx, addr); } + tlb_addr = tlb_addr_write(entry); + } + + /* Handle watchpoints. */ + if ((tlb_addr & TLB_WATCHPOINT) && size > 0) { + cpu_check_watchpoint(env_cpu(env), addr, size, + env_tlb(env)->d[mmu_idx].iotlb[index].attrs, + BP_MEM_WRITE, retaddr); } } |