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authorGustavo Romero <gustavo.romero@linaro.org>2025-10-06 00:10:18 +0000
committerPeter Maydell <peter.maydell@linaro.org>2025-10-10 13:22:05 +0100
commit00936783abf77ebb47a78312a2e6500c6a13d938 (patch)
treef2fe3c15ad081c0e8b018982ebf78657665426c9
parent700f08d5829f3736fdfafe92d8223254ffc9c495 (diff)
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target/arm: Enable FEAT_MEC in -cpu max
Advertise FEAT_MEC in AA64MMFR3 ID register for the Arm64 cpu max as a first step to fully support FEAT_MEC. The FEAT_MEC is an extension to FEAT_RME that implements multiple Memory Encryption Contexts (MEC) so the memory in a realm can be encrypted and accessing it from the wrong encryption context is not possible. An encryption context allow the selection of a memory encryption engine. At this point, no real memory encryption is supported, but software stacks that rely on FEAT_MEC should work properly. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Gustavo Romero <gustavo.romero@linaro.org> Message-id: 20251006001018.219756-4-gustavo.romero@linaro.org Message-ID: <20250711140828.1714666-7-gustavo.romero@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Gustavo Romero <gustavo.romero@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-rw-r--r--docs/system/arm/emulation.rst3
-rw-r--r--target/arm/tcg/cpu64.c1
2 files changed, 4 insertions, 0 deletions
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
index 4496178..bf81da1 100644
--- a/docs/system/arm/emulation.rst
+++ b/docs/system/arm/emulation.rst
@@ -94,6 +94,9 @@ the following architecture extensions:
- FEAT_LSE2 (Large System Extensions v2)
- FEAT_LSE128 (128-bit Atomics)
- FEAT_LVA (Large Virtual Address space)
+- FEAT_MEC (Memory Encryption Contexts)
+
+ * This is a register-only implementation without encryption.
- FEAT_MixedEnd (Mixed-endian support)
- FEAT_MixedEndEL0 (Mixed-endian support at EL0)
- FEAT_MOPS (Standardization of memory operations)
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index cc42dfd..1bffe66 100644
--- a/target/arm/tcg/cpu64.c
+++ b/target/arm/tcg/cpu64.c
@@ -1327,6 +1327,7 @@ void aarch64_max_tcg_initfn(Object *obj)
t = GET_IDREG(isar, ID_AA64MMFR3);
t = FIELD_DP64(t, ID_AA64MMFR3, TCRX, 1); /* FEAT_TCR2 */
t = FIELD_DP64(t, ID_AA64MMFR3, SCTLRX, 1); /* FEAT_SCTLR2 */
+ t = FIELD_DP64(t, ID_AA64MMFR3, MEC, 1); /* FEAT_MEC */
t = FIELD_DP64(t, ID_AA64MMFR3, SPEC_FPACC, 1); /* FEAT_FPACC_SPEC */
t = FIELD_DP64(t, ID_AA64MMFR3, S1PIE, 1); /* FEAT_S1PIE */
t = FIELD_DP64(t, ID_AA64MMFR3, S2PIE, 1); /* FEAT_S2PIE */