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authorWeiwei Li <liweiwei@iscas.ac.cn>2023-05-23 17:35:34 +0800
committerAlistair Francis <alistair.francis@wdc.com>2023-06-13 17:27:33 +1000
commit454c2201005b5f47a76116ab529c923e194ec615 (patch)
treee281ea7ff1ffd1ed9cc3165eb9430e35e45d0195 /.editorconfig
parentb902ff2946adcc72d65604321ae3ca2fb41ae644 (diff)
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target/riscv: Pass RISCVCPUConfig as target_info to disassemble_info
Pass RISCVCPUConfig as disassemble_info.target_info to support disas of conflict instructions related to specific extensions. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230523093539.203909-4-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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