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Tested using the RocketChip CPU option.
(see https://github.com/enjoy-digital/litex)
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
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* add device tree in elf, using --with-dts to add the absolute path of device tree
* Disable device tree filter
* Remove *.dtb dependence, when the --with-dts option is not used
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This reverts commit a161e6f3ef31004e47a5b94b85c2e84b764f8637.
Resolves #218
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* add device tree in elf, using --with-dts to add the absolute path of device tree
* Disable device tree filter
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Recent QEMU will fault for 8-byte accesses. Use a uint32_t instead of
uintptr_t to avoid those problems.
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While it's unused upstream, according to the SiFive FU540 document, the
UART divisor register is at offset 0x18.
This also maps the interrupt enable and interrupt pending register
offsets.
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QEMU's finisher is "sifive,test1\0sifive,test0\0syscon" so we fail to
detect it currently. Instead, search the entire list, and for
completeness do the same with the HTIF and SiFive UART drivers.
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- Update to riscv-opcodes/231c5d58940113b006aa9fa22f47c18d5fac4123
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Some ELF loaders, in particular gdb's load command for dynamically
loading files into memory, which is often used to load binaries onto
FPGAs over JTAG, do not zero out BSS, leaving the memory in whatever
state it was previously in. Thus, introduce a new --enable-zero-bss
configure flag, which will include code to zero out BSS when booting.
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77a5df569451571d608650a34183d53df99790ec)
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SV32 is presented in RISC-V Privileged Architecture Manual (version
20190608-Priv-MSU-Ratified) Section 4.3 for RV32 systems. However, BBL
responds to sv32 with:
hart_filter_mask saw unknown hart type: status="okay", mmu_type="riscv,sv32"
and hangs.
This patch is adopted from the original 'riscv-pk.diff' patch written
by Fabrice Bellard, distributed as part of the following tarball:
https://bellard.org/tinyemu/diskimage-linux-riscv-2018-09-23.tar.gz
Closes: https://github.com/riscv/riscv-pk/issues/160
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This commit makes bbl read some additional fields from
the device tree if it detects an ns16550a:
- reg-shift
- reg-offset
- clock-frequency
For explanation of these check out the Linux Kernel doc:
https://www.kernel.org/doc/Documentation/devicetree/bindings/serial/8250.txt
In particular this allows the Xilinx AXI UART 16550 to act
as serial console with bbl and the Linux early boot console.
This also fixes a bug in which bbl will ignore any other than the first
"compatible" string when iterating over the nodes.
Previously this line would not have worked:
compatible = "xlnx,xps-uart16550-2.00.a", "ns16550a";
Before bbl would have just checked the first field instead of checking
all strings in the list.
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This supports bbl living above 4 GiB.
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This allows bbl to be loaded above 4 GiB on RV64.
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On 64-bit Rocket with 'DefaultFPGAConfig' (using 'WithNSmallCores'),
the 'U' extension is not supported, and accessing 'mcounteren' would
trigger an 'Illegal Instruction' trap.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
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This indicates the access is actually invalid, i.e., should not
be emulated.
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This reverts commit 7bee30c1ff56975041ffc67cd0170d7477aba865.
All ones is no longer "reserved", so the old code is OK.
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The number of interrupt enable words should be the number of devices
divided by the number of bits per word (not the number of bytes per
word) and it should round up.
Without this fix, when using a larger number of interrupts,
the user will see a number of errors in qemu of the form:
plic: invalid register write: %08x
Signed-off-by: Logan Gunthorpe <logang@deltatee.com>
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Use a proxy syscall instead of a blocking character write.
Resolves #84
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Currently it's being used by both enter_supervisor_mode and enter_machine_mode
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Upgrade SoftFloat
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Correct the comment of timer interrupt
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Can't cast to pointer from 64 bit size integer directly on 32 bit
environment.
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Support for separate firmware and kernel payload is added
by updating BBL to read optional preloaded kernel address
attributes from device-tree using a similar mechanism to
that used to pass init ramdisk addresses to linux kernel.
chosen {
riscv,kernel-start = <0x00000000 0x80200000>;
riscv,kernel-end = <0x00000000 0x80590634>;
};
These attributes are added by QEMU and read by BBL when combining
-bios <firmware-image> and -kernel <kernel-image> options. e.g.
$ qemu-system-riscv64 -machine virt -bios bbl -kernel vmlinux
With this change, bbl can be compiled without --with-payload
and the dummy payload alignment is altered to make the memory
footprint of the firmware-only bbl smaller. The dummy payload
message is updated to indicate the alternative load method.
This load method could also be supported by a first stage boot
loader that reads seperate firmware and kernel from SPI flash.
The main advantage of this new mechanism is that it eases kernel
development by avoiding the riscv-pk packaging step after kernel
builds, makes building per repository artefacts for CI simpler,
and mimics bootloaders on other platforms that can load a kernel
image file directly. Ultimately BBL should use an SPI driver to
load the kernel image however this mechanism supports use cases
such such as QEMU's -bios, -kernel and -initrd options following
examples from other platforms that pass kernel entry to firmware
via device-tree.
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Alistair Francis <Alistair.Francis@wdc.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
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* If BBL emulates the FPU, the trap handler will load emulated FCSR from
x0's save slot into tp. The emulated FCSR should be initialized, else
the field of rounding mode will contain garbage codes. This will
lead to raising SIGABRT for a user mode program which tries to print a
floating point variable. In glibc, __printf_fp_l() (defined in
riscv-glibc/stdio-common/printf_fp.c) will call round_away() (defined
in riscv-glibc/include/rounding-mode.h). With a garbage rounding mode
in emulated FCSR, round_away() may call abort().
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The E51 core on the U54-MC lacks supervisor mode, thus the plic_s_ie and plic_s_thresh are NULL when running on this core. This adds checks for this case.
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The MENTRY_IPI_PENDING_OFFSET offset is based on stack pointer
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Reboot does not work reliably without this.
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Otherwise, linux complains the moment an interrupt arrives and
wakes up one of the not-looping cores.
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gcc sometimes takes liberties with optimizing away our important halt function!
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This code is broken, and it's left over from before we could read the
DTB to find harts to boot on.
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Add __riscv_flush_icache
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For BBL's purposes a local i-cache flush should be sufficient.
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QEMU currently provides the console via HTIF and the SBI. That's a bit
messy because BBL polls for serial input, which means that typing too
quickly loses characters. While QEMU has a standard 16550 device model,
there's no way to have two consoles share the console in QEMU (as they'd
step all over each other) so that means we can't have both the HTIF
console and the 16550 console.
With this patch, QEMU can be changed to use a 16650 instead of the HTIF
for serial output. Linux will use the SBI for early printk support
(which is fine, polling for output is stable) and then swap over as soon
as it detects the UART. When Linux swaps it prints out the whole
history, but there's probably a way to get around that. There's a few
lines that are output to both, but it appears the Linux driver is close
enough to ours that nothing catastrophic happens -- there's not much to
the device, so hopefully that pans out on real hardware too.
Once Linux swaps over to natively using the driver we get reliable
console input. If you don't have the in-kernel driver then Linux never
swaps over and keeps using the SBI console just like before.
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