riscv-gnu-toolchain/pk.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2018-07-09	Properly license all nontrivial files	Andrew Waterman	28	-0/+56
2018-06-20	Fix problem of casting u64 to void* on 32-bit environment (#111)	Zong Li	1	-2/+2
2018-05-22	RISC-V: Support separate firmware and kernel payload	Michael Clark	3	-0/+65
2018-05-21	machine,minit: initialize emulated FCSR in enter_supervisor_mode() (#106)	Zihao Yu	1	-0/+4
2018-05-15	Fix for missing supervisor mode when running on E51 (#96)	Jim Straus	1	-3/+10
2018-04-27	Fix typo of perf counter (#100)	Zong Li	1	-2/+2
2018-04-10	SBI emulation of reads and writes to perf counters and config (#98)	Alex Solomatnikov	1	-0/+58
2018-04-09	Fix the wrong access of ipi pending address (#99)	Zong Li	1	-2/+2
2018-03-20	minit: insert printm as work-around for a race condition	Wesley W. Terpstra	1	-0/+1
2018-03-05	mtrap: add a halt IPI used for poweroff (#86)	Wesley W. Terpstra	3	-11/+18
2018-01-22	mtrap: loop forever, really	Wesley W. Terpstra	1	-1/+1
2018-01-22	Boot on the first hart	Palmer Dabbelt	1	-9/+2
2018-01-09	Remove the repeating bitmask of medeleg register (#74)	Zong Li	1	-1/+0
2017-12-16	Merge pull request #73 from riscv/flush_icache	Palmer Dabbelt	2	-0/+4
2017-12-13	Add __riscv_flush_icache	Palmer Dabbelt	2	-0/+4
2017-12-12	Add a 16550 UART driver to back the SBI console	Palmer Dabbelt	5	-0/+95
2017-12-12	Bump encoding.h	Andrew Waterman	2	-22/+25
2017-11-03	Remove the platform interface	Palmer Dabbelt	5	-6/+58
2017-11-02	Check if we have extensions before using them	Palmer Dabbelt	1	-5/+12
2017-11-02	Initialize the UART first	Palmer Dabbelt	1	-3/+3
2017-11-02	Detect harts that can't boot Linux instead of hard-coding them	Palmer Dabbelt	6	-10/+34
2017-11-01	Fix(?) fcvt.s.w emulation for rs1 = -2^31 (#66)	Andrew Waterman	1	-1/+1
2017-10-23	Make 4-byte aligned instruction-emulation loads atomic	Andrew Waterman	1	-3/+12
2017-08-14	finisher: support terminating sifive devices simulation (#61)	Wesley W. Terpstra	6	-4/+84
2017-08-03	Add the '--enable-print-device-tree' argument	Palmer Dabbelt	4	-4/+142
2017-08-02	Move DISABLED_HART_MASK to the platform	Palmer Dabbelt	4	-9/+10
2017-08-02	Allow the platform to disable HTIF	Palmer Dabbelt	1	-3/+10
2017-08-02	Add a platform interface	Palmer Dabbelt	1	-0/+1
2017-07-17	Fix emulation of misaligned RVC loads/stores	Andrew Waterman	1	-2/+5
2017-05-04	FMV.X.S/FMV.S.X -> FMV.X.W/FMV.W.X	Andrew Waterman	2	-11/+8
2017-04-18	Use uint64_t, not uintptr_t, to represent FDT addresses/sizes	Andrew Waterman	3	-21/+24
2017-04-18	Fix RV32 compilation error	Andrew Waterman	1	-1/+2
2017-04-11	Always write sbadaddr on trap redirection	Andrew Waterman	3	-6/+6
2017-04-11	Load instructions as unsigned values, not signed	Andrew Waterman	1	-4/+4
2017-04-06	mtrap: allow override of DISABLED_HART_MASK from CFLAGS	Wesley W. Terpstra	1	-0/+2
2017-04-05	Remove num_harts; use hart_mask exclusively	Andrew Waterman	4	-6/+5
2017-04-05	Rename HART_MASK to DISABLED_HART_MASK to clarify polarity	Andrew Waterman	4	-5/+5
2017-04-05	fdt: update the status length when masking cpus	Wesley W. Terpstra	1	-1/+4
2017-04-05	bbl: prevent named cores from booting	Wesley W. Terpstra	4	-2/+18
2017-04-05	fdt: redact clint, plic, and debug hardware	Wesley W. Terpstra	2	-2/+160
2017-04-05	fdt: support redaction	Wesley W. Terpstra	2	-9/+13
2017-04-04	Remove SBI console printm to speed up PK simulation	Andrew Waterman	1	-1/+0
2017-03-31	clint: move hart wakeup till after all FDT parsing	Wesley W. Terpstra	3	-6/+20
2017-03-30	New PMP encoding	Andrew Waterman	2	-6/+7
2017-03-30	fdt: look for the phandle of a cpu's nested interrupt controller	Wesley W. Terpstra	1	-15/+34
2017-03-29	Attempt to read instruction from mbadaddr	Andrew Waterman	1	-5/+9
2017-03-28	plic: discovered via fdt	Wesley W. Terpstra	3	-0/+103
2017-03-27	uart: find it using fdt	Wesley W. Terpstra	1	-3/+41
2017-03-27	fdt: rewrite parser using a single design pattern	Wesley W. Terpstra	2	-105/+176
2017-03-27	uart: add physical device driver	Wesley W. Terpstra	5	-2/+77