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2025-06-20Fix build failure when using gcc-15 (#348)HEADmasterLiao Shihua1-0/+1
2025-04-29Add exceedingly fake version of sys_getrandomAndrew Waterman2-0/+23
Resolves #344
2025-04-21Fixes #330 Set mstatus before querying uart (#343)Airat Galiamov1-0/+1
Co-authored-by: Airat Galiamov <DuzaBF@users.noreply.github.com>
2025-03-28Fix UB in RV32 versions of GET_F64_REG/SET_F64_REGAndrew Waterman1-9/+20
Resolves #342
2025-02-04Add no-op futex syscall implementation (#341)Abraham Gonzalez2-2/+4
2024-10-08Avoid dependence on asm ssp symbolAndrew Waterman1-1/+1
Resolves #336
2024-09-26Enable CBOs (but upgrade inval to flush for safety)Andrew Waterman2-1/+3
2024-09-26Support CFI shadow stacks via --zicfiss command-line argAndrew Waterman4-3/+25
2024-09-08README.md: add _zicsr_zifencei on configure option for rv32i (#334)hirooih1-2/+2
Signed-off-by: Hiroo HAYASHI <24754036+hirooih@users.noreply.github.com>
2024-08-13README.md: configure option for rv32ic (#332)hirooih1-0/+3
cf. https://github.com/riscv-software-src/riscv-isa-sim/issues/1361 Signed-off-by: Hiroo HAYASHI <24754036+hirooih@users.noreply.github.com>
2024-05-22Don't require software check exceptions be delegableAndrew Waterman1-3/+5
2024-05-20Merge branch 'mylai-mtk-zicfilp-upstream'Andrew Waterman4-18/+47
2024-05-20update encoding.hAndrew Waterman1-1264/+56
2024-05-20Use kassert in load_elf (#327)Zixian Cai1-3/+3
Signed-off-by: Zixian Cai <2891235+caizixian@users.noreply.github.com>
2024-05-20support emulation of misaligned vector loads/storesAndrew Waterman4-0/+156
2024-05-20Support emulation of misaligned FLH/FSHAndrew Waterman1-1/+8
2024-05-20Fix emulation of misaligned c.swsp/c.sdsp with rd=x0Andrew Waterman1-2/+2
2024-05-20Implementation of riscv_hwprobe syscall from Linux (#325)Wojciech Muła4-0/+55
See: https://www.kernel.org/doc/html/latest/arch/riscv/hwprobe.html
2024-05-20mprotect whole ELF segment, not just file portionAndrew Waterman1-3/+3
2024-05-20Don't mmap ELF segments with zero fileszAndrew Waterman1-2/+4
2024-05-20Add ELF header sanity checkAndrew Waterman1-0/+2
2024-05-20Implement syscall readlinkat and readv (#318)mylai-mtk2-0/+88
* Implement syscall readlinkat * Implement syscall readv by read syscalls Since pk lacks kernel-space dynamic memory management, we implement readv with normal read syscalls rather than forwarding it to spike
2024-05-20Remove "bbl loader" message (#313)Andrew Waterman1-1/+0
It was originally added as a temporary hack to hide a race condition in a prototype. It should've been removed long ago. Resolves #312
2024-05-17update encoding.hAndrew Waterman1-12672/+3149
2024-04-30Use kassert in load_elf (#327)Zixian Cai1-3/+3
Signed-off-by: Zixian Cai <2891235+caizixian@users.noreply.github.com>
2024-04-30support emulation of misaligned vector loads/storesAndrew Waterman4-0/+156
2024-04-30Support emulation of misaligned FLH/FSHAndrew Waterman1-1/+8
2024-04-25Fix emulation of misaligned c.swsp/c.sdsp with rd=x0Andrew Waterman1-2/+2
2024-04-23Implementation of riscv_hwprobe syscall from Linux (#325)Wojciech Muła4-0/+55
See: https://www.kernel.org/doc/html/latest/arch/riscv/hwprobe.html
2024-04-17mprotect whole ELF segment, not just file portionAndrew Waterman1-3/+3
2024-04-17Don't mmap ELF segments with zero fileszAndrew Waterman1-2/+4
2024-04-17Add ELF header sanity checkAndrew Waterman1-0/+2
2024-03-22Implement syscall readlinkat and readv (#318)mylai-mtk2-0/+88
* Implement syscall readlinkat * Implement syscall readv by read syscalls Since pk lacks kernel-space dynamic memory management, we implement readv with normal read syscalls rather than forwarding it to spike
2024-02-15Zicfilp: Handle software check exception -- landing pad faultMing-Yi Lai3-1/+21
2024-02-15Add index comments to machine trap table to enhance code readabilityMing-Yi Lai1-17/+17
2024-02-15Zicfilp: Support enabling userspace Zicfilp mechanismMing-Yi Lai1-0/+9
2024-02-15Zicfilp: Regenerate machine/encoding.hMing-Yi Lai1-12381/+4066
2024-01-28Remove "bbl loader" message (#313)Andrew Waterman1-1/+0
It was originally added as a temporary hack to hide a race condition in a prototype. It should've been removed long ago. Resolves #312
2023-11-17add support for "riscv-none-*" host name (#309)valentinThomazic1-1/+4
2023-05-16Revert "[GCC]: Fix fence.i bug (#296)"Andrew Waterman1-15/+4
This reverts commit 54de960a5e4c91734fcfd454fdc7e593c6ac571d. See #298 for explanation.
2023-05-02[GCC]: Fix fence.i bug (#296)Mark Goncharov1-4/+15
There are many issues: 260, 285, 287 has to be solved This workaround helps to add neccessary zicsr and zifencei for cssr and fence.i accordingly.
2023-05-01pk: fix __do_brk when new addr is not feasible (#295)xukl2-7/+3
Linux kernel simply return current brk when request brk addr is not feasible. The pk should probably do the same.
2023-03-27Revert "Revert "SBI emulation of reads and writes to perf counters and ↵Andrew Waterman1-0/+58
config (#98)"" This reverts commit 7ae86fb97b792586493255f935f2f12ff068b13f. This will continue to allow accesses to cycle/time via mcycle/mtime despite https://github.com/riscv-software-src/riscv-isa-sim/pull/1297. The hope is this will keep most people happy while doing the right thing with Spike.
2023-01-05Regenerated the configure file with autoconf 2.71 (#288)Kenneth Ostby1-1262/+2101
Regenerated the configure file using autoconf 2.71 to avoid the Syntax error problem when running on OSX/AArch64.
2022-08-05Specify text section in rest_of_boot_loader definitionAndrew Waterman1-1/+3
Fixes #282
2022-04-30Fix a file leak in function `at_kfd` (#276)MaxXing1-1/+3
2022-04-20Link -lgcc if it existsLucheng Zhang2-15/+130
2022-04-11Handle unimplemented syscalls gracefullyAndrew Waterman1-11/+1
We previously kernel-panicked because that made it more obvious when a syscall implementation was missing. These days, it's more common that the C library will do something sensible in response to returning -ENOSYS. Favor that approach to avoid frustrating users.
2022-04-08Stub out sysinfo syscallAndrew Waterman3-260/+10462
2022-02-17Fix sbi_console_getchar return value if no UART is presentAndrew Waterman1-1/+1
The UART drivers all return -1 if no character is present, and so that's what we should do if there's no UART at all. See discussion on https://github.com/riscv-non-isa/riscv-sbi-doc/issues/82