diff options
-rw-r--r-- | machine/emulation.c | 8 | ||||
-rw-r--r-- | machine/fp_asm.S | 6 | ||||
-rw-r--r-- | machine/fp_emulation.h | 2 | ||||
-rw-r--r-- | machine/mentry.S | 4 | ||||
-rw-r--r-- | machine/minit.c | 2 | ||||
-rw-r--r-- | machine/mtrap.h | 2 |
6 files changed, 14 insertions, 10 deletions
diff --git a/machine/emulation.c b/machine/emulation.c index e574b99..d8e0f1e 100644 --- a/machine/emulation.c +++ b/machine/emulation.c @@ -10,7 +10,7 @@ void illegal_insn_trap(uintptr_t* regs, uintptr_t mcause, uintptr_t mepc) asm (".pushsection .rodata\n" "illegal_insn_trap_table:\n" " .word truly_illegal_insn\n" -#if !defined(__riscv_hard_float) && defined(PK_ENABLE_FP_EMULATION) +#if !defined(__riscv_flen) && defined(PK_ENABLE_FP_EMULATION) " .word emulate_float_load\n" #else " .word truly_illegal_insn\n" @@ -22,7 +22,7 @@ void illegal_insn_trap(uintptr_t* regs, uintptr_t mcause, uintptr_t mepc) " .word truly_illegal_insn\n" " .word truly_illegal_insn\n" " .word truly_illegal_insn\n" -#if !defined(__riscv_hard_float) && defined(PK_ENABLE_FP_EMULATION) +#if !defined(__riscv_flen) && defined(PK_ENABLE_FP_EMULATION) " .word emulate_float_store\n" #else " .word truly_illegal_insn\n" @@ -106,7 +106,7 @@ static inline int emulate_read_csr(int num, uintptr_t mstatus, uintptr_t* result *result = *mtime >> 32; return 0; #endif -#if !defined(__riscv_hard_float) && defined(PK_ENABLE_FP_EMULATION) +#if !defined(__riscv_flen) && defined(PK_ENABLE_FP_EMULATION) case CSR_FRM: if ((mstatus & MSTATUS_FS) == 0) break; *result = GET_FRM(); @@ -128,7 +128,7 @@ static inline int emulate_write_csr(int num, uintptr_t value, uintptr_t mstatus) { switch (num) { -#if !defined(__riscv_hard_float) && defined(PK_ENABLE_FP_EMULATION) +#if !defined(__riscv_flen) && defined(PK_ENABLE_FP_EMULATION) case CSR_FRM: SET_FRM(value); return 0; case CSR_FFLAGS: SET_FFLAGS(value); return 0; case CSR_FCSR: SET_FCSR(value); return 0; diff --git a/machine/fp_asm.S b/machine/fp_asm.S index 4b8dce1..a3e5ef4 100644 --- a/machine/fp_asm.S +++ b/machine/fp_asm.S @@ -1,6 +1,10 @@ // See LICENSE for license details. -#ifdef __riscv_hard_float +#ifdef __riscv_flen + +#if __riscv_flen != 64 +# error single-float only is not supported +#endif #define get_f32(which) fmv.x.s a0, which; jr t0 #define put_f32(which) fmv.s.x which, a0; jr t0 diff --git a/machine/fp_emulation.h b/machine/fp_emulation.h index 8d209e1..c2177a2 100644 --- a/machine/fp_emulation.h +++ b/machine/fp_emulation.h @@ -8,7 +8,7 @@ #define PRECISION_S 0 #define PRECISION_D 1 -#ifdef __riscv_hard_float +#ifdef __riscv_flen # define GET_F32_REG(insn, pos, regs) ({ \ register int32_t value asm("a0") = ((insn) >> ((pos)-3)) & 0xf8; \ uintptr_t tmp; \ diff --git a/machine/mentry.S b/machine/mentry.S index 64c60c3..95653c1 100644 --- a/machine/mentry.S +++ b/machine/mentry.S @@ -107,7 +107,7 @@ trap_vector: STORE t6,31*REGBYTES(sp) STORE t0, 2*REGBYTES(sp) # sp -#ifndef __riscv_hard_float +#ifndef __riscv_flen lw tp, (sp) # Move the emulated FCSR from x0's save slot into tp. #endif STORE x0, (sp) # Zero x0's save slot. @@ -115,7 +115,7 @@ trap_vector: # Invoke the handler. jalr t1 -#ifndef __riscv_hard_float +#ifndef __riscv_flen sw tp, (sp) # Move the emulated FCSR from tp into x0's save slot. #endif diff --git a/machine/minit.c b/machine/minit.c index 33a1e3b..b3f2c86 100644 --- a/machine/minit.c +++ b/machine/minit.c @@ -54,7 +54,7 @@ static void fp_init() { assert(read_csr(mstatus) & MSTATUS_FS); -#ifdef __riscv_hard_float +#ifdef __riscv_flen if (!supports_extension('D')) die("FPU not found; recompile pk with -msoft-float"); for (int i = 0; i < 32; i++) diff --git a/machine/mtrap.h b/machine/mtrap.h index ff071fd..9995203 100644 --- a/machine/mtrap.h +++ b/machine/mtrap.h @@ -85,7 +85,7 @@ static inline void wfi() #define MENTRY_FRAME_SIZE (INTEGER_CONTEXT_SIZE + SOFT_FLOAT_CONTEXT_SIZE \ + HLS_SIZE) -#ifdef __riscv_hard_float +#ifdef __riscv_flen # define SOFT_FLOAT_CONTEXT_SIZE 0 #else # define SOFT_FLOAT_CONTEXT_SIZE (8 * 32) |