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| author | Andrew Waterman <andrew@sifive.com> | 2019-07-17 16:36:16 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2019-07-17 16:36:16 -0700 |
| commit | 3d681ed0d01df2fa65f15df86e06b63a7a696d1f (patch) | |
| tree | 913dde2e9330a3a9de53926beedae3a1209961fc | |
| parent | d5909ee6f6c41ac0c539b687fb6e849401b0aecc (diff) | |
| download | pk-3d681ed0d01df2fa65f15df86e06b63a7a696d1f.zip pk-3d681ed0d01df2fa65f15df86e06b63a7a696d1f.tar.gz pk-3d681ed0d01df2fa65f15df86e06b63a7a696d1f.tar.bz2 | |
Use pointer-sized entries in trap table
This allows bbl to be loaded above 4 GiB on RV64.
| -rw-r--r-- | machine/mentry.S | 38 |
1 files changed, 19 insertions, 19 deletions
diff --git a/machine/mentry.S b/machine/mentry.S index 99e1b72..84bd3c1 100644 --- a/machine/mentry.S +++ b/machine/mentry.S @@ -8,27 +8,27 @@ .align 6 trap_table: #define BAD_TRAP_VECTOR 0 - .word bad_trap - .word pmp_trap - .word illegal_insn_trap - .word bad_trap - .word misaligned_load_trap - .word pmp_trap - .word misaligned_store_trap - .word pmp_trap - .word bad_trap - .word mcall_trap - .word bad_trap + .dc.a bad_trap + .dc.a pmp_trap + .dc.a illegal_insn_trap + .dc.a bad_trap + .dc.a misaligned_load_trap + .dc.a pmp_trap + .dc.a misaligned_store_trap + .dc.a pmp_trap + .dc.a bad_trap + .dc.a mcall_trap + .dc.a bad_trap #ifdef BBL_BOOT_MACHINE - .word mcall_trap + .dc.a mcall_trap #else - .word bad_trap + .dc.a bad_trap #endif /* BBL_BOOT_MACHINE */ - .word bad_trap + .dc.a bad_trap #define TRAP_FROM_MACHINE_MODE_VECTOR 13 - .word __trap_from_machine_mode - .word bad_trap - .word bad_trap + .dc.a __trap_from_machine_mode + .dc.a bad_trap + .dc.a bad_trap .option norvc .section .text.init,"ax",@progbits @@ -112,11 +112,11 @@ trap_vector: STORE t0, 5*REGBYTES(sp) 1:auipc t0, %pcrel_hi(trap_table) # t0 <- %hi(trap_table) STORE t1, 6*REGBYTES(sp) - sll t1, a1, 2 # t1 <- mcause << 2 + sll t1, a1, LOG_REGBYTES # t1 <- mcause * ptr size STORE t2, 7*REGBYTES(sp) add t1, t0, t1 # t1 <- %hi(trap_table)[mcause] STORE s0, 8*REGBYTES(sp) - LWU t1, %pcrel_lo(1b)(t1) # t1 <- trap_table[mcause] + LOAD t1, %pcrel_lo(1b)(t1) # t1 <- trap_table[mcause] STORE s1, 9*REGBYTES(sp) mv a0, sp # a0 <- regs STORE a2,12*REGBYTES(sp) |