diff options
Diffstat (limited to 'include/opcode')
65 files changed, 0 insertions, 40855 deletions
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog deleted file mode 100644 index caf7aee..0000000 --- a/include/opcode/ChangeLog +++ /dev/null @@ -1,1903 +0,0 @@ -2013-08-23 Yuri Chornoivan <yurchor@ukr.net> - - PR binutils/15834 - * i960.h: Fix typos. - -2013-08-19 Richard Sandiford <rdsandiford@googlemail.com> - - * mips.h: Remove references to "+I" and imm2_expr. - -2013-08-19 Richard Sandiford <rdsandiford@googlemail.com> - - * mips.h (M_DEXT, M_DINS): Delete. - -2013-08-19 Richard Sandiford <rdsandiford@googlemail.com> - - * mips.h (OP_OPTIONAL_REG): New mips_operand_type. - (mips_optional_operand_p): New function. - -2013-08-04 Jürgen Urban <JuergenUrban@gmx.de> - Richard Sandiford <rdsandiford@googlemail.com> - - * mips.h: Document new VU0 operand characters. - (OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types. - (OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R) - (OP_REG_R5900_ACC): New mips_reg_operand_types. - (INSN2_VU0_CHANNEL_SUFFIX): New macro. - (mips_vu0_channel_mask): Declare. - -2013-08-03 Richard Sandiford <rdsandiford@googlemail.com> - - * mips.h (mips_pcrel_operand): Inherit from mips_int_operand. - (mips_int_operand_min, mips_int_operand_max): New functions. - (mips_decode_pcrel_operand): Use mips_decode_int_operand. - -2013-08-01 Richard Sandiford <rdsandiford@googlemail.com> - - * mips.h (mips_decode_reg_operand): New function. - (INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL) - (INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4) - (INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI): - New macros. - (INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D) - (INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T) - (INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S) - (INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z) - (INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D) - (INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD) - (INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG) - (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP) - (INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP) - (INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete. Renumber other - macros to cover the gaps. - (INSN2_MOD_SP): Replace with... - (INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros. - (MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z) - (MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y) - (MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z) - (MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X): - Delete. - -2013-08-01 Richard Sandiford <rdsandiford@googlemail.com> - - * mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31) - (MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH) - (MIPS16_INSN_COND_BRANCH): Delete. - -2013-07-24 Anna Tikhonova <anna.tikhonova@intel.com> - Kirill Yukhin <kirill.yukhin@intel.com> - Michael Zolotukhin <michael.v.zolotukhin@intel.com> - - * i386.h (BND_PREFIX_OPCODE): New. - -2013-07-14 Richard Sandiford <rdsandiford@googlemail.com> - - * mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and - OP_SAVE_RESTORE_LIST. - (decode_mips16_operand): Declare. - -2013-07-14 Richard Sandiford <rdsandiford@googlemail.com> - - * mips.h (mips_operand_type, mips_reg_operand_type): New enums. - (mips_operand, mips_int_operand, mips_mapped_int_operand) - (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand) - (mips_pcrel_operand): New structures. - (mips_insert_operand, mips_extract_operand, mips_signed_operand) - (mips_decode_int_operand, mips_decode_pcrel_operand): New functions. - (decode_mips_operand, decode_micromips_operand): Declare. - -2013-07-14 Richard Sandiford <rdsandiford@googlemail.com> - - * mips.h: Document MIPS16 "I" opcode. - -2013-07-07 Richard Sandiford <rdsandiford@googlemail.com> - - * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB) - (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB) - (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A) - (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB) - (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB) - (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB) - (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB) - (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB) - (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A) - (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A) - (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB) - (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete. - (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A): - Rename to... - (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB) - (M_USD_AB): ...these. - -2013-07-07 Richard Sandiford <rdsandiford@googlemail.com> - - * mips.h: Remove documentation of "[" and "]". Update documentation - of "k" and the MDMX formats. - -2013-07-07 Richard Sandiford <rdsandiford@googlemail.com> - - * mips.h: Update documentation of "+s" and "+S". - -2013-07-07 Richard Sandiford <rdsandiford@googlemail.com> - - * mips.h: Document "+i". - -2013-07-07 Richard Sandiford <rdsandiford@googlemail.com> - - * mips.h: Remove "mi" documentation. Update "mh" documentation. - (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI): - Delete. - (INSN2_WRITE_GPR_MHI): Rename to... - (INSN2_WRITE_GPR_MH): ...this. - -2013-07-07 Richard Sandiford <rdsandiford@googlemail.com> - - * mips.h: Remove documentation of "+D" and "+T". - -2013-06-26 Richard Sandiford <rdsandiford@googlemail.com> - - * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT. - Use "source" rather than "destination" for microMIPS "G". - -2013-06-25 Maciej W. Rozycki <macro@codesourcery.com> - - * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum - values. - -2013-06-23 Richard Sandiford <rdsandiford@googlemail.com> - - * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS. - -2013-06-17 Catherine Moore <clm@codesourcery.com> - Maciej W. Rozycki <macro@codesourcery.com> - Chao-Ying Fu <fu@mips.com> - - * mips.h (OP_SH_EVAOFFSET): Define. - (OP_MASK_EVAOFFSET): Define. - (INSN_ASE_MASK): Delete. - (ASE_EVA): Define. - (M_CACHEE_AB, M_CACHEE_OB): New. - (M_LBE_OB, M_LBE_AB): New. - (M_LBUE_OB, M_LBUE_AB): New. - (M_LHE_OB, M_LHE_AB): New. - (M_LHUE_OB, M_LHUE_AB): New. - (M_LLE_AB, M_LLE_OB): New. - (M_LWE_OB, M_LWE_AB): New. - (M_LWLE_AB, M_LWLE_OB): New. - (M_LWRE_AB, M_LWRE_OB): New. - (M_PREFE_AB, M_PREFE_OB): New. - (M_SCE_AB, M_SCE_OB): New. - (M_SBE_OB, M_SBE_AB): New. - (M_SHE_OB, M_SHE_AB): New. - (M_SWE_OB, M_SWE_AB): New. - (M_SWLE_AB, M_SWLE_OB): New. - (M_SWRE_AB, M_SWRE_OB): New. - (MICROMIPSOP_SH_EVAOFFSET): Define. - (MICROMIPSOP_MASK_EVAOFFSET): Define. - -2013-06-12 Sandra Loosemore <sandra@codesourcery.com> - - * nios2.h (OP_MATCH_ERET): Correct eret encoding. - -2013-05-22 Jürgen Urban <JuergenUrban@gmx.de> - - * mips.h (M_LQC2_AB, M_SQC2_AB): New macros. - -2013-05-09 Andrew Pinski <apinski@cavium.com> - - * mips.h (OP_MASK_CODE10): Correct definition. - (OP_SH_CODE10): Likewise. - Add a comment that "+J" is used now for OP_*CODE10. - (INSN_ASE_MASK): Update. - (INSN_VIRT): New macro. - (INSN_VIRT64): New macro - -2013-05-02 Nick Clifton <nickc@redhat.com> - - * msp430.h: Add patterns for MSP430X instructions. - -2013-04-06 David S. Miller <davem@davemloft.net> - - * sparc.h (F_PREFERRED): Define. - (F_PREF_ALIAS): Define. - -2013-04-03 Nick Clifton <nickc@redhat.com> - - * v850.h (V850_INVERSE_PCREL): Define. - -2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com> - - PR binutils/15068 - * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor. - -2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com> - - PR binutils/15068 - * tic6xc-insn-formats.h (FLD): Add use of bitfield array. - Add 16-bit opcodes. - * tic6xc-opcode-table.h: Add 16-bit insns. - * tic6x.h: Add support for 16-bit insns. - -2013-03-21 Michael Schewe <michael.schewe@gmx.net> - - * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd - and mov.b/w/l Rs,@(d:32,ERd). - -2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com> - - PR gas/15082 - * tic6x-opcode-table.h: Rename mpydp's specific operand type macro - from ORREGD1324 to ORXREGD1324 and make it cross-path-able through - tic6x_operand_xregpair operand coding type. - Make mpydp instruction cross-path-able, ie: remove the FIXed 'x' - opcode field, usu ORXREGD1324 for the src2 operand and remove the - TIC6X_FLAG_NO_CROSS. - -2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com> - - PR gas/15095 - * tic6x.h (enum tic6x_coding_method): Add - tic6x_coding_dreg_(msb|lsb) field coding type in order to encode - separately the msb and lsb of a register pair. This is needed to - encode the opcodes in the same way as TI assembler does. - * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp - and rsqrdp opcodes to use the new field coding types. - -2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com> - - * arm.h (CRC_EXT_ARMV8): New constant. - (ARCH_CRC_ARMV8): New macro. - -2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com> - - * aarch64.h (AARCH64_FEATURE_CRC): New macro. - -2013-02-06 Sandra Loosemore <sandra@codesourcery.com> - Andrew Jenner <andrew@codesourcery.com> - - Based on patches from Altera Corporation. - - * nios2.h: New file. - -2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com> - - * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2. - -2013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com> - - PR gas/15069 - * tic6x-opcode-table.h: Fix encoding of BNOP instruction. - -2013-01-24 Nick Clifton <nickc@redhat.com> - - * v850.h: Add e3v5 support. - -2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com> - - * aarch64.h (aarch64_op): Remove OP_V_MOVI_B. - -2013-01-10 Peter Bergner <bergner@vnet.ibm.com> - - * ppc.h (PPC_OPCODE_POWER8): New define. - (PPC_OPCODE_HTM): Likewise. - -2013-01-10 Will Newton <will.newton@imgtec.com> - - * metag.h: New file. - -2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com> - - * cr16.h (make_instruction): Rename to cr16_make_instruction. - (match_opcode): Rename to cr16_match_opcode. - -2013-01-04 Juergen Urban <JuergenUrban@gmx.de> - - * mips.h: Add support for r5900 instructions including lq and sq. - -2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com> - - * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c - (make_instruction,match_opcode): Added function prototypes. - (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern. - -2012-11-23 Alan Modra <amodra@gmail.com> - - * ppc.h (ppc_parse_cpu): Update prototype. - -2012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> - - * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx - opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes. - -2012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> - - * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12. - -2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com> - - * ia64.h (ia64_opnd): Add new operand types. - -2012-08-21 David S. Miller <davem@davemloft.net> - - * sparc.h (F3F4): New macro. - -2012-08-13 Ian Bolton <ian.bolton@arm.com> - Laurent Desnogues <laurent.desnogues@arm.com> - Jim MacArthur <jim.macarthur@arm.com> - Marcus Shawcroft <marcus.shawcroft@arm.com> - Nigel Stephens <nigel.stephens@arm.com> - Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> - Richard Earnshaw <rearnsha@arm.com> - Sofiane Naci <sofiane.naci@arm.com> - Tejas Belagod <tejas.belagod@arm.com> - Yufeng Zhang <yufeng.zhang@arm.com> - - * aarch64.h: New file. - -2012-08-13 Richard Sandiford <rdsandiford@googlemail.com> - Maciej W. Rozycki <macro@codesourcery.com> - - * mips.h (mips_opcode): Add the exclusions field. - (OPCODE_IS_MEMBER): Remove macro. - (cpu_is_member): New inline function. - (opcode_is_member): Likewise. - -2012-07-31 Chao-Ying Fu <fu@mips.com> - Catherine Moore <clm@codesourcery.com> - Maciej W. Rozycki <macro@codesourcery.com> - - * mips.h: Document microMIPS DSP ASE usage. - (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for - microMIPS DSP ASE support. - (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise. - (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise. - (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise. - (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise. - (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise. - (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise. - (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise. - -2012-07-06 Maciej W. Rozycki <macro@codesourcery.com> - - * mips.h: Fix a typo in description. - -2012-06-07 Georg-Johann Lay <avr@gjlay.de> - - * avr.h: (AVR_ISA_XCH): New define. - (AVR_ISA_XMEGA): Use it. - (XCH, LAS, LAT, LAC): New XMEGA opcodes. - -2012-05-15 James Murray <jsm@jsm-net.demon.co.uk> - - * m68hc11.h: Add XGate definitions. - (struct m68hc11_opcode): Add xg_mask field. - -2012-05-14 Catherine Moore <clm@codesourcery.com> - Maciej W. Rozycki <macro@codesourcery.com> - Rhonda Wittels <rhonda@codesourcery.com> - - * ppc.h (PPC_OPCODE_VLE): New definition. - (PPC_OP_SA): New macro. - (PPC_OP_SE_VLE): New macro. - (PPC_OP): Use a variable shift amount. - (powerpc_operand): Update comments. - (PPC_OPSHIFT_INV): New macro. - (PPC_OPERAND_CR): Replace with... - (PPC_OPERAND_CR_BIT): ...this and - (PPC_OPERAND_CR_REG): ...this. - - -2012-05-03 Sean Keys <skeys@ipdatasys.com> - - * xgate.h: Header file for XGATE assembler. - -2012-04-27 David S. Miller <davem@davemloft.net> - - * sparc.h: Document new arg code' )' for crypto RS3 - immediates. - - * sparc.h (struct sparc_opcode): New field 'hwcaps'. - F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2, - F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS, - F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete. - (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC, - HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF, - HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU, - HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES, - HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1, - HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE, - HWCAP_CBCOND, HWCAP_CRC32): New defines. - -2012-03-10 Edmar Wienskoski <edmar@freescale.com> - - * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR. - -2012-02-27 Alan Modra <amodra@gmail.com> - - * crx.h (cst4_map): Update declaration. - -2012-02-25 Walter Lee <walt@tilera.com> - - * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS, - TILEGX_OPC_LD_TLS. - * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS, - TILEPRO_OPC_LW_TLS_SN. - -2012-02-08 H.J. Lu <hongjiu.lu@intel.com> - - * i386.h (XACQUIRE_PREFIX_OPCODE): New. - (XRELEASE_PREFIX_OPCODE): Likewise. - -2011-12-08 Andrew Pinski <apinski@cavium.com> - Adam Nemet <anemet@caviumnetworks.com> - - * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2. - (INSN_OCTEON2): New macro. - (CPU_OCTEON2): New macro. - (OPCODE_IS_MEMBER): Add Octeon2. - -2011-11-29 Andrew Pinski <apinski@cavium.com> - - * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP. - (INSN_OCTEONP): New macro. - (CPU_OCTEONP): New macro. - (OPCODE_IS_MEMBER): Add Octeon+. - (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values. - -2011-11-01 DJ Delorie <dj@redhat.com> - - * rl78.h: New file. - -2011-10-24 Maciej W. Rozycki <macro@codesourcery.com> - - * mips.h: Fix a typo in description. - -2011-09-21 David S. Miller <davem@davemloft.net> - - * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int. - (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2, - F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS, - F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits. - -2011-08-09 Chao-ying Fu <fu@mips.com> - Maciej W. Rozycki <macro@codesourcery.com> - - * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros. - (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine. - (INSN_ASE_MASK): Add the MCU bit. - (INSN_MCU): New macro. - (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values. - (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros. - -2011-08-09 Maciej W. Rozycki <macro@codesourcery.com> - - * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros. - (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise. - (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise. - (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise. - (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise. - (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise. - (INSN2_READ_GPR_MMN): Likewise. - (INSN2_READ_FPR_D): Change the bit used. - (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise. - (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise. - (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise. - (INSN2_COND_BRANCH): Likewise. - (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros. - (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise. - (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise. - (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise. - (INSN2_MOD_GPR_MN): Likewise. - -2011-08-05 David S. Miller <davem@davemloft.net> - - * sparc.h: Document new format codes '4', '5', and '('. - (OPF_LOW4, RS3): New macros. - -2011-08-03 Maciej W. Rozycki <macro@codesourcery.com> - - * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the - order of flags documented. - -2011-07-29 Maciej W. Rozycki <macro@codesourcery.com> - - * mips.h: Clarify the description of microMIPS instruction - manipulation macros. - (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros. - -2011-07-24 Chao-ying Fu <fu@mips.com> - Maciej W. Rozycki <macro@codesourcery.com> - - * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros. - (OP_MASK_STYPE, OP_SH_STYPE): Likewise. - (OP_MASK_CODE10, OP_SH_CODE10): Likewise. - (OP_MASK_TRAP, OP_SH_TRAP): Likewise. - (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise. - (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise. - (OP_MASK_RS3, OP_SH_RS3): Likewise. - (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise. - (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise. - (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise. - (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise. - (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise. - (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise. - (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise. - (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise. - (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise. - (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise. - (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise. - (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise. - (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise. - (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise. - (INSN_WRITE_GPR_S): New macro. - (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise. - (INSN2_READ_FPR_D): Likewise. - (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise. - (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise. - (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise. - (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise. - (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise. - (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise. - (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise. - (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise. - (CPU_MICROMIPS): New macro. - (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values. - (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise. - (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise. - (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise. - (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise. - (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise. - (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise. - (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise. - (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise. - (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise. - (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise. - (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise. - (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise. - (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros. - (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise. - (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise. - (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise. - (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise. - (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise. - (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise. - (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise. - (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise. - (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise. - (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise. - (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise. - (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise. - (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise. - (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise. - (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise. - (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise. - (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise. - (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise. - (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise. - (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise. - (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise. - (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise. - (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise. - (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise. - (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise. - (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise. - (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise. - (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise. - (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise. - (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise. - (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise. - (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise. - (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise. - (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise. - (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise. - (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise. - (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise. - (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise. - (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise. - (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise. - (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise. - (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise. - (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise. - (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise. - (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise. - (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise. - (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise. - (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise. - (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise. - (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise. - (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise. - (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise. - (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise. - (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise. - (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise. - (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise. - (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise. - (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise. - (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise. - (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise. - (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise. - (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise. - (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise. - (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise. - (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise. - (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise. - (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise. - (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise. - (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise. - (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise. - (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise. - (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise. - (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise. - (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise. - (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise. - (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise. - (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise. - (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise. - (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise. - (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise. - (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise. - (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise. - (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise. - (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise. - (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise. - (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise. - (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise. - (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise. - (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise. - (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise. - (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise. - (micromips_opcodes): New declaration. - (bfd_micromips_num_opcodes): Likewise. - -2011-07-24 Maciej W. Rozycki <macro@codesourcery.com> - - * mips.h (INSN_TRAP): Rename to... - (INSN_NO_DELAY_SLOT): ... this. - (INSN_SYNC): Remove macro. - -2011-07-01 Eric B. Weddington <eric.weddington@atmel.com> - - * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually - a duplicate of AVR_ISA_SPM. - -2011-07-01 Nick Clifton <nickc@redhat.com> - - * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX. - -2011-06-18 Robin Getz <robin.getz@analog.com> - - * bfin.h (is_macmod_signed): New func - -2011-06-18 Mike Frysinger <vapier@gentoo.org> - - * bfin.h (is_macmod_pmove): Add missing space before func args. - (is_macmod_hmove): Likewise. - -2011-06-13 Walter Lee <walt@tilera.com> - - * tilegx.h: New file. - * tilepro.h: New file. - -2011-05-31 Paul Brook <paul@codesourcery.com> - - * arm.h (ARM_ARCH_V7R_IDIV): Define. - -2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> - - * s390.h: Replace S390_OPERAND_REG_EVEN with - S390_OPERAND_REG_PAIR. - -2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> - - * s390.h: Add S390_OPCODE_REG_EVEN flag. - -2011-04-18 Julian Brown <julian@codesourcery.com> - - * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask. - -2011-04-11 Dan McDonald <dan@wellkeeper.com> - - PR gas/12296 - * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS. - -2011-03-22 Eric B. Weddington <eric.weddington@atmel.com> - - * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA): - New instruction set flags. - (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA. - -2011-02-28 Maciej W. Rozycki <macro@codesourcery.com> - - * mips.h (M_PREF_AB): New enum value. - -2011-02-12 Mike Frysinger <vapier@gentoo.org> - - * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH, - M_IU): Define. - (is_macmod_pmove, is_macmod_hmove): New functions. - -2011-02-11 Mike Frysinger <vapier@gentoo.org> - - * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection. - -2011-02-04 Bernd Schmidt <bernds@codesourcery.com> - - * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP. - * tic6x.h (TIC6X_INSN_ATOMIC): Remove. - -2010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> - - PR gas/11395 - * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit - "bb" entries. - -2010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> - - PR gas/11395 - * hppa.h: Clear "d" bit in "add" and "sub" patterns. - -2010-12-18 Richard Sandiford <rdsandiford@googlemail.com> - - * mips.h: Update commentary after last commit. - -2010-12-18 Mingjie Xing <mingjie.xing@gmail.com> - - * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C) - (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z) - (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define. - -2010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> - - * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU. - -2010-11-23 Richard Sandiford <rdsandiford@googlemail.com> - - * mips.h: Fix previous commit. - -2010-11-23 Maciej W. Rozycki <macro@linux-mips.org> - - * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A. - (INSN_LOONGSON_3A): Clear bit 31. - -2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> - - PR gas/12198 - * arm.h (ARM_AEXT_V6M_ONLY): New define. - (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY. - (ARM_ARCH_V6M_ONLY): New define. - -2010-11-11 Mingming Sun <mingm.sun@gmail.com> - - * mips.h (INSN_LOONGSON_3A): Defined. - (CPU_LOONGSON_3A): Defined. - (OPCODE_IS_MEMBER): Add LOONGSON_3A. - -2010-10-09 Matt Rice <ratmice@gmail.com> - - * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_. - (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise. - -2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> - - * arm.h (ARM_EXT_VIRT): New define. - (ARM_ARCH_V7A_IDIV_MP_SEC): Rename... - (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization - Extensions. - -2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> - - * arm.h (ARM_AEXT_ADIV): New define. - (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise. - -2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> - - * arm.h (ARM_EXT_OS): New define. - (ARM_AEXT_V6SM): Likewise. - (ARM_ARCH_V6SM): Likewise. - -2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> - - * arm.h (ARM_EXT_MP): Add. - (ARM_ARCH_V7A_MP): Likewise. - -2010-09-22 Mike Frysinger <vapier@gentoo.org> - - * bfin.h: Declare pseudoChr structs/defines. - -2010-09-21 Mike Frysinger <vapier@gentoo.org> - - * bfin.h: Strip trailing whitespace. - -2010-07-29 DJ Delorie <dj@redhat.com> - - * rx.h (RX_Operand_Type): Add TwoReg. - (RX_Opcode_ID): Remove ediv and ediv2. - -2010-07-27 DJ Delorie <dj@redhat.com> - - * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics. - -2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com> - Ina Pandit <ina.pandit@kpitcummins.com> - - * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION, - PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and - PROCESSOR_V850E2_ALL. - Remove PROCESSOR_V850EA support. - (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC, - V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI, - V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED, - V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP, - V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and - V850_OPERAND_PERCENT. - Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and - V850_NOT_R0. - Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP - and V850E_PUSH_POP - -2010-07-06 Maciej W. Rozycki <macro@codesourcery.com> - - * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro. - (MIPS16_INSN_BRANCH): Rename to... - (MIPS16_INSN_COND_BRANCH): ... this. - -2010-07-03 Alan Modra <amodra@gmail.com> - - * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete. - Renumber other PPC_OPCODE defines. - -2010-07-03 Alan Modra <amodra@gmail.com> - - * ppc.h (PPC_OPCODE_COMMON): Expand comment. - -2010-06-29 Alan Modra <amodra@gmail.com> - - * maxq.h: Delete file. - -2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de> - - * ppc.h (PPC_OPCODE_E500): Define. - -2010-05-26 Catherine Moore <clm@codesourcery.com> - - * opcode/mips.h (INSN_MIPS16): Remove. - -2010-04-21 Joseph Myers <joseph@codesourcery.com> - - * tic6x-insn-formats.h (s_branch): Correct typo in bitmask. - -2010-04-15 Nick Clifton <nickc@redhat.com> - - * alpha.h: Update copyright notice to use GPLv3. - * arc.h: Likewise. - * arm.h: Likewise. - * avr.h: Likewise. - * bfin.h: Likewise. - * cgen.h: Likewise. - * convex.h: Likewise. - * cr16.h: Likewise. - * cris.h: Likewise. - * crx.h: Likewise. - * d10v.h: Likewise. - * d30v.h: Likewise. - * dlx.h: Likewise. - * h8300.h: Likewise. - * hppa.h: Likewise. - * i370.h: Likewise. - * i386.h: Likewise. - * i860.h: Likewise. - * i960.h: Likewise. - * ia64.h: Likewise. - * m68hc11.h: Likewise. - * m68k.h: Likewise. - * m88k.h: Likewise. - * maxq.h: Likewise. - * mips.h: Likewise. - * mmix.h: Likewise. - * mn10200.h: Likewise. - * mn10300.h: Likewise. - * msp430.h: Likewise. - * np1.h: Likewise. - * ns32k.h: Likewise. - * or32.h: Likewise. - * pdp11.h: Likewise. - * pj.h: Likewise. - * pn.h: Likewise. - * ppc.h: Likewise. - * pyr.h: Likewise. - * rx.h: Likewise. - * s390.h: Likewise. - * score-datadep.h: Likewise. - * score-inst.h: Likewise. - * sparc.h: Likewise. - * spu-insns.h: Likewise. - * spu.h: Likewise. - * tic30.h: Likewise. - * tic4x.h: Likewise. - * tic54x.h: Likewise. - * tic80.h: Likewise. - * v850.h: Likewise. - * vax.h: Likewise. - -2010-03-25 Joseph Myers <joseph@codesourcery.com> - - * tic6x-control-registers.h, tic6x-insn-formats.h, - tic6x-opcode-table.h, tic6x.h: New. - -2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com> - - * mips.h: (LOONGSON2F_NOP_INSN): New macro. - -2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com> - - * opcode/ppc.h (PPC_OPCODE_TITAN): Define. - -2010-01-14 H.J. Lu <hongjiu.lu@intel.com> - - * ia64.h (ia64_find_opcode): Remove argument name. - (ia64_find_next_opcode): Likewise. - (ia64_dis_opcode): Likewise. - (ia64_free_opcode): Likewise. - (ia64_find_dependency): Likewise. - -2009-11-22 Doug Evans <dje@sebabeach.org> - - * cgen.h: Include bfd_stdint.h. - (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types. - -2009-11-18 Paul Brook <paul@codesourcery.com> - - * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define. - -2009-11-17 Paul Brook <paul@codesourcery.com> - Daniel Jacobowitz <dan@codesourcery.com> - - * arm.h (ARM_EXT_V6_DSP): Define. - (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP. - (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define. - -2009-11-04 DJ Delorie <dj@redhat.com> - - * rx.h (rx_decode_opcode) (mvtipl): Add. - (mvtcp, mvfcp, opecp): Remove. - -2009-11-02 Paul Brook <paul@codesourcery.com> - - * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA, - FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define. - (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD, - FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16, - FPU_ARCH_NEON_VFP_V4): Define. - -2009-10-23 Doug Evans <dje@sebabeach.org> - - * cgen-bitset.h: Delete, moved to ../cgen/bitset.h. - * cgen.h: Update. Improve multi-inclusion macro name. - -2009-10-02 Peter Bergner <bergner@vnet.ibm.com> - - * ppc.h (PPC_OPCODE_476): Define. - -2009-10-01 Peter Bergner <bergner@vnet.ibm.com> - - * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2. - -2009-09-29 DJ Delorie <dj@redhat.com> - - * rx.h: New file. - -2009-09-22 Peter Bergner <bergner@vnet.ibm.com> - - * ppc.h (ppc_cpu_t): Typedef to uint64_t. - -2009-09-21 Ben Elliston <bje@au.ibm.com> - - * ppc.h (PPC_OPCODE_PPCA2): New. - -2009-09-05 Martin Thuresson <martin@mtme.org> - - * ia64.h (struct ia64_operand): Renamed member class to op_class. - -2009-08-29 Martin Thuresson <martin@mtme.org> - - * tic30.h (template): Rename type template to - insn_template. Updated code to use new name. - * tic54x.h (template): Rename type template to - insn_template. - -2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk> - - * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT. - -2009-06-11 Anthony Green <green@moxielogic.com> - - * moxie.h (MOXIE_F3_PCREL): Define. - (moxie_form3_opc_info): Grow. - -2009-06-06 Anthony Green <green@moxielogic.com> - - * moxie.h (MOXIE_F1_M): Define. - -2009-04-15 Anthony Green <green@moxielogic.com> - - * moxie.h: Created. - -2009-04-06 DJ Delorie <dj@redhat.com> - - * h8300.h: Add relaxation attributes to MOVA opcodes. - -2009-03-10 Alan Modra <amodra@bigpond.net.au> - - * ppc.h (ppc_parse_cpu): Declare. - -2009-03-02 Qinwei <qinwei@sunnorth.com.cn> - - * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5 - and _IMM11 for mbitclr and mbitset. - * score-datadep.h: Update dependency information. - -2009-02-26 Peter Bergner <bergner@vnet.ibm.com> - - * ppc.h (PPC_OPCODE_POWER7): New. - -2009-02-06 Doug Evans <dje@google.com> - - * i386.h: Add comment regarding sse* insns and prefixes. - -2009-02-03 Sandip Matte <sandip@rmicorp.com> - - * mips.h (INSN_XLR): Define. - (INSN_CHIP_MASK): Update. - (CPU_XLR): Define. - (OPCODE_IS_MEMBER): Update. - (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define. - -2009-01-28 Doug Evans <dje@google.com> - - * opcode/i386.h: Add multiple inclusion protection. - (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM) - (EDI_REG_NUM): New macros. - (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros. - (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros. - (REX_PREFIX_P): New macro. - -2009-01-09 Peter Bergner <bergner@vnet.ibm.com> - - * ppc.h (struct powerpc_opcode): New field "deprecated". - (PPC_OPCODE_NOPOWER4): Delete. - -2008-11-28 Joshua Kinard <kumba@gentoo.org> - - * mips.h: Define CPU_R14000, CPU_R16000. - (OPCODE_IS_MEMBER): Include R14000, R16000 in test. - -2008-11-18 Catherine Moore <clm@codesourcery.com> - - * arm.h (FPU_NEON_FP16): New. - (FPU_ARCH_NEON_FP16): New. - -2008-11-06 Chao-ying Fu <fu@mips.com> - - * mips.h: Doucument '1' for 5-bit sync type. - -2008-08-28 H.J. Lu <hongjiu.lu@intel.com> - - * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update - IA64_RS_CR. - -2008-08-01 Peter Bergner <bergner@vnet.ibm.com> - - * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New. - -2008-07-30 Michael J. Eager <eager@eagercon.com> - - * ppc.h (PPC_OPCODE_405): Define. - (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define. - -2008-06-13 Peter Bergner <bergner@vnet.ibm.com> - - * ppc.h (ppc_cpu_t): New typedef. - (struct powerpc_opcode <flags>): Use it. - (struct powerpc_operand <insert, extract>): Likewise. - (struct powerpc_macro <flags>): Likewise. - -2008-06-12 Adam Nemet <anemet@caviumnetworks.com> - - * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S. - Update comment before MIPS16 field descriptors to mention MIPS16. - (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for - BBIT. - (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1): - New bit masks and shift counts for cins and exts. - - * mips.h: Document new field descriptors +Q. - (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI. - -2008-04-28 Adam Nemet <anemet@caviumnetworks.com> - - * mips.h (INSN_MACRO): Move it up to the pinfo macros. - (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros. - -2008-04-14 Edmar Wienskoski <edmar@freescale.com> - - * ppc.h: (PPC_OPCODE_E500MC): New. - -2008-04-03 H.J. Lu <hongjiu.lu@intel.com> - - * i386.h (MAX_OPERANDS): Set to 5. - (MAX_MNEM_SIZE): Changed to 20. - -2008-03-28 Eric B. Weddington <eric.weddington@atmel.com> - - * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167. - -2008-03-09 Paul Brook <paul@codesourcery.com> - - * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define. - -2008-03-04 Paul Brook <paul@codesourcery.com> - - * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define. - (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags. - (ARM_AEXT_V6M, ARM_ARCH_V6M): Define. - -2008-02-27 Denis Vlasenko <vda.linux@googlemail.com> - Nick Clifton <nickc@redhat.com> - - PR 3134 - * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction - with a 32-bit displacement but without the top bit of the 4th byte - set. - -2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com> - - * cr16.h (cr16_num_optab): Declared. - -2008-02-14 Hakan Ardo <hakan@debian.org> - - PR gas/2626 - * avr.h (AVR_ISA_2xxe): Define. - -2008-02-04 Adam Nemet <anemet@caviumnetworks.com> - - * mips.h: Update copyright. - (INSN_CHIP_MASK): New macro. - (INSN_OCTEON): New macro. - (CPU_OCTEON): New macro. - (OPCODE_IS_MEMBER): Handle Octeon instructions. - -2008-01-23 Eric B. Weddington <eric.weddington@atmel.com> - - * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401. - -2008-01-03 Eric B. Weddington <eric.weddington@atmel.com> - - * avr.h (AVR_ISA_USB162): Add new opcode set. - (AVR_ISA_AVR3): Likewise. - -2007-11-29 Mark Shinwell <shinwell@codesourcery.com> - - * mips.h (INSN_LOONGSON_2E): New. - (INSN_LOONGSON_2F): New. - (CPU_LOONGSON_2E): New. - (CPU_LOONGSON_2F): New. - (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags. - -2007-11-29 Mark Shinwell <shinwell@codesourcery.com> - - * mips.h (INSN_ISA*): Redefine certain values as an - enumeration. Update comments. - (mips_isa_table): New. - (ISA_MIPS*): Redefine to match enumeration. - (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA* - values. - -2007-08-08 Ben Elliston <bje@au.ibm.com> - - * ppc.h (PPC_OPCODE_PPCPS): New. - -2007-07-03 Nathan Sidwell <nathan@codesourcery.com> - - * m68k.h: Document j K & E. - -2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com> - - * cr16.h: New file for CR16 target. - -2007-05-02 Alan Modra <amodra@bigpond.net.au> - - * ppc.h (PPC_OPERAND_PLUS1): Update comment. - -2007-04-23 Nathan Sidwell <nathan@codesourcery.com> - - * m68k.h (mcfisa_c): New. - (mcfusp, mcf_mask): Adjust. - -2007-04-20 Alan Modra <amodra@bigpond.net.au> - - * ppc.h (struct powerpc_operand): Replace "bits" with "bitm". - (num_powerpc_operands): Declare. - (PPC_OPERAND_SIGNED et al): Redefine as hex. - (PPC_OPERAND_PLUS1): Define. - -2007-03-21 H.J. Lu <hongjiu.lu@intel.com> - - * i386.h (REX_MODE64): Renamed to ... - (REX_W): This. - (REX_EXTX): Renamed to ... - (REX_R): This. - (REX_EXTY): Renamed to ... - (REX_X): This. - (REX_EXTZ): Renamed to ... - (REX_B): This. - -2007-03-15 H.J. Lu <hongjiu.lu@intel.com> - - * i386.h: Add entries from config/tc-i386.h and move tables - to opcodes/i386-opc.h. - -2007-03-13 H.J. Lu <hongjiu.lu@intel.com> - - * i386.h (FloatDR): Removed. - (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR. - -2007-03-01 Alan Modra <amodra@bigpond.net.au> - - * spu-insns.h: Add soma double-float insns. - -2007-02-20 Thiemo Seufer <ths@mips.com> - Chao-Ying Fu <fu@mips.com> - - * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction. - (INSN_DSPR2): Add flag for DSP R2 instructions. - (M_BALIGN): New macro. - -2007-02-14 Alan Modra <amodra@bigpond.net.au> - - * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm - and Seg3ShortFrom with Shortform. - -2007-02-11 H.J. Lu <hongjiu.lu@intel.com> - - PR gas/4027 - * i386.h (i386_optab): Put the real "test" before the pseudo - one. - -2007-01-08 Kazu Hirata <kazu@codesourcery.com> - - * m68k.h (m68010up): OR fido_a. - -2006-12-25 Kazu Hirata <kazu@codesourcery.com> - - * m68k.h (fido_a): New. - -2006-12-24 Kazu Hirata <kazu@codesourcery.com> - - * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a, - mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined - values. - -2006-11-08 H.J. Lu <hongjiu.lu@intel.com> - - * i386.h (i386_optab): Replace CpuPNI with CpuSSE3. - -2006-10-31 Mei Ligang <ligang@sunnorth.com.cn> - - * score-inst.h (enum score_insn_type): Add Insn_internal. - -2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com> - Yukishige Shibata <shibata@rd.scei.sony.co.jp> - Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp> - Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp> - Alan Modra <amodra@bigpond.net.au> - - * spu-insns.h: New file. - * spu.h: New file. - -2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com> - - * ppc.h (PPC_OPCODE_CELL): Define. - -2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> - - * i386.h : Modify opcode to support for the change in POPCNT opcode - in amdfam10 architecture. - -2006-09-28 H.J. Lu <hongjiu.lu@intel.com> - - * i386.h: Replace CpuMNI with CpuSSSE3. - -2006-09-26 Mark Shinwell <shinwell@codesourcery.com> - Joseph Myers <joseph@codesourcery.com> - Ian Lance Taylor <ian@wasabisystems.com> - Ben Elliston <bje@wasabisystems.com> - - * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define. - -2006-09-17 Mei Ligang <ligang@sunnorth.com.cn> - - * score-datadep.h: New file. - * score-inst.h: New file. - -2006-07-14 H.J. Lu <hongjiu.lu@intel.com> - - * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps, - movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu, - movdq2q and movq2dq. - -2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> - Michael Meissner <michael.meissner@amd.com> - - * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions). - -2006-06-12 H.J. Lu <hongjiu.lu@intel.com> - - * i386.h (i386_optab): Add "nop" with memory reference. - -2006-06-12 H.J. Lu <hongjiu.lu@intel.com> - - * i386.h (i386_optab): Update comment for 64bit NOP. - -2006-06-06 Ben Elliston <bje@au.ibm.com> - Anton Blanchard <anton@samba.org> - - * ppc.h (PPC_OPCODE_POWER6): Define. - Adjust whitespace. - -2006-06-05 Thiemo Seufer <ths@mips.com> - - * mips.h: Improve description of MT flags. - -2006-05-25 Richard Sandiford <richard@codesourcery.com> - - * m68k.h (mcf_mask): Define. - -2006-05-05 Thiemo Seufer <ths@mips.com> - David Ung <davidu@mips.com> - - * mips.h (enum): Add macro M_CACHE_AB. - -2006-05-04 Thiemo Seufer <ths@mips.com> - Nigel Stephens <nigel@mips.com> - David Ung <davidu@mips.com> - - * mips.h: Add INSN_SMARTMIPS define. - -2006-04-30 Thiemo Seufer <ths@mips.com> - David Ung <davidu@mips.com> - - * mips.h: Defines udi bits and masks. Add description of - characters which may appear in the args field of udi - instructions. - -2006-04-26 Thiemo Seufer <ths@networkno.de> - - * mips.h: Improve comments describing the bitfield instruction - fields. - -2006-04-26 Julian Brown <julian@codesourcery.com> - - * arm.h (FPU_VFP_EXT_V3): Define constant. - (FPU_NEON_EXT_V1): Likewise. - (FPU_VFP_HARD): Update. - (FPU_VFP_V3): Define macro. - (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros. - -2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de> - - * avr.h (AVR_ISA_PWMx): New. - -2006-03-28 Nathan Sidwell <nathan@codesourcery.com> - - * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010, - cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851, - cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e, - cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x, - cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove. - -2006-03-10 Paul Brook <paul@codesourcery.com> - - * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions. - -2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> - - * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come - first. Correct mask of bb "B" opcode. - -2006-02-27 H.J. Lu <hongjiu.lu@intel.com> - - * i386.h (i386_optab): Support Intel Merom New Instructions. - -2006-02-24 Paul Brook <paul@codesourcery.com> - - * arm.h: Add V7 feature bits. - -2006-02-23 H.J. Lu <hongjiu.lu@intel.com> - - * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b. - -2006-01-31 Paul Brook <paul@codesourcery.com> - Richard Earnshaw <rearnsha@arm.com> - - * arm.h: Use ARM_CPU_FEATURE. - (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New. - (arm_feature_set): Change to a structure. - (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE, - ARM_FEATURE): New macros. - -2005-12-07 Hans-Peter Nilsson <hp@axis.com> - - * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS) - (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros. - (ADD_PC_INCR_OPCODE): Don't define. - -2005-12-06 H.J. Lu <hongjiu.lu@intel.com> - - PR gas/1874 - * i386.h (i386_optab): Add 64bit support for monitor and mwait. - -2005-11-14 David Ung <davidu@mips.com> - - * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore - instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for - save/restore encoding of the args field. - -2005-10-28 Dave Brolley <brolley@redhat.com> - - Contribute the following changes: - 2005-02-16 Dave Brolley <brolley@redhat.com> - - * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename - cgen_isa_mask_* to cgen_bitset_*. - * cgen.h: Likewise. - - 2003-10-21 Richard Sandiford <rsandifo@redhat.com> - - * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition. - (CGEN_ATTR_ENTRY): Change "value" to type "unsigned". - (CGEN_CPU_TABLE): Make isas a ponter. - - 2003-09-29 Dave Brolley <brolley@redhat.com> - - * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef. - (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto. - (CGEN_ATTR_VALUE_TYPE): Use these new typedefs. - - 2002-12-13 Dave Brolley <brolley@redhat.com> - - * cgen.h (symcat.h): #include it. - (cgen-bitset.h): #include it. - (CGEN_ATTR_VALUE_TYPE): Now a union. - (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h. - (CGEN_ATTR_ENTRY): 'value' now unsigned. - (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*). - * cgen-bitset.h: New file. - -2005-09-30 Catherine Moore <clm@cm00re.com> - - * bfin.h: New file. - -2005-10-24 Jan Beulich <jbeulich@novell.com> - - * ia64.h (enum ia64_opnd): Move memory operand out of set of - indirect operands. - -2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> - - * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes. - Add FLAG_STRICT to pa10 ftest opcode. - -2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> - - * hppa.h (pa_opcodes): Remove lha entries. - -2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> - - * hppa.h (FLAG_STRICT): Revise comment. - (pa_opcode): Revise ordering rules. Add/move strict pa10 variants - before corresponding pa11 opcodes. Add strict pa10 register-immediate - entries for "fdc". - -2005-09-30 Catherine Moore <clm@cm00re.com> - - * bfin.h: New file. - -2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> - - * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries. - -2005-09-06 Chao-ying Fu <fu@mips.com> - - * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H, - OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New - define. - Document !, $, *, &, g, +t, +T operand formats for MT instructions. - (INSN_ASE_MASK): Update to include INSN_MT. - (INSN_MT): New define for MT ASE. - -2005-08-25 Chao-ying Fu <fu@mips.com> - - * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S, - OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7, - OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4, - OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP, - OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define. - Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP - instructions. - (INSN_DSP): New define for DSP ASE. - -2005-08-18 Alan Modra <amodra@bigpond.net.au> - - * a29k.h: Delete. - -2005-08-15 Daniel Jacobowitz <dan@codesourcery.com> - - * ppc.h (PPC_OPCODE_E300): Define. - -2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com> - - * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109. - -2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> - - PR gas/336 - * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb - and pitlb. - -2005-07-27 Jan Beulich <jbeulich@novell.com> - - * i386.h (i386_optab): Add comment to movd. Use LongMem for all - movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers. - Add movq-s as 64-bit variants of movd-s. - -2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> - - * hppa.h: Fix punctuation in comment. - - * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for - implicit space-register addressing. Set space-register bits on opcodes - using implicit space-register addressing. Add various missing pa20 - long-immediate opcodes. Remove various opcodes using implicit 3-bit - space-register addressing. Use "fE" instead of "fe" in various - fstw opcodes. - -2005-07-18 Jan Beulich <jbeulich@novell.com> - - * i386.h (i386_optab): Operands of aam and aad are unsigned. - -2007-07-15 H.J. Lu <hongjiu.lu@intel.com> - - * i386.h (i386_optab): Support Intel VMX Instructions. - -2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> - - * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores. - -2005-07-05 Jan Beulich <jbeulich@novell.com> - - * i386.h (i386_optab): Add new insns. - -2005-07-01 Nick Clifton <nickc@redhat.com> - - * sparc.h: Add typedefs to structure declarations. - -2005-06-20 H.J. Lu <hongjiu.lu@intel.com> - - PR 1013 - * i386.h (i386_optab): Update comments for 64bit addressing on - mov. Allow 64bit addressing for mov and movq. - -2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> - - * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx, - respectively, in various floating-point load and store patterns. - -2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> - - * hppa.h (FLAG_STRICT): Correct comment. - (pa_opcodes): Update load and store entries to allow both PA 1.X and - PA 2.0 mneumonics when equivalent. Entries with cache control - completers now require PA 1.1. Adjust whitespace. - -2005-05-19 Anton Blanchard <anton@samba.org> - - * ppc.h (PPC_OPCODE_POWER5): Define. - -2005-05-10 Nick Clifton <nickc@redhat.com> - - * Update the address and phone number of the FSF organization in - the GPL notices in the following files: - a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h, - crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h, - i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h, - mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h, - pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h, - tic54x.h, tic80.h, v850.h, vax.h - -2005-05-09 Jan Beulich <jbeulich@novell.com> - - * i386.h (i386_optab): Add ht and hnt. - -2005-04-18 Mark Kettenis <kettenis@gnu.org> - - * i386.h: Insert hyphens into selected VIA PadLock extensions. - Add xcrypt-ctr. Provide aliases without hyphens. - -2005-04-13 H.J. Lu <hongjiu.lu@intel.com> - - Moved from ../ChangeLog - - 2005-04-12 Paul Brook <paul@codesourcery.com> - * m88k.h: Rename psr macros to avoid conflicts. - - 2005-03-12 Zack Weinberg <zack@codesourcery.com> - * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T. - Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2, - and ARM_ARCH_V6ZKT2. - - 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com> - * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4. - Remove redundant instruction types. - (struct argument): X_op - new field. - (struct cst4_entry): Remove. - (no_op_insn): Declare. - - 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com> - * crx.h (enum argtype): Rename types, remove unused types. - - 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com> - * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'. - (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE. - (enum operand_type): Rearrange operands, edit comments. - replace us<N> with ui<N> for unsigned immediate. - replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped - displacements (respectively). - replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index. - (instruction type): Add NO_TYPE_INS. - (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR. - (operand_entry): New field - 'flags'. - (operand flags): New. - - 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com> - * crx.h (operand_type): Remove redundant types i3, i4, - i5, i8, i12. - Add new unsigned immediate types us3, us4, us5, us16. - -2005-04-12 Mark Kettenis <kettenis@gnu.org> - - * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and - adjust them accordingly. - -2005-04-01 Jan Beulich <jbeulich@novell.com> - - * i386.h (i386_optab): Add rdtscp. - -2005-03-29 H.J. Lu <hongjiu.lu@intel.com> - - * i386.h (i386_optab): Don't allow the `l' suffix for moving - between memory and segment register. Allow movq for moving between - general-purpose register and segment register. - -2005-02-09 Jan Beulich <jbeulich@novell.com> - - PR gas/707 - * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and - FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and - fnstsw. - -2006-02-07 Nathan Sidwell <nathan@codesourcery.com> - - * m68k.h (m68008, m68ec030, m68882): Remove. - (m68k_mask): New. - (cpu_m68k, cpu_cf): New. - (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407, - mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants. - -2005-01-25 Alexandre Oliva <aoliva@redhat.com> - - 2004-11-10 Alexandre Oliva <aoliva@redhat.com> - * cgen.h (enum cgen_parse_operand_type): Add - CGEN_PARSE_OPERAND_SYMBOLIC. - -2005-01-21 Fred Fish <fnf@specifixinc.com> - - * mips.h: Change INSN_ALIAS to INSN2_ALIAS. - Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC. - Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC. - -2005-01-19 Fred Fish <fnf@specifixinc.com> - - * mips.h (struct mips_opcode): Add new pinfo2 member. - (INSN_ALIAS): New define for opcode table entries that are - specific instances of another entry, such as 'move' for an 'or' - with a zero operand. - (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2. - (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4. - -2004-12-09 Ian Lance Taylor <ian@wasabisystems.com> - - * mips.h (CPU_RM9000): Define. - (OPCODE_IS_MEMBER): Handle CPU_RM9000. - -2004-11-25 Jan Beulich <jbeulich@novell.com> - - * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves - to/from test registers are illegal in 64-bit mode. Add missing - NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix - (previously one had to explicitly encode a rex64 prefix). Re-enable - lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings - support it there. Add cmpxchg16b as per Intel's 64-bit documentation. - -2004-11-23 Jan Beulich <jbeulich@novell.com> - - * i386.h (i386_optab): paddq and psubq, even in their MMX form, are - available only with SSE2. Change the MMX additions introduced by SSE - and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A - instructions by their now designated identifier (since combining i686 - and 3DNow! does not really imply 3DNow!A). - -2004-11-19 Alan Modra <amodra@bigpond.net.au> - - * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes, - struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c. - -2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com> - Vineet Sharma <vineets@noida.hcltech.com> - - * maxq.h: New file: Disassembly information for the maxq port. - -2004-11-05 H.J. Lu <hongjiu.lu@intel.com> - - * i386.h (i386_optab): Put back "movzb". - -2004-11-04 Hans-Peter Nilsson <hp@axis.com> - - * cris.h (enum cris_insn_version_usage): Tweak formatting and - comments. Remove member cris_ver_sim. Add members - cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10, - cris_ver_v8_10, cris_ver_v10, cris_ver_v10p. - (struct cris_support_reg, struct cris_cond15): New types. - (cris_conds15): Declare. - (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON) - (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS) - (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros. - (NOP_Z_BITS): Define in terms of NOP_OPCODE. - (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and - SIZE_FIELD_UNSIGNED. - -2004-11-04 Jan Beulich <jbeulich@novell.com> - - * i386.h (sldx_Suf): Remove. - (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize. - (q_FP): Define, implying no REX64. - (x_FP, sl_FP): Imply FloatMF. - (i386_optab): Split reg and mem forms of moving from segment registers - so that the memory forms can ignore the 16-/32-bit operand size - distinction. Adjust a few others for Intel mode. Remove *FP uses from - all non-floating-point instructions. Unite 32- and 64-bit forms of - movsx, movzx, and movd. Adjust floating point operations for the above - changes to the *FP macros. Add DefaultSize to floating point control - insns operating on larger memory ranges. Remove left over comments - hinting at certain insns being Intel-syntax ones where the ones - actually meant are already gone. - -2004-10-07 Tomer Levi <Tomer.Levi@nsc.com> - - * crx.h: Add COPS_REG_INS - Coprocessor Special register - instruction type. - -2004-09-30 Paul Brook <paul@codesourcery.com> - - * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define. - (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define. - -2004-09-11 Theodore A. Roth <troth@openavr.org> - - * avr.h: Add support for - atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128. - -2004-09-09 Segher Boessenkool <segher@kernel.crashing.org> - - * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment. - -2004-08-24 Dmitry Diky <diwil@spec.ru> - - * msp430.h (msp430_opc): Add new instructions. - (msp430_rcodes): Declare new instructions. - (msp430_hcodes): Likewise.. - -2004-08-13 Nick Clifton <nickc@redhat.com> - - PR/301 - * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX - processors. - -2004-08-30 Michal Ludvig <mludvig@suse.cz> - - * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns. - -2004-07-22 H.J. Lu <hongjiu.lu@intel.com> - - * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints. - -2004-07-21 Jan Beulich <jbeulich@novell.com> - - * i386.h: Adjust instruction descriptions to better match the - specification. - -2004-07-16 Richard Earnshaw <rearnsha@arm.com> - - * arm.h: Remove all old content. Replace with architecture defines - from gas/config/tc-arm.c. - -2004-07-09 Andreas Schwab <schwab@suse.de> - - * m68k.h: Fix comment. - -2004-07-07 Tomer Levi <Tomer.Levi@nsc.com> - - * crx.h: New file. - -2004-06-24 Alan Modra <amodra@bigpond.net.au> - - * i386.h (i386_optab): Remove fildd, fistpd and fisttpd. - -2004-05-24 Peter Barada <peter@the-baradas.com> - - * m68k.h: Add 'size' to m68k_opcode. - -2004-05-05 Peter Barada <peter@the-baradas.com> - - * m68k.h: Switch from ColdFire chip name to core variant. - -2004-04-22 Peter Barada <peter@the-baradas.com> - - * m68k.h: Add mcfmac/mcfemac definitions. Update operand - descriptions for new EMAC cases. - Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly - handle Motorola MAC syntax. - Allow disassembly of ColdFire V4e object files. - -2004-03-16 Alan Modra <amodra@bigpond.net.au> - - * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines. - -2004-03-12 Jakub Jelinek <jakub@redhat.com> - - * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit. - -2004-03-12 Michal Ludvig <mludvig@suse.cz> - - * i386.h (i386_optab): Added xstore as an alias for xstorerng. - -2004-03-12 Michal Ludvig <mludvig@suse.cz> - - * i386.h (i386_optab): Added xstore/xcrypt insns. - -2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com> - - * h8300.h (32bit ldc/stc): Add relaxing support. - -2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com> - - * h8300.h (BITOP): Pass MEMRELAX flag. - -2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com> - - * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32 - except for the H8S. - -For older changes see ChangeLog-9103 - -Copyright (C) 2004-2012 Free Software Foundation, Inc. - -Copying and distribution of this file, with or without modification, -are permitted in any medium without royalty provided the copyright -notice and this notice are preserved. - -Local Variables: -mode: change-log -left-margin: 8 -fill-column: 74 -version-control: never -End: diff --git a/include/opcode/ChangeLog-9103 b/include/opcode/ChangeLog-9103 deleted file mode 100644 index b56e7d5..0000000 --- a/include/opcode/ChangeLog-9103 +++ /dev/null @@ -1,3131 +0,0 @@ -2005-04-13 H.J. Lu <hongjiu.lu@intel.com> - - 2003-11-18 Maciej W. Rozycki <macro@ds2.pg.gda.pl> - * mips.h: Define new enum members, M_LCA_AB and M_DLCA_AB. - - 2003-04-04 Svein E. Seldal <Svein.Seldal@solidas.com> - * tic4x.h: Namespace cleanup. Replace s/c4x/tic4x - - 2002-11-16 Klee Dienes <kdienes@apple.com> - * m88k.h (INSTAB): Remove 'next' field. - (instruction): Remove definition; replace with extern declaration - and mark as const. - - 2002-08-28 Michael Hayes <m.hayes@elec.canterbury.ac.nz> - * tic4x.h: New file. - - 2002-07-25 Richard Sandiford <rsandifo@redhat.com> - * mips.h (CPU_R2000): Remove. - -2003-10-21 Peter Barada <pbarada@mail.wm.sps.mot.com> - Bernardo Innocenti <bernie@develer.com> - - * m68k.h: Add MCFv4/MCF5528x support. - -2003-10-19 Hans-Peter Nilsson <hp@bitrange.com> - - * mmix.h (JMP_INSN_BYTE): Define. - -2003-09-30 Chris Demetriou <cgd@broadcom.com> - - * mips.h: Document +E, +F, +G, +H, and +I operand types. - Update documentation of I, +B and +C operand types. - (INSN_ISA64R2, ISA_MIPS64R2, CPU_MIPS64R2): New defines. - (M_DEXT, M_DINS): New enum values. - -2003-09-04 Nick Clifton <nickc@redhat.com> - - * v850.h (PROCESSOR_V850E1): Define. - -2003-08-19 Alan Modra <amodra@bigpond.net.au> - - * ppc.h (PPC_OPCODE_440): Define. Formatting. Use hex for other - PPC_OPCODE_* defines. - -2003-08-16 Jason Eckhardt <jle@rice.edu> - - * i860.h (fmov.ds): Expand as famov.ds. - (fmov.sd): Expand as famov.sd. - (pfmov.ds): Expand as pfamov.ds. - -2003-08-07 Michael Meissner <gnu@the-meissners.org> - - * cgen.h: Remove PARAM macro usage in all prototypes. - (CGEN_EXTRACT_INFO): Use void * instead of PTR. - (cgen_print_fn): Ditto. - (CGEN_HW_ENTRY): Ditto. - (CGEN_MAYBE_MULTI_IFLD): Ditto. - (struct cgen_insn): Ditto. - (CGEN_CPU_TABLE): Ditto. - -2003-08-07 Alan Modra <amodra@bigpond.net.au> - - * alpha.h: Remove PARAMS macro. - * arc.h: Likewise. - * d10v.h: Likewise. - * d30v.h: Likewise. - * i370.h: Likewise. - * or32.h: Likewise. - * pj.h: Likewise. - * ppc.h: Likewise. - * sparc.h: Likewise. - * tic80.h: Likewise. - * v850.h: Likewise. - -2003-07-18 Michael Snyder <msnyder@redhat.com> - - * include/opcode/h8sx.h (DO_MOVA1, DO_MOVA2): Reformatting. - -2003-07-15 Richard Sandiford <rsandifo@redhat.com> - - * mips.h (CPU_RM7000): New macro. - (OPCODE_IS_MEMBER): Match CPU_RM7000 against 4650 insns. - -2003-07-09 Alexandre Oliva <aoliva@redhat.com> - - 2000-04-01 Alexandre Oliva <aoliva@cygnus.com> - * mn10300.h (AM33_2): Renamed from AM33. - 2000-03-31 Alexandre Oliva <aoliva@cygnus.com> - * mn10300.h (AM332, FMT_D3): Defined. - (MN10300_OPERAND_FSREG, MN10300_OPERAND_FDREG): Likewise. - (MN10300_OPERAND_FPCR): Likewise. - -2003-07-01 Martin Schwidefsky <schwidefsky@de.ibm.com> - - * s390.h (s390_opcode_cpu_val): Add enum for cpu type z990. - -2003-06-25 Richard Sandiford <rsandifo@redhat.com> - - * h8300.h (IMM2_NS, IMM8_NS, IMM16_NS): Remove. - (IMM8U, IMM8U_NS): Define. - (h8_opcodes): Use IMM8U_NS for mov.[wl] #xx:8,@yy. - -2003-06-25 Richard Sandiford <rsandifo@redhat.com> - - * h8300.h (h8_opcodes): Fix the mov.l @(dd:32,ERs),ERd and - mov.l ERs,@(dd:32,ERd) entries. - -2003-06-23 H.J. Lu <hongjiu.lu@intel.com> - - * i386.h (i386_optab): Support Intel Precott New Instructions. - -2003-06-10 Gary Hade <garyhade@us.ibm.com> - - * ppc.h (PPC_OPERAND_DQ): Define. - -2003-06-10 Richard Sandiford <rsandifo@redhat.com> - - * h8300.h (IMM4_NS, IMM8_NS): New. - (h8_opcodes): Replace IMM4 with IMM4_NS in mov.b and mov.w entries. - Likewise IMM8 for mov.w and mov.l. Likewise IMM16U for mov.l. - -2003-06-03 Michael Snyder <msnyder@redhat.com> - - * h8300.h (enum h8_model): Add AV_H8S to distinguish from H8H. - (ldc): Split ccr ops from exr ops (which are only available - on H8S or H8SX). - (stc): Ditto. - (andc, orc, xorc): Ditto. - (ldmac, stmac, clrmac, mac): Change access to AV_H8S. - -2003-06-03 Michael Snyder <msnyder@redhat.com> - and Bernd Schmidt <bernds@redhat.com> - and Alexandre Oliva <aoliva@redhat.com> - * h8300.h: Add support for h8300sx instruction set. - -2003-05-23 Jason Eckhardt <jle@rice.edu> - - * i860.h (expand_type): Add XP_ONLY. - (scyc.b): New XP instruction. - (ldio.l): Likewise. - (ldio.s): Likewise. - (ldio.b): Likewise. - (ldint.l): Likewise. - (ldint.s): Likewise. - (ldint.b): Likewise. - (stio.l): Likewise. - (stio.s): Likewise. - (stio.b): Likewise. - (pfld.q): Likewise. - -2003-05-20 Jason Eckhardt <jle@rice.edu> - - * i860.h (flush): Set lower 3 bits properly and use 'L' - for the immediate operand type instead of 'i'. - -2003-05-20 Jason Eckhardt <jle@rice.edu> - - * i860.h (fzchks): Both S and R bits must be set. - (pfzchks): Likewise. - (faddp): Likewise. - (pfaddp): Likewise. - (fix.ss): Remove (invalid instruction). - (pfix.ss): Likewise. - (ftrunc.ss): Likewise. - (pftrunc.ss): Likewise. - -2003-05-18 Jason Eckhardt <jle@rice.edu> - - * i860.h (form, pform): Add missing .dd suffix. - -2003-05-13 Stephane Carrez <stcarrez@nerim.fr> - - * m68hc11.h (M68HC12_BANK_VIRT): Define to 0x010000 - -2003-04-07 Michael Snyder <msnyder@redhat.com> - - * h8300.h (ldc/stc): Fix up src/dst swaps. - -2003-04-09 J. Grant <jg-binutils@jguk.org> - - * mips.h: Correct comment typo. - -2003-03-21 Martin Schwidefsky <schwidefsky@de.ibm.com> - - * s390.h (s390_opcode_arch_val): Rename to s390_opcode_mode_val. - (S390_OPCODE_ESAME): Rename to S390_OPCODE_ZARCH. - (s390_opcode): Remove architecture. Add modes and min_cpu. - -2003-03-17 D.Venkatasubramanian <dvenkat@noida.hcltech.com> - - * h8300.h (O_SYS_CMDLINE): New pseudo opcode for command line - processing. - -2003-02-21 Noida D.Venkatasubramanian <dvenkat@noida.hcltech.com> - - * h8300.h (ldmac, stmac): Replace MACREG with MS32 and MD32. - -2003-01-23 Alan Modra <amodra@bigpond.net.au> - - * m68hc11.h (cpu6812s): Define. - -2003-01-07 Chris Demetriou <cgd@broadcom.com> - - * mips.h: Fix missing space in comment. - (INSN_ISA1, INSN_ISA2, INSN_ISA3, INSN_ISA4, INSN_ISA5) - (INSN_ISA32, INSN_ISA32R2, INSN_ISA64): Shift values right - by four bits. - -2003-01-02 Chris Demetriou <cgd@broadcom.com> - - * mips.h: Update copyright years to include 2002 (which had - been missed previously) and 2003. Make comments about "+A", - "+B", and "+C" operand types more descriptive. - -2002-12-31 Chris Demetriou <cgd@broadcom.com> - - * mips.h: Note that the "+D" operand type name is now used. - -2002-12-30 Chris Demetriou <cgd@broadcom.com> - - * mips.h: Document "+" as the start of two-character operand - type names, and add new "K", "+A", "+B", and "+C" operand types. - (OP_MASK_INSMSB, OP_SH_INSMSB, OP_MASK_EXTMSB) - (OP_SH_EXTMSB, INSN_ISA32R2, ISA_MIPS32R2, CPU_MIPS32R2): New - defines. - -2002-12-24 Dmitry Diky <diwil@mail.ru> - - * msp430.h: New file. Defines msp430 opcodes. - -2002-12-30 D.Venkatasubramanian <dvenkat@noida.hcltech.com> - - * h8300.h: Added some more pseudo opcodes for system call - processing. - -2002-12-19 Chris Demetriou <cgd@broadcom.com> - - * mips.h (OP_OP_COP0, OP_OP_COP1, OP_OP_COP2, OP_OP_COP3) - (OP_OP_LWC1, OP_OP_LWC2, OP_OP_LWC3, OP_OP_LDC1, OP_OP_LDC2) - (OP_OP_LDC3, OP_OP_SWC1, OP_OP_SWC2, OP_OP_SWC3, OP_OP_SDC1) - (OP_OP_SDC2, OP_OP_SDC3): Define. - -2002-12-16 Alan Modra <amodra@bigpond.net.au> - - * hppa.h (completer_chars): #if 0 out. - - * ns32k.h (struct ns32k_opcode): Constify "name", "operands" and - "default_args". - (struct not_wot): Constify "args". - (struct not): Constify "name". - (numopcodes): Delete. - (endop): Delete. - -2002-12-13 Alan Modra <amodra@bigpond.net.au> - - * pj.h (pj_opc_info_t): Add union. - -2002-12-04 David Mosberger <davidm@hpl.hp.com> - - * ia64.h: Fix copyright message. - (IA64_OPND_AR_CSD): New operand kind. - -2002-12-03 Richard Henderson <rth@redhat.com> - - * ia64.h (enum ia64_opnd): Add IA64_OPND_LDXMOV. - -2002-12-03 Alan Modra <amodra@bigpond.net.au> - - * cgen.h (struct cgen_maybe_multi_ifield): Add "const PTR p" to union. - Constify "leaf" and "multi". - -2002-11-19 Klee Dienes <kdienes@apple.com> - - * h8300.h (h8_opcode): Remove 'noperands', 'idx', and 'size' - fields. - (h8_opcodes). Modify initializer and initializer macros to no - longer initialize the removed fields. - -2002-11-19 Svein E. Seldal <Svein.Seldal@solidas.com> - - * tic4x.h (c4x_insts): Fixed LDHI constraint - -2002-11-18 Klee Dienes <kdienes@apple.com> - - * h8300.h (h8_opcode): Remove 'length' field. - (h8_opcodes): Mark as 'const' (both the declaration and - definition). Modify initializer and initializer macros to no - longer initialize the length field. - -2002-11-18 Klee Dienes <kdienes@apple.com> - - * arc.h (arc_ext_opcodes): Declare as extern. - (arc_ext_operands): Declare as extern. - * i860.h (i860_opcodes): Declare as const. - -2002-11-18 Svein E. Seldal <Svein.Seldal@solidas.com> - - * tic4x.h: File reordering. Added enhanced opcodes. - -2002-11-16 Svein E. Seldal <Svein.Seldal@solidas.com> - - * tic4x.h: Major rewrite of entire file. Define instruction - classes, and put each instruction into a class. - -2002-11-11 Svein E. Seldal <Svein.Seldal@solidas.com> - - * tic4x.h: Added new opcodes and corrected some bugs. Add support - for new DSP types. - -2002-10-14 Alan Modra <amodra@bigpond.net.au> - - * cgen.h: Test __BFD_H_SEEN__ rather than BFD_VERSION_DATE. - -2002-09-30 Gavin Romig-Koch <gavin@redhat.com> - Ken Raeburn <raeburn@cygnus.com> - Aldy Hernandez <aldyh@redhat.com> - Eric Christopher <echristo@redhat.com> - Richard Sandiford <rsandifo@redhat.com> - - * mips.h: Update comment for new opcodes. - (OP_MASK_VECBYTE, OP_SH_VECBYTE): New. - (OP_MASK_VECALIGN, OP_SH_VECALIGN): New. - (INSN_4111, INSN_4120, INSN_5400, INSN_5500): New. - (CPU_VR4120, CPU_VR5400, CPU_VR5500): New. - (OPCODE_IS_MEMBER): Handle the new CPU_* values and INSN_* flags. - Don't match CPU_R4111 with INSN_4100. - -2002-08-19 Elena Zannoni <ezannoni@redhat.com> - - From matthew green <mrg@redhat.com> - - * ppc.h (PPC_OPCODE_SPE): New opcode flag for Powerpc e500 - instructions. - (PPC_OPCODE_ISEL, PPC_OPCODE_BRLOCK, PPC_OPCODE_PMR, - PPC_OPCODE_CACHELCK, PPC_OPCODE_RFMCI): New opcode flags for the - e500x2 Integer select, branch locking, performance monitor, - cache locking and machine check APUs, respectively. - (PPC_OPCODE_EFS): New opcode type for efs* instructions. - (PPC_OPCODE_CLASSIC): New opcode type for Classic PowerPC instructions. - -2002-08-13 Stephane Carrez <stcarrez@nerim.fr> - - * m68hc11.h (M6812_OP_PAGE): Define to identify call operand. - (M68HC12_BANK_VIRT, M68HC12_BANK_MASK, M68HC12_BANK_BASE, - M68HC12_BANK_SHIFT, M68HC12_BANK_PAGE_MASK): Define for 68HC12 - memory banks. - (M6811_OC1M5, M6811_OC1M4, M6811_MODF): Fix value. - -2002-07-09 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de> - - * mips.h (INSN_MIPS16): New define. - -2002-07-08 Alan Modra <amodra@bigpond.net.au> - - * i386.h: Remove IgnoreSize from movsx and movzx. - -2002-06-08 Alan Modra <amodra@bigpond.net.au> - - * a29k.h: Replace CONST with const. - (CONST): Don't define. - * convex.h: Replace CONST with const. - (CONST): Don't define. - * dlx.h: Replace CONST with const. - * or32.h (CONST): Don't define. - -2002-05-30 Chris G. Demetriou <cgd@broadcom.com> - - * mips.h (OP_SH_ALN, OP_MASK_ALN, OP_SH_VSEL, OP_MASK_VSEL) - (MDMX_FMTSEL_IMM_QH, MDMX_FMTSEL_IMM_OB, MDMX_FMTSEL_VEC_QH) - (MDMX_FMTSEL_VEC_OB, INSN_READ_MDMX_ACC, INSN_WRITE_MDMX_ACC) - (INSN_MDMX): New constants, for MDMX support. - (opcode character list): Add "O", "Q", "X", "Y", and "Z" for MDMX. - -2002-05-28 Kuang Hwa Lin <kuang@sbcglobal.net> - - * dlx.h: New file. - -2002-05-25 Alan Modra <amodra@bigpond.net.au> - - * ia64.h: Use #include "" instead of <> for local header files. - * sparc.h: Likewise. - -2002-05-22 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de> - - * mips.h: Add M_DROL, M_DROL_I, M_DROR, M_DROR_I macro cases. - -2002-05-17 Andrey Volkov <avolkov@sources.redhat.com> - - * h8300.h: Corrected defs of all control regs - and eepmov instr. - -2002-04-11 Alan Modra <amodra@bigpond.net.au> - - * i386.h: Add intel mode cmpsd and movsd. - Put them before SSE2 insns, so that rep prefix works. - -2002-03-15 Chris G. Demetriou <cgd@broadcom.com> - - * mips.h (INSN_MIPS3D): New definition used to mark MIPS-3D - instructions. - (OPCODE_IS_MEMBER): Adjust comments to indicate that ASE bit masks - may be passed along with the ISA bitmask. - -2002-03-05 Paul Koning <pkoning@equallogic.com> - - * pdp11.h: Add format codes for float instruction formats. - -2002-02-25 Alan Modra <amodra@bigpond.net.au> - - * ppc.h (PPC_OPCODE_POWER4, PPC_OPCODE_NOPOWER4): Define. - -Mon Feb 18 17:31:48 CET 2002 Jan Hubicka <jh@suse.cz> - - * i386.h (push,pop): Fix Reg64 to WordReg to allow 16bit operands. - -Mon Feb 11 12:53:19 CET 2002 Jan Hubicka <jh@suse.cz> - - * i386.h (push,pop): Allow 16bit operands in 64bit mode. - (xchg): Fix. - (in, out): Disable 64bit operands. - (call, jmp): Avoid REX prefixes. - (jcxz): Prohibit in 64bit mode - (jrcxz, loop): Add 64bit variants. - (movq): Fix patterns. - (movmskps, pextrw, pinstrw): Add 64bit variants. - -2002-01-31 Ivan Guzvinec <ivang@opencores.org> - - * or32.h: New file. - -2002-01-22 Graydon Hoare <graydon@redhat.com> - - * cgen.h (CGEN_MAYBE_MULTI_IFLD): New structure. - (CGEN_OPERAND): Add CGEN_MAYBE_MULTI_IFLD field. - -2002-01-21 Thomas Klausner <wiz@danbala.ifoer.tuwien.ac.at> - - * h8300.h: Comment typo fix. - -2002-01-03 matthew green <mrg@redhat.com> - - * ppc.h (PPC_OPCODE_BOOKE): BookE is not Motorola specific. - (PPC_OPCODE_BOOKE64): Likewise. - -Mon Dec 31 16:45:41 2001 Jeffrey A Law (law@cygnus.com) - - * hppa.h (call, ret): Move to end of table. - (addb, addib): PA2.0 variants should have been PA2.0W. - (ldw, ldh, ldb, stw, sth, stb, stwa): Reorder to keep disassembler - happy. - (fldw, fldd, fstw, fstd, bb): Likewise. - (short loads/stores): Tweak format specifier slightly to keep - disassembler happy. - (indexed loads/stores): Likewise. - (absolute loads/stores): Likewise. - -2001-12-04 Alexandre Oliva <aoliva@redhat.com> - - * d10v.h (OPERAND_NOSP): New macro. - -2001-11-29 Alexandre Oliva <aoliva@redhat.com> - - * d10v.h (OPERAND_SP): New macro. - -2001-11-15 Alan Modra <amodra@bigpond.net.au> - - * ppc.h (struct powerpc_operand <insert, extract>): Add dialect param. - -2001-11-11 Timothy Wall <twall@alum.mit.edu> - - * tic54x.h: Revise opcode layout; don't really need a separate - structure for parallel opcodes. - -2001-11-13 Zack Weinberg <zack@codesourcery.com> - Alan Modra <amodra@bigpond.net.au> - - * i386.h (i386_optab): Add entries for "sldr", "smsw" and "str" to - accept WordReg. - -2001-11-04 Chris Demetriou <cgd@broadcom.com> - - * mips.h (OPCODE_IS_MEMBER): Remove extra space. - -2001-10-30 Hans-Peter Nilsson <hp@bitrange.com> - - * mmix.h: New file. - -2001-10-18 Chris Demetriou <cgd@broadcom.com> - - * mips.h (OPCODE_IS_MEMBER): Add a no-op term to the end - of the expression, to make source code merging easier. - -2001-10-17 Chris Demetriou <cgd@broadcom.com> - - * mips.h: Sort coprocessor instruction argument characters - in comment, add a few more words of description for "H". - -2001-10-17 Chris Demetriou <cgd@broadcom.com> - - * mips.h (INSN_SB1): New cpu-specific instruction bit. - (OPCODE_IS_MEMBER): Allow instructions matching INSN_SB1 - if cpu is CPU_SB1. - -2001-10-17 matthew green <mrg@redhat.com> - - * ppc.h (PPC_OPCODE_BOOKE64): Fix typo. - -2001-10-12 matthew green <mrg@redhat.com> - - * ppc.h (PPC_OPCODE_BOOKE, PPC_OPCODE_BOOKE64, PPC_OPCODE_403): New - opcode flags for BookE 32-bit, BookE 64-bit and PowerPC 403 - instructions, respectively. - -2001-09-27 Nick Clifton <nickc@cambridge.redhat.com> - - * v850.h: Remove spurious comment. - -2001-09-21 Nick Clifton <nickc@cambridge.redhat.com> - - * h8300.h: Fix compile time warning messages - -2001-09-04 Richard Henderson <rth@redhat.com> - - * alpha.h (struct alpha_operand): Pack elements into bitfields. - -2001-08-31 Eric Christopher <echristo@redhat.com> - - * mips.h: Remove CPU_MIPS32_4K. - -2001-08-27 Torbjorn Granlund <tege@swox.com> - - * ppc.h (PPC_OPERAND_DS): Define. - -2001-08-25 Andreas Jaeger <aj@suse.de> - - * d30v.h: Fix declaration of reg_name_cnt. - - * d10v.h: Fix declaration of d10v_reg_name_cnt. - - * arc.h: Add prototypes from opcodes/arc-opc.c. - -2001-08-16 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de> - - * mips.h (INSN_10000): Define. - (OPCODE_IS_MEMBER): Check for INSN_10000. - -2001-08-10 Alan Modra <amodra@one.net.au> - - * ppc.h: Revert 2001-08-08. - -2001-08-10 Richard Sandiford <rsandifo@redhat.com> - - * mips.h (INSN_GP32): Remove. - (OPCODE_IS_MEMBER): Remove gp32 parameter. - (M_MOVE): New macro identifier. - -2001-08-08 Alan Modra <amodra@one.net.au> - - 1999-10-25 Torbjorn Granlund <tege@swox.com> - * ppc.h (struct powerpc_operand): New field `reloc'. - -2001-08-01 Aldy Hernandez <aldyh@redhat.com> - - * mips.h (INSN_ISA_MASK): Nuke bits 12-15. - -2001-07-12 Jeff Johnston <jjohnstn@redhat.com> - - * cgen.h (CGEN_INSN): Add regex support. - (build_insn_regex): Declare. - -2001-07-11 Frank Ch. Eigler <fche@redhat.com> - - * cgen.h (CGEN_MACH): Add insn_chunk_bitsize field. - (cgen_cpu_desc): Ditto. - -2001-07-07 Ben Elliston <bje@redhat.com> - - * m88k.h: Clean up and reformat. Remove unused code. - -2001-06-14 Geoffrey Keating <geoffk@redhat.com> - - * cgen.h (cgen_keyword): Add nonalpha_chars field. - -2001-05-23 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de> - - * mips.h (CPU_R12000): Define. - -2001-05-23 John Healy <jhealy@redhat.com> - - * cgen.h: Increased CGEN_MAX_SYNTAX_ELEMENTS to 48. - -2001-05-15 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de> - - * mips.h (INSN_ISA_MASK): Define. - -2001-05-12 Alan Modra <amodra@one.net.au> - - * i386.h (i386_optab): Second operand of cvtps2dq is an xmm reg, - not an mmx reg. Swap xmm/mmx regs on both movdq2q and movq2dq, - and use InvMem as these insns must have register operands. - -2001-05-04 Alan Modra <amodra@one.net.au> - - * i386.h (i386_optab): Move InvMem to first operand of pmovmskb - and pextrw to swap reg/rm assignments. - -2001-04-05 Hans-Peter Nilsson <hp@axis.com> - - * cris.h (enum cris_insn_version_usage): Correct comment for - cris_ver_v3p. - -2001-03-24 Alan Modra <alan@linuxcare.com.au> - - * i386.h (i386_optab): Correct entry for "movntdq". Add "punpcklqdq". - Add InvMem to first operand of "maskmovdqu". - -2001-03-22 Hans-Peter Nilsson <hp@axis.com> - - * cris.h (ADD_PC_INCR_OPCODE): New macro. - -2001-03-21 Kazu Hirata <kazu@hxi.com> - - * h8300.h: Fix formatting. - -2001-03-22 Alan Modra <alan@linuxcare.com.au> - - * i386.h (i386_optab): Add paddq, psubq. - -2001-03-19 Alan Modra <alan@linuxcare.com.au> - - * i386.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Define. - -2001-02-28 Igor Shevlyakov <igor@windriver.com> - - * m68k.h: new defines for Coldfire V4. Update mcf to know - about mcf5407. - -2001-02-18 lars brinkhoff <lars@nocrew.org> - - * pdp11.h: New file. - -2001-02-12 Jan Hubicka <jh@suse.cz> - - * i386.h (i386_optab): SSE integer converison instructions have - 64bit versions on x86-64. - -2001-02-10 Nick Clifton <nickc@redhat.com> - - * mips.h: Remove extraneous whitespace. Formating change to allow - for future contribution. - -2001-02-09 Martin Schwidefsky <schwidefsky@de.ibm.com> - - * s390.h: New file. - -2001-02-02 Patrick Macdonald <patrickm@redhat.com> - - * cgen.h (CGEN_SYNTAX_CHAR_TYPE): Typedef as unsigned short. - (CGEN_MAX_SYNTAX_ELEMENTS): Rename from CGEN_MAX_SYNTAX_BYTES. - (CGEN_SYNTAX): Define using CGEN_MAX_SYNTAX_ELEMENTS. - -2001-01-24 Karsten Keil <kkeil@suse.de> - - * i386.h (i386_optab): Fix swapgs - -2001-01-14 Alan Modra <alan@linuxcare.com.au> - - * hppa.h: Describe new '<' and '>' operand types, and tidy - existing comments. - (pa_opcodes): Add entries for missing wide mode ldi,ldo,ldw,stw. - Remove duplicate "ldw j(s,b),x". Sort some entries. - -2001-01-13 Jan Hubicka <jh@suse.cz> - - * i386.h (i386_optab): Fix pusha and ret templates. - -2001-01-11 Peter Targett <peter.targett@arccores.com> - - * arc.h (ARC_MACH_5, ARC_MACH_6, ARC_MACH_7, ARC_MACH_8): New - definitions for masking cpu type. - (arc_ext_operand_value) New structure for storing extended - operands. - (ARC_OPERAND_*) Flags for operand values. - -2001-01-10 Jan Hubicka <jh@suse.cz> - - * i386.h (pinsrw): Add. - (pshufw): Remove. - (cvttpd2dq): Fix operands. - (cvttps2dq): Likewise. - (movq2q): Rename to movdq2q. - -2001-01-10 Richard Schaal <richard.schaal@intel.com> - - * i386.h: Correct movnti instruction. - -2001-01-09 Jeff Johnston <jjohnstn@redhat.com> - - * cgen.h (CGEN_SYNTAX_CHAR_TYPE): New typedef based on max number - of operands (unsigned char or unsigned short). - (CGEN_SYNTAX): Changed to make array CGEN_SYNTAX_CHAR_TYPE. - (CGEN_SYNTAX_CHAR): Changed to cast to unsigned char. - -2001-01-05 Jan Hubicka <jh@suse.cz> - - * i386.h (i386_optab): Make [sml]fence template to use immext field. - -2001-01-03 Jan Hubicka <jh@suse.cz> - - * i386.h (i386_optab): Fix 64bit pushf template; Add instructions - introduced by Pentium4 - -2000-12-30 Jan Hubicka <jh@suse.cz> - - * i386.h (i386_optab): Add "rex*" instructions; - add swapgs; disable jmp/call far direct instructions for - 64bit mode; add syscall and sysret; disable registers for 0xc6 - template. Add 'q' suffixes to extendable instructions, disable - obsolete instructions, add new sign/zero extension ones. - (i386_regtab): Add extended registers. - (*Suf): Add No_qSuf. - (q_Suf, wlq_Suf, bwlq_Suf): New. - -2000-12-20 Jan Hubicka <jh@suse.cz> - - * i386.h (i386_optab): Replace "Imm" with "EncImm". - (i386_regtab): Add flags field. - -2000-12-12 Nick Clifton <nickc@redhat.com> - - * mips.h: Fix formatting. - -2000-12-01 Chris Demetriou <cgd@sibyte.com> - - mips.h (OP_MASK_SYSCALL, OP_SH_SYSCALL): Delete. - (OP_MASK_CODE20, OP_SH_CODE20): Define, with values of old - OP_*_SYSCALL definitions. - (OP_SH_CODE19, OP_MASK_CODE19): Define, for use as - 19 bit wait codes. - (MIPS operand specifier comments): Remove 'm', add 'U' and - 'J', and update the meaning of 'B' so that it's more general. - - * mips.h (INSN_ISA1, INSN_ISA2, INSN_ISA3, INSN_ISA4, - INSN_ISA5): Renumber, redefine to mean the ISA at which the - instruction was added. - (INSN_ISA32): New constant. - (INSN_4650, INSN_4010, INSN_4100, INSN_3900, INSN_GP32): - Renumber to avoid new and/or renumbered INSN_* constants. - (INSN_MIPS32): Delete. - (ISA_UNKNOWN): New constant to indicate unknown ISA. - (ISA_MIPS1, ISA_MIPS2, ISA_MIPS3, ISA_MIPS4, ISA_MIPS5, - ISA_MIPS32): New constants, defined to be the mask of INSN_* - constants available at that ISA level. - (CPU_UNKNOWN): New constant to indicate unknown CPU. - (CPU_4K, CPU_MIPS32_4K): Rename the former to the latter, - define it with a unique value. - (OPCODE_IS_MEMBER): Update for new ISA membership-related - constant meanings. - - * mips.h (INSN_ISA64, ISA_MIPS5, ISA_MIPS64): New - definitions. - - * mips.h (CPU_SB1): New constant. - -2000-10-20 Jakub Jelinek <jakub@redhat.com> - - * sparc.h (enum sparc_opcode_arch_val): Add SPARC_OPCODE_ARCH_V9B. - Note that '3' is used for siam operand. - -2000-09-22 Jim Wilson <wilson@cygnus.com> - - * ia64.h (enum ia64_dependency_semantics): Add IA64_DVS_STOP. - -2000-09-13 Anders Norlander <anorland@acc.umu.se> - - * mips.h: Use defines instead of hard-coded processor numbers. - (CPU_R2000, CPU_R3000, CPU_R3900, CPU_R4000, CPU_R4010, - CPU_VR4100, CPU_R4111, CPU_R4300, CPU_R4400, CPU_R4600, CPU_R4650, - CPU_R5000, CPU_R6000, CPU_R8000, CPU_R10000, CPU_MIPS32, CPU_4K, - CPU_4KC, CPU_4KM, CPU_4KP): Define.. - (OPCODE_IS_MEMBER): Use new defines. - (OP_MASK_SEL, OP_SH_SEL): Define. - (OP_MASK_CODE20, OP_SH_CODE20): Define. - Add 'P' to used characters. - Use 'H' for coprocessor select field. - Use 'm' for 20 bit breakpoint code. - Document new arg characters and add to used characters. - (INSN_MIPS32): New define for MIPS32 extensions. - (OPCODE_IS_MEMBER): Recognize MIPS32 instructions. - -2000-09-05 Alan Modra <alan@linuxcare.com.au> - - * hppa.h: Mention cz completer. - -2000-08-16 Jim Wilson <wilson@cygnus.com> - - * ia64.h (IA64_OPCODE_POSTINC): New. - -2000-08-15 H.J. Lu <hjl@gnu.org> - - * i386.h: Swap the Intel syntax "movsx"/"movzx" due to the - IgnoreSize change. - -2000-08-08 Jason Eckhardt <jle@cygnus.com> - - * i860.h: Small formatting adjustments. - -2000-07-29 Marek Michalkiewicz <marekm@linux.org.pl> - - * avr.h (AVR_UNDEF_P, AVR_SKIP_P, AVR_DISP0_P): New macros. - Move related opcodes closer to each other. - Minor changes in comments, list undefined opcodes. - -2000-07-26 Dave Brolley <brolley@redhat.com> - - * cgen.h (cgen_hw_lookup_by_num): Second parameter is unsigned. - -2000-07-22 Jason Eckhardt <jle@cygnus.com> - - * i860.h (btne, bte, bla): Changed these opcodes - to use sbroff ('r') instead of split16 ('s'). - (J, K, L, M): New operand types for 16-bit aligned fields. - (ld.x, {p}fld.x, fst.x, pst.d): Changed these opcodes to - use I, J, K, L, M instead of just I. - (T, U): New operand types for split 16-bit aligned fields. - (st.x): Changed these opcodes to use S, T, U instead of just S. - (andh, andnoth, orh, xorh): Deleted 3-register forms as they do not - exist on the i860. - (pfgt.sd, pfle.sd): Deleted these as they do not exist on the i860. - (pfeq.ss, pfeq.dd): New opcodes. - (st.s): Fixed incorrect mask bits. - (fmlow): Fixed incorrect mask bits. - (fzchkl, pfzchkl): Fixed incorrect mask bits. - (faddz, pfaddz): Fixed incorrect mask bits. - (form, pform): Fixed incorrect mask bits. - (pfld.l): Fixed incorrect mask bits. - (fst.q): Fixed incorrect mask bits. - (all floating point opcodes): Fixed incorrect mask bits for - handling of dual bit. - -2000-07-20 Hans-Peter Nilsson <hp@axis.com> - - cris.h: New file. - -2000-06-26 Marek Michalkiewicz <marekm@linux.org.pl> - - * avr.h (AVR_ISA_WRAP): Remove, now assumed if not AVR_ISA_MEGA. - (AVR_ISA_ESPM): Remove, because ESPM removed in databook update. - (AVR_ISA_85xx): Remove, all uses changed back to AVR_ISA_2xxx. - (AVR_ISA_M83): Define for ATmega83, ATmega85. - (espm): Remove, because ESPM removed in databook update. - (eicall, eijmp): Move to the end of opcode table. - -2000-06-18 Stephane Carrez <stcarrez@worldnet.fr> - - * m68hc11.h: New file for support of Motorola 68hc11. - -Fri Jun 9 21:51:50 2000 Denis Chertykov <denisc@overta.ru> - - * avr.h: clr,lsl,rol, ... moved after add,adc, ... - -Wed Jun 7 21:39:54 2000 Denis Chertykov <denisc@overta.ru> - - * avr.h: New file with AVR opcodes. - -Wed Apr 12 17:11:20 2000 Donald Lindsay <dlindsay@hound.cygnus.com> - - * d10v.h: added ALONE attribute for d10v_opcode.exec_type. - -2000-05-23 Maciej W. Rozycki <macro@ds2.pg.gda.pl> - - * i386.h: Allow d suffix on iret, and add DefaultSize modifier. - -2000-05-17 Maciej W. Rozycki <macro@ds2.pg.gda.pl> - - * i386.h: Use sl_FP, not sl_Suf for fild. - -2000-05-16 Frank Ch. Eigler <fche@redhat.com> - - * cgen.h (CGEN_MAX_SYNTAX_BYTES): Increase to 32. Check that - it exceeds CGEN_ACTUAL_MAX_SYNTAX_BYTES, if set. - (CGEN_MAX_IFMT_OPERANDS): Increase to 16. Check that it exceeds - CGEN_ACTUAL_MAX_IFMT_OPERANDS, if set. - -2000-05-13 Alan Modra <alan@linuxcare.com.au>, - - * i386.h (i386_optab): Cpu686 for sysenter,sysexit,fxsave,fxrestore. - -2000-05-13 Alan Modra <alan@linuxcare.com.au>, - Alexander Sokolov <robocop@netlink.ru> - - * i386.h (i386_optab): Add cpu_flags for all instructions. - -2000-05-13 Alan Modra <alan@linuxcare.com.au> - - From Gavin Romig-Koch <gavin@cygnus.com> - * i386.h (wld_Suf): Define. Use on pushf, popf, pusha, popa. - -2000-05-04 Timothy Wall <twall@cygnus.com> - - * tic54x.h: New. - -2000-05-03 J.T. Conklin <jtc@redback.com> - - * ppc.h (PPC_OPCODE_ALTIVEC): New opcode flag for vector unit. - (PPC_OPERAND_VR): New operand flag for vector registers. - -2000-05-01 Kazu Hirata <kazu@hxi.com> - - * h8300.h (EOP): Add missing initializer. - -Fri Apr 21 15:03:37 2000 Jason Eckhardt <jle@cygnus.com> - - * hppa.h (pa_opcodes): New opcodes for PA2.0 wide mode - forms of ld/st{b,h,w,d} and fld/fst{w,d} (16-bit displacements). - New operand types l,y,&,fe,fE,fx added to support above forms. - (pa_opcodes): Replaced usage of 'x' as source/target for - floating point double-word loads/stores with 'fx'. - -Fri Apr 21 13:20:53 2000 Richard Henderson <rth@cygnus.com> - David Mosberger <davidm@hpl.hp.com> - Timothy Wall <twall@cygnus.com> - Jim Wilson <wilson@cygnus.com> - - * ia64.h: New file. - -2000-03-27 Nick Clifton <nickc@cygnus.com> - - * d30v.h (SHORT_A1): Fix value. - (SHORT_AR): Renumber so that it is at the end of the list of short - instructions, not the end of the list of long instructions. - -2000-03-26 Alan Modra <alan@linuxcare.com> - - * i386.h: (UNIXWARE_COMPAT): Rename to SYSV386_COMPAT as the - problem isn't really specific to Unixware. - (OLDGCC_COMPAT): Define. - (i386_optab): If !OLDGCC_COMPAT, don't handle fsubp etc. with - destination %st(0). - Fix lots of comments. - -2000-03-02 J"orn Rennecke <amylaar@cygnus.co.uk> - - * d30v.h: - (SHORT_B2r, SHORT_B3, SHORT_B3r, SHORT_B3b, SHORT_B3br): Updated. - (SHORT_D1r, SHORT_D2, SHORT_D2r, SHORT_D2Br, SHORT_U): Updated. - (SHORT_F, SHORT_AF, SHORT_T, SHORT_A5, SHORT_CMP, SHORT_CMPU): Updated. - (SHORT_A1, SHORT_AA, SHORT_RA, SHORT_MODINC, SHORT_MODDEC): Updated. - (SHORT_C1, SHORT_C2, SHORT_UF, SHORT_A2, SHORT_NONE, LONG): Updated. - (LONG_U, LONG_Ur, LONG_CMP, LONG_M, LONG_M2, LONG_2, LONG_2r): Updated. - (LONG_2b, LONG_2br, LONG_D, LONG_Dr, LONG_Dbr): Updated. - -2000-02-25 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386.h (fild, fistp): Change intel d_Suf form to fildd and - fistpd without suffix. - -2000-02-24 Nick Clifton <nickc@cygnus.com> - - * cgen.h (cgen_cpu_desc): Rename field 'flags' to - 'signed_overflow_ok_p'. - Delete prototypes for cgen_set_flags() and cgen_get_flags(). - -2000-02-24 Andrew Haley <aph@cygnus.com> - - * cgen.h (CGEN_INSN_MACH_HAS_P): New macro. - (CGEN_CPU_TABLE): flags: new field. - Add prototypes for new functions. - -2000-02-24 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386.h: Add some more UNIXWARE_COMPAT comments. - -2000-02-23 Linas Vepstas <linas@linas.org> - - * i370.h: New file. - -2000-02-22 Chandra Chavva <cchavva@cygnus.com> - - * d30v.h (FLAG_NOT_WITH_ADDSUBppp): Redefined as operation - cannot be combined in parallel with ADD/SUBppp. - -2000-02-22 Andrew Haley <aph@cygnus.com> - - * mips.h: (OPCODE_IS_MEMBER): Add comment. - -1999-12-30 Andrew Haley <aph@cygnus.com> - - * mips.h (OPCODE_IS_MEMBER): Add gp32 arg, which determines - whether synthetic opcodes (e.g. move) generate 32-bit or 64-bit - insns. - -2000-01-15 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386.h: Qualify intel mode far call and jmp with x_Suf. - -1999-12-27 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386.h: Add JumpAbsolute qualifier to all non-intel mode - indirect jumps and calls. Add FF/3 call for intel mode. - -Wed Dec 1 03:05:25 1999 Jeffrey A Law (law@cygnus.com) - - * mn10300.h: Add new operand types. Add new instruction formats. - -Wed Nov 24 20:28:58 1999 Jeffrey A Law (law@cygnus.com) - - * hppa.h (pa_opcodes): Correctly handle immediate for PA2.0 "bb" - instruction. - -1999-11-18 Gavin Romig-Koch <gavin@cygnus.com> - - * mips.h (INSN_ISA5): New. - -1999-11-01 Gavin Romig-Koch <gavin@cygnus.com> - - * mips.h (OPCODE_IS_MEMBER): New. - -1999-10-29 Nick Clifton <nickc@cygnus.com> - - * d30v.h (SHORT_AR): Define. - -1999-10-18 Michael Meissner <meissner@cygnus.com> - - * alpha.h (alpha_num_opcodes): Convert to unsigned. - (alpha_num_operands): Ditto. - -Sun Oct 10 01:46:56 1999 Jerry Quinn <jerry.quinn.adv91@alum.dartmouth.org> - - * hppa.h (pa_opcodes): Add load and store cache control to - instructions. Add ordered access load and store. - - * hppa.h (pa_opcode): Add new entries for addb and addib. - - * hppa.h (pa_opcodes): Fix cmpb and cmpib entries. - - * hppa.h (pa_opcodes): Add entries for cmpb and cmpib. - -Thu Oct 7 00:12:25 MDT 1999 Diego Novillo <dnovillo@cygnus.com> - - * d10v.h: Add flag RESTRICTED_NUM3 for imm3 operands. - -Thu Sep 23 07:08:38 1999 Jerry Quinn <jquinn@nortelnetworks.com> - - * hppa.h (pa_opcodes): Add "call" and "ret". Clean up "b", "bve" - and "be" using completer prefixes. - - * hppa.h (pa_opcodes): Add initializers to silence compiler. - - * hppa.h: Update comments about character usage. - -Mon Sep 20 03:55:31 1999 Jeffrey A Law (law@cygnus.com) - - * hppa.h (pa_opcodes): Fix minor thinkos introduced while cleaning - up the new fstw & bve instructions. - -Sun Sep 19 10:40:59 1999 Jeffrey A Law (law@cygnus.com) - - * hppa.h (pa_opcodes): Add remaining PA2.0 integer load/store - instructions. - - * hppa.h (pa_opcodes): Add remaining PA2.0 FP load/store instructions. - - * hppa.h (pa_opcodes): Add long offset double word load/store - instructions. - - * hppa.h (pa_opcodes): Add FLAG_STRICT variants of FP loads and - stores. - - * hppa.h (pa_opcodes): Handle PA2.0 fcnv, fcmp and ftest insns. - - * hppa.h (pa_opcodes): Finish support for PA2.0 "b" instructions. - - * hppa.h (pa_opcodes): Handle PA2.0 "bve" instructions. - - * hppa.h (pa_opcodes): Add new syntax "be" instructions. - - * hppa.h (pa_opcodes): Note use of 'M' and 'L'. - - * hppa.h (pa_opcodes): Add support for "b,l". - - * hppa.h (pa_opcodes): Add support for "b,gate". - -Sat Sep 18 11:41:16 1999 Jeffrey A Law (law@cygnus.com) - - * hppa.h (pa_opcodes): Use 'fX' for first register operand - in xmpyu. - - * hppa.h (pa_opcodes): Fix mask for probe and probei. - - * hppa.h (pa_opcodes): Fix mask for depwi. - -Tue Sep 7 13:44:25 1999 Jeffrey A Law (law@cygnus.com) - - * hppa.h (pa_opcodes): Add "addil" variant which has the %r1 as - an explicit output argument. - -Mon Sep 6 04:41:42 1999 Jeffrey A Law (law@cygnus.com) - - * hppa.h: Add strict variants of PA1.0/PA1.1 loads and stores. - Add a few PA2.0 loads and store variants. - -1999-09-04 Steve Chamberlain <sac@pobox.com> - - * pj.h: New file. - -1999-08-29 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386.h (i386_regtab): Move %st to top of table, and split off - other fp reg entries. - (i386_float_regtab): To here. - -Sat Aug 28 00:25:25 1999 Jerry Quinn <jquinn@nortelnetworks.com> - - * hppa.h (pa_opcodes): Replace 'f' by 'v'. Prefix float register args - by 'f'. - - * hppa.h (pa_opcodes): Add extrd, extrw, depd, depdi, depw, depwi. - Add supporting args. - - * hppa.h: Document new completers and args. - * hppa.h (pa_opcodes): Add 64 bit patterns and pa2.0 syntax for uxor, - uaddcm, dcor, addi, add, sub, subi, shladd, rfi, and probe. Add pa2.0 - extensions for ssm, rsm, pdtlb, pitlb. Add performance instructions - pmenb and pmdis. - - * hppa.h (pa_opcodes): Add pa2.0 instructions hadd, hshl, - hshr, hsub, mixh, mixw, permh. - - * hppa.h (pa_opcodes): Change completers in instructions to - use 'c' prefix. - - * hppa.h (pa_opcodes): Add popbts, new forms of bb, havg, - hshladd, hshradd, shrpd, and shrpw instructions. Update arg comments. - - * hppa.h (pa_opcodes): Change fmpyfadd, fmpynfadd, fneg, - fnegabs to use 'I' instead of 'F'. - -1999-08-21 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386.h: Add AMD athlon instructions, pfnacc, pfpnacc, pswapd. - Document pf2iw and pi2fw as athlon insns. Remove pswapw. - Alphabetically sort PIII insns. - -Wed Aug 18 18:14:40 1999 Doug Evans <devans@canuck.cygnus.com> - - * cgen.h (CGEN_INSN_MACH_HAS_P): New macro. - -Fri Aug 6 09:46:35 1999 Jerry Quinn <jquinn@nortelnetworks.com> - - * hppa.h (pa_opcodes): Add 64 bit versions of or, xor, and, - and andcm. Add 32 and 64 bit version of cmpclr, cmpiclr. - - * hppa.h: Document 64 bit condition completers. - -Thu Aug 5 16:56:07 1999 Jerry Quinn <jquinn@nortelnetworks.com> - - * hppa.h (pa_opcodes): Change condition args to use '?' prefix. - -1999-08-04 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386.h (i386_optab): Add DefaultSize modifier to all insns - that implicitly modify %esp. #undef d_Suf, x_suf, sld_suf, - sldx_suf, bwld_Suf, d_FP, x_FP, sld_FP, sldx_FP at end of table. - -Wed Jul 28 02:04:24 1999 Jerry Quinn <jquinn@nortelnetworks.com> - Jeff Law <law@cygnus.com> - - * hppa.h (pa_opcodes): Add "pushnom" and "pushbts". - - * hppa.h (pa_opcodes): Mark all PA2.0 opcodes with FLAG_STRICT. - - * hppa.h (pa_opcodes): Change xmpyu, fmpyfadd, - and fmpynfadd to use 'J' and 'K' instead of 'E' and 'X'. - -1999-07-13 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386.h: Add "undocumented" AMD 3DNow! pf2iw, pi2fw, pswapw insns. - -Thu Jul 1 00:17:24 1999 Jeffrey A Law (law@cygnus.com) - - * hppa.h (struct pa_opcode): Add new field "flags". - (FLAGS_STRICT): Define. - -Fri Jun 25 04:22:04 1999 Jerry Quinn <jquinn@nortelnetworks.com> - Jeff Law <law@cygnus.com> - - * hppa.h (pa_opcodes): Add pa2.0 clrbts instruction. - - * hppa.h (pa_opcodes): Add entries for mfia and mtsarcm instructions. - -1999-06-23 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386.h: Allow `l' suffix on bswap. Allow `w' suffix on arpl, - lldt, lmsw, ltr, str, verr, verw. Add FP flag to fcmov*. Add FP - flag to fcomi and friends. - -Fri May 28 15:26:11 1999 Jeffrey A Law (law@cygnus.com) - - * hppa.h (pa_opcodes): Move integer arithmetic instructions after - integer logical instructions. - -1999-05-28 Linus Nordberg <linus.nordberg@canit.se> - - * m68k.h: Document new formats `E', `G', `H' and new places `N', - `n', `o'. - - * m68k.h: Define mcf5206e, mcf5307, mcf. Document new format `u' - and new places `m', `M', `h'. - -Thu May 27 04:13:54 1999 Joel Sherrill (joel@OARcorp.com - - * hppa.h (pa_opcodes): Add several processor specific system - instructions. - -Wed May 26 16:57:44 1999 Jeffrey A Law (law@cygnus.com) - - * hppa.h (pa_opcodes): Add second entry for "comb", "comib", - "addb", and "addib" to be used by the disassembler. - -1999-05-12 Alan Modra <alan@apri.levels.unisa.edu.au> - - * i386.h (ReverseModrm): Remove all occurences. - (InvMem): Add to control/debug/test mov insns, movhlps, movlhps, - movmskps, pextrw, pmovmskb, maskmovq. - Change NoSuf to FP on all MMX, XMM and AMD insns as these all - ignore the data size prefix. - - * i386.h (i386_optab, i386_regtab): Add support for PIII SIMD. - Mostly stolen from Doug Ledford <dledford@redhat.com> - -Sat May 8 23:27:35 1999 Richard Henderson <rth@cygnus.com> - - * ppc.h (PPC_OPCODE_64_BRIDGE): New. - -1999-04-14 Doug Evans <devans@casey.cygnus.com> - - * cgen.h (CGEN_ATTR): Delete member num_nonbools. - (CGEN_ATTR_TYPE): Update. - (CGEN_ATTR_MASK): Number booleans starting at 0. - (CGEN_ATTR_VALUE): Update. - (CGEN_INSN_ATTR): Update. - -Mon Apr 12 23:43:27 1999 Jeffrey A Law (law@cygnus.com) - - * hppa.h (fmpyfadd, fmpynfadd, fneg, fnegabs): New PA2.0 - instructions. - -Tue Mar 23 11:24:38 1999 Jeffrey A Law (law@cygnus.com) - - * hppa.h (bb, bvb): Tweak opcode/mask. - - -1999-03-22 Doug Evans <devans@casey.cygnus.com> - - * cgen.h (CGEN_ISA,CGEN_MACH): New typedefs. - (struct cgen_cpu_desc): Rename member mach to machs. New member isas. - New members word_bitsize,default_insn_bitsize,base_insn-bitsize, - min_insn_bitsize,max_insn_bitsize,isa_table,mach_table,rebuild_tables. - Delete member max_insn_size. - (enum cgen_cpu_open_arg): New enum. - (cpu_open): Update prototype. - (cpu_open_1): Declare. - (cgen_set_cpu): Delete. - -1999-03-11 Doug Evans <devans@casey.cygnus.com> - - * cgen.h (CGEN_HW_TABLE): Delete `num_init_entries' member. - (CGEN_OPERAND_NIL): New macro. - (CGEN_OPERAND): New member `type'. - (@arch@_cgen_operand_table): Delete decl. - (CGEN_OPERAND_INDEX,CGEN_OPERAND_TYPE,CGEN_OPERAND_ENTRY): Delete. - (CGEN_OPERAND_TABLE): New struct. - (cgen_operand_lookup_by_name,cgen_operand_lookup_by_num): Declare. - (CGEN_OPINST): Pointer to operand table entry replaced with enum. - (CGEN_CPU_TABLE): New member `isa'. Change member `operand_table', - now a CGEN_OPERAND_TABLE. Add CGEN_CPU_DESC arg to - {get,set}_{int,vma}_operand. - (@arch@_cgen_cpu_open): New arg `isa'. - (cgen_set_cpu): Ditto. - -Fri Feb 26 02:36:45 1999 Richard Henderson <rth@cygnus.com> - - * i386.h: Fill in cmov and fcmov alternates. Add fcomi short forms. - -1999-02-25 Doug Evans <devans@casey.cygnus.com> - - * cgen.h (enum cgen_asm_type): Add CGEN_ASM_NONE. - (CGEN_HW_ENTRY): Delete member `next'. Change type of `type' to - enum cgen_hw_type. - (CGEN_HW_TABLE): New struct. - (hw_table): Delete declaration. - (CGEN_OPERAND): Change member hw to hw_type, change type from pointer - to table entry to enum. - (CGEN_OPINST): Ditto. - (CGEN_CPU_TABLE): Change member hw_list to hw_table. - -Sat Feb 13 14:13:44 1999 Richard Henderson <rth@cygnus.com> - - * alpha.h (AXP_OPCODE_EV6): New. - (AXP_OPCODE_NOPAL): Include it. - -1999-02-09 Doug Evans <devans@casey.cygnus.com> - - * cgen.h (CGEN_CPU_DESC): Renamed from CGEN_OPCODE_DESC. - All uses updated. New members int_insn_p, max_insn_size, - parse_operand,insert_operand,extract_operand,print_operand, - sizeof_fields,set_fields_bitsize,get_int_operand,set_int_operand, - get_vma_operand,set_vma_operand,parse_handlers,insert_handlers, - extract_handlers,print_handlers. - (CGEN_ATTR): Change type of num_nonbools to unsigned int. - (CGEN_ATTR_BOOL_OFFSET): New macro. - (CGEN_ATTR_MASK): Subtract it to compute bit number. - (CGEN_ATTR_VALUE): Redo bool/nonbool attr calculation. - (cgen_opcode_handler): Renamed from cgen_base. - (CGEN_HW_ATTR_VALUE): Renamed from CGEN_HW_ATTR, all uses updated. - (CGEN_OPERAND_ATTR_VALUE): Renamed from CGEN_OPERAND_ATTR, - all uses updated. - (CGEN_OPERAND_INDEX): Rewrite to use table entry, not global. - (enum cgen_opinst_type): Renamed from cgen_operand_instance_type. - (CGEN_IFLD_ATTR_VALUE): Renamed from CGEN_IFLD_ATTR, all uses updated. - (CGEN_OPCODE,CGEN_IBASE): New types. - (CGEN_INSN): Rewrite. - (CGEN_{ASM,DIS}_HASH*): Delete. - (init_opcode_table,init_ibld_table): Declare. - (CGEN_INSN_ATTR): New type. - -Mon Feb 1 21:09:14 1999 Catherine Moore <clm@cygnus.com> - - * i386.h (d_Suf, x_Suf, sld_Suf, sldx_Suf, bwld_Suf): Define. - (x_FP, d_FP, dls_FP, sldx_FP): Define. - Change *Suf definitions to include x and d suffixes. - (movsx): Use w_Suf and b_Suf. - (movzx): Likewise. - (movs): Use bwld_Suf. - (fld): Change ordering. Use sld_FP. - (fild): Add Intel Syntax equivalent of fildq. - (fst): Use sld_FP. - (fist): Use sld_FP. - (fstp): Use sld_FP. Add x_FP version. - (fistp): LLongMem version for Intel Syntax. - (fcom, fcomp): Use sld_FP. - (fadd, fiadd, fsub): Use sld_FP. - (fsubr): Use sld_FP. - (fmul, fimul, fdvi, fidiv, fdivr): Use sld_FP. - -1999-01-27 Doug Evans <devans@casey.cygnus.com> - - * cgen.h (enum cgen_mode): Add CGEN_MODE_TARGET_MAX, CGEN_MODE_INT, - CGEN_MODE_UINT. - -1999-01-16 Jeffrey A Law (law@cygnus.com) - - * hppa.h (bv): Fix mask. - -1999-01-05 Doug Evans <devans@casey.cygnus.com> - - * cgen.h (CGEN_ATTR_VALUE_TYPE): New typedef. - (CGEN_ATTR): Use it. - (CGEN_ATTR_TYPE,CGEN_ATTR_ENTRY): Ditto. - (CGEN_ATTR_TABLE): New member dfault. - -1998-12-30 Gavin Romig-Koch <gavin@cygnus.com> - - * mips.h (MIPS16_INSN_BRANCH): New. - -Wed Dec 9 10:38:48 1998 David Taylor <taylor@texas.cygnus.com> - - The following is part of a change made by Edith Epstein - <eepstein@sophia.cygnus.com> as part of a project to merge in - changes by HP; HP did not create ChangeLog entries. - - * hppa.h (completer_chars): list of chars to not put a space - after. - -Sun Dec 6 13:21:34 1998 Ian Lance Taylor <ian@cygnus.com> - - * i386.h (i386_optab): Permit w suffix on processor control and - status word instructions. - -1998-11-30 Doug Evans <devans@casey.cygnus.com> - - * cgen.h (struct cgen_hw_entry): Delete const on attrs member. - (struct cgen_keyword_entry): Ditto. - (struct cgen_operand): Ditto. - (CGEN_IFLD): New typedef, with associated access macros. - (CGEN_IFMT): New typedef, with associated access macros. - (CGEN_IFMT): Renamed from CGEN_FORMAT. New member `iflds'. - (CGEN_IVALUE): New typedef. - (struct cgen_insn): Delete const on syntax,attrs members. - `format' now points to format data. Type of `value' is now - CGEN_IVALUE. - (struct cgen_opcode_table): New member ifld_table. - -1998-11-18 Doug Evans <devans@casey.cygnus.com> - - * cgen.h (cgen_extract_fn): Update type of `base_insn' arg. - (CGEN_OPERAND_INSTANCE): New member `attrs'. - (CGEN_OPERAND_INSTANCE_{ATTRS,ATTR}): New macros. - (cgen_dis_lookup_insn): Update type of `base_insn' arg. - (cgen_opcode_table): Update type of dis_hash fn. - (extract_operand): Update type of `insn_value' arg. - -Thu Oct 29 11:38:36 1998 Doug Evans <devans@canuck.cygnus.com> - - * cgen.h (CGEN_VERSION_{MAJOR,MINOR,FIXLEVEL}): Delete. - -Tue Oct 27 08:57:59 1998 Gavin Romig-Koch <gavin@cygnus.com> - - * mips.h (INSN_MULT): Added. - -Tue Oct 20 11:31:34 1998 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386.h (MAX_MNEM_SIZE): Rename from MAX_OPCODE_SIZE. - -Mon Oct 19 12:50:00 1998 Doug Evans <devans@seba.cygnus.com> - - * cgen.h (CGEN_INSN_INT): New typedef. - (CGEN_INT_INSN_P): Renamed from CGEN_INT_INSN. - (CGEN_INSN_BYTES): Renamed from cgen_insn_t. - (CGEN_INSN_BYTES_PTR): New typedef. - (CGEN_EXTRACT_INFO): New typedef. - (cgen_insert_fn,cgen_extract_fn): Update. - (cgen_opcode_table): New member `insn_endian'. - (assemble_insn,lookup_insn,lookup_get_insn_operands): Update. - (insert_operand,extract_operand): Update. - (cgen_get_insn_value,cgen_put_insn_value): Add prototypes. - -Fri Oct 9 13:38:13 1998 Doug Evans <devans@seba.cygnus.com> - - * cgen.h (CGEN_ATTR_BOOLS): New macro. - (struct CGEN_HW_ENTRY): New member `attrs'. - (CGEN_HW_ATTR): New macro. - (struct CGEN_OPERAND_INSTANCE): New member `name'. - (CGEN_INSN_INVALID_P): New macro. - -Mon Oct 5 00:21:07 1998 Jeffrey A Law (law@cygnus.com) - - * hppa.h: Add "fid". - -Sun Oct 4 21:00:00 1998 Alan Modra <alan@spri.levels.unisa.edu.au> - - From Robert Andrew Dale <rob@nb.net> - * i386.h (i386_optab): Add AMD 3DNow! instructions. - (AMD_3DNOW_OPCODE): Define. - -Tue Sep 22 17:53:47 1998 Nick Clifton <nickc@cygnus.com> - - * d30v.h (EITHER_BUT_PREFER_MU): Define. - -Mon Aug 10 14:09:38 1998 Doug Evans <devans@canuck.cygnus.com> - - * cgen.h (cgen_insn): #if 0 out element `cdx'. - -Mon Aug 3 12:21:57 1998 Doug Evans <devans@seba.cygnus.com> - - Move all global state data into opcode table struct, and treat - opcode table as something that is "opened/closed". - * cgen.h (CGEN_OPCODE_DESC): New type. - (all fns): New first arg of opcode table descriptor. - (cgen_set_parse_operand_fn): Add prototype. - (cgen_current_machine,cgen_current_endian): Delete. - (CGEN_OPCODE_TABLE): New members mach,endian,operand_table, - parse_operand_fn,asm_hash_table,asm_hash_table_entries, - dis_hash_table,dis_hash_table_entries. - (opcode_open,opcode_close): Add prototypes. - - * cgen.h (cgen_insn): New element `cdx'. - -Thu Jul 30 21:44:25 1998 Frank Ch. Eigler <fche@cygnus.com> - - * d30v.h (FLAG_LKR): New flag for "left-kills-right" instructions. - -Tue Jul 28 10:59:07 1998 Jeffrey A Law (law@cygnus.com) - - * mn10300.h: Add "no_match_operands" field for instructions. - (MN10300_MAX_OPERANDS): Define. - -Fri Jul 24 11:44:24 1998 Doug Evans <devans@canuck.cygnus.com> - - * cgen.h (cgen_macro_insn_count): Declare. - -Tue Jul 21 13:12:13 1998 Doug Evans <devans@seba.cygnus.com> - - * cgen.h (CGEN_VERSION_{MAJOR,MINOR,FIXLEVEL}): Define. - (cgen_insert_fn,cgen_extract_fn): New arg `pc'. - (get_operand,put_operand): Replaced with get_{int,vma}_operand, - set_{int,vma}_operand. - -Fri Jun 26 11:09:06 1998 Jeffrey A Law (law@cygnus.com) - - * mn10300.h: Add "machine" field for instructions. - (MN103, AM30): Define machine types. - -Fri Jun 19 16:09:09 1998 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386.h: Use FP, not sl_Suf, for fxsave and fxrstor. - -1998-06-18 Ulrich Drepper <drepper@cygnus.com> - - * i386.h: Add support for fxsave, fxrstor, sysenter and sysexit. - -Sat Jun 13 11:31:35 1998 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386.h (i386_optab): Add general form of aad and aam. Add ud2a - and ud2b. - (i386_regtab): Allow cr0..7, db0..7, dr0..7, tr0..7, not just - those that happen to be implemented on pentiums. - -Tue Jun 9 12:16:01 1998 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386.h: Change occurences of Data16 to Size16, Data32 to Size32, - IgnoreDataSize to IgnoreSize. Flag address and data size prefixes - with Size16|IgnoreSize or Size32|IgnoreSize. - -Mon Jun 8 12:15:52 1998 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386.h (REPNE): Rename to REPNE_PREFIX_OPCODE. - (REPE): Rename to REPE_PREFIX_OPCODE. - (i386_regtab_end): Remove. - (i386_prefixtab, i386_prefixtab_end): Remove. - (i386_optab): Use NULL as sentinel rather than "" to suit rewrite - of md_begin. - (MAX_OPCODE_SIZE): Define. - (i386_optab_end): Remove. - (sl_Suf): Define. - (sl_FP): Use sl_Suf. - - * i386.h (i386_optab): Allow 16 bit displacement for `mov - mem,acc'. Combine 16 and 32 bit forms of various insns. Allow 16 - bit form of ljmp. Add IsPrefix modifier to prefixes. Add addr32, - data32, dword, and adword prefixes. - (i386_regtab): Add BaseIndex modifier to valid 16 bit base/index - regs. - -Fri Jun 5 23:42:43 1998 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386.h (i386_regtab): Remove BaseIndex modifier from esp. - - * i386.h: Allow `l' suffix on fld, fst, fstp, fcom, fcomp with - register operands, because this is a common idiom. Flag them with - a warning. Allow illegal faddp, fsubp, fsubrp, fmulp, fdivp, - fdivrp because gcc erroneously generates them. Also flag with a - warning. - - * i386.h: Add suffix modifiers to most insns, and tighter operand - checks in some cases. Fix a number of UnixWare compatibility - issues with float insns. Merge some floating point opcodes, using - new FloatMF modifier. - (WORD_PREFIX_OPCODE): Rename to DATA_PREFIX_OPCODE for - consistency. - - * i386.h: Change occurence of ShortformW to W|ShortForm. Add - IgnoreDataSize where appropriate. - -Wed Jun 3 18:28:45 1998 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386.h: (one_byte_segment_defaults): Remove. - (two_byte_segment_defaults): Remove. - (i386_regtab): Add BaseIndex to 32 bit regs reg_type. - -Fri May 15 15:59:04 1998 Doug Evans <devans@seba.cygnus.com> - - * cgen.h (cgen_hw_lookup_by_name): Renamed from cgen_hw_lookup. - (cgen_hw_lookup_by_num): Declare. - -Thu May 7 09:27:58 1998 Frank Ch. Eigler <fche@cygnus.com> - - * mips.h (OP_{SH,MASK}_CODE2): Added "q" operand format for lower - ten bits of MIPS ISA1 "break" instruction, and for "sdbbp" - -Thu May 7 02:14:08 1998 Doug Evans <devans@charmed.cygnus.com> - - * cgen.h (cgen_asm_init_parse): Delete. - (cgen_save_fixups,cgen_restore_fixups,cgen_swap_fixups): Delete. - (cgen_asm_record_register,cgen_asm_finish_insn): Delete. - -Mon Apr 27 10:13:11 1998 Doug Evans <devans@seba.cygnus.com> - - * cgen.h (CGEN_ATTR_TYPE): Delete `const', moved to uses. - (cgen_asm_finish_insn): Update prototype. - (cgen_insn): New members num, data. - (CGEN_INSN_TABLE): Members asm_hash, asm_hash_table_size, - dis_hash, dis_hash_table_size moved to ... - (CGEN_OPCODE_TABLE). Here. Renamed from CGEN_OPCODE_DATA. - All uses updated. New members asm_hash_p, dis_hash_p. - (CGEN_MINSN_EXPANSION): New struct. - (cgen_expand_macro_insn): Declare. - (cgen_macro_insn_count): Declare. - (get_insn_operands): Update prototype. - (lookup_get_insn_operands): Declare. - -Tue Apr 21 17:11:32 1998 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386.h (i386_optab): Change iclrKludge and imulKludge to - regKludge. Add operands types for string instructions. - -Mon Apr 20 14:40:29 1998 Tom Tromey <tromey@cygnus.com> - - * i386.h (X): Renamed from `Z_' to preserve formatting of opcode - table. - -Sun Apr 19 13:54:06 1998 Tom Tromey <tromey@cygnus.com> - - * i386.h (Z_): Renamed from `_' to avoid clash with common alias - for `gettext'. - -Fri Apr 3 12:04:48 1998 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386.h: Remove NoModrm flag from all insns: it's never checked. - Add IsString flag to string instructions. - (IS_STRING): Don't define. - (LOCK_PREFIX_OPCODE, CS_PREFIX_OPCODE, DS_PREFIX_OPCODE): Define. - (ES_PREFIX_OPCODE, FS_PREFIX_OPCODE, GS_PREFIX_OPCODE): Define. - (SS_PREFIX_OPCODE): Define. - -Mon Mar 30 21:31:56 1998 Ian Lance Taylor <ian@cygnus.com> - - * i386.h: Revert March 24 patch; no more LinearAddress. - -Mon Mar 30 10:25:54 1998 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386.h (i386_optab): Remove fwait (9b) from all floating point - instructions, and instead add FWait opcode modifier. Add short - form of fldenv and fstenv. - (FWAIT_OPCODE): Define. - - * i386.h (i386_optab): Change second operand constraint of `mov - sreg,reg|mem' instruction from Reg16|Mem to WordReg|WordMem to - allow legal instructions such as `movl %gs,%esi' - -Fri Mar 27 18:30:52 1998 Ian Lance Taylor <ian@cygnus.com> - - * h8300.h: Various changes to fully bracket initializers. - -Tue Mar 24 18:32:47 1998 H.J. Lu <hjl@gnu.org> - - * i386.h: Set LinearAddress for lidt and lgdt. - -Mon Mar 2 10:44:07 1998 Doug Evans <devans@seba.cygnus.com> - - * cgen.h (CGEN_BOOL_ATTR): New macro. - -Thu Feb 26 15:54:31 1998 Michael Meissner <meissner@cygnus.com> - - * d30v.h (FLAG_DELAY): New flag for delayed branches/jumps. - -Mon Feb 23 10:38:21 1998 Doug Evans <devans@seba.cygnus.com> - - * cgen.h (CGEN_CAT3): Delete. Use CONCAT3 now. - (cgen_insn): Record syntax and format entries here, rather than - separately. - -Tue Feb 17 21:42:56 1998 Nick Clifton <nickc@cygnus.com> - - * cgen.h (CGEN_SYNTAX_MAKE_FIELD): New macro. - -Tue Feb 17 16:00:56 1998 Doug Evans <devans@seba.cygnus.com> - - * cgen.h (cgen_insert_fn): Change type of result to const char *. - (cgen_parse_{signed,unsigned}_integer): Delete min,max arguments. - (CGEN_{INSN,KEYWORD,OPERAND}_NBOOL_ATTRS): Renamed from ..._MAX_ATTRS. - -Thu Feb 12 18:30:41 1998 Doug Evans <devans@canuck.cygnus.com> - - * cgen.h (lookup_insn): New argument alias_p. - -Thu Feb 12 03:41:00 1998 J"orn Rennecke <amylaar@cygnus.co.uk> - -Fix rac to accept only a0: - * d10v.h (OPERAND_ACC): Split into: - (OPERAND_ACC0, OPERAND_ACC1) . - (OPERAND_GPR): Define. - -Wed Feb 11 17:31:53 1998 Doug Evans <devans@seba.cygnus.com> - - * cgen.h (CGEN_FIELDS): Define here. - (CGEN_HW_ENTRY): New member `type'. - (hw_list): Delete decl. - (enum cgen_mode): Declare. - (CGEN_OPERAND): New member `hw'. - (enum cgen_operand_instance_type): Declare. - (CGEN_OPERAND_INSTANCE): New type. - (CGEN_INSN): New member `operands'. - (CGEN_OPCODE_DATA): Make hw_list const. - (get_insn_operands,lookup_insn): Add prototypes for. - -Tue Feb 3 17:11:23 1998 Doug Evans <devans@seba.cygnus.com> - - * cgen.h (CGEN_INSN_MAX_ATTRS): Renamed from CGEN_MAX_INSN_ATTRS. - (CGEN_HW_ENTRY): Move `next' entry to end of struct. - (CGEN_KEYWORD_MAX_ATTRS): Renamed from CGEN_MAX_KEYWORD_ATTRS. - (CGEN_OPERAND_MAX_ATTRS): Renamed from CGEN_MAX_OPERAND_ATTRS. - -Mon Feb 2 19:19:15 1998 Ian Lance Taylor <ian@cygnus.com> - - * cgen.h: Correct typo in comment end marker. - -Mon Feb 2 17:10:38 1998 Steve Haworth <steve@pm.cse.rmit.EDU.AU> - - * tic30.h: New file. - -Thu Jan 22 17:54:56 1998 Nick Clifton <nickc@cygnus.com> - - * cgen.h: Add prototypes for cgen_save_fixups(), - cgen_restore_fixups(), and cgen_swap_fixups(). Change prototype - of cgen_asm_finish_insn() to return a char *. - -Wed Jan 14 17:21:43 1998 Nick Clifton <nickc@cygnus.com> - - * cgen.h: Formatting changes to improve readability. - -Mon Jan 12 11:37:36 1998 Doug Evans <devans@seba.cygnus.com> - - * cgen.h (*): Clean up pass over `struct foo' usage. - (CGEN_ATTR): Make unsigned char. - (CGEN_ATTR_TYPE): Update. - (CGEN_ATTR_{ENTRY,TABLE}): New types. - (cgen_base): Move member `attrs' to cgen_insn. - (CGEN_KEYWORD): New member `null_entry'. - (CGEN_{SYNTAX,FORMAT}): New types. - (cgen_insn): Format and syntax separated from each other. - -Tue Dec 16 15:15:52 1997 Michael Meissner <meissner@cygnus.com> - - * d30v.h (d30v_opcode): Reorder flags somewhat, add new flags for - 2 word load/store, ADDppp/SUBppp, 16/32 bit multiply. Make - flags_{used,set} long. - (d30v_operand): Make flags field long. - -Mon Dec 1 12:24:44 1997 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de> - - * m68k.h: Fix comment describing operand types. - -Sun Nov 23 22:31:27 1997 Michael Meissner <meissner@cygnus.com> - - * d30v.h (SHORT_CMPU): Add case for cmpu instruction, and move - everything else after down. - -Tue Nov 18 18:45:14 1997 J"orn Rennecke <amylaar@cygnus.co.uk> - - * d10v.h (OPERAND_FLAG): Split into: - (OPERAND_FFLAG, OPERAND_CFLAG) . - -Thu Nov 13 11:04:24 1997 Gavin Koch <gavin@cygnus.com> - - * mips.h (struct mips_opcode): Changed comments to reflect new - field usage. - -Fri Oct 24 22:36:20 1997 Ken Raeburn <raeburn@cygnus.com> - - * mips.h: Added to comments a quick-ref list of all assigned - operand type characters. - (OP_{MASK,SH}_PERFREG): New macros. - -Wed Oct 22 17:28:33 1997 Richard Henderson <rth@cygnus.com> - - * sparc.h: Add '_' and '/' for v9a asr's. - Patch from David Miller <davem@vger.rutgers.edu> - -Tue Oct 14 13:22:29 1997 Jeffrey A Law (law@cygnus.com) - - * h8300.h: Bit ops with absolute addresses not in the 8 bit - area are not available in the base model (H8/300). - -Thu Sep 25 13:03:41 1997 Ian Lance Taylor <ian@cygnus.com> - - * m68k.h: Remove documentation of ` operand specifier. - -Wed Sep 24 19:00:34 1997 Ian Lance Taylor <ian@cygnus.com> - - * m68k.h: Document q and v operand specifiers. - -Mon Sep 15 18:28:37 1997 Nick Clifton <nickc@cygnus.com> - - * v850.h (struct v850_opcode): Add processors field. - (PROCESSOR_V850, PROCESSOR_ALL): New bit constants. - (PROCESSOR_V850E, PROCESSOR_NOT_V850): New bit constants. - (PROCESSOR_V850EA): New bit constants. - -Mon Sep 15 11:29:43 1997 Ken Raeburn <raeburn@cygnus.com> - - Merge changes from Martin Hunt: - - * d30v.h: Allow up to 64 control registers. Add - SHORT_A5S format. - - * d30v.h (LONG_Db): New form for delayed branches. - - * d30v.h: (LONG_Db): New form for repeati. - - * d30v.h (SHORT_D2B): New form. - - * d30v.h (SHORT_A2): New form. - - * d30v.h (OPERAND_2REG): Add new operand to indicate 2 - registers are used. Needed for VLIW optimization. - -Mon Sep 8 14:05:45 1997 Doug Evans <dje@canuck.cygnus.com> - - * cgen.h: Move assembler interface section - up so cgen_parse_operand_result is defined for cgen_parse_address. - (cgen_parse_address): Update prototype. - -Tue Sep 2 15:32:32 1997 Nick Clifton <nickc@cygnus.com> - - * v850.h (V850_OPREAND_ADJUST_SHORT_MEMORY): Removed. - -Tue Aug 26 12:21:52 1997 Ian Lance Taylor <ian@cygnus.com> - - * i386.h (two_byte_segment_defaults): Correct base register 5 in - modes 1 and 2 to be ss rather than ds. From Gabriel Paubert - <paubert@iram.es>. - - * i386.h: Set ud2 to 0x0f0b. From Gabriel Paubert - <paubert@iram.es>. - - * i386.h: Comment fixes for ficom[p]?{s,l} from Gabriel Paubert - <paubert@iram.es>. - - * i386.h (JUMP_ON_CX_ZERO): Uncomment (define again). - (JUMP_ON_ECX_ZERO): Remove commented out macro. - -Fri Aug 22 10:38:29 1997 Nick Clifton <nickc@cygnus.com> - - * v850.h (V850_NOT_R0): New flag. - -Mon Aug 18 11:05:58 1997 Nick Clifton <nickc@cygnus.com> - - * v850.h (struct v850_opcode): Remove flags field. - -Wed Aug 13 18:45:48 1997 Nick Clifton <nickc@cygnus.com> - - * v850.h (struct v850_opcode): Add flags field. - (struct v850_operand): Extend meaning of 'bits' and 'shift' - fields. - (V850E_INSTRUCTION, V850EA_INSTRUCTION): New flags. - (V850E_PUSH_POP, V850E_IMMEDIATE16, V850E_IMMEDIATE32): New flags. - -Fri Aug 8 16:58:42 1997 Doug Evans <dje@canuck.cygnus.com> - - * arc.h: New file. - -Thu Jul 24 21:16:58 1997 Doug Evans <dje@canuck.cygnus.com> - - * sparc.h (sparc_opcodes): Declare as const. - -Thu Jul 10 12:53:25 1997 Jeffrey A Law (law@cygnus.com) - - * mips.h (FP_S, FP_D): Define. Bitmasks indicating if an insn - uses single or double precision floating point resources. - (INSN_NO_ISA, INSN_ISA1): Define. - (cpu specific INSN macros): Tweak into bitmasks outside the range - of INSN_ISA field. - -Mon Jun 16 14:10:00 1997 H.J. Lu <hjl@gnu.ai.mit.edu> - - * i386.h: Fix pand opcode. - -Mon Jun 2 11:35:09 1997 Gavin Koch <gavin@cygnus.com> - - * mips.h: Widen INSN_ISA and move it to a more convenient - bit position. Add INSN_3900. - -Tue May 20 11:25:29 1997 Gavin Koch <gavin@cygnus.com> - - * mips.h (struct mips_opcode): added new field membership. - -Mon May 12 16:26:50 1997 H.J. Lu <hjl@gnu.ai.mit.edu> - - * i386.h (movd): only Reg32 is allowed. - - * i386.h: add fcomp and ud2. From Wayne Scott - <wscott@ichips.intel.com>. - -Mon May 5 17:16:21 1997 Ian Lance Taylor <ian@cygnus.com> - - * i386.h: Add MMX instructions. - -Mon May 5 12:45:19 1997 H.J. Lu <hjl@gnu.ai.mit.edu> - - * i386.h: Remove W modifier from conditional move instructions. - -Mon Apr 14 14:56:58 1997 Ian Lance Taylor <ian@cygnus.com> - - * i386.h: Change the opcodes for fsubp, fsubrp, fdivp, and fdivrp - with no arguments to match that generated by the UnixWare - assembler. - -Thu Apr 10 14:35:00 1997 Doug Evans <dje@canuck.cygnus.com> - - * cgen.h (<cpu>_cgen_assemble_insn): New arg for errmsg. - (cgen_parse_operand_fn): Declare. - (cgen_init_parse_operand): Declare. - (cgen_parse_operand): Renamed from cgen_asm_parse_operand, - new argument `want'. - (enum cgen_parse_operand_result): Renamed from cgen_asm_result. - (enum cgen_parse_operand_type): New enum. - -Sat Apr 5 13:14:05 1997 Ian Lance Taylor <ian@cygnus.com> - - * i386.h: Revert last patch for the NON_BROKEN_OPCODES cases. - -Fri Apr 4 11:46:11 1997 Doug Evans <dje@canuck.cygnus.com> - - * cgen.h: New file. - -Fri Apr 4 14:02:32 1997 Ian Lance Taylor <ian@cygnus.com> - - * i386.h: Correct opcode values for fsubp, fsubrp, fdivp, and - fdivrp. - -Tue Mar 25 22:57:26 1997 Stu Grossman (grossman@critters.cygnus.com) - - * v850.h (extract): Make unsigned. - -Mon Mar 24 14:38:15 1997 Ian Lance Taylor <ian@cygnus.com> - - * i386.h: Add iclr. - -Thu Mar 20 19:49:10 1997 Ian Lance Taylor <ian@cygnus.com> - - * i386.h: Change DW to W for cmpxchg and xadd, since they don't - take a direction bit. - -Sat Mar 15 19:03:29 1997 H.J. Lu <hjl@lucon.org> - - * sparc.h (sparc_opcode_lookup_arch): Use full prototype. - -Fri Mar 14 15:22:01 1997 Ian Lance Taylor <ian@cygnus.com> - - * sparc.h: Include <ansidecl.h>. Update function declarations to - use prototypes, and to use const when appropriate. - -Thu Mar 6 14:18:30 1997 Jeffrey A Law (law@cygnus.com) - - * mn10300.h (MN10300_OPERAND_RELAX): Define. - -Mon Feb 24 15:15:56 1997 Martin M. Hunt <hunt@pizza.cygnus.com> - - * d10v.h: Change pre_defined_registers to - d10v_predefined_registers and reg_name_cnt to d10v_reg_name_cnt. - -Sat Feb 22 21:25:00 1997 Dawn Perchik <dawn@cygnus.com> - - * mips.h: Add macros for cop0, cop1 cop2 and cop3. - Change mips_opcodes from const array to a pointer, - and change bfd_mips_num_opcodes from const int to int, - so that we can increase the size of the mips opcodes table - dynamically. - -Fri Feb 21 16:34:18 1997 Martin M. Hunt <hunt@pizza.cygnus.com> - - * d30v.h (FLAG_X): Remove unused flag. - -Tue Feb 18 17:37:20 1997 Martin M. Hunt <hunt@pizza.cygnus.com> - - * d30v.h: New file. - -Fri Feb 14 13:16:15 1997 Fred Fish <fnf@cygnus.com> - - * tic80.h (PDS_NAME): Macro to access name field of predefined symbols. - (PDS_VALUE): Macro to access value field of predefined symbols. - (tic80_next_predefined_symbol): Add prototype. - -Mon Feb 10 10:32:17 1997 Fred Fish <fnf@cygnus.com> - - * tic80.h (tic80_symbol_to_value): Change prototype to match - change in function, added class parameter. - -Thu Feb 6 17:30:15 1997 Fred Fish <fnf@cygnus.com> - - * tic80.h (TIC80_OPERAND_ENDMASK): Add for flagging TIc80 - endmask fields, which are somewhat weird in that 0 and 32 are - treated exactly the same. - -Thu Jan 30 13:46:18 1997 Fred Fish <fnf@cygnus.com> - - * tic80.h: Change all the OPERAND defines to use the form (1 << X) - rather than a constant that is 2**X. Reorder them to put bits for - operands that have symbolic names in the upper bits, so they can - be packed into an int where the lower bits contain the value that - corresponds to that symbolic name. - (predefined_symbo): Add struct. - (tic80_predefined_symbols): Declare array of translations. - (tic80_num_predefined_symbols): Declare size of that array. - (tic80_value_to_symbol): Declare function. - (tic80_symbol_to_value): Declare function. - -Wed Jan 29 09:37:25 1997 Jeffrey A Law (law@cygnus.com) - - * mn10200.h (MN10200_OPERAND_RELAX): Define. - -Sat Jan 18 15:18:59 1997 Fred Fish <fnf@cygnus.com> - - * tic80.h (TIC80_NO_R0_DEST): Add for opcodes where r0 cannot - be the destination register. - -Thu Jan 16 20:48:55 1997 Fred Fish <fnf@cygnus.com> - - * tic80.h (struct tic80_opcode): Change "format" field to "flags". - (FMT_UNUSED, FMT_SI, FMT_LI, FMT_REG): Delete. - (TIC80_VECTOR): Define a flag bit for the flags. This one means - that the opcode can have two vector instructions in a single - 32 bit word and we have to encode/decode both. - -Tue Jan 14 19:37:09 1997 Fred Fish <fnf@cygnus.com> - - * tic80.h (TIC80_OPERAND_PCREL): Renamed from - TIC80_OPERAND_RELATIVE for PC relative. - (TIC80_OPERAND_BASEREL): New flag bit for register - base relative. - -Mon Jan 13 15:56:38 1997 Fred Fish <fnf@cygnus.com> - - * tic80.h (TIC80_OPERAND_FLOAT): Add for floating point operands. - -Mon Jan 6 10:51:15 1997 Fred Fish <fnf@cygnus.com> - - * tic80.h (TIC80_OPERAND_SCALED): Operand may have optional - ":s" modifier for scaling. - -Sun Jan 5 12:12:19 1997 Fred Fish <fnf@cygnus.com> - - * tic80.h (TIC80_OPERAND_M_SI): Add operand modifier for ":m". - (TIC80_OPERAND_M_LI): Ditto - -Sat Jan 4 19:02:44 1997 Fred Fish <fnf@cygnus.com> - - * tic80.h (TIC80_OPERAND_BITNUM): Renamed from TIC80_OPERAND_CC_SZ. - (TIC80_OPERAND_CC): New define for condition code operand. - (TIC80_OPERAND_CR): New define for control register operand. - -Fri Jan 3 16:22:23 1997 Fred Fish <fnf@cygnus.com> - - * tic80.h (struct tic80_opcode): Name changed. - (struct tic80_opcode): Remove format field. - (struct tic80_operand): Add insertion and extraction functions. - (TIC80_OPERAND_*): Remove old bogus values, start adding new - correct ones. - (FMT_*): Ditto. - -Tue Dec 31 15:05:41 1996 Michael Meissner <meissner@tiktok.cygnus.com> - - * v850.h (V850_OPERAND_ADJUST_SHORT_MEMORY): New flag to adjust - type IV instruction offsets. - -Fri Dec 27 22:23:10 1996 Fred Fish <fnf@cygnus.com> - - * tic80.h: New file. - -Wed Dec 18 10:06:31 1996 Jeffrey A Law (law@cygnus.com) - - * mn10200.h (MN10200_OPERAND_NOCHECK): Define. - -Sat Dec 14 10:48:31 1996 Fred Fish <fnf@ninemoons.com> - - * mn10200.h: Fix comment, mn10200_operand not powerpc_operand. - * mn10300.h: Fix comment, mn10300_operand not powerpc_operand. - * v850.h: Fix comment, v850_operand not powerpc_operand. - -Mon Dec 9 16:45:39 1996 Jeffrey A Law (law@cygnus.com) - - * mn10200.h: Flesh out structures and definitions needed by - the mn10200 assembler & disassembler. - -Tue Nov 26 10:46:56 1996 Ian Lance Taylor <ian@cygnus.com> - - * mips.h: Add mips16 definitions. - -Mon Nov 25 17:56:54 1996 J.T. Conklin <jtc@cygnus.com> - - * m68k.h: Document new <, >, m, n, o and p operand specifiers. - -Wed Nov 20 10:59:41 1996 Jeffrey A Law (law@cygnus.com) - - * mn10300.h (MN10300_OPERAND_PCREL): Define. - (MN10300_OPERAND_MEMADDR): Define. - -Tue Nov 19 13:30:40 1996 Jeffrey A Law (law@cygnus.com) - - * mn10300.h (MN10300_OPERAND_REG_LIST): Define. - -Wed Nov 6 13:41:08 1996 Jeffrey A Law (law@cygnus.com) - - * mn10300.h (MN10300_OPERAND_SPLIT): Define. - -Tue Nov 5 13:26:12 1996 Jeffrey A Law (law@cygnus.com) - - * mn10300.h (MN10300_OPERAND_EXTENDED): Define. - -Mon Nov 4 12:52:48 1996 Jeffrey A Law (law@cygnus.com) - - * mn10300.h (MN10300_OPERAND_REPEATED): Define. - -Fri Nov 1 10:31:02 1996 Richard Henderson <rth@tamu.edu> - - * alpha.h: Don't include "bfd.h"; private relocation types are now - negative to minimize problems with shared libraries. Organize - instruction subsets by AMASK extensions and PALcode - implementation. - (struct alpha_operand): Move flags slot for better packing. - -Tue Oct 29 12:19:10 1996 Jeffrey A Law (law@cygnus.com) - - * v850.h (V850_OPERAND_RELAX): New operand flag. - -Thu Oct 10 14:29:11 1996 Jeffrey A Law (law@cygnus.com) - - * mn10300.h (FMT_*): Move operand format definitions - here. - -Tue Oct 8 14:48:07 1996 Jeffrey A Law (law@cygnus.com) - - * mn10300.h (MN10300_OPERAND_PAREN): Define. - -Mon Oct 7 16:52:11 1996 Jeffrey A Law (law@cygnus.com) - - * mn10300.h (mn10300_opcode): Add "format" field. - (MN10300_OPERAND_*): Define. - -Thu Oct 3 10:33:46 1996 Jeffrey A Law (law@cygnus.com) - - * mn10x00.h: Delete. - * mn10200.h, mn10300.h: New files. - -Wed Oct 2 21:31:26 1996 Jeffrey A Law (law@cygnus.com) - - * mn10x00.h: New file. - -Fri Sep 27 18:26:46 1996 Stu Grossman (grossman@critters.cygnus.com) - - * v850.h: Add new flag to indicate this instruction uses a PC - displacement. - -Fri Sep 13 14:58:13 1996 Jeffrey A Law (law@cygnus.com) - - * h8300.h (stmac): Add missing instruction. - -Sat Aug 31 16:02:03 1996 Jeffrey A Law (law@cygnus.com) - - * v850.h (v850_opcode): Remove "size" field. Add "memop" - field. - -Fri Aug 23 10:39:08 1996 Jeffrey A Law (law@cygnus.com) - - * v850.h (V850_OPERAND_EP): Define. - - * v850.h (v850_opcode): Add size field. - -Thu Aug 22 16:51:25 1996 J.T. Conklin <jtc@rtl.cygnus.com> - - * v850.h (v850_operands): Add insert and extract fields, pointers - to functions used to handle unusual operand encoding. - (V850_OPERAND_REG, V850_OPERAND_SRG, V850_OPERAND_CC, - V850_OPERAND_SIGNED): Defined. - -Wed Aug 21 17:45:10 1996 J.T. Conklin <jtc@rtl.cygnus.com> - - * v850.h (v850_operands): Add flags field. - (OPERAND_REG, OPERAND_NUM): Defined. - -Tue Aug 20 14:52:02 1996 J.T. Conklin <jtc@rtl.cygnus.com> - - * v850.h: New file. - -Fri Aug 16 14:44:15 1996 James G. Smith <jsmith@cygnus.co.uk> - - * mips.h (OP_SH_LOCC, OP_SH_HICC, OP_MASK_CC, OP_SH_COP1NORM, - OP_MASK_COP1NORM, OP_SH_COP1SPEC, OP_MASK_COP1SPEC, - OP_MASK_COP1SCLR, OP_MASK_COP1CMP, OP_SH_COP1CMP, OP_SH_FORMAT, - OP_MASK_FORMAT, OP_SH_TRUE, OP_MASK_TRUE, OP_SH_GE, OP_MASK_GE, - OP_SH_UNSIGNED, OP_MASK_UNSIGNED, OP_SH_HINT, OP_MASK_HINT): - Defined. - -Fri Aug 16 00:15:15 1996 Jeffrey A Law (law@cygnus.com) - - * hppa.h (pitlb, pitlbe, iitlba, iitlbp, fic, fice): Accept - a 3 bit space id instead of a 2 bit space id. - -Thu Aug 15 13:11:46 1996 Martin M. Hunt <hunt@pizza.cygnus.com> - - * d10v.h: Add some additional defines to support the - assembler in determining which operations can be done in parallel. - -Tue Aug 6 11:13:22 1996 Jeffrey A Law (law@cygnus.com) - - * h8300.h (SN): Define. - (eepmov.b): Renamed from "eepmov" - (nop, bpt, rte, rts, sleep, clrmac): These have no size associated - with them. - -Fri Jul 26 11:47:10 1996 Martin M. Hunt <hunt@pizza.cygnus.com> - - * d10v.h (OPERAND_SHIFT): New operand flag. - -Thu Jul 25 12:06:22 1996 Martin M. Hunt <hunt@pizza.cygnus.com> - - * d10v.h: Changes for divs, parallel-only instructions, and - signed numbers. - -Mon Jul 22 11:21:15 1996 Martin M. Hunt <hunt@pizza.cygnus.com> - - * d10v.h (pd_reg): Define. Putting the definition here allows - the assembler and disassembler to share the same struct. - -Mon Jul 22 12:15:25 1996 Ian Lance Taylor <ian@cygnus.com> - - * i960.h (i960_opcodes): "halt" takes an argument. From Stephen - Williams <steve@icarus.com>. - -Wed Jul 17 14:46:38 1996 Martin M. Hunt <hunt@pizza.cygnus.com> - - * d10v.h: New file. - -Thu Jul 11 12:09:15 1996 Jeffrey A Law (law@cygnus.com) - - * h8300.h (band, bclr): Force high bit of immediate nibble to zero. - -Wed Jul 3 14:30:12 1996 J.T. Conklin <jtc@rtl.cygnus.com> - - * m68k.h (mcf5200): New macro. - Document names of coldfire control registers. - -Tue Jul 2 23:05:45 1996 Jeffrey A Law (law@cygnus.com) - - * h8300.h (SRC_IN_DST): Define. - - * h8300.h (UNOP3): Mark the register operand in this insn - as a source operand, not a destination operand. - (SHIFT_2, SHIFT_IMM): Remove. Eliminate all references. - (UNOP3): Change SHIFT_IMM to IMM for H8/S bitops. Mark - register operand with SRC_IN_DST. - -Fri Jun 21 13:52:17 1996 Richard Henderson <rth@tamu.edu> - - * alpha.h: New file. - -Thu Jun 20 15:02:57 1996 Ian Lance Taylor <ian@cygnus.com> - - * rs6k.h: Remove obsolete file. - -Wed Jun 19 15:29:38 1996 Ian Lance Taylor <ian@cygnus.com> - - * i386.h: Correct opcode values for faddp, fsubp, fsubrp, fmulp, - fdivp, and fdivrp. Add ffreep. - -Tue Jun 18 16:06:00 1996 Jeffrey A. Law <law@rtl.cygnus.com> - - * h8300.h: Reorder various #defines for readability. - (ABS32SRC, ABS32DST, DSP32LIST, ABS32LIST, A32LIST): Define. - (BITOP): Accept additional (unused) argument. All callers changed. - (EBITOP): Likewise. - (O_LAST): Bump. - (ldc, stc, movb, movw, movl): Use 32bit offsets and absolutes. - - * h8300.h (EXR, SHIFT_2, MACREG, SHIFT_IMM, RDINC): Define. - (O_TAS, O_CLRMAC, O_LDMAC, O_MAC, O_LDM, O_STM): Define. - (BITOP, EBITOP): Handle new H8/S addressing modes for - bit insns. - (UNOP3): Handle new shift/rotate insns on the H8/S. - (insns using exr): New instructions. - (tas, mac, ldmac, clrmac, ldm, stm): New instructions. - -Thu May 23 16:56:48 1996 Jeffrey A Law (law@cygnus.com) - - * h8300.h (add.l): Undo Apr 5th change. The manual I had - was incorrect. - -Mon May 6 23:38:22 1996 Jeffrey A Law (law@cygnus.com) - - * h8300.h (START): Remove. - (MEMRELAX): Define. Mark absolute memory operands in mov.b, mov.w - and mov.l insns that can be relaxed. - -Tue Apr 30 18:30:58 1996 Ian Lance Taylor <ian@cygnus.com> - - * i386.h: Remove Abs32 from lcall. - -Mon Apr 22 17:09:23 1996 Doug Evans <dje@blues.cygnus.com> - - * sparc.h (SPARC_OPCODE_ARCH_V9_P): New macro. - (SLCPOP): New macro. - Mark X,Y opcode letters as in use. - -Thu Apr 11 17:28:18 1996 Ian Lance Taylor <ian@cygnus.com> - - * sparc.h (F_FLOAT, F_FBR): Define. - -Fri Apr 5 16:55:34 1996 Jeffrey A Law (law@cygnus.com) - - * h8300.h (ABS8MEM): Renamed from ABSMOV. Remove ABSMOV - from all insns. - (ABS8SRC,ABS8DST): Add ABS8MEM. - (add.l): Fix reg+reg variant. - (eepmov.w): Renamed from eepmovw. - (ldc,stc): Fix many cases. - -Sun Mar 31 13:30:03 1996 Doug Evans <dje@canuck.cygnus.com> - - * sparc.h (SPARC_OPCODE_ARCH_MASK): New macro. - -Thu Mar 7 15:08:23 1996 Doug Evans <dje@charmed.cygnus.com> - - * sparc.h (O): Mark operand letter as in use. - -Tue Feb 20 20:46:21 1996 Doug Evans <dje@charmed.cygnus.com> - - * sparc.h (sparc_{encode,decode}_sparclet_cpreg): Declare. - Mark operand letters uU as in use. - -Mon Feb 19 01:59:08 1996 Doug Evans <dje@charmed.cygnus.com> - - * sparc.h (sparc_opcode_arch_val): Add SPARC_OPCODE_ARCH_SPARCLET. - (sparc_opcode_arch): Delete member `conflicts'. Add `supported'. - (SPARC_OPCODE_SUPPORTED): New macro. - (SPARC_OPCODE_CONFLICT_P): Rewrite. - (F_NOTV9): Delete. - -Fri Feb 16 12:23:34 1996 Jeffrey A Law (law@cygnus.com) - - * sparc.h (sparc_opcode_lookup_arch) Make return type in - declaration consistent with return type in definition. - -Wed Feb 14 18:14:11 1996 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386.h (i386_optab): Remove Data32 from pushf and popf. - -Thu Feb 8 14:27:21 1996 James Carlson <carlson@xylogics.com> - - * i386.h (i386_regtab): Add 80486 test registers. - -Mon Feb 5 18:35:46 1996 Ian Lance Taylor <ian@cygnus.com> - - * i960.h (I_HX): Define. - (i960_opcodes): Add HX instruction. - -Mon Jan 29 12:43:39 1996 Ken Raeburn <raeburn@cygnus.com> - - * i386.h: Fix waiting forms of finit, fstenv, fsave, fstsw, fstcw, - and fclex. - -Wed Jan 24 22:36:59 1996 Doug Evans <dje@charmed.cygnus.com> - - * sparc.h (enum sparc_opcode_arch_val): Replaces sparc_architecture. - (SPARC_OPCODE_CONFLICT_P): Renamed from ARCHITECTURES_CONFLICT_P. - (bfd_* defines): Delete. - (sparc_opcode_archs): Replaces architecture_pname. - (sparc_opcode_lookup_arch): Declare. - (NUMOPCODES): Delete. - -Mon Jan 22 08:24:32 1996 Doug Evans <dje@charmed.cygnus.com> - - * sparc.h (enum sparc_architecture): Add v9a. - (ARCHITECTURES_CONFLICT_P): Update. - -Thu Dec 28 13:27:53 1995 John Hassey <hassey@rtp.dg.com> - - * i386.h: Added Pentium Pro instructions. - -Thu Nov 2 22:59:22 1995 Ian Lance Taylor <ian@cygnus.com> - - * m68k.h: Document new 'W' operand place. - -Tue Oct 24 10:49:10 1995 Jeffrey A Law (law@cygnus.com) - - * hppa.h: Add lci and syncdma instructions. - -Mon Oct 23 11:09:16 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk> - - * mips.h: Added INSN_4100 flag to mark NEC VR4100 specific - instructions. - -Mon Oct 16 10:28:15 1995 Michael Meissner <meissner@tiktok.cygnus.com> - - * ppc.h (PPC_OPCODE_{COMMON,ANY}): New opcode flags for - assembler's -mcom and -many switches. - -Wed Oct 11 16:56:33 1995 Ken Raeburn <raeburn@cygnus.com> - - * i386.h: Fix cmpxchg8b extension opcode description. - -Thu Oct 5 18:03:36 1995 Ken Raeburn <raeburn@cygnus.com> - - * i386.h: Add Pentium instructions wrmsr, rdtsc, rdmsr, cmpxchg8b, - and register cr4. - -Tue Sep 19 15:26:43 1995 Ian Lance Taylor <ian@cygnus.com> - - * m68k.h: Change comment: split type P into types 0, 1 and 2. - -Wed Aug 30 13:50:55 1995 Doug Evans <dje@canuck.cygnus.com> - - * sparc.h (sparc_{encode,decode}_prefetch): Declare. - -Tue Aug 29 15:34:58 1995 Doug Evans <dje@canuck.cygnus.com> - - * sparc.h (sparc_{encode,decode}_{asi,membar}): Declare. - -Wed Aug 2 18:32:19 1995 Ian Lance Taylor <ian@cygnus.com> - - * m68kmri.h: Remove. - - * m68k.h: Move tables into opcodes/m68k-opc.c, leaving just the - declarations. Remove F_ALIAS and flag field of struct - m68k_opcode. Change arch field of struct m68k_opcode to unsigned - int. Make name and args fields of struct m68k_opcode const. - -Wed Aug 2 08:16:46 1995 Doug Evans <dje@canuck.cygnus.com> - - * sparc.h (F_NOTV9): Define. - -Tue Jul 11 14:20:42 1995 Jeff Spiegel <jeffs@lsil.com> - - * mips.h (INSN_4010): Define. - -Wed Jun 21 18:49:51 1995 Ken Raeburn <raeburn@cujo.cygnus.com> - - * m68k.h (TBL1): Reverse sense of "round" argument in result. - - Changes from Andreas Schwab <schwab@issan.informatik.uni-dortmund.de>: - * m68k.h: Fix argument descriptions of coprocessor - instructions to allow only alterable operands where appropriate. - [!NO_DEFAULT_SIZES]: An omitted size defaults to `w'. - (m68k_opcode_aliases): Add more aliases. - -Fri Apr 14 22:15:34 1995 Ken Raeburn <raeburn@cujo.cygnus.com> - - * m68k.h: Added explcitly short-sized conditional branches, and a - bunch of aliases (fmov*, ftest*, tdivul) to support gcc's - svr4-based configurations. - -Mon Mar 13 21:30:01 1995 Ken Raeburn <raeburn@cujo.cygnus.com> - - Mon Feb 27 08:36:39 1995 Bryan Ford <baford@cs.utah.edu> - * i386.h: added missing Data16/Data32 flags to a few instructions. - -Wed Mar 8 15:19:53 1995 Ian Lance Taylor <ian@cygnus.com> - - * mips.h (OP_MASK_FR, OP_SH_FR): Define. - (OP_MASK_BCC, OP_SH_BCC): Define. - (OP_MASK_PREFX, OP_SH_PREFX): Define. - (OP_MASK_CCC, OP_SH_CCC): Define. - (INSN_READ_FPR_R): Define. - (INSN_RFE): Delete. - -Wed Mar 8 03:13:23 1995 Ken Raeburn <raeburn@cujo.cygnus.com> - - * m68k.h (enum m68k_architecture): Deleted. - (struct m68k_opcode_alias): New type. - (m68k_opcodes): Now const. Deleted opcode aliases with exactly - matching constraints, values and flags. As a side effect of this, - the MOTOROLA_SYNTAX_ONLY and MIT_SYNTAX_ONLY macros, which so far - as I know were never used, now may need re-examining. - (numopcodes): Now const. - (m68k_opcode_aliases, numaliases): New variables. - (endop): Deleted. - [DONT_DEFINE_TABLE]: Declare numopcodes, numaliases, and - m68k_opcode_aliases; update declaration of m68k_opcodes. - -Mon Mar 6 10:02:00 1995 Jeff Law (law@snake.cs.utah.edu) - - * hppa.h (delay_type): Delete unused enumeration. - (pa_opcode): Replace unused delayed field with an architecture - field. - (pa_opcodes): Mark each instruction as either PA1.0 or PA1.1. - -Fri Mar 3 16:10:24 1995 Ian Lance Taylor <ian@cygnus.com> - - * mips.h (INSN_ISA4): Define. - -Fri Feb 24 19:13:37 1995 Ian Lance Taylor <ian@cygnus.com> - - * mips.h (M_DLA_AB, M_DLI): Define. - -Thu Feb 23 17:33:09 1995 Jeff Law (law@snake.cs.utah.edu) - - * hppa.h (fstwx): Fix single-bit error. - -Wed Feb 15 12:19:52 1995 Ian Lance Taylor <ian@cygnus.com> - - * mips.h (M_ULD, M_ULD_A, M_USD, M_USD_A): Define. - -Mon Feb 6 10:35:23 1995 J.T. Conklin <jtc@rtl.cygnus.com> - - * i386.h: added cpuid instruction , and dr[0-7] aliases for the - debug registers. From Charles Hannum (mycroft@netbsd.org). - -Mon Feb 6 03:31:54 1995 Ken Raeburn <raeburn@cujo.cygnus.com> - - Changes from Bryan Ford <baford@schirf.cs.utah.edu> for 16-bit - i386 support: - * i386.h (MOV_AX_DISP32): New macro. - (i386_optab): Added Data16 and Data32 as needed. Added "w" forms - of several call/return instructions. - (ADDR_PREFIX_OPCODE): New macro. - -Mon Jan 23 16:45:43 1995 Ken Raeburn <raeburn@cujo.cygnus.com> - - Sat Jan 21 17:50:38 1995 Pat Rankin (rankin@eql.caltech.edu) - - * vax.h (struct vot_wot, field `args'): Make it pointer to const - char. - (struct vot, field `name'): ditto. - -Thu Jan 19 14:47:53 1995 Ken Raeburn <raeburn@cujo.cygnus.com> - - * vax.h: Supply and properly group all values in end sentinel. - -Tue Jan 17 10:55:30 1995 Ian Lance Taylor <ian@sanguine.cygnus.com> - - * mips.h (INSN_ISA, INSN_4650): Define. - -Wed Oct 19 13:34:17 1994 Ian Lance Taylor <ian@sanguine.cygnus.com> - - * a29k.h: Add operand type 'I' for `inv' and `iretinv'. On - systems with a separate instruction and data cache, such as the - 29040, these instructions take an optional argument. - -Wed Sep 14 17:44:20 1994 Ian Lance Taylor (ian@sanguine.cygnus.com) - - * mips.h (INSN_STORE_MEMORY): Correct value to not conflict with - INSN_TRAP. - -Tue Sep 6 11:39:08 1994 Ian Lance Taylor (ian@sanguine.cygnus.com) - - * mips.h (INSN_STORE_MEMORY): Define. - -Thu Jul 28 19:28:07 1994 Ken Raeburn (raeburn@cujo.cygnus.com) - - * sparc.h: Document new operand type 'x'. - -Tue Jul 26 17:48:05 1994 Ken Raeburn (raeburn@cujo.cygnus.com) - - * i960.h (I_CX2): New instruction category. It includes - instructions available on Cx and Jx processors. - (I_JX): New instruction category, for JX-only instructions. - (i960_opcodes): Put eshro and sysctl in I_CX2 category. Added - Jx-only instructions, in I_JX category. - -Wed Jul 13 18:43:47 1994 Ken Raeburn (raeburn@cujo.cygnus.com) - - * ns32k.h (endop): Made pointer const too. - -Sun Jul 10 11:01:09 1994 Ian Dall (dall@hfrd.dsto.gov.au) - - * ns32k.h: Drop Q operand type as there is no correct use - for it. Add I and Z operand types which allow better checking. - -Thu Jul 7 12:34:48 1994 Steve Chamberlain (sac@jonny.cygnus.com) - - * h8300.h (xor.l) :fix bit pattern. - (L_2): New size of operand. - (trapa): Use it. - -Fri Jun 10 16:38:11 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * m68k.h: Move "trap" before "tpcc" to change disassembly. - -Fri Jun 3 15:57:36 1994 Ken Raeburn (raeburn@cujo.cygnus.com) - - * sparc.h: Include v9 definitions. - -Thu Jun 2 12:23:17 1994 Ken Raeburn (raeburn@cujo.cygnus.com) - - * m68k.h (m68060): Defined. - (m68040up, mfloat, mmmu): Include it. - (struct m68k_opcode): Widen `arch' field. - (m68k_opcodes): Updated for M68060. Removed comments that were - instructions commented out by "JF" years ago. - -Thu Apr 28 18:31:14 1994 Ken Raeburn (raeburn@cujo.cygnus.com) - - * m68k.h (struct m68k_opcode): Shorten `arch' field to 8 bits, and - add a one-bit `flags' field. - (F_ALIAS): New macro. - -Wed Apr 27 11:29:52 1994 Steve Chamberlain (sac@cygnus.com) - - * h8300.h (dec, inc): Get encoding right. - -Mon Apr 4 13:12:43 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * ppc.h (struct powerpc_operand): Removed signedp field; just use - a flag instead. - (PPC_OPERAND_SIGNED): Define. - (PPC_OPERAND_SIGNOPT): Define. - -Thu Mar 31 19:34:08 1994 Ken Raeburn (raeburn@cujo.cygnus.com) - - * i386.h (IS_JUMP_ON_ECX_ZERO, "jcxz" pattern): Operand size - prefix is 0x66, not 0x67. Patch from H.J. Lu (hlu@nynexst.com). - -Thu Mar 3 15:51:05 1994 Ken Raeburn (raeburn@cujo.cygnus.com) - - * i386.h: Reverse last change. It'll be handled in gas instead. - -Thu Feb 24 15:29:05 1994 Ken Raeburn (raeburn@cujo.cygnus.com) - - * i386.h (sar): Disabled the two-operand Imm1 form, since it was - slower on the 486 and used the implicit shift count despite the - explicit operand. The one-operand form is still available to get - the shorter form with the implicit shift count. - -Thu Feb 17 12:27:52 1994 Torbjorn Granlund (tege@mexican.cygnus.com) - - * hppa.h: Fix typo in fstws arg string. - -Wed Feb 9 21:23:52 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * ppc.h (struct powerpc_opcode): Make operands field unsigned. - -Mon Feb 7 19:14:58 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * ppc.h (PPC_OPCODE_601): Define. - -Fri Feb 4 23:43:50 1994 Jeffrey A. Law (law@snake.cs.utah.edu) - - * hppa.h (addb): Use '@' for addb and addib pseudo ops. - (so we can determine valid completers for both addb and addb[tf].) - - * hppa.h (xmpyu): No floating point format specifier for the - xmpyu instruction. - -Fri Feb 4 23:36:52 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * ppc.h (PPC_OPERAND_NEXT): Define. - (PPC_OPERAND_NEGATIVE): Change value to make room for above. - (struct powerpc_macro): Define. - (powerpc_macros, powerpc_num_macros): Declare. - -Fri Jan 21 19:13:50 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * ppc.h: New file. Header file for PowerPC opcode table. - -Mon Jan 17 00:14:23 1994 Jeffrey A. Law (law@snake.cs.utah.edu) - - * hppa.h: More minor template fixes for sfu and copr (to allow - for easier disassembly). - - * hppa.h: Fix templates for all the sfu and copr instructions. - -Wed Dec 15 15:12:42 1993 Ken Raeburn (raeburn@cujo.cygnus.com) - - * i386.h (push): Permit Imm16 operand too. - -Sat Dec 11 16:14:06 1993 Steve Chamberlain (sac@thepub.cygnus.com) - - * h8300.h (andc): Exists in base arch. - -Wed Dec 1 12:15:32 1993 Jeffrey A. Law (law@snake.cs.utah.edu) - - * From Hisashi MINAMINO <minamino@sramhc.sra.co.jp> - * hppa.h: #undef NONE to avoid conflict with hiux include files. - -Sun Nov 21 22:06:57 1993 Jeffrey A. Law (law@snake.cs.utah.edu) - - * hppa.h: Add FP quadword store instructions. - -Wed Nov 17 17:13:16 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * mips.h: (M_J_A): Added. - (M_LA): Removed. - -Mon Nov 8 12:12:47 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * mips.h (OP_MASK_CACHE, OP_SH_CACHE): Define. From Ted Lemon - <mellon@pepper.ncd.com>. - -Sun Nov 7 00:30:11 1993 Jeffrey A. Law (law@snake.cs.utah.edu) - - * hppa.h: Immediate field in probei instructions is unsigned, - not low-sign extended. - -Wed Nov 3 10:30:00 1993 Jim Kingdon (kingdon@lioth.cygnus.com) - - * m88k.h (RRI10MASK): Change from 0xfc00ffe0 to 0xfc00fc00. - -Tue Nov 2 12:41:30 1993 Ken Raeburn (raeburn@rover.cygnus.com) - - * i386.h: Add "fxch" without operand. - -Mon Nov 1 18:13:03 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * mips.h (M_JAL_1, M_JAL_2, M_JAL_A): Added. - -Sat Oct 2 22:26:11 1993 Jeffrey A Law (law@snake.cs.utah.edu) - - * hppa.h: Add gfw and gfr to the opcode table. - -Wed Sep 29 16:23:00 1993 K. Richard Pixley (rich@sendai.cygnus.com) - - * m88k.h: extended to handle m88110. - -Tue Sep 28 19:19:08 1993 Jeffrey A Law (law@snake.cs.utah.edu) - - * hppa.h (be, ble): Use operand type 'z' to denote absolute branch - addresses. - -Tue Sep 14 14:04:35 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * i960.h (i960_opcodes): Properly bracket initializers. - -Mon Sep 13 12:50:52 1993 K. Richard Pixley (rich@sendai.cygnus.com) - - * m88k.h (BOFLAG): rewrite to avoid nested comment. - -Mon Sep 13 15:46:06 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * m68k.h (two): Protect second argument with parentheses. - -Fri Sep 10 16:29:47 1993 Ken Raeburn (raeburn@cambridge.cygnus.com) - - * i386.h (i386_optab): Added new instruction "rsm" (for i386sl). - Deleted old in/out instructions in "#if 0" section. - -Thu Sep 9 17:42:19 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * i386.h (i386_optab): Properly bracket initializers. - -Wed Aug 25 13:50:56 1993 Ken Raeburn (raeburn@cambridge.cygnus.com) - - * hppa.h (pa_opcode): Use '|' for movb and movib insns. (From - Jeff Law, law@cs.utah.edu). - -Mon Aug 23 16:55:03 1993 Ken Raeburn (raeburn@cambridge.cygnus.com) - - * i386.h (lcall): Accept Imm32 operand also. - -Mon Aug 23 12:43:11 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * mips.h (M_ABSU): Removed (absolute value of unsigned number??). - (M_DABS): Added. - -Thu Aug 19 15:08:37 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * mips.h (INSN_*): Changed values. Removed unused definitions. - Added INSN_COND_BRANCH_LIKELY, INSN_ISA2 and INSN_ISA3. Split - INSN_LOAD_DELAY into INSN_LOAD_MEMORY_DELAY and - INSN_LOAD_COPROC_DELAY. Split INSN_COPROC_DELAY into - INSN_COPROC_MOVE_DELAY and INSN_COPROC_MEMORY_DELAY. - (M_*): Added new values for r6000 and r4000 macros. - (ANY_DELAY): Removed. - -Wed Aug 18 15:37:48 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * mips.h: Added M_LI_S and M_LI_SS. - -Tue Aug 17 07:08:08 1993 Steve Chamberlain (sac@phydeaux.cygnus.com) - - * h8300.h: Get some rare mov.bs correct. - -Thu Aug 5 09:15:17 1993 Jim Kingdon (kingdon@lioth.cygnus.com) - - * sparc.h: Don't define const ourself; rely on ansidecl.h having - been included. - -Fri Jul 30 18:41:11 1993 John Gilmore (gnu@cygnus.com) - - * sparc.h (F_JSR, F_UNBR, F_CONDBR): Add new flags to mark - jump instructions, for use in disassemblers. - -Thu Jul 22 07:25:27 1993 Ian Lance Taylor (ian@cygnus.com) - - * m88k.h: Make bitfields just unsigned, not unsigned long or - unsigned short. - -Wed Jul 21 11:55:31 1993 Jim Kingdon (kingdon@deneb.cygnus.com) - - * hppa.h: New argument type 'y'. Use in various float instructions. - -Mon Jul 19 17:17:03 1993 Jim Kingdon (kingdon@deneb.cygnus.com) - - * hppa.h (break): First immediate field is unsigned. - - * hppa.h: Add rfir instruction. - -Sun Jul 18 16:28:08 1993 Jim Kingdon (kingdon@rtl.cygnus.com) - - * mips.h: Split the actual table out into ../../opcodes/mips-opc.c. - -Fri Jul 16 09:59:29 1993 Ian Lance Taylor (ian@cygnus.com) - - * mips.h: Reworked the hazard information somewhat, and fixed some - bugs in the instruction hazard descriptions. - -Thu Jul 15 12:42:01 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * m88k.h: Corrected a couple of opcodes. - -Tue Jul 6 15:17:35 1993 Ian Lance Taylor (ian@cygnus.com) - - * mips.h: Replaced with version from Ralph Campbell and OSF. The - new version includes instruction hazard information, but is - otherwise reasonably similar. - -Thu Jul 1 20:36:17 1993 Doug Evans (dje@canuck.cygnus.com) - - * h8300.h: Fix typo in UNOP3 (affected sh[al][lr].l). - -Fri Jun 11 18:38:44 1993 Ken Raeburn (raeburn@cygnus.com) - - Patches from Jeff Law, law@cs.utah.edu: - * hppa.h: Clean up some of the OLD_TABLE, non-OLD_TABLE braindamage. - Make the tables be the same for the following instructions: - "bb", "addb[tf]", "addib[tf]", "add", "add[loc]", "addco", - "sh[123]add", "sh[123]add[lo]", "sub", "sub[obt]", "sub[bt]o", - "ds", "comclr", "addi", "addi[ot]", "addito", "subi", "subio", - "comiclr", "fadd", "fsub", "fmpy", "fdiv", "fsqrt", "fabs", - "frnd", "fcpy", "fcnvff", "fcnvxf", "fcnvfx", "fcnvfxt", - "fcmp", and "ftest". - - * hppa.h: Make new and old tables the same for "break", "mtctl", - "mfctl", "bb", "ssm", "rsm", "xmpyu", "fmpyadd", "fmpysub". - Fix typo in last patch. Collapse several #ifdefs into a - single #ifdef. - - * hppa.h: Delete remaining OLD_TABLE code. Bring some - of the comments up-to-date. - - * hppa.h: Update "free list" of letters and update - comments describing each letter's function. - -Thu Jul 8 09:05:26 1993 Doug Evans (dje@canuck.cygnus.com) - - * h8300.h: Lots of little fixes for the h8/300h. - -Tue Jun 8 12:16:03 1993 Steve Chamberlain (sac@phydeaux.cygnus.com) - - Support for H8/300-H - * h8300.h: Lots of new opcodes. - -Fri Jun 4 15:41:37 1993 Steve Chamberlain (sac@phydeaux.cygnus.com) - - * h8300.h: checkpoint, includes H8/300-H opcodes. - -Thu Jun 3 15:42:59 1993 Stu Grossman (grossman@cygnus.com) - - * Patches from Jeffrey Law <law@cs.utah.edu>. - * hppa.h: Rework single precision FP - instructions so that they correctly disassemble code - PA1.1 code. - -Thu May 27 19:21:22 1993 Bruce Bauman (boot@osf.org) - - * i386.h (i386_optab, mov pattern): Remove Mem16 restriction from - mov to allow instructions like mov ss,xyz(ecx) to assemble. - -Tue May 25 00:39:40 1993 Ken Raeburn (raeburn@cygnus.com) - - * hppa.h: Use new version from Utah if OLD_TABLE isn't defined; - gdb will define it for now. - -Mon May 24 15:20:06 1993 Ken Raeburn (raeburn@cambridge.cygnus.com) - - * sparc.h: Don't end enumerator list with comma. - -Fri May 14 15:15:50 1993 Ian Lance Taylor (ian@cygnus.com) - - * Based on patches from davidj@ICSI.Berkeley.EDU (David Johnson): - * mips.h (OP_MASK_COPZ, OP_SH_COPZ): Define. - ("bc2t"): Correct typo. - ("[ls]wc[023]"): Use T rather than t. - ("c[0123]"): Define general coprocessor instructions. - -Mon May 10 06:02:25 1993 Ken Raeburn (raeburn@kr-pc.cygnus.com) - - * m68k.h: Move split point for gcc compilation more towards - middle. - -Fri Apr 9 13:26:16 1993 Jim Kingdon (kingdon@cygnus.com) - - * rs6k.h: Clean up instructions for primary opcode 19 (many were - simply wrong, ics, rfi, & rfsvc were missing). - Add "a" to opr_ext for "bb". Doc fix. - -Thu Mar 18 13:45:31 1993 Per Bothner (bothner@rtl.cygnus.com) - - * i386.h: 486 extensions from John Hassey (hassey@dg-rtp.dg.com). - * mips.h: Add casts, to suppress warnings about shifting too much. - * m68k.h: Document the placement code '9'. - -Thu Feb 18 02:03:14 1993 John Gilmore (gnu@cygnus.com) - - * m68k.h (BREAK_UP_BIG_DECL, AND_OTHER_PART): Add kludge which - allows callers to break up the large initialized struct full of - opcodes into two half-sized ones. This permits GCC to compile - this module, since it takes exponential space for initializers. - (numopcodes, endop): Revise to use AND_OTHER_PART in size calcs. - -Thu Feb 4 02:06:56 1993 John Gilmore (gnu@cygnus.com) - - * a29k.h: Remove RCS crud, update GPL to v2, update copyrights. - * convex.h: Added, from GDB's convx-opcode.h. Added CONST to all - initialized structs in it. - -Thu Jan 28 21:32:22 1993 John Gilmore (gnu@cygnus.com) - - Delta 88 changes inspired by Carl Greco, <cgreco@Creighton.Edu>: - * m88k.h (PMEM): Avoid previous definition from <sys/param.h>. - (AND): Change to AND_ to avoid ansidecl.h `AND' conflict. - -Sat Jan 23 18:10:49 PST 1993 Ralph Campbell (ralphc@pyramid.com) - - * mips.h: document "i" and "j" operands correctly. - -Thu Jan 7 15:58:13 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * mips.h: Removed endianness dependency. - -Sun Jan 3 14:13:35 1993 Steve Chamberlain (sac@thepub.cygnus.com) - - * h8300.h: include info on number of cycles per instruction. - -Mon Dec 21 21:29:08 1992 Stu Grossman (grossman at cygnus.com) - - * hppa.h: Move handy aliases to the front. Fix masks for extract - and deposit instructions. - -Sat Dec 12 16:09:48 1992 Ian Lance Taylor (ian@cygnus.com) - - * i386.h: accept shld and shrd both with and without the shift - count argument, which is always %cl. - -Fri Nov 27 17:13:18 1992 Ken Raeburn (raeburn at cygnus.com) - - * i386.h (i386_optab_end, i386_regtab_end): Now const. - (one_byte_segment_defaults, two_byte_segment_defaults, - i386_prefixtab_end): Ditto. - -Mon Nov 23 10:47:25 1992 Ken Raeburn (raeburn@cygnus.com) - - * vax.h (bb*): Use "v" (bitfield type), not "a" (address operand) - for operand 2; from John Carr, jfc@dsg.dec.com. - -Wed Nov 4 07:36:49 1992 Ken Raeburn (raeburn@cygnus.com) - - * m68k.h: Define FIXED_SIZE_BRANCH, so bsr and bra instructions - always use 16-bit offsets. Makes calculated-size jump tables - feasible. - -Fri Oct 16 22:52:43 1992 Ken Raeburn (raeburn@cygnus.com) - - * i386.h: Fix one-operand forms of in* and out* patterns. - -Tue Sep 22 14:08:14 1992 Ken Raeburn (raeburn@cambridge.cygnus.com) - - * m68k.h: Added CPU32 support. - -Tue Sep 22 00:38:41 1992 John Gilmore (gnu@cygnus.com) - - * mips.h (break): Disassemble the argument. Patch from - jonathan@cs.stanford.edu (Jonathan Stone). - -Wed Sep 9 11:25:28 1992 Ian Lance Taylor (ian@cygnus.com) - - * m68k.h: merged Motorola and MIT syntax. - -Thu Sep 3 09:33:22 1992 Steve Chamberlain (sac@thepub.cygnus.com) - - * m68k.h (pmove): make the tests less strict, the 68k book is - wrong. - -Tue Aug 25 23:25:19 1992 Ken Raeburn (raeburn@cambridge.cygnus.com) - - * m68k.h (m68ec030): Defined as alias for 68030. - (m68k_opcodes): New type characters "3" for 68030 MMU regs and "t" - for immediate 0-7 added. Set up some opcodes (ptest, bkpt) to use - them. Tightened description of "fmovex" to distinguish it from - some "pmove" encodings. Added "pmove" for 68030 MMU regs, cleaned - up descriptions that claimed versions were available for chips not - supporting them. Added "pmovefd". - -Mon Aug 24 12:04:51 1992 Steve Chamberlain (sac@thepub.cygnus.com) - - * m68k.h: fix where the . goes in divull - -Wed Aug 19 11:22:24 1992 Ian Lance Taylor (ian@cygnus.com) - - * m68k.h: the cas2 instruction is supposed to be written with - indirection on the last two operands, which can be either data or - address registers. Added a new operand type 'r' which accepts - either register type. Added new cases for cas2l and cas2w which - use them. Corrected masks for cas2 which failed to recognize use - of address register. - -Fri Aug 14 14:20:38 1992 Per Bothner (bothner@cygnus.com) - - * m68k.h: Merged in patches (mostly m68040-specific) from - Colin Smith <colin@wrs.com>. - - * m68k.h: Merged m68kmri.h and m68k.h (using the former as a - base). Also cleaned up duplicates, re-ordered instructions for - the sake of dis-assembling (so aliases come after standard names). - * m68kmri.h: Now just defines some macros, and #includes m68k.h. - -Wed Aug 12 16:38:15 1992 Steve Chamberlain (sac@thepub.cygnus.com) - - * m68kmri.h: added various opcodes. Moved jbxx to bxxes. Filled in - all missing .s - -Mon Aug 10 23:22:33 1992 Ken Raeburn (raeburn@cygnus.com) - - * sparc.h: Moved tables to BFD library. - - * i386.h (i386_optab): Add fildq, fistpq aliases used by gcc. - -Sun Jun 28 13:29:03 1992 Fred Fish (fnf@cygnus.com) - - * h8300.h: Finish filling in all the holes in the opcode table, - so that the Lucid C compiler can digest this as well... - -Fri Jun 26 21:27:17 1992 John Gilmore (gnu at cygnus.com) - - * i386.h: Add setc, setnc, addr16, data16, repz, repnz aliases. - Fix opcodes on various sizes of fild/fist instructions - (16bit=no suffix, 32bit="l" suffix, 64bit="ll" suffix). - Use tabs to indent for comments. Fixes suggested by Minh Tran-Le. - -Thu Jun 25 16:13:26 1992 Stu Grossman (grossman at cygnus.com) - - * h8300.h: Fill in all the holes in the opcode table so that the - losing HPUX C compiler can digest this... - -Thu Jun 11 12:15:25 1992 John Gilmore (gnu at cygnus.com) - - * mips.h: Fix decoding of coprocessor instructions, somewhat. - (Fix by Eric Anderson, 3jean@maas-neotek.arc.nasa.gov.) - -Thu May 28 11:17:44 1992 Jim Wilson (wilson@sphagnum.cygnus.com) - - * sparc.h: Add new architecture variant sparclite; add its scan - and divscc opcodes. Define ARCHITECTURES_CONFLICT_P macro. - -Tue May 5 14:23:27 1992 Per Bothner (bothner@rtl.cygnus.com) - - * mips.h: Add some more opcode synonyms (from Frank Yellin, - fy@lucid.com). - -Thu Apr 16 18:25:26 1992 Per Bothner (bothner@cygnus.com) - - * rs6k.h: New version from IBM (Metin). - -Thu Apr 9 00:31:19 1992 Per Bothner (bothner@rtl.cygnus.com) - - * rs6k.h: Fix incorrect extended opcode for instructions `fm' - and `fd'. (From metin@ibmpa.awdpa.ibm.com (Metin G. Ozisik).) - -Tue Apr 7 13:38:47 1992 Stu Grossman (grossman at cygnus.com) - - * rs6k.h: Move from ../../gdb/rs6k-opcode.h. - -Fri Apr 3 11:30:20 1992 Fred Fish (fnf@cygnus.com) - - * m68k.h (one, two): Cast macro args to unsigned to suppress - complaints from compiler and lint about integer overflow during - shift. - -Sun Mar 29 12:22:08 1992 John Gilmore (gnu at cygnus.com) - - * sparc.h (OP): Avoid signed overflow when shifting to high order bit. - -Fri Mar 6 00:22:38 1992 John Gilmore (gnu at cygnus.com) - - * mips.h: Make bitfield layout depend on the HOST compiler, - not on the TARGET system. - -Fri Feb 21 01:29:51 1992 K. Richard Pixley (rich@cygnus.com) - - * i386.h: added inb, inw, outb, outw opcodes, added att syntax for - scmp, slod, smov, ssca, ssto. Curtesy Minh Tran-Le - <TRANLE@INTELLICORP.COM>. - -Thu Jan 30 07:31:44 1992 Steve Chamberlain (sac at rtl.cygnus.com) - - * h8300.h: turned op_type enum into #define list - -Thu Jan 30 01:07:24 1992 John Gilmore (gnu at cygnus.com) - - * sparc.h: Remove "cypress" architecture. Remove "fitox" and - similar instructions -- they've been renamed to "fitoq", etc. - REALLY fix tsubcctv. Fix "fcmpeq" and "fcmpq" which had wrong - number of arguments. - * h8300.h: Remove extra ; which produces compiler warning. - -Tue Jan 28 22:59:22 1992 Stu Grossman (grossman at cygnus.com) - - * sparc.h: fix opcode for tsubcctv. - -Tue Jan 7 17:19:39 1992 K. Richard Pixley (rich at cygnus.com) - - * sparc.h: fba and cba are now aliases for fb and cb respectively. - -Fri Dec 27 10:55:50 1991 Per Bothner (bothner at cygnus.com) - - * sparc.h (nop): Made the 'lose' field be even tighter, - so only a standard 'nop' is disassembled as a nop. - -Sun Dec 22 12:18:18 1991 Michael Tiemann (tiemann at cygnus.com) - - * sparc.h (nop): Add RD_GO to `lose' so that only %g0 in dest is - disassembled as a nop. - -Wed Dec 18 17:19:44 1991 Stu Grossman (grossman at cygnus.com) - - * m68k.h, sparc.h: ANSIfy enums. - -Tue Dec 10 00:22:20 1991 K. Richard Pixley (rich at rtl.cygnus.com) - - * sparc.h: fix a typo. - -Sat Nov 30 20:40:51 1991 Steve Chamberlain (sac at rtl.cygnus.com) - - * a29k.h, arm.h, h8300.h, i386.h, i860.h, i960.h , m68k.h, - m88k.h, mips.h , np1.h, ns32k.h, pn.h, pyr.h, sparc.h, tahoe.h, - vax.h: Renamed from ../<foo>-opcode.h. - - -Copyright (C) 1991-2003 Free Software Foundation, Inc. - -Copying and distribution of this file, with or without modification, -are permitted in any medium without royalty provided the copyright -notice and this notice are preserved. - -Local Variables: -mode: change-log -left-margin: 8 -fill-column: 74 -version-control: never -End: - diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h deleted file mode 100644 index eaf3cda..0000000 --- a/include/opcode/aarch64.h +++ /dev/null @@ -1,932 +0,0 @@ -/* AArch64 assembler/disassembler support. - - Copyright 2009, 2010, 2011, 2012, 2013 Free Software Foundation, Inc. - Contributed by ARM Ltd. - - This file is part of GNU Binutils. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the license, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; see the file COPYING3. If not, - see <http://www.gnu.org/licenses/>. */ - -#ifndef OPCODE_AARCH64_H -#define OPCODE_AARCH64_H - -#include "bfd.h" -#include "bfd_stdint.h" -#include <assert.h> -#include <stdlib.h> - -/* The offset for pc-relative addressing is currently defined to be 0. */ -#define AARCH64_PCREL_OFFSET 0 - -typedef uint32_t aarch64_insn; - -/* The following bitmasks control CPU features. */ -#define AARCH64_FEATURE_V8 0x00000001 /* All processors. */ -#define AARCH64_FEATURE_CRYPTO 0x00010000 /* Crypto instructions. */ -#define AARCH64_FEATURE_FP 0x00020000 /* FP instructions. */ -#define AARCH64_FEATURE_SIMD 0x00040000 /* SIMD instructions. */ -#define AARCH64_FEATURE_CRC 0x00080000 /* CRC instructions. */ - -/* Architectures are the sum of the base and extensions. */ -#define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \ - AARCH64_FEATURE_FP \ - | AARCH64_FEATURE_SIMD) -#define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0) -#define AARCH64_ANY AARCH64_FEATURE (-1, 0) /* Any basic core. */ - -/* CPU-specific features. */ -typedef unsigned long aarch64_feature_set; - -#define AARCH64_CPU_HAS_FEATURE(CPU,FEAT) \ - (((CPU) & (FEAT)) != 0) - -#define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2) \ - do \ - { \ - (TARG) = (F1) | (F2); \ - } \ - while (0) - -#define AARCH64_CLEAR_FEATURE(TARG,F1,F2) \ - do \ - { \ - (TARG) = (F1) &~ (F2); \ - } \ - while (0) - -#define AARCH64_FEATURE(core,coproc) ((core) | (coproc)) - -#define AARCH64_OPCODE_HAS_FEATURE(OPC,FEAT) \ - (((OPC) & (FEAT)) != 0) - -enum aarch64_operand_class -{ - AARCH64_OPND_CLASS_NIL, - AARCH64_OPND_CLASS_INT_REG, - AARCH64_OPND_CLASS_MODIFIED_REG, - AARCH64_OPND_CLASS_FP_REG, - AARCH64_OPND_CLASS_SIMD_REG, - AARCH64_OPND_CLASS_SIMD_ELEMENT, - AARCH64_OPND_CLASS_SISD_REG, - AARCH64_OPND_CLASS_SIMD_REGLIST, - AARCH64_OPND_CLASS_CP_REG, - AARCH64_OPND_CLASS_ADDRESS, - AARCH64_OPND_CLASS_IMMEDIATE, - AARCH64_OPND_CLASS_SYSTEM, -}; - -/* Operand code that helps both parsing and coding. - Keep AARCH64_OPERANDS synced. */ - -enum aarch64_opnd -{ - AARCH64_OPND_NIL, /* no operand---MUST BE FIRST!*/ - - AARCH64_OPND_Rd, /* Integer register as destination. */ - AARCH64_OPND_Rn, /* Integer register as source. */ - AARCH64_OPND_Rm, /* Integer register as source. */ - AARCH64_OPND_Rt, /* Integer register used in ld/st instructions. */ - AARCH64_OPND_Rt2, /* Integer register used in ld/st pair instructions. */ - AARCH64_OPND_Rs, /* Integer register used in ld/st exclusive. */ - AARCH64_OPND_Ra, /* Integer register used in ddp_3src instructions. */ - AARCH64_OPND_Rt_SYS, /* Integer register used in system instructions. */ - - AARCH64_OPND_Rd_SP, /* Integer Rd or SP. */ - AARCH64_OPND_Rn_SP, /* Integer Rn or SP. */ - AARCH64_OPND_Rm_EXT, /* Integer Rm extended. */ - AARCH64_OPND_Rm_SFT, /* Integer Rm shifted. */ - - AARCH64_OPND_Fd, /* Floating-point Fd. */ - AARCH64_OPND_Fn, /* Floating-point Fn. */ - AARCH64_OPND_Fm, /* Floating-point Fm. */ - AARCH64_OPND_Fa, /* Floating-point Fa. */ - AARCH64_OPND_Ft, /* Floating-point Ft. */ - AARCH64_OPND_Ft2, /* Floating-point Ft2. */ - - AARCH64_OPND_Sd, /* AdvSIMD Scalar Sd. */ - AARCH64_OPND_Sn, /* AdvSIMD Scalar Sn. */ - AARCH64_OPND_Sm, /* AdvSIMD Scalar Sm. */ - - AARCH64_OPND_Vd, /* AdvSIMD Vector Vd. */ - AARCH64_OPND_Vn, /* AdvSIMD Vector Vn. */ - AARCH64_OPND_Vm, /* AdvSIMD Vector Vm. */ - AARCH64_OPND_VdD1, /* AdvSIMD <Vd>.D[1]; for FMOV only. */ - AARCH64_OPND_VnD1, /* AdvSIMD <Vn>.D[1]; for FMOV only. */ - AARCH64_OPND_Ed, /* AdvSIMD Vector Element Vd. */ - AARCH64_OPND_En, /* AdvSIMD Vector Element Vn. */ - AARCH64_OPND_Em, /* AdvSIMD Vector Element Vm. */ - AARCH64_OPND_LVn, /* AdvSIMD Vector register list used in e.g. TBL. */ - AARCH64_OPND_LVt, /* AdvSIMD Vector register list used in ld/st. */ - AARCH64_OPND_LVt_AL, /* AdvSIMD Vector register list for loading single - structure to all lanes. */ - AARCH64_OPND_LEt, /* AdvSIMD Vector Element list. */ - - AARCH64_OPND_Cn, /* Co-processor register in CRn field. */ - AARCH64_OPND_Cm, /* Co-processor register in CRm field. */ - - AARCH64_OPND_IDX, /* AdvSIMD EXT index operand. */ - AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left. */ - AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right. */ - AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift. */ - AARCH64_OPND_SIMD_IMM_SFT, /* AdvSIMD modified immediate with shift. */ - AARCH64_OPND_SIMD_FPIMM,/* AdvSIMD 8-bit fp immediate. */ - AARCH64_OPND_SHLL_IMM,/* Immediate shift for AdvSIMD SHLL instruction - (no encoding). */ - AARCH64_OPND_IMM0, /* Immediate for #0. */ - AARCH64_OPND_FPIMM0, /* Immediate for #0.0. */ - AARCH64_OPND_FPIMM, /* Floating-point Immediate. */ - AARCH64_OPND_IMMR, /* Immediate #<immr> in e.g. BFM. */ - AARCH64_OPND_IMMS, /* Immediate #<imms> in e.g. BFM. */ - AARCH64_OPND_WIDTH, /* Immediate #<width> in e.g. BFI. */ - AARCH64_OPND_IMM, /* Immediate. */ - AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field. */ - AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field. */ - AARCH64_OPND_UIMM4, /* Unsigned 4-bit immediate in the CRm field. */ - AARCH64_OPND_UIMM7, /* Unsigned 7-bit immediate in the CRm:op2 fields. */ - AARCH64_OPND_BIT_NUM, /* Immediate. */ - AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions. */ - AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions. */ - AARCH64_OPND_NZCV, /* Flag bit specifier giving an alternative value for - each condition flag. */ - - AARCH64_OPND_LIMM, /* Logical Immediate. */ - AARCH64_OPND_AIMM, /* Arithmetic immediate. */ - AARCH64_OPND_HALF, /* #<imm16>{, LSL #<shift>} operand in move wide. */ - AARCH64_OPND_FBITS, /* FP #<fbits> operand in e.g. SCVTF */ - AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias. */ - - AARCH64_OPND_COND, /* Standard condition as the last operand. */ - - AARCH64_OPND_ADDR_ADRP, /* Memory address for ADRP */ - AARCH64_OPND_ADDR_PCREL14, /* 14-bit PC-relative address for e.g. TBZ. */ - AARCH64_OPND_ADDR_PCREL19, /* 19-bit PC-relative address for e.g. LDR. */ - AARCH64_OPND_ADDR_PCREL21, /* 21-bit PC-relative address for e.g. ADR. */ - AARCH64_OPND_ADDR_PCREL26, /* 26-bit PC-relative address for e.g. BL. */ - - AARCH64_OPND_ADDR_SIMPLE, /* Address of ld/st exclusive. */ - AARCH64_OPND_ADDR_REGOFF, /* Address of register offset. */ - AARCH64_OPND_ADDR_SIMM7, /* Address of signed 7-bit immediate. */ - AARCH64_OPND_ADDR_SIMM9, /* Address of signed 9-bit immediate. */ - AARCH64_OPND_ADDR_SIMM9_2, /* Same as the above, but the immediate is - negative or unaligned and there is - no writeback allowed. This operand code - is only used to support the programmer- - friendly feature of using LDR/STR as the - the mnemonic name for LDUR/STUR instructions - wherever there is no ambiguity. */ - AARCH64_OPND_ADDR_UIMM12, /* Address of unsigned 12-bit immediate. */ - AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures. */ - AARCH64_OPND_SIMD_ADDR_POST, /* Address of ld/st multiple post-indexed. */ - - AARCH64_OPND_SYSREG, /* System register operand. */ - AARCH64_OPND_PSTATEFIELD, /* PSTATE field name operand. */ - AARCH64_OPND_SYSREG_AT, /* System register <at_op> operand. */ - AARCH64_OPND_SYSREG_DC, /* System register <dc_op> operand. */ - AARCH64_OPND_SYSREG_IC, /* System register <ic_op> operand. */ - AARCH64_OPND_SYSREG_TLBI, /* System register <tlbi_op> operand. */ - AARCH64_OPND_BARRIER, /* Barrier operand. */ - AARCH64_OPND_BARRIER_ISB, /* Barrier operand for ISB. */ - AARCH64_OPND_PRFOP, /* Prefetch operation. */ -}; - -/* Qualifier constrains an operand. It either specifies a variant of an - operand type or limits values available to an operand type. - - N.B. Order is important; keep aarch64_opnd_qualifiers synced. */ - -enum aarch64_opnd_qualifier -{ - /* Indicating no further qualification on an operand. */ - AARCH64_OPND_QLF_NIL, - - /* Qualifying an operand which is a general purpose (integer) register; - indicating the operand data size or a specific register. */ - AARCH64_OPND_QLF_W, /* Wn, WZR or WSP. */ - AARCH64_OPND_QLF_X, /* Xn, XZR or XSP. */ - AARCH64_OPND_QLF_WSP, /* WSP. */ - AARCH64_OPND_QLF_SP, /* SP. */ - - /* Qualifying an operand which is a floating-point register, a SIMD - vector element or a SIMD vector element list; indicating operand data - size or the size of each SIMD vector element in the case of a SIMD - vector element list. - These qualifiers are also used to qualify an address operand to - indicate the size of data element a load/store instruction is - accessing. - They are also used for the immediate shift operand in e.g. SSHR. Such - a use is only for the ease of operand encoding/decoding and qualifier - sequence matching; such a use should not be applied widely; use the value - constraint qualifiers for immediate operands wherever possible. */ - AARCH64_OPND_QLF_S_B, - AARCH64_OPND_QLF_S_H, - AARCH64_OPND_QLF_S_S, - AARCH64_OPND_QLF_S_D, - AARCH64_OPND_QLF_S_Q, - - /* Qualifying an operand which is a SIMD vector register or a SIMD vector - register list; indicating register shape. - They are also used for the immediate shift operand in e.g. SSHR. Such - a use is only for the ease of operand encoding/decoding and qualifier - sequence matching; such a use should not be applied widely; use the value - constraint qualifiers for immediate operands wherever possible. */ - AARCH64_OPND_QLF_V_8B, - AARCH64_OPND_QLF_V_16B, - AARCH64_OPND_QLF_V_4H, - AARCH64_OPND_QLF_V_8H, - AARCH64_OPND_QLF_V_2S, - AARCH64_OPND_QLF_V_4S, - AARCH64_OPND_QLF_V_1D, - AARCH64_OPND_QLF_V_2D, - AARCH64_OPND_QLF_V_1Q, - - /* Constraint on value. */ - AARCH64_OPND_QLF_imm_0_7, - AARCH64_OPND_QLF_imm_0_15, - AARCH64_OPND_QLF_imm_0_31, - AARCH64_OPND_QLF_imm_0_63, - AARCH64_OPND_QLF_imm_1_32, - AARCH64_OPND_QLF_imm_1_64, - - /* Indicate whether an AdvSIMD modified immediate operand is shift-zeros - or shift-ones. */ - AARCH64_OPND_QLF_LSL, - AARCH64_OPND_QLF_MSL, - - /* Special qualifier helping retrieve qualifier information during the - decoding time (currently not in use). */ - AARCH64_OPND_QLF_RETRIEVE, -}; - -/* Instruction class. */ - -enum aarch64_insn_class -{ - addsub_carry, - addsub_ext, - addsub_imm, - addsub_shift, - asimdall, - asimddiff, - asimdelem, - asimdext, - asimdimm, - asimdins, - asimdmisc, - asimdperm, - asimdsame, - asimdshf, - asimdtbl, - asisddiff, - asisdelem, - asisdlse, - asisdlsep, - asisdlso, - asisdlsop, - asisdmisc, - asisdone, - asisdpair, - asisdsame, - asisdshf, - bitfield, - branch_imm, - branch_reg, - compbranch, - condbranch, - condcmp_imm, - condcmp_reg, - condsel, - cryptoaes, - cryptosha2, - cryptosha3, - dp_1src, - dp_2src, - dp_3src, - exception, - extract, - float2fix, - float2int, - floatccmp, - floatcmp, - floatdp1, - floatdp2, - floatdp3, - floatimm, - floatsel, - ldst_immpost, - ldst_immpre, - ldst_imm9, /* immpost or immpre */ - ldst_pos, - ldst_regoff, - ldst_unpriv, - ldst_unscaled, - ldstexcl, - ldstnapair_offs, - ldstpair_off, - ldstpair_indexed, - loadlit, - log_imm, - log_shift, - movewide, - pcreladdr, - ic_system, - testbranch, -}; - -/* Opcode enumerators. */ - -enum aarch64_op -{ - OP_NIL, - OP_STRB_POS, - OP_LDRB_POS, - OP_LDRSB_POS, - OP_STRH_POS, - OP_LDRH_POS, - OP_LDRSH_POS, - OP_STR_POS, - OP_LDR_POS, - OP_STRF_POS, - OP_LDRF_POS, - OP_LDRSW_POS, - OP_PRFM_POS, - - OP_STURB, - OP_LDURB, - OP_LDURSB, - OP_STURH, - OP_LDURH, - OP_LDURSH, - OP_STUR, - OP_LDUR, - OP_STURV, - OP_LDURV, - OP_LDURSW, - OP_PRFUM, - - OP_LDR_LIT, - OP_LDRV_LIT, - OP_LDRSW_LIT, - OP_PRFM_LIT, - - OP_ADD, - OP_B, - OP_BL, - - OP_MOVN, - OP_MOVZ, - OP_MOVK, - - OP_MOV_IMM_LOG, /* MOV alias for moving bitmask immediate. */ - OP_MOV_IMM_WIDE, /* MOV alias for moving wide immediate. */ - OP_MOV_IMM_WIDEN, /* MOV alias for moving wide immediate (negated). */ - - OP_MOV_V, /* MOV alias for moving vector register. */ - - OP_ASR_IMM, - OP_LSR_IMM, - OP_LSL_IMM, - - OP_BIC, - - OP_UBFX, - OP_BFXIL, - OP_SBFX, - OP_SBFIZ, - OP_BFI, - OP_UBFIZ, - OP_UXTB, - OP_UXTH, - OP_UXTW, - - OP_CINC, - OP_CINV, - OP_CNEG, - OP_CSET, - OP_CSETM, - - OP_FCVT, - OP_FCVTN, - OP_FCVTN2, - OP_FCVTL, - OP_FCVTL2, - OP_FCVTXN_S, /* Scalar version. */ - - OP_ROR_IMM, - - OP_SXTL, - OP_SXTL2, - OP_UXTL, - OP_UXTL2, - - OP_TOTAL_NUM, /* Pseudo. */ -}; - -/* Maximum number of operands an instruction can have. */ -#define AARCH64_MAX_OPND_NUM 6 -/* Maximum number of qualifier sequences an instruction can have. */ -#define AARCH64_MAX_QLF_SEQ_NUM 10 -/* Operand qualifier typedef; optimized for the size. */ -typedef unsigned char aarch64_opnd_qualifier_t; -/* Operand qualifier sequence typedef. */ -typedef aarch64_opnd_qualifier_t \ - aarch64_opnd_qualifier_seq_t [AARCH64_MAX_OPND_NUM]; - -/* FIXME: improve the efficiency. */ -static inline bfd_boolean -empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers) -{ - int i; - for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i) - if (qualifiers[i] != AARCH64_OPND_QLF_NIL) - return FALSE; - return TRUE; -} - -/* This structure holds information for a particular opcode. */ - -struct aarch64_opcode -{ - /* The name of the mnemonic. */ - const char *name; - - /* The opcode itself. Those bits which will be filled in with - operands are zeroes. */ - aarch64_insn opcode; - - /* The opcode mask. This is used by the disassembler. This is a - mask containing ones indicating those bits which must match the - opcode field, and zeroes indicating those bits which need not - match (and are presumably filled in by operands). */ - aarch64_insn mask; - - /* Instruction class. */ - enum aarch64_insn_class iclass; - - /* Enumerator identifier. */ - enum aarch64_op op; - - /* Which architecture variant provides this instruction. */ - const aarch64_feature_set *avariant; - - /* An array of operand codes. Each code is an index into the - operand table. They appear in the order which the operands must - appear in assembly code, and are terminated by a zero. */ - enum aarch64_opnd operands[AARCH64_MAX_OPND_NUM]; - - /* A list of operand qualifier code sequence. Each operand qualifier - code qualifies the corresponding operand code. Each operand - qualifier sequence specifies a valid opcode variant and related - constraint on operands. */ - aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM]; - - /* Flags providing information about this instruction */ - uint32_t flags; -}; - -typedef struct aarch64_opcode aarch64_opcode; - -/* Table describing all the AArch64 opcodes. */ -extern aarch64_opcode aarch64_opcode_table[]; - -/* Opcode flags. */ -#define F_ALIAS (1 << 0) -#define F_HAS_ALIAS (1 << 1) -/* Disassembly preference priority 1-3 (the larger the higher). If nothing - is specified, it is the priority 0 by default, i.e. the lowest priority. */ -#define F_P1 (1 << 2) -#define F_P2 (2 << 2) -#define F_P3 (3 << 2) -/* Flag an instruction that is truly conditional executed, e.g. b.cond. */ -#define F_COND (1 << 4) -/* Instruction has the field of 'sf'. */ -#define F_SF (1 << 5) -/* Instruction has the field of 'size:Q'. */ -#define F_SIZEQ (1 << 6) -/* Floating-point instruction has the field of 'type'. */ -#define F_FPTYPE (1 << 7) -/* AdvSIMD scalar instruction has the field of 'size'. */ -#define F_SSIZE (1 << 8) -/* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q". */ -#define F_T (1 << 9) -/* Size of GPR operand in AdvSIMD instructions encoded in Q. */ -#define F_GPRSIZE_IN_Q (1 << 10) -/* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22. */ -#define F_LDS_SIZE (1 << 11) -/* Optional operand; assume maximum of 1 operand can be optional. */ -#define F_OPD0_OPT (1 << 12) -#define F_OPD1_OPT (2 << 12) -#define F_OPD2_OPT (3 << 12) -#define F_OPD3_OPT (4 << 12) -#define F_OPD4_OPT (5 << 12) -/* Default value for the optional operand when omitted from the assembly. */ -#define F_DEFAULT(X) (((X) & 0x1f) << 15) -/* Instruction that is an alias of another instruction needs to be - encoded/decoded by converting it to/from the real form, followed by - the encoding/decoding according to the rules of the real opcode. - This compares to the direct coding using the alias's information. - N.B. this flag requires F_ALIAS to be used together. */ -#define F_CONV (1 << 20) -/* Use together with F_ALIAS to indicate an alias opcode is a programmer - friendly pseudo instruction available only in the assembly code (thus will - not show up in the disassembly). */ -#define F_PSEUDO (1 << 21) -/* Instruction has miscellaneous encoding/decoding rules. */ -#define F_MISC (1 << 22) -/* Instruction has the field of 'N'; used in conjunction with F_SF. */ -#define F_N (1 << 23) -/* Opcode dependent field. */ -#define F_OD(X) (((X) & 0x7) << 24) -/* Next bit is 27. */ - -static inline bfd_boolean -alias_opcode_p (const aarch64_opcode *opcode) -{ - return (opcode->flags & F_ALIAS) ? TRUE : FALSE; -} - -static inline bfd_boolean -opcode_has_alias (const aarch64_opcode *opcode) -{ - return (opcode->flags & F_HAS_ALIAS) ? TRUE : FALSE; -} - -/* Priority for disassembling preference. */ -static inline int -opcode_priority (const aarch64_opcode *opcode) -{ - return (opcode->flags >> 2) & 0x3; -} - -static inline bfd_boolean -pseudo_opcode_p (const aarch64_opcode *opcode) -{ - return (opcode->flags & F_PSEUDO) != 0lu ? TRUE : FALSE; -} - -static inline bfd_boolean -optional_operand_p (const aarch64_opcode *opcode, unsigned int idx) -{ - return (((opcode->flags >> 12) & 0x7) == idx + 1) - ? TRUE : FALSE; -} - -static inline aarch64_insn -get_optional_operand_default_value (const aarch64_opcode *opcode) -{ - return (opcode->flags >> 15) & 0x1f; -} - -static inline unsigned int -get_opcode_dependent_value (const aarch64_opcode *opcode) -{ - return (opcode->flags >> 24) & 0x7; -} - -static inline bfd_boolean -opcode_has_special_coder (const aarch64_opcode *opcode) -{ - return (opcode->flags & (F_SF | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T - | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE - : FALSE; -} - -struct aarch64_name_value_pair -{ - const char * name; - aarch64_insn value; -}; - -extern const struct aarch64_name_value_pair aarch64_operand_modifiers []; -extern const struct aarch64_name_value_pair aarch64_sys_regs []; -extern const struct aarch64_name_value_pair aarch64_pstatefields []; -extern const struct aarch64_name_value_pair aarch64_barrier_options [16]; -extern const struct aarch64_name_value_pair aarch64_prfops [32]; - -typedef struct -{ - const char *template; - uint32_t value; - int has_xt; -} aarch64_sys_ins_reg; - -extern const aarch64_sys_ins_reg aarch64_sys_regs_ic []; -extern const aarch64_sys_ins_reg aarch64_sys_regs_dc []; -extern const aarch64_sys_ins_reg aarch64_sys_regs_at []; -extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi []; - -/* Shift/extending operator kinds. - N.B. order is important; keep aarch64_operand_modifiers synced. */ -enum aarch64_modifier_kind -{ - AARCH64_MOD_NONE, - AARCH64_MOD_MSL, - AARCH64_MOD_ROR, - AARCH64_MOD_ASR, - AARCH64_MOD_LSR, - AARCH64_MOD_LSL, - AARCH64_MOD_UXTB, - AARCH64_MOD_UXTH, - AARCH64_MOD_UXTW, - AARCH64_MOD_UXTX, - AARCH64_MOD_SXTB, - AARCH64_MOD_SXTH, - AARCH64_MOD_SXTW, - AARCH64_MOD_SXTX, -}; - -bfd_boolean -aarch64_extend_operator_p (enum aarch64_modifier_kind); - -enum aarch64_modifier_kind -aarch64_get_operand_modifier (const struct aarch64_name_value_pair *); -/* Condition. */ - -typedef struct -{ - /* A list of names with the first one as the disassembly preference; - terminated by NULL if fewer than 3. */ - const char *names[3]; - aarch64_insn value; -} aarch64_cond; - -extern const aarch64_cond aarch64_conds[16]; - -const aarch64_cond* get_cond_from_value (aarch64_insn value); -const aarch64_cond* get_inverted_cond (const aarch64_cond *cond); - -/* Structure representing an operand. */ - -struct aarch64_opnd_info -{ - enum aarch64_opnd type; - aarch64_opnd_qualifier_t qualifier; - int idx; - - union - { - struct - { - unsigned regno; - } reg; - struct - { - unsigned regno : 5; - unsigned index : 4; - } reglane; - /* e.g. LVn. */ - struct - { - unsigned first_regno : 5; - unsigned num_regs : 3; - /* 1 if it is a list of reg element. */ - unsigned has_index : 1; - /* Lane index; valid only when has_index is 1. */ - unsigned index : 4; - } reglist; - /* e.g. immediate or pc relative address offset. */ - struct - { - int64_t value; - unsigned is_fp : 1; - } imm; - /* e.g. address in STR (register offset). */ - struct - { - unsigned base_regno; - struct - { - union - { - int imm; - unsigned regno; - }; - unsigned is_reg; - } offset; - unsigned pcrel : 1; /* PC-relative. */ - unsigned writeback : 1; - unsigned preind : 1; /* Pre-indexed. */ - unsigned postind : 1; /* Post-indexed. */ - } addr; - const aarch64_cond *cond; - /* The encoding of the system register. */ - aarch64_insn sysreg; - /* The encoding of the PSTATE field. */ - aarch64_insn pstatefield; - const aarch64_sys_ins_reg *sysins_op; - const struct aarch64_name_value_pair *barrier; - const struct aarch64_name_value_pair *prfop; - }; - - /* Operand shifter; in use when the operand is a register offset address, - add/sub extended reg, etc. e.g. <R><m>{, <extend> {#<amount>}}. */ - struct - { - enum aarch64_modifier_kind kind; - int amount; - unsigned operator_present: 1; /* Only valid during encoding. */ - /* Value of the 'S' field in ld/st reg offset; used only in decoding. */ - unsigned amount_present: 1; - } shifter; - - unsigned skip:1; /* Operand is not completed if there is a fixup needed - to be done on it. In some (but not all) of these - cases, we need to tell libopcodes to skip the - constraint checking and the encoding for this - operand, so that the libopcodes can pick up the - right opcode before the operand is fixed-up. This - flag should only be used during the - assembling/encoding. */ - unsigned present:1; /* Whether this operand is present in the assembly - line; not used during the disassembly. */ -}; - -typedef struct aarch64_opnd_info aarch64_opnd_info; - -/* Structure representing an instruction. - - It is used during both the assembling and disassembling. The assembler - fills an aarch64_inst after a successful parsing and then passes it to the - encoding routine to do the encoding. During the disassembling, the - disassembler calls the decoding routine to decode a binary instruction; on a - successful return, such a structure will be filled with information of the - instruction; then the disassembler uses the information to print out the - instruction. */ - -struct aarch64_inst -{ - /* The value of the binary instruction. */ - aarch64_insn value; - - /* Corresponding opcode entry. */ - const aarch64_opcode *opcode; - - /* Condition for a truly conditional-executed instrutions, e.g. b.cond. */ - const aarch64_cond *cond; - - /* Operands information. */ - aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM]; -}; - -typedef struct aarch64_inst aarch64_inst; - -/* Diagnosis related declaration and interface. */ - -/* Operand error kind enumerators. - - AARCH64_OPDE_RECOVERABLE - Less severe error found during the parsing, very possibly because that - GAS has picked up a wrong instruction template for the parsing. - - AARCH64_OPDE_SYNTAX_ERROR - General syntax error; it can be either a user error, or simply because - that GAS is trying a wrong instruction template. - - AARCH64_OPDE_FATAL_SYNTAX_ERROR - Definitely a user syntax error. - - AARCH64_OPDE_INVALID_VARIANT - No syntax error, but the operands are not a valid combination, e.g. - FMOV D0,S0 - - AARCH64_OPDE_OUT_OF_RANGE - Error about some immediate value out of a valid range. - - AARCH64_OPDE_UNALIGNED - Error about some immediate value not properly aligned (i.e. not being a - multiple times of a certain value). - - AARCH64_OPDE_REG_LIST - Error about the register list operand having unexpected number of - registers. - - AARCH64_OPDE_OTHER_ERROR - Error of the highest severity and used for any severe issue that does not - fall into any of the above categories. - - The enumerators are only interesting to GAS. They are declared here (in - libopcodes) because that some errors are detected (and then notified to GAS) - by libopcodes (rather than by GAS solely). - - The first three errors are only deteced by GAS while the - AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as - only libopcodes has the information about the valid variants of each - instruction. - - The enumerators have an increasing severity. This is helpful when there are - multiple instruction templates available for a given mnemonic name (e.g. - FMOV); this mechanism will help choose the most suitable template from which - the generated diagnostics can most closely describe the issues, if any. */ - -enum aarch64_operand_error_kind -{ - AARCH64_OPDE_NIL, - AARCH64_OPDE_RECOVERABLE, - AARCH64_OPDE_SYNTAX_ERROR, - AARCH64_OPDE_FATAL_SYNTAX_ERROR, - AARCH64_OPDE_INVALID_VARIANT, - AARCH64_OPDE_OUT_OF_RANGE, - AARCH64_OPDE_UNALIGNED, - AARCH64_OPDE_REG_LIST, - AARCH64_OPDE_OTHER_ERROR -}; - -/* N.B. GAS assumes that this structure work well with shallow copy. */ -struct aarch64_operand_error -{ - enum aarch64_operand_error_kind kind; - int index; - const char *error; - int data[3]; /* Some data for extra information. */ -}; - -typedef struct aarch64_operand_error aarch64_operand_error; - -/* Encoding entrypoint. */ - -extern int -aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *, - aarch64_insn *, aarch64_opnd_qualifier_t *, - aarch64_operand_error *); - -extern const aarch64_opcode * -aarch64_replace_opcode (struct aarch64_inst *, - const aarch64_opcode *); - -/* Given the opcode enumerator OP, return the pointer to the corresponding - opcode entry. */ - -extern const aarch64_opcode * -aarch64_get_opcode (enum aarch64_op); - -/* Generate the string representation of an operand. */ -extern void -aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *, - const aarch64_opnd_info *, int, int *, bfd_vma *); - -/* Miscellaneous interface. */ - -extern int -aarch64_operand_index (const enum aarch64_opnd *, enum aarch64_opnd); - -extern aarch64_opnd_qualifier_t -aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int, - const aarch64_opnd_qualifier_t, int); - -extern int -aarch64_num_of_operands (const aarch64_opcode *); - -extern int -aarch64_stack_pointer_p (const aarch64_opnd_info *); - -extern -int aarch64_zero_register_p (const aarch64_opnd_info *); - -/* Given an operand qualifier, return the expected data element size - of a qualified operand. */ -extern unsigned char -aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t); - -extern enum aarch64_operand_class -aarch64_get_operand_class (enum aarch64_opnd); - -extern const char * -aarch64_get_operand_name (enum aarch64_opnd); - -extern const char * -aarch64_get_operand_desc (enum aarch64_opnd); - -#ifdef DEBUG_AARCH64 -extern int debug_dump; - -extern void -aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2))); - -#define DEBUG_TRACE(M, ...) \ - { \ - if (debug_dump) \ - aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \ - } - -#define DEBUG_TRACE_IF(C, M, ...) \ - { \ - if (debug_dump && (C)) \ - aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \ - } -#else /* !DEBUG_AARCH64 */ -#define DEBUG_TRACE(M, ...) ; -#define DEBUG_TRACE_IF(C, M, ...) ; -#endif /* DEBUG_AARCH64 */ - -#endif /* OPCODE_AARCH64_H */ diff --git a/include/opcode/alpha.h b/include/opcode/alpha.h deleted file mode 100644 index 2c0d4f6..0000000 --- a/include/opcode/alpha.h +++ /dev/null @@ -1,238 +0,0 @@ -/* alpha.h -- Header file for Alpha opcode table - Copyright 1996, 1999, 2001, 2003, 2010 Free Software Foundation, Inc. - Contributed by Richard Henderson <rth@tamu.edu>, - patterned after the PPC opcode table written by Ian Lance Taylor. - - This file is part of GDB, GAS, and the GNU binutils. - - GDB, GAS, and the GNU binutils are free software; you can redistribute - them and/or modify them under the terms of the GNU General Public - License as published by the Free Software Foundation; either version 3, - or (at your option) any later version. - - GDB, GAS, and the GNU binutils are distributed in the hope that they - will be useful, but WITHOUT ANY WARRANTY; without even the implied - warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See - the GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this file; see the file COPYING3. If not, write to the Free - Software Foundation, 51 Franklin Street - Fifth Floor, Boston, - MA 02110-1301, USA. */ - -#ifndef OPCODE_ALPHA_H -#define OPCODE_ALPHA_H - -/* The opcode table is an array of struct alpha_opcode. */ - -struct alpha_opcode -{ - /* The opcode name. */ - const char *name; - - /* The opcode itself. Those bits which will be filled in with - operands are zeroes. */ - unsigned opcode; - - /* The opcode mask. This is used by the disassembler. This is a - mask containing ones indicating those bits which must match the - opcode field, and zeroes indicating those bits which need not - match (and are presumably filled in by operands). */ - unsigned mask; - - /* One bit flags for the opcode. These are primarily used to - indicate specific processors and environments support the - instructions. The defined values are listed below. */ - unsigned flags; - - /* An array of operand codes. Each code is an index into the - operand table. They appear in the order which the operands must - appear in assembly code, and are terminated by a zero. */ - unsigned char operands[4]; -}; - -/* The table itself is sorted by major opcode number, and is otherwise - in the order in which the disassembler should consider - instructions. */ -extern const struct alpha_opcode alpha_opcodes[]; -extern const unsigned alpha_num_opcodes; - -/* Values defined for the flags field of a struct alpha_opcode. */ - -/* CPU Availability */ -#define AXP_OPCODE_BASE 0x0001 /* Base architecture -- all cpus. */ -#define AXP_OPCODE_EV4 0x0002 /* EV4 specific PALcode insns. */ -#define AXP_OPCODE_EV5 0x0004 /* EV5 specific PALcode insns. */ -#define AXP_OPCODE_EV6 0x0008 /* EV6 specific PALcode insns. */ -#define AXP_OPCODE_BWX 0x0100 /* Byte/word extension (amask bit 0). */ -#define AXP_OPCODE_CIX 0x0200 /* "Count" extension (amask bit 1). */ -#define AXP_OPCODE_MAX 0x0400 /* Multimedia extension (amask bit 8). */ - -#define AXP_OPCODE_NOPAL (~(AXP_OPCODE_EV4|AXP_OPCODE_EV5|AXP_OPCODE_EV6)) - -/* A macro to extract the major opcode from an instruction. */ -#define AXP_OP(i) (((i) >> 26) & 0x3F) - -/* The total number of major opcodes. */ -#define AXP_NOPS 0x40 - - -/* The operands table is an array of struct alpha_operand. */ - -struct alpha_operand -{ - /* The number of bits in the operand. */ - unsigned int bits : 5; - - /* How far the operand is left shifted in the instruction. */ - unsigned int shift : 5; - - /* The default relocation type for this operand. */ - signed int default_reloc : 16; - - /* One bit syntax flags. */ - unsigned int flags : 16; - - /* Insertion function. This is used by the assembler. To insert an - operand value into an instruction, check this field. - - If it is NULL, execute - i |= (op & ((1 << o->bits) - 1)) << o->shift; - (i is the instruction which we are filling in, o is a pointer to - this structure, and op is the opcode value; this assumes twos - complement arithmetic). - - If this field is not NULL, then simply call it with the - instruction and the operand value. It will return the new value - of the instruction. If the ERRMSG argument is not NULL, then if - the operand value is illegal, *ERRMSG will be set to a warning - string (the operand will be inserted in any case). If the - operand value is legal, *ERRMSG will be unchanged (most operands - can accept any value). */ - unsigned (*insert) (unsigned instruction, int op, const char **errmsg); - - /* Extraction function. This is used by the disassembler. To - extract this operand type from an instruction, check this field. - - If it is NULL, compute - op = ((i) >> o->shift) & ((1 << o->bits) - 1); - if ((o->flags & AXP_OPERAND_SIGNED) != 0 - && (op & (1 << (o->bits - 1))) != 0) - op -= 1 << o->bits; - (i is the instruction, o is a pointer to this structure, and op - is the result; this assumes twos complement arithmetic). - - If this field is not NULL, then simply call it with the - instruction value. It will return the value of the operand. If - the INVALID argument is not NULL, *INVALID will be set to - non-zero if this operand type can not actually be extracted from - this operand (i.e., the instruction does not match). If the - operand is valid, *INVALID will not be changed. */ - int (*extract) (unsigned instruction, int *invalid); -}; - -/* Elements in the table are retrieved by indexing with values from - the operands field of the alpha_opcodes table. */ - -extern const struct alpha_operand alpha_operands[]; -extern const unsigned alpha_num_operands; - -/* Values defined for the flags field of a struct alpha_operand. */ - -/* Mask for selecting the type for typecheck purposes */ -#define AXP_OPERAND_TYPECHECK_MASK \ - (AXP_OPERAND_PARENS | AXP_OPERAND_COMMA | AXP_OPERAND_IR | \ - AXP_OPERAND_FPR | AXP_OPERAND_RELATIVE | AXP_OPERAND_SIGNED | \ - AXP_OPERAND_UNSIGNED) - -/* This operand does not actually exist in the assembler input. This - is used to support extended mnemonics, for which two operands fields - are identical. The assembler should call the insert function with - any op value. The disassembler should call the extract function, - ignore the return value, and check the value placed in the invalid - argument. */ -#define AXP_OPERAND_FAKE 01 - -/* The operand should be wrapped in parentheses rather than separated - from the previous by a comma. This is used for the load and store - instructions which want their operands to look like "Ra,disp(Rb)". */ -#define AXP_OPERAND_PARENS 02 - -/* Used in combination with PARENS, this supresses the supression of - the comma. This is used for "jmp Ra,(Rb),hint". */ -#define AXP_OPERAND_COMMA 04 - -/* This operand names an integer register. */ -#define AXP_OPERAND_IR 010 - -/* This operand names a floating point register. */ -#define AXP_OPERAND_FPR 020 - -/* This operand is a relative branch displacement. The disassembler - prints these symbolically if possible. */ -#define AXP_OPERAND_RELATIVE 040 - -/* This operand takes signed values. */ -#define AXP_OPERAND_SIGNED 0100 - -/* This operand takes unsigned values. This exists primarily so that - a flags value of 0 can be treated as end-of-arguments. */ -#define AXP_OPERAND_UNSIGNED 0200 - -/* Supress overflow detection on this field. This is used for hints. */ -#define AXP_OPERAND_NOOVERFLOW 0400 - -/* Mask for optional argument default value. */ -#define AXP_OPERAND_OPTIONAL_MASK 07000 - -/* This operand defaults to zero. This is used for jump hints. */ -#define AXP_OPERAND_DEFAULT_ZERO 01000 - -/* This operand should default to the first (real) operand and is used - in conjunction with AXP_OPERAND_OPTIONAL. This allows - "and $0,3,$0" to be written as "and $0,3", etc. I don't like - it, but it's what DEC does. */ -#define AXP_OPERAND_DEFAULT_FIRST 02000 - -/* Similarly, this operand should default to the second (real) operand. - This allows "negl $0" instead of "negl $0,$0". */ -#define AXP_OPERAND_DEFAULT_SECOND 04000 - - -/* Register common names */ - -#define AXP_REG_V0 0 -#define AXP_REG_T0 1 -#define AXP_REG_T1 2 -#define AXP_REG_T2 3 -#define AXP_REG_T3 4 -#define AXP_REG_T4 5 -#define AXP_REG_T5 6 -#define AXP_REG_T6 7 -#define AXP_REG_T7 8 -#define AXP_REG_S0 9 -#define AXP_REG_S1 10 -#define AXP_REG_S2 11 -#define AXP_REG_S3 12 -#define AXP_REG_S4 13 -#define AXP_REG_S5 14 -#define AXP_REG_FP 15 -#define AXP_REG_A0 16 -#define AXP_REG_A1 17 -#define AXP_REG_A2 18 -#define AXP_REG_A3 19 -#define AXP_REG_A4 20 -#define AXP_REG_A5 21 -#define AXP_REG_T8 22 -#define AXP_REG_T9 23 -#define AXP_REG_T10 24 -#define AXP_REG_T11 25 -#define AXP_REG_RA 26 -#define AXP_REG_PV 27 -#define AXP_REG_T12 27 -#define AXP_REG_AT 28 -#define AXP_REG_GP 29 -#define AXP_REG_SP 30 -#define AXP_REG_ZERO 31 - -#endif /* OPCODE_ALPHA_H */ diff --git a/include/opcode/arc.h b/include/opcode/arc.h deleted file mode 100644 index 695fec1..0000000 --- a/include/opcode/arc.h +++ /dev/null @@ -1,322 +0,0 @@ -/* Opcode table for the ARC. - Copyright 1994, 1995, 1997, 2001, 2002, 2003, 2010 - Free Software Foundation, Inc. - Contributed by Doug Evans (dje@cygnus.com). - - This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and - the GNU Binutils. - - GAS/GDB is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3, or (at your option) - any later version. - - GAS/GDB is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with GAS or GDB; see the file COPYING3. If not, write to - the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, - MA 02110-1301, USA. */ - -/* List of the various cpu types. - The tables currently use bit masks to say whether the instruction or - whatever is supported by a particular cpu. This lets us have one entry - apply to several cpus. - - The `base' cpu must be 0. The cpu type is treated independently of - endianness. The complete `mach' number includes endianness. - These values are internal to opcodes/bfd/binutils/gas. */ -#define ARC_MACH_5 0 -#define ARC_MACH_6 1 -#define ARC_MACH_7 2 -#define ARC_MACH_8 4 - -/* Additional cpu values can be inserted here and ARC_MACH_BIG moved down. */ -#define ARC_MACH_BIG 16 - -/* Mask of number of bits necessary to record cpu type. */ -#define ARC_MACH_CPU_MASK (ARC_MACH_BIG - 1) - -/* Mask of number of bits necessary to record cpu type + endianness. */ -#define ARC_MACH_MASK ((ARC_MACH_BIG << 1) - 1) - -/* Type to denote an ARC instruction (at least a 32 bit unsigned int). */ - -typedef unsigned int arc_insn; - -struct arc_opcode { - char *syntax; /* syntax of insn */ - unsigned long mask, value; /* recognize insn if (op&mask) == value */ - int flags; /* various flag bits */ - -/* Values for `flags'. */ - -/* Return CPU number, given flag bits. */ -#define ARC_OPCODE_CPU(bits) ((bits) & ARC_MACH_CPU_MASK) - -/* Return MACH number, given flag bits. */ -#define ARC_OPCODE_MACH(bits) ((bits) & ARC_MACH_MASK) - -/* First opcode flag bit available after machine mask. */ -#define ARC_OPCODE_FLAG_START (ARC_MACH_MASK + 1) - -/* This insn is a conditional branch. */ -#define ARC_OPCODE_COND_BRANCH (ARC_OPCODE_FLAG_START) -#define SYNTAX_3OP (ARC_OPCODE_COND_BRANCH << 1) -#define SYNTAX_LENGTH (SYNTAX_3OP ) -#define SYNTAX_2OP (SYNTAX_3OP << 1) -#define OP1_MUST_BE_IMM (SYNTAX_2OP << 1) -#define OP1_IMM_IMPLIED (OP1_MUST_BE_IMM << 1) -#define SYNTAX_VALID (OP1_IMM_IMPLIED << 1) - -#define I(x) (((x) & 31) << 27) -#define A(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGA) -#define B(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGB) -#define C(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGC) -#define R(x,b,m) (((x) & (m)) << (b)) /* value X, mask M, at bit B */ - -/* These values are used to optimize assembly and disassembly. Each insn - is on a list of related insns (same first letter for assembly, same - insn code for disassembly). */ - - struct arc_opcode *next_asm; /* Next instr to try during assembly. */ - struct arc_opcode *next_dis; /* Next instr to try during disassembly. */ - -/* Macros to create the hash values for the lists. */ -#define ARC_HASH_OPCODE(string) \ - ((string)[0] >= 'a' && (string)[0] <= 'z' ? (string)[0] - 'a' : 26) -#define ARC_HASH_ICODE(insn) \ - ((unsigned int) (insn) >> 27) - - /* Macros to access `next_asm', `next_dis' so users needn't care about the - underlying mechanism. */ -#define ARC_OPCODE_NEXT_ASM(op) ((op)->next_asm) -#define ARC_OPCODE_NEXT_DIS(op) ((op)->next_dis) -}; - -/* this is an "insert at front" linked list per Metaware spec - that new definitions override older ones. */ -extern struct arc_opcode *arc_ext_opcodes; - -struct arc_operand_value { - char *name; /* eg: "eq" */ - short value; /* eg: 1 */ - unsigned char type; /* index into `arc_operands' */ - unsigned char flags; /* various flag bits */ - -/* Values for `flags'. */ - -/* Return CPU number, given flag bits. */ -#define ARC_OPVAL_CPU(bits) ((bits) & ARC_MACH_CPU_MASK) -/* Return MACH number, given flag bits. */ -#define ARC_OPVAL_MACH(bits) ((bits) & ARC_MACH_MASK) -}; - -struct arc_ext_operand_value { - struct arc_ext_operand_value *next; - struct arc_operand_value operand; -}; - -extern struct arc_ext_operand_value *arc_ext_operands; - -struct arc_operand { -/* One of the insn format chars. */ - unsigned char fmt; - -/* The number of bits in the operand (may be unused for a modifier). */ - unsigned char bits; - -/* How far the operand is left shifted in the instruction, or - the modifier's flag bit (may be unused for a modifier. */ - unsigned char shift; - -/* Various flag bits. */ - int flags; - -/* Values for `flags'. */ - -/* This operand is a suffix to the opcode. */ -#define ARC_OPERAND_SUFFIX 1 - -/* This operand is a relative branch displacement. The disassembler - prints these symbolically if possible. */ -#define ARC_OPERAND_RELATIVE_BRANCH 2 - -/* This operand is an absolute branch address. The disassembler - prints these symbolically if possible. */ -#define ARC_OPERAND_ABSOLUTE_BRANCH 4 - -/* This operand is an address. The disassembler - prints these symbolically if possible. */ -#define ARC_OPERAND_ADDRESS 8 - -/* This operand is a long immediate value. */ -#define ARC_OPERAND_LIMM 0x10 - -/* This operand takes signed values. */ -#define ARC_OPERAND_SIGNED 0x20 - -/* This operand takes signed values, but also accepts a full positive - range of values. That is, if bits is 16, it takes any value from - -0x8000 to 0xffff. */ -#define ARC_OPERAND_SIGNOPT 0x40 - -/* This operand should be regarded as a negative number for the - purposes of overflow checking (i.e., the normal most negative - number is disallowed and one more than the normal most positive - number is allowed). This flag will only be set for a signed - operand. */ -#define ARC_OPERAND_NEGATIVE 0x80 - -/* This operand doesn't really exist. The program uses these operands - in special ways. */ -#define ARC_OPERAND_FAKE 0x100 - -/* separate flags operand for j and jl instructions */ -#define ARC_OPERAND_JUMPFLAGS 0x200 - -/* allow warnings and errors to be issued after call to insert_xxxxxx */ -#define ARC_OPERAND_WARN 0x400 -#define ARC_OPERAND_ERROR 0x800 - -/* this is a load operand */ -#define ARC_OPERAND_LOAD 0x8000 - -/* this is a store operand */ -#define ARC_OPERAND_STORE 0x10000 - -/* Modifier values. */ -/* A dot is required before a suffix. Eg: .le */ -#define ARC_MOD_DOT 0x1000 - -/* A normal register is allowed (not used, but here for completeness). */ -#define ARC_MOD_REG 0x2000 - -/* An auxiliary register name is expected. */ -#define ARC_MOD_AUXREG 0x4000 - -/* Sum of all ARC_MOD_XXX bits. */ -#define ARC_MOD_BITS 0x7000 - -/* Non-zero if the operand type is really a modifier. */ -#define ARC_MOD_P(X) ((X) & ARC_MOD_BITS) - -/* enforce read/write only register restrictions */ -#define ARC_REGISTER_READONLY 0x01 -#define ARC_REGISTER_WRITEONLY 0x02 -#define ARC_REGISTER_NOSHORT_CUT 0x04 - -/* Insertion function. This is used by the assembler. To insert an - operand value into an instruction, check this field. - - If it is NULL, execute - i |= (p & ((1 << o->bits) - 1)) << o->shift; - (I is the instruction which we are filling in, O is a pointer to - this structure, and OP is the opcode value; this assumes twos - complement arithmetic). - - If this field is not NULL, then simply call it with the - instruction and the operand value. It will return the new value - of the instruction. If the ERRMSG argument is not NULL, then if - the operand value is illegal, *ERRMSG will be set to a warning - string (the operand will be inserted in any case). If the - operand value is legal, *ERRMSG will be unchanged. - - REG is non-NULL when inserting a register value. */ - - arc_insn (*insert) - (arc_insn insn, const struct arc_operand *operand, int mods, - const struct arc_operand_value *reg, long value, const char **errmsg); - -/* Extraction function. This is used by the disassembler. To - extract this operand type from an instruction, check this field. - - If it is NULL, compute - op = ((i) >> o->shift) & ((1 << o->bits) - 1); - if ((o->flags & ARC_OPERAND_SIGNED) != 0 - && (op & (1 << (o->bits - 1))) != 0) - op -= 1 << o->bits; - (I is the instruction, O is a pointer to this structure, and OP - is the result; this assumes twos complement arithmetic). - - If this field is not NULL, then simply call it with the - instruction value. It will return the value of the operand. If - the INVALID argument is not NULL, *INVALID will be set to - non-zero if this operand type can not actually be extracted from - this operand (i.e., the instruction does not match). If the - operand is valid, *INVALID will not be changed. - - INSN is a pointer to an array of two `arc_insn's. The first element is - the insn, the second is the limm if present. - - Operands that have a printable form like registers and suffixes have - their struct arc_operand_value pointer stored in OPVAL. */ - - long (*extract) - (arc_insn *insn, const struct arc_operand *operand, int mods, - const struct arc_operand_value **opval, int *invalid); -}; - -/* Bits that say what version of cpu we have. These should be passed to - arc_init_opcode_tables. At present, all there is is the cpu type. */ - -/* CPU number, given value passed to `arc_init_opcode_tables'. */ -#define ARC_HAVE_CPU(bits) ((bits) & ARC_MACH_CPU_MASK) -/* MACH number, given value passed to `arc_init_opcode_tables'. */ -#define ARC_HAVE_MACH(bits) ((bits) & ARC_MACH_MASK) - -/* Special register values: */ -#define ARC_REG_SHIMM_UPDATE 61 -#define ARC_REG_SHIMM 63 -#define ARC_REG_LIMM 62 - -/* Non-zero if REG is a constant marker. */ -#define ARC_REG_CONSTANT_P(REG) ((REG) >= 61) - -/* Positions and masks of various fields: */ -#define ARC_SHIFT_REGA 21 -#define ARC_SHIFT_REGB 15 -#define ARC_SHIFT_REGC 9 -#define ARC_MASK_REG 63 - -/* Delay slot types. */ -#define ARC_DELAY_NONE 0 /* no delay slot */ -#define ARC_DELAY_NORMAL 1 /* delay slot in both cases */ -#define ARC_DELAY_JUMP 2 /* delay slot only if branch taken */ - -/* Non-zero if X will fit in a signed 9 bit field. */ -#define ARC_SHIMM_CONST_P(x) ((long) (x) >= -256 && (long) (x) <= 255) - -extern const struct arc_operand arc_operands[]; -extern const int arc_operand_count; -extern struct arc_opcode arc_opcodes[]; -extern const int arc_opcodes_count; -extern const struct arc_operand_value arc_suffixes[]; -extern const int arc_suffixes_count; -extern const struct arc_operand_value arc_reg_names[]; -extern const int arc_reg_names_count; -extern unsigned char arc_operand_map[]; - -/* Utility fns in arc-opc.c. */ -int arc_get_opcode_mach (int, int); - -/* `arc_opcode_init_tables' must be called before `arc_xxx_supported'. */ -void arc_opcode_init_tables (int); -void arc_opcode_init_insert (void); -void arc_opcode_init_extract (void); -const struct arc_opcode *arc_opcode_lookup_asm (const char *); -const struct arc_opcode *arc_opcode_lookup_dis (unsigned int); -int arc_opcode_limm_p (long *); -const struct arc_operand_value *arc_opcode_lookup_suffix - (const struct arc_operand *type, int value); -int arc_opcode_supported (const struct arc_opcode *); -int arc_opval_supported (const struct arc_operand_value *); -int arc_limm_fixup_adjust (arc_insn); -int arc_insn_is_j (arc_insn); -int arc_insn_not_jl (arc_insn); -int arc_operand_type (int); -struct arc_operand_value *get_ext_suffix (char *); -int arc_get_noshortcut_flag (void); diff --git a/include/opcode/arm.h b/include/opcode/arm.h deleted file mode 100644 index 851fd3c..0000000 --- a/include/opcode/arm.h +++ /dev/null @@ -1,289 +0,0 @@ -/* ARM assembler/disassembler support. - Copyright 2004, 2010, 2011 Free Software Foundation, Inc. - - This file is part of GDB and GAS. - - GDB and GAS are free software; you can redistribute it and/or - modify it under the terms of the GNU General Public License as - published by the Free Software Foundation; either version 3, or (at - your option) any later version. - - GDB and GAS are distributed in the hope that it will be useful, but - WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - General Public License for more details. - - You should have received a copy of the GNU General Public License - along with GDB or GAS; see the file COPYING3. If not, write to the - Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, - MA 02110-1301, USA. */ - -/* The following bitmasks control CPU extensions: */ -#define ARM_EXT_V1 0x00000001 /* All processors (core set). */ -#define ARM_EXT_V2 0x00000002 /* Multiply instructions. */ -#define ARM_EXT_V2S 0x00000004 /* SWP instructions. */ -#define ARM_EXT_V3 0x00000008 /* MSR MRS. */ -#define ARM_EXT_V3M 0x00000010 /* Allow long multiplies. */ -#define ARM_EXT_V4 0x00000020 /* Allow half word loads. */ -#define ARM_EXT_V4T 0x00000040 /* Thumb. */ -#define ARM_EXT_V5 0x00000080 /* Allow CLZ, etc. */ -#define ARM_EXT_V5T 0x00000100 /* Improved interworking. */ -#define ARM_EXT_V5ExP 0x00000200 /* DSP core set. */ -#define ARM_EXT_V5E 0x00000400 /* DSP Double transfers. */ -#define ARM_EXT_V5J 0x00000800 /* Jazelle extension. */ -#define ARM_EXT_V6 0x00001000 /* ARM V6. */ -#define ARM_EXT_V6K 0x00002000 /* ARM V6K. */ -/* 0x00004000 Was ARM V6Z. */ -#define ARM_EXT_V8 0x00004000 /* is now ARMv8. */ -#define ARM_EXT_V6T2 0x00008000 /* Thumb-2. */ -#define ARM_EXT_DIV 0x00010000 /* Integer division. */ -/* The 'M' in Arm V7M stands for Microcontroller. - On earlier architecture variants it stands for Multiply. */ -#define ARM_EXT_V5E_NOTM 0x00020000 /* Arm V5E but not Arm V7M. */ -#define ARM_EXT_V6_NOTM 0x00040000 /* Arm V6 but not Arm V7M. */ -#define ARM_EXT_V7 0x00080000 /* Arm V7. */ -#define ARM_EXT_V7A 0x00100000 /* Arm V7A. */ -#define ARM_EXT_V7R 0x00200000 /* Arm V7R. */ -#define ARM_EXT_V7M 0x00400000 /* Arm V7M. */ -#define ARM_EXT_V6M 0x00800000 /* ARM V6M. */ -#define ARM_EXT_BARRIER 0x01000000 /* DSB/DMB/ISB. */ -#define ARM_EXT_THUMB_MSR 0x02000000 /* Thumb MSR/MRS. */ -#define ARM_EXT_V6_DSP 0x04000000 /* ARM v6 (DSP-related), - not in v7-M. */ -#define ARM_EXT_MP 0x08000000 /* Multiprocessing Extensions. */ -#define ARM_EXT_SEC 0x10000000 /* Security extensions. */ -#define ARM_EXT_OS 0x20000000 /* OS Extensions. */ -#define ARM_EXT_ADIV 0x40000000 /* Integer divide extensions in ARM - state. */ -#define ARM_EXT_VIRT 0x80000000 /* Virtualization extensions. */ - -/* Co-processor space extensions. */ -#define ARM_CEXT_XSCALE 0x00000001 /* Allow MIA etc. */ -#define ARM_CEXT_MAVERICK 0x00000002 /* Use Cirrus/DSP coprocessor. */ -#define ARM_CEXT_IWMMXT 0x00000004 /* Intel Wireless MMX technology coprocessor. */ -#define ARM_CEXT_IWMMXT2 0x00000008 /* Intel Wireless MMX technology coprocessor version 2. */ - -#define FPU_ENDIAN_PURE 0x80000000 /* Pure-endian doubles. */ -#define FPU_ENDIAN_BIG 0 /* Double words-big-endian. */ -#define FPU_FPA_EXT_V1 0x40000000 /* Base FPA instruction set. */ -#define FPU_FPA_EXT_V2 0x20000000 /* LFM/SFM. */ -#define FPU_MAVERICK 0x10000000 /* Cirrus Maverick. */ -#define FPU_VFP_EXT_V1xD 0x08000000 /* Base VFP instruction set. */ -#define FPU_VFP_EXT_V1 0x04000000 /* Double-precision insns. */ -#define FPU_VFP_EXT_V2 0x02000000 /* ARM10E VFPr1. */ -#define FPU_VFP_EXT_V3xD 0x01000000 /* VFPv3 single-precision. */ -#define FPU_VFP_EXT_V3 0x00800000 /* VFPv3 double-precision. */ -#define FPU_NEON_EXT_V1 0x00400000 /* Neon (SIMD) insns. */ -#define FPU_VFP_EXT_D32 0x00200000 /* Registers D16-D31. */ -#define FPU_VFP_EXT_FP16 0x00100000 /* Half-precision extensions. */ -#define FPU_NEON_EXT_FMA 0x00080000 /* Neon fused multiply-add */ -#define FPU_VFP_EXT_FMA 0x00040000 /* VFP fused multiply-add */ -#define FPU_VFP_EXT_ARMV8 0x00020000 /* FP for ARMv8. */ -#define FPU_NEON_EXT_ARMV8 0x00010000 /* Neon for ARMv8. */ -#define FPU_CRYPTO_EXT_ARMV8 0x00008000 /* Crypto for ARMv8. */ -#define CRC_EXT_ARMV8 0x00004000 /* CRC32 for ARMv8. */ - -/* Architectures are the sum of the base and extensions. The ARM ARM (rev E) - defines the following: ARMv3, ARMv3M, ARMv4xM, ARMv4, ARMv4TxM, ARMv4T, - ARMv5xM, ARMv5, ARMv5TxM, ARMv5T, ARMv5TExP, ARMv5TE. To these we add - three more to cover cores prior to ARM6. Finally, there are cores which - implement further extensions in the co-processor space. */ -#define ARM_AEXT_V1 ARM_EXT_V1 -#define ARM_AEXT_V2 (ARM_AEXT_V1 | ARM_EXT_V2) -#define ARM_AEXT_V2S (ARM_AEXT_V2 | ARM_EXT_V2S) -#define ARM_AEXT_V3 (ARM_AEXT_V2S | ARM_EXT_V3) -#define ARM_AEXT_V3M (ARM_AEXT_V3 | ARM_EXT_V3M) -#define ARM_AEXT_V4xM (ARM_AEXT_V3 | ARM_EXT_V4) -#define ARM_AEXT_V4 (ARM_AEXT_V3M | ARM_EXT_V4) -#define ARM_AEXT_V4TxM (ARM_AEXT_V4xM | ARM_EXT_V4T) -#define ARM_AEXT_V4T (ARM_AEXT_V4 | ARM_EXT_V4T) -#define ARM_AEXT_V5xM (ARM_AEXT_V4xM | ARM_EXT_V5) -#define ARM_AEXT_V5 (ARM_AEXT_V4 | ARM_EXT_V5) -#define ARM_AEXT_V5TxM (ARM_AEXT_V5xM | ARM_EXT_V4T | ARM_EXT_V5T) -#define ARM_AEXT_V5T (ARM_AEXT_V5 | ARM_EXT_V4T | ARM_EXT_V5T) -#define ARM_AEXT_V5TExP (ARM_AEXT_V5T | ARM_EXT_V5ExP) -#define ARM_AEXT_V5TE (ARM_AEXT_V5TExP | ARM_EXT_V5E) -#define ARM_AEXT_V5TEJ (ARM_AEXT_V5TE | ARM_EXT_V5J) -#define ARM_AEXT_V6 (ARM_AEXT_V5TEJ | ARM_EXT_V6) -#define ARM_AEXT_V6K (ARM_AEXT_V6 | ARM_EXT_V6K) -#define ARM_AEXT_V6Z (ARM_AEXT_V6K | ARM_EXT_SEC) -#define ARM_AEXT_V6ZK (ARM_AEXT_V6K | ARM_EXT_SEC) -#define ARM_AEXT_V6T2 (ARM_AEXT_V6 \ - | ARM_EXT_V6T2 | ARM_EXT_V6_NOTM | ARM_EXT_THUMB_MSR \ - | ARM_EXT_V6_DSP ) -#define ARM_AEXT_V6KT2 (ARM_AEXT_V6T2 | ARM_EXT_V6K) -#define ARM_AEXT_V6ZT2 (ARM_AEXT_V6T2 | ARM_EXT_SEC) -#define ARM_AEXT_V6ZKT2 (ARM_AEXT_V6T2 | ARM_EXT_V6K | ARM_EXT_SEC) -#define ARM_AEXT_V7_ARM (ARM_AEXT_V6KT2 | ARM_EXT_V7 | ARM_EXT_BARRIER) -#define ARM_AEXT_V7A (ARM_AEXT_V7_ARM | ARM_EXT_V7A) -#define ARM_AEXT_V7R (ARM_AEXT_V7_ARM | ARM_EXT_V7R | ARM_EXT_DIV) -#define ARM_AEXT_NOTM \ - (ARM_AEXT_V4 | ARM_EXT_V5ExP | ARM_EXT_V5J | ARM_EXT_V6_NOTM \ - | ARM_EXT_V6_DSP ) -#define ARM_AEXT_V6M_ONLY \ - ((ARM_EXT_BARRIER | ARM_EXT_V6M | ARM_EXT_THUMB_MSR) & ~(ARM_AEXT_NOTM)) -#define ARM_AEXT_V6M \ - ((ARM_AEXT_V6K | ARM_AEXT_V6M_ONLY) & ~(ARM_AEXT_NOTM)) -#define ARM_AEXT_V6SM (ARM_AEXT_V6M | ARM_EXT_OS) -#define ARM_AEXT_V7M \ - ((ARM_AEXT_V7_ARM | ARM_EXT_V6M | ARM_EXT_V7M | ARM_EXT_DIV) \ - & ~(ARM_AEXT_NOTM)) -#define ARM_AEXT_V7 (ARM_AEXT_V7A & ARM_AEXT_V7R & ARM_AEXT_V7M) -#define ARM_AEXT_V7EM \ - (ARM_AEXT_V7M | ARM_EXT_V5ExP | ARM_EXT_V6_DSP) -#define ARM_AEXT_V8A \ - (ARM_AEXT_V7A | ARM_EXT_MP | ARM_EXT_SEC | ARM_EXT_DIV | ARM_EXT_ADIV \ - | ARM_EXT_VIRT | ARM_EXT_V8) - -/* Processors with specific extensions in the co-processor space. */ -#define ARM_ARCH_XSCALE ARM_FEATURE (ARM_AEXT_V5TE, ARM_CEXT_XSCALE) -#define ARM_ARCH_IWMMXT \ - ARM_FEATURE (ARM_AEXT_V5TE, ARM_CEXT_XSCALE | ARM_CEXT_IWMMXT) -#define ARM_ARCH_IWMMXT2 \ - ARM_FEATURE (ARM_AEXT_V5TE, ARM_CEXT_XSCALE | ARM_CEXT_IWMMXT | ARM_CEXT_IWMMXT2) - -#define FPU_VFP_V1xD (FPU_VFP_EXT_V1xD | FPU_ENDIAN_PURE) -#define FPU_VFP_V1 (FPU_VFP_V1xD | FPU_VFP_EXT_V1) -#define FPU_VFP_V2 (FPU_VFP_V1 | FPU_VFP_EXT_V2) -#define FPU_VFP_V3D16 (FPU_VFP_V2 | FPU_VFP_EXT_V3xD | FPU_VFP_EXT_V3) -#define FPU_VFP_V3 (FPU_VFP_V3D16 | FPU_VFP_EXT_D32) -#define FPU_VFP_V3xD (FPU_VFP_V1xD | FPU_VFP_EXT_V2 | FPU_VFP_EXT_V3xD) -#define FPU_VFP_V4D16 (FPU_VFP_V3D16 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA) -#define FPU_VFP_V4 (FPU_VFP_V3 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA) -#define FPU_VFP_V4_SP_D16 (FPU_VFP_V3xD | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA) -#define FPU_VFP_ARMV8 (FPU_VFP_V4 | FPU_VFP_EXT_ARMV8) -#define FPU_NEON_ARMV8 (FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA | FPU_NEON_EXT_ARMV8) -#define FPU_CRYPTO_ARMV8 (FPU_CRYPTO_EXT_ARMV8) -#define FPU_VFP_HARD (FPU_VFP_EXT_V1xD | FPU_VFP_EXT_V1 | FPU_VFP_EXT_V2 \ - | FPU_VFP_EXT_V3xD | FPU_VFP_EXT_FMA | FPU_NEON_EXT_FMA \ - | FPU_VFP_EXT_V3 | FPU_NEON_EXT_V1 | FPU_VFP_EXT_D32) -#define FPU_FPA (FPU_FPA_EXT_V1 | FPU_FPA_EXT_V2) - -/* Deprecated. */ -#define FPU_ARCH_VFP ARM_FEATURE (0, FPU_ENDIAN_PURE) - -#define FPU_ARCH_FPE ARM_FEATURE (0, FPU_FPA_EXT_V1) -#define FPU_ARCH_FPA ARM_FEATURE (0, FPU_FPA) - -#define FPU_ARCH_VFP_V1xD ARM_FEATURE (0, FPU_VFP_V1xD) -#define FPU_ARCH_VFP_V1 ARM_FEATURE (0, FPU_VFP_V1) -#define FPU_ARCH_VFP_V2 ARM_FEATURE (0, FPU_VFP_V2) -#define FPU_ARCH_VFP_V3D16 ARM_FEATURE (0, FPU_VFP_V3D16) -#define FPU_ARCH_VFP_V3D16_FP16 \ - ARM_FEATURE (0, FPU_VFP_V3D16 | FPU_VFP_EXT_FP16) -#define FPU_ARCH_VFP_V3 ARM_FEATURE (0, FPU_VFP_V3) -#define FPU_ARCH_VFP_V3_FP16 ARM_FEATURE (0, FPU_VFP_V3 | FPU_VFP_EXT_FP16) -#define FPU_ARCH_VFP_V3xD ARM_FEATURE (0, FPU_VFP_V3xD) -#define FPU_ARCH_VFP_V3xD_FP16 ARM_FEATURE (0, FPU_VFP_V3xD | FPU_VFP_EXT_FP16) -#define FPU_ARCH_NEON_V1 ARM_FEATURE (0, FPU_NEON_EXT_V1) -#define FPU_ARCH_VFP_V3_PLUS_NEON_V1 \ - ARM_FEATURE (0, FPU_VFP_V3 | FPU_NEON_EXT_V1) -#define FPU_ARCH_NEON_FP16 \ - ARM_FEATURE (0, FPU_VFP_V3 | FPU_NEON_EXT_V1 | FPU_VFP_EXT_FP16) -#define FPU_ARCH_VFP_HARD ARM_FEATURE (0, FPU_VFP_HARD) -#define FPU_ARCH_VFP_V4 ARM_FEATURE(0, FPU_VFP_V4) -#define FPU_ARCH_VFP_V4D16 ARM_FEATURE(0, FPU_VFP_V4D16) -#define FPU_ARCH_VFP_V4_SP_D16 ARM_FEATURE(0, FPU_VFP_V4_SP_D16) -#define FPU_ARCH_NEON_VFP_V4 \ - ARM_FEATURE(0, FPU_VFP_V4 | FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA) -#define FPU_ARCH_VFP_ARMV8 ARM_FEATURE(0, FPU_VFP_ARMV8) -#define FPU_ARCH_NEON_VFP_ARMV8 ARM_FEATURE(0, FPU_NEON_ARMV8 | FPU_VFP_ARMV8) -#define FPU_ARCH_CRYPTO_NEON_VFP_ARMV8 \ - ARM_FEATURE(0, FPU_CRYPTO_ARMV8 | FPU_NEON_ARMV8 | FPU_VFP_ARMV8) -#define ARCH_CRC_ARMV8 ARM_FEATURE(0, CRC_EXT_ARMV8) - -#define FPU_ARCH_ENDIAN_PURE ARM_FEATURE (0, FPU_ENDIAN_PURE) - -#define FPU_ARCH_MAVERICK ARM_FEATURE (0, FPU_MAVERICK) - -#define ARM_ARCH_V1 ARM_FEATURE (ARM_AEXT_V1, 0) -#define ARM_ARCH_V2 ARM_FEATURE (ARM_AEXT_V2, 0) -#define ARM_ARCH_V2S ARM_FEATURE (ARM_AEXT_V2S, 0) -#define ARM_ARCH_V3 ARM_FEATURE (ARM_AEXT_V3, 0) -#define ARM_ARCH_V3M ARM_FEATURE (ARM_AEXT_V3M, 0) -#define ARM_ARCH_V4xM ARM_FEATURE (ARM_AEXT_V4xM, 0) -#define ARM_ARCH_V4 ARM_FEATURE (ARM_AEXT_V4, 0) -#define ARM_ARCH_V4TxM ARM_FEATURE (ARM_AEXT_V4TxM, 0) -#define ARM_ARCH_V4T ARM_FEATURE (ARM_AEXT_V4T, 0) -#define ARM_ARCH_V5xM ARM_FEATURE (ARM_AEXT_V5xM, 0) -#define ARM_ARCH_V5 ARM_FEATURE (ARM_AEXT_V5, 0) -#define ARM_ARCH_V5TxM ARM_FEATURE (ARM_AEXT_V5TxM, 0) -#define ARM_ARCH_V5T ARM_FEATURE (ARM_AEXT_V5T, 0) -#define ARM_ARCH_V5TExP ARM_FEATURE (ARM_AEXT_V5TExP, 0) -#define ARM_ARCH_V5TE ARM_FEATURE (ARM_AEXT_V5TE, 0) -#define ARM_ARCH_V5TEJ ARM_FEATURE (ARM_AEXT_V5TEJ, 0) -#define ARM_ARCH_V6 ARM_FEATURE (ARM_AEXT_V6, 0) -#define ARM_ARCH_V6K ARM_FEATURE (ARM_AEXT_V6K, 0) -#define ARM_ARCH_V6Z ARM_FEATURE (ARM_AEXT_V6Z, 0) -#define ARM_ARCH_V6ZK ARM_FEATURE (ARM_AEXT_V6ZK, 0) -#define ARM_ARCH_V6T2 ARM_FEATURE (ARM_AEXT_V6T2, 0) -#define ARM_ARCH_V6KT2 ARM_FEATURE (ARM_AEXT_V6KT2, 0) -#define ARM_ARCH_V6ZT2 ARM_FEATURE (ARM_AEXT_V6ZT2, 0) -#define ARM_ARCH_V6ZKT2 ARM_FEATURE (ARM_AEXT_V6ZKT2, 0) -#define ARM_ARCH_V6M ARM_FEATURE (ARM_AEXT_V6M, 0) -#define ARM_ARCH_V6SM ARM_FEATURE (ARM_AEXT_V6SM, 0) -#define ARM_ARCH_V7 ARM_FEATURE (ARM_AEXT_V7, 0) -#define ARM_ARCH_V7A ARM_FEATURE (ARM_AEXT_V7A, 0) -#define ARM_ARCH_V7R ARM_FEATURE (ARM_AEXT_V7R, 0) -#define ARM_ARCH_V7M ARM_FEATURE (ARM_AEXT_V7M, 0) -#define ARM_ARCH_V7EM ARM_FEATURE (ARM_AEXT_V7EM, 0) -#define ARM_ARCH_V8A ARM_FEATURE (ARM_AEXT_V8A, 0) - -/* Some useful combinations: */ -#define ARM_ARCH_NONE ARM_FEATURE (0, 0) -#define FPU_NONE ARM_FEATURE (0, 0) -#define ARM_ANY ARM_FEATURE (-1, 0) /* Any basic core. */ -#define FPU_ANY_HARD ARM_FEATURE (0, FPU_FPA | FPU_VFP_HARD | FPU_MAVERICK) -#define ARM_ARCH_THUMB2 ARM_FEATURE (ARM_EXT_V6T2 | ARM_EXT_V7 | ARM_EXT_V7A | ARM_EXT_V7R | ARM_EXT_V7M | ARM_EXT_DIV, 0) -/* v7-a+sec. */ -#define ARM_ARCH_V7A_SEC ARM_FEATURE (ARM_AEXT_V7A | ARM_EXT_SEC, 0) -/* v7-a+mp+sec. */ -#define ARM_ARCH_V7A_MP_SEC \ - ARM_FEATURE (ARM_AEXT_V7A | ARM_EXT_MP | ARM_EXT_SEC, \ - 0) -/* v7-a+idiv+mp+sec+virt. */ -#define ARM_ARCH_V7A_IDIV_MP_SEC_VIRT \ - ARM_FEATURE (ARM_AEXT_V7A | ARM_EXT_MP | ARM_EXT_SEC \ - | ARM_EXT_DIV | ARM_EXT_ADIV \ - | ARM_EXT_VIRT, 0) -/* v7-r+idiv. */ -#define ARM_ARCH_V7R_IDIV ARM_FEATURE (ARM_AEXT_V7R | ARM_EXT_ADIV, 0) -/* Features that are present in v6M and v6S-M but not other v6 cores. */ -#define ARM_ARCH_V6M_ONLY ARM_FEATURE (ARM_AEXT_V6M_ONLY, 0) -/* v8-a+fp. */ -#define ARM_ARCH_V8A_FP ARM_FEATURE (ARM_AEXT_V8A, FPU_ARCH_VFP_ARMV8) -/* v8-a+simd (implies fp). */ -#define ARM_ARCH_V8A_SIMD ARM_FEATURE (ARM_AEXT_V8A, \ - FPU_ARCH_NEON_VFP_ARMV8) -/* v8-a+crypto (implies simd+fp). */ -#define ARM_ARCH_V8A_CRYPTOV1 ARM_FEATURE (ARM_AEXT_V8A, \ - FPU_ARCH_CRYPTO_NEON_VFP_ARMV8) - -/* There are too many feature bits to fit in a single word, so use a - structure. For simplicity we put all core features in one word and - everything else in the other. */ -typedef struct -{ - unsigned long core; - unsigned long coproc; -} arm_feature_set; - -#define ARM_CPU_HAS_FEATURE(CPU,FEAT) \ - (((CPU).core & (FEAT).core) != 0 || ((CPU).coproc & (FEAT).coproc) != 0) - -#define ARM_CPU_IS_ANY(CPU) \ - ((CPU).core == ((arm_feature_set)ARM_ANY).core) - -#define ARM_MERGE_FEATURE_SETS(TARG,F1,F2) \ - do { \ - (TARG).core = (F1).core | (F2).core; \ - (TARG).coproc = (F1).coproc | (F2).coproc; \ - } while (0) - -#define ARM_CLEAR_FEATURE(TARG,F1,F2) \ - do { \ - (TARG).core = (F1).core &~ (F2).core; \ - (TARG).coproc = (F1).coproc &~ (F2).coproc; \ - } while (0) - -#define ARM_FEATURE(core, coproc) {(core), (coproc)} diff --git a/include/opcode/avr.h b/include/opcode/avr.h deleted file mode 100644 index f1d73ad..0000000 --- a/include/opcode/avr.h +++ /dev/null @@ -1,300 +0,0 @@ -/* Opcode table for the Atmel AVR micro controllers. - - Copyright 2000, 2001, 2004, 2006, 2008, 2010, 2012 Free Software Foundation, Inc. - Contributed by Denis Chertykov <denisc@overta.ru> - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3, or (at your option) - any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, - MA 02110-1301, USA. */ - -#define AVR_ISA_1200 0x0001 /* In the beginning there was ... */ -#define AVR_ISA_LPM 0x0002 /* device has LPM */ -#define AVR_ISA_LPMX 0x0004 /* device has LPM Rd,Z[+] */ -#define AVR_ISA_SRAM 0x0008 /* device has SRAM (LD, ST, PUSH, POP, ...) */ -#define AVR_ISA_MEGA 0x0020 /* device has >8K program memory (JMP and CALL - supported, no 8K wrap on RJMP and RCALL) */ -#define AVR_ISA_MUL 0x0040 /* device has new core (MUL, FMUL, ...) */ -#define AVR_ISA_ELPM 0x0080 /* device has >64K program memory (ELPM) */ -#define AVR_ISA_ELPMX 0x0100 /* device has ELPM Rd,Z[+] */ -#define AVR_ISA_SPM 0x0200 /* device can program itself */ -#define AVR_ISA_BRK 0x0400 /* device has BREAK (on-chip debug) */ -#define AVR_ISA_EIND 0x0800 /* device has >128K program memory (none yet) */ -#define AVR_ISA_MOVW 0x1000 /* device has MOVW */ -#define AVR_ISA_SPMX 0x2000 /* device has SPM Z[+] */ -#define AVR_ISA_DES 0x4000 /* device has DES */ -#define AVR_ISA_RMW 0x8000 /* device has RMW instructions XCH,LAC,LAS,LAT */ - -#define AVR_ISA_TINY1 (AVR_ISA_1200 | AVR_ISA_LPM) -#define AVR_ISA_2xxx (AVR_ISA_TINY1 | AVR_ISA_SRAM) -/* For the attiny26 which is missing LPM Rd,Z+. */ -#define AVR_ISA_2xxe (AVR_ISA_2xxx | AVR_ISA_LPMX) -#define AVR_ISA_RF401 (AVR_ISA_2xxx | AVR_ISA_MOVW | AVR_ISA_LPMX) -#define AVR_ISA_TINY2 (AVR_ISA_2xxx | AVR_ISA_MOVW | AVR_ISA_LPMX | \ - AVR_ISA_SPM | AVR_ISA_BRK) -#define AVR_ISA_M603 (AVR_ISA_2xxx | AVR_ISA_MEGA) -#define AVR_ISA_M103 (AVR_ISA_M603 | AVR_ISA_ELPM) -#define AVR_ISA_M8 (AVR_ISA_2xxx | AVR_ISA_MUL | AVR_ISA_MOVW | \ - AVR_ISA_LPMX | AVR_ISA_SPM) -#define AVR_ISA_PWMx (AVR_ISA_M8 | AVR_ISA_BRK) -#define AVR_ISA_M161 (AVR_ISA_M603 | AVR_ISA_MUL | AVR_ISA_MOVW | \ - AVR_ISA_LPMX | AVR_ISA_SPM) -#define AVR_ISA_94K (AVR_ISA_M603 | AVR_ISA_MUL | AVR_ISA_MOVW | AVR_ISA_LPMX) -#define AVR_ISA_M323 (AVR_ISA_M161 | AVR_ISA_BRK) -#define AVR_ISA_M128 (AVR_ISA_M323 | AVR_ISA_ELPM | AVR_ISA_ELPMX) -#define AVR_ISA_M256 (AVR_ISA_M128 | AVR_ISA_EIND) -#define AVR_ISA_XMEGA (AVR_ISA_M256 | AVR_ISA_SPMX | AVR_ISA_DES) -#define AVR_ISA_XMEGAU (AVR_ISA_XMEGA | AVR_ISA_RMW) - -#define AVR_ISA_AVR1 AVR_ISA_TINY1 -#define AVR_ISA_AVR2 AVR_ISA_2xxx -#define AVR_ISA_AVR25 AVR_ISA_TINY2 -#define AVR_ISA_AVR3 AVR_ISA_M603 -#define AVR_ISA_AVR31 AVR_ISA_M103 -#define AVR_ISA_AVR35 (AVR_ISA_AVR3 | AVR_ISA_MOVW | \ - AVR_ISA_LPMX | AVR_ISA_SPM | AVR_ISA_BRK) -#define AVR_ISA_AVR3_ALL (AVR_ISA_AVR3 | AVR_ISA_AVR31 | AVR_ISA_AVR35) -#define AVR_ISA_AVR4 AVR_ISA_PWMx -#define AVR_ISA_AVR5 AVR_ISA_M323 -#define AVR_ISA_AVR51 AVR_ISA_M128 -#define AVR_ISA_AVR6 (AVR_ISA_1200 | AVR_ISA_LPM | AVR_ISA_LPMX | \ - AVR_ISA_SRAM | AVR_ISA_MEGA | AVR_ISA_MUL | \ - AVR_ISA_ELPM | AVR_ISA_ELPMX | AVR_ISA_SPM | \ - AVR_ISA_BRK | AVR_ISA_EIND | AVR_ISA_MOVW) - -#define REGISTER_P(x) ((x) == 'r' \ - || (x) == 'd' \ - || (x) == 'w' \ - || (x) == 'a' \ - || (x) == 'v') - -/* Undefined combination of operands - does the register - operand overlap with pre-decremented or post-incremented - pointer register (like ld r31,Z+)? */ -#define AVR_UNDEF_P(x) (((x) & 0xFFED) == 0x91E5 || \ - ((x) & 0xFDEF) == 0x91AD || ((x) & 0xFDEF) == 0x91AE || \ - ((x) & 0xFDEF) == 0x91C9 || ((x) & 0xFDEF) == 0x91CA || \ - ((x) & 0xFDEF) == 0x91E1 || ((x) & 0xFDEF) == 0x91E2) - -/* Is this a skip instruction {cpse,sbic,sbis,sbrc,sbrs}? */ -#define AVR_SKIP_P(x) (((x) & 0xFC00) == 0x1000 || \ - ((x) & 0xFD00) == 0x9900 || ((x) & 0xFC08) == 0xFC00) - -/* Is this `ldd r,b+0' or `std b+0,r' (b={Y,Z}, disassembled as - `ld r,b' or `st b,r' respectively - next opcode entry)? */ -#define AVR_DISP0_P(x) (((x) & 0xFC07) == 0x8000) - -/* constraint letters - r - any register - d - `ldi' register (r16-r31) - v - `movw' even register (r0, r2, ..., r28, r30) - a - `fmul' register (r16-r23) - w - `adiw' register (r24,r26,r28,r30) - e - pointer registers (X,Y,Z) - b - base pointer register and displacement ([YZ]+disp) - z - Z pointer register (for [e]lpm Rd,Z[+]) - M - immediate value from 0 to 255 - n - immediate value from 0 to 255 ( n = ~M ). Relocation impossible - s - immediate value from 0 to 7 - P - Port address value from 0 to 63. (in, out) - p - Port address value from 0 to 31. (cbi, sbi, sbic, sbis) - K - immediate value from 0 to 63 (used in `adiw', `sbiw') - i - immediate value - l - signed pc relative offset from -64 to 63 - L - signed pc relative offset from -2048 to 2047 - h - absolute code address (call, jmp) - S - immediate value from 0 to 7 (S = s << 4) - E - immediate value from 0 to 15, shifted left by 4 (des) - ? - use this opcode entry if no parameters, else use next opcode entry - - Order is important - some binary opcodes have more than one name, - the disassembler will only see the first match. - - Remaining undefined opcodes (1699 total - some of them might work - as normal instructions if not all of the bits are decoded): - - 0x0001...0x00ff (255) (known to be decoded as `nop' by the old core) - "100100xxxxxxx011" (128) 0x9[0-3][0-9a-f][3b] - "100100xxxxxx1000" (64) 0x9[0-3][0-9a-f]8 - "1001010xxxxx0100" (32) 0x9[45][0-9a-f]4 - "1001010x001x1001" (4) 0x9[45][23]9 - "1001010x01xx1001" (8) 0x9[45][4-7]9 - "1001010x1xxx1001" (16) 0x9[45][8-9a-f]9 - "1001010xxxxx1011" (32) 0x9[45][0-9a-f]b - "10010101001x1000" (2) 0x95[23]8 - "1001010101xx1000" (4) 0x95[4-7]8 - "1001010110111000" (1) 0x95b8 - "1001010111111000" (1) 0x95f8 (`espm' removed in databook update) - "11111xxxxxxx1xxx" (1024) 0xf[8-9a-f][0-9a-f][8-9a-f] - */ - -AVR_INSN (clc, "", "1001010010001000", 1, AVR_ISA_1200, 0x9488) -AVR_INSN (clh, "", "1001010011011000", 1, AVR_ISA_1200, 0x94d8) -AVR_INSN (cli, "", "1001010011111000", 1, AVR_ISA_1200, 0x94f8) -AVR_INSN (cln, "", "1001010010101000", 1, AVR_ISA_1200, 0x94a8) -AVR_INSN (cls, "", "1001010011001000", 1, AVR_ISA_1200, 0x94c8) -AVR_INSN (clt, "", "1001010011101000", 1, AVR_ISA_1200, 0x94e8) -AVR_INSN (clv, "", "1001010010111000", 1, AVR_ISA_1200, 0x94b8) -AVR_INSN (clz, "", "1001010010011000", 1, AVR_ISA_1200, 0x9498) - -AVR_INSN (sec, "", "1001010000001000", 1, AVR_ISA_1200, 0x9408) -AVR_INSN (seh, "", "1001010001011000", 1, AVR_ISA_1200, 0x9458) -AVR_INSN (sei, "", "1001010001111000", 1, AVR_ISA_1200, 0x9478) -AVR_INSN (sen, "", "1001010000101000", 1, AVR_ISA_1200, 0x9428) -AVR_INSN (ses, "", "1001010001001000", 1, AVR_ISA_1200, 0x9448) -AVR_INSN (set, "", "1001010001101000", 1, AVR_ISA_1200, 0x9468) -AVR_INSN (sev, "", "1001010000111000", 1, AVR_ISA_1200, 0x9438) -AVR_INSN (sez, "", "1001010000011000", 1, AVR_ISA_1200, 0x9418) - - /* Same as {cl,se}[chinstvz] above. */ -AVR_INSN (bclr, "S", "100101001SSS1000", 1, AVR_ISA_1200, 0x9488) -AVR_INSN (bset, "S", "100101000SSS1000", 1, AVR_ISA_1200, 0x9408) - -AVR_INSN (icall,"", "1001010100001001", 1, AVR_ISA_2xxx, 0x9509) -AVR_INSN (ijmp, "", "1001010000001001", 1, AVR_ISA_2xxx, 0x9409) - -AVR_INSN (lpm, "?", "1001010111001000", 1, AVR_ISA_TINY1,0x95c8) -AVR_INSN (lpm, "r,z", "1001000ddddd010+", 1, AVR_ISA_LPMX, 0x9004) -AVR_INSN (elpm, "?", "1001010111011000", 1, AVR_ISA_ELPM, 0x95d8) -AVR_INSN (elpm, "r,z", "1001000ddddd011+", 1, AVR_ISA_ELPMX,0x9006) - -AVR_INSN (nop, "", "0000000000000000", 1, AVR_ISA_1200, 0x0000) -AVR_INSN (ret, "", "1001010100001000", 1, AVR_ISA_1200, 0x9508) -AVR_INSN (reti, "", "1001010100011000", 1, AVR_ISA_1200, 0x9518) -AVR_INSN (sleep,"", "1001010110001000", 1, AVR_ISA_1200, 0x9588) -AVR_INSN (break,"", "1001010110011000", 1, AVR_ISA_BRK, 0x9598) -AVR_INSN (wdr, "", "1001010110101000", 1, AVR_ISA_1200, 0x95a8) -AVR_INSN (spm, "?", "1001010111101000", 1, AVR_ISA_SPM, 0x95e8) -AVR_INSN (spm, "z", "10010101111+1000", 1, AVR_ISA_SPMX, 0x95e8) - -AVR_INSN (adc, "r,r", "000111rdddddrrrr", 1, AVR_ISA_1200, 0x1c00) -AVR_INSN (add, "r,r", "000011rdddddrrrr", 1, AVR_ISA_1200, 0x0c00) -AVR_INSN (and, "r,r", "001000rdddddrrrr", 1, AVR_ISA_1200, 0x2000) -AVR_INSN (cp, "r,r", "000101rdddddrrrr", 1, AVR_ISA_1200, 0x1400) -AVR_INSN (cpc, "r,r", "000001rdddddrrrr", 1, AVR_ISA_1200, 0x0400) -AVR_INSN (cpse, "r,r", "000100rdddddrrrr", 1, AVR_ISA_1200, 0x1000) -AVR_INSN (eor, "r,r", "001001rdddddrrrr", 1, AVR_ISA_1200, 0x2400) -AVR_INSN (mov, "r,r", "001011rdddddrrrr", 1, AVR_ISA_1200, 0x2c00) -AVR_INSN (mul, "r,r", "100111rdddddrrrr", 1, AVR_ISA_MUL, 0x9c00) -AVR_INSN (or, "r,r", "001010rdddddrrrr", 1, AVR_ISA_1200, 0x2800) -AVR_INSN (sbc, "r,r", "000010rdddddrrrr", 1, AVR_ISA_1200, 0x0800) -AVR_INSN (sub, "r,r", "000110rdddddrrrr", 1, AVR_ISA_1200, 0x1800) - - /* Shorthand for {eor,add,adc,and} r,r above. */ -AVR_INSN (clr, "r=r", "001001rdddddrrrr", 1, AVR_ISA_1200, 0x2400) -AVR_INSN (lsl, "r=r", "000011rdddddrrrr", 1, AVR_ISA_1200, 0x0c00) -AVR_INSN (rol, "r=r", "000111rdddddrrrr", 1, AVR_ISA_1200, 0x1c00) -AVR_INSN (tst, "r=r", "001000rdddddrrrr", 1, AVR_ISA_1200, 0x2000) - -AVR_INSN (andi, "d,M", "0111KKKKddddKKKK", 1, AVR_ISA_1200, 0x7000) - /*XXX special case*/ -AVR_INSN (cbr, "d,n", "0111KKKKddddKKKK", 1, AVR_ISA_1200, 0x7000) - -AVR_INSN (ldi, "d,M", "1110KKKKddddKKKK", 1, AVR_ISA_1200, 0xe000) -AVR_INSN (ser, "d", "11101111dddd1111", 1, AVR_ISA_1200, 0xef0f) - -AVR_INSN (ori, "d,M", "0110KKKKddddKKKK", 1, AVR_ISA_1200, 0x6000) -AVR_INSN (sbr, "d,M", "0110KKKKddddKKKK", 1, AVR_ISA_1200, 0x6000) - -AVR_INSN (cpi, "d,M", "0011KKKKddddKKKK", 1, AVR_ISA_1200, 0x3000) -AVR_INSN (sbci, "d,M", "0100KKKKddddKKKK", 1, AVR_ISA_1200, 0x4000) -AVR_INSN (subi, "d,M", "0101KKKKddddKKKK", 1, AVR_ISA_1200, 0x5000) - -AVR_INSN (sbrc, "r,s", "1111110rrrrr0sss", 1, AVR_ISA_1200, 0xfc00) -AVR_INSN (sbrs, "r,s", "1111111rrrrr0sss", 1, AVR_ISA_1200, 0xfe00) -AVR_INSN (bld, "r,s", "1111100ddddd0sss", 1, AVR_ISA_1200, 0xf800) -AVR_INSN (bst, "r,s", "1111101ddddd0sss", 1, AVR_ISA_1200, 0xfa00) - -AVR_INSN (in, "r,P", "10110PPdddddPPPP", 1, AVR_ISA_1200, 0xb000) -AVR_INSN (out, "P,r", "10111PPrrrrrPPPP", 1, AVR_ISA_1200, 0xb800) - -AVR_INSN (adiw, "w,K", "10010110KKddKKKK", 1, AVR_ISA_2xxx, 0x9600) -AVR_INSN (sbiw, "w,K", "10010111KKddKKKK", 1, AVR_ISA_2xxx, 0x9700) - -AVR_INSN (cbi, "p,s", "10011000pppppsss", 1, AVR_ISA_1200, 0x9800) -AVR_INSN (sbi, "p,s", "10011010pppppsss", 1, AVR_ISA_1200, 0x9a00) -AVR_INSN (sbic, "p,s", "10011001pppppsss", 1, AVR_ISA_1200, 0x9900) -AVR_INSN (sbis, "p,s", "10011011pppppsss", 1, AVR_ISA_1200, 0x9b00) - -AVR_INSN (brcc, "l", "111101lllllll000", 1, AVR_ISA_1200, 0xf400) -AVR_INSN (brcs, "l", "111100lllllll000", 1, AVR_ISA_1200, 0xf000) -AVR_INSN (breq, "l", "111100lllllll001", 1, AVR_ISA_1200, 0xf001) -AVR_INSN (brge, "l", "111101lllllll100", 1, AVR_ISA_1200, 0xf404) -AVR_INSN (brhc, "l", "111101lllllll101", 1, AVR_ISA_1200, 0xf405) -AVR_INSN (brhs, "l", "111100lllllll101", 1, AVR_ISA_1200, 0xf005) -AVR_INSN (brid, "l", "111101lllllll111", 1, AVR_ISA_1200, 0xf407) -AVR_INSN (brie, "l", "111100lllllll111", 1, AVR_ISA_1200, 0xf007) -AVR_INSN (brlo, "l", "111100lllllll000", 1, AVR_ISA_1200, 0xf000) -AVR_INSN (brlt, "l", "111100lllllll100", 1, AVR_ISA_1200, 0xf004) -AVR_INSN (brmi, "l", "111100lllllll010", 1, AVR_ISA_1200, 0xf002) -AVR_INSN (brne, "l", "111101lllllll001", 1, AVR_ISA_1200, 0xf401) -AVR_INSN (brpl, "l", "111101lllllll010", 1, AVR_ISA_1200, 0xf402) -AVR_INSN (brsh, "l", "111101lllllll000", 1, AVR_ISA_1200, 0xf400) -AVR_INSN (brtc, "l", "111101lllllll110", 1, AVR_ISA_1200, 0xf406) -AVR_INSN (brts, "l", "111100lllllll110", 1, AVR_ISA_1200, 0xf006) -AVR_INSN (brvc, "l", "111101lllllll011", 1, AVR_ISA_1200, 0xf403) -AVR_INSN (brvs, "l", "111100lllllll011", 1, AVR_ISA_1200, 0xf003) - - /* Same as br?? above. */ -AVR_INSN (brbc, "s,l", "111101lllllllsss", 1, AVR_ISA_1200, 0xf400) -AVR_INSN (brbs, "s,l", "111100lllllllsss", 1, AVR_ISA_1200, 0xf000) - -AVR_INSN (rcall, "L", "1101LLLLLLLLLLLL", 1, AVR_ISA_1200, 0xd000) -AVR_INSN (rjmp, "L", "1100LLLLLLLLLLLL", 1, AVR_ISA_1200, 0xc000) - -AVR_INSN (call, "h", "1001010hhhhh111h", 2, AVR_ISA_MEGA, 0x940e) -AVR_INSN (jmp, "h", "1001010hhhhh110h", 2, AVR_ISA_MEGA, 0x940c) - -AVR_INSN (asr, "r", "1001010rrrrr0101", 1, AVR_ISA_1200, 0x9405) -AVR_INSN (com, "r", "1001010rrrrr0000", 1, AVR_ISA_1200, 0x9400) -AVR_INSN (dec, "r", "1001010rrrrr1010", 1, AVR_ISA_1200, 0x940a) -AVR_INSN (inc, "r", "1001010rrrrr0011", 1, AVR_ISA_1200, 0x9403) -AVR_INSN (lsr, "r", "1001010rrrrr0110", 1, AVR_ISA_1200, 0x9406) -AVR_INSN (neg, "r", "1001010rrrrr0001", 1, AVR_ISA_1200, 0x9401) -AVR_INSN (pop, "r", "1001000rrrrr1111", 1, AVR_ISA_2xxx, 0x900f) -AVR_INSN (push, "r", "1001001rrrrr1111", 1, AVR_ISA_2xxx, 0x920f) -AVR_INSN (ror, "r", "1001010rrrrr0111", 1, AVR_ISA_1200, 0x9407) -AVR_INSN (swap, "r", "1001010rrrrr0010", 1, AVR_ISA_1200, 0x9402) - - /* Atomic memory operations for XMEGA. List before `sts'. */ -AVR_INSN (xch, "z,r", "1001001rrrrr0100", 1, AVR_ISA_RMW, 0x9204) -AVR_INSN (las, "z,r", "1001001rrrrr0101", 1, AVR_ISA_RMW, 0x9205) -AVR_INSN (lac, "z,r", "1001001rrrrr0110", 1, AVR_ISA_RMW, 0x9206) -AVR_INSN (lat, "z,r", "1001001rrrrr0111", 1, AVR_ISA_RMW, 0x9207) - - /* Known to be decoded as `nop' by the old core. */ -AVR_INSN (movw, "v,v", "00000001ddddrrrr", 1, AVR_ISA_MOVW, 0x0100) -AVR_INSN (muls, "d,d", "00000010ddddrrrr", 1, AVR_ISA_MUL, 0x0200) -AVR_INSN (mulsu,"a,a", "000000110ddd0rrr", 1, AVR_ISA_MUL, 0x0300) -AVR_INSN (fmul, "a,a", "000000110ddd1rrr", 1, AVR_ISA_MUL, 0x0308) -AVR_INSN (fmuls,"a,a", "000000111ddd0rrr", 1, AVR_ISA_MUL, 0x0380) -AVR_INSN (fmulsu,"a,a","000000111ddd1rrr", 1, AVR_ISA_MUL, 0x0388) - -AVR_INSN (sts, "i,r", "1001001ddddd0000", 2, AVR_ISA_2xxx, 0x9200) -AVR_INSN (lds, "r,i", "1001000ddddd0000", 2, AVR_ISA_2xxx, 0x9000) - - /* Special case for b+0, `e' must be next entry after `b', - b={Y=1,Z=0}, ee={X=11,Y=10,Z=00}, !=1 if -e or e+ or X. */ -AVR_INSN (ldd, "r,b", "10o0oo0dddddbooo", 1, AVR_ISA_2xxx, 0x8000) -AVR_INSN (ld, "r,e", "100!000dddddee-+", 1, AVR_ISA_1200, 0x8000) -AVR_INSN (std, "b,r", "10o0oo1rrrrrbooo", 1, AVR_ISA_2xxx, 0x8200) -AVR_INSN (st, "e,r", "100!001rrrrree-+", 1, AVR_ISA_1200, 0x8200) - - /* These are for devices that don't exist yet - (>128K program memory, PC = EIND:Z). */ -AVR_INSN (eicall, "", "1001010100011001", 1, AVR_ISA_EIND, 0x9519) -AVR_INSN (eijmp, "", "1001010000011001", 1, AVR_ISA_EIND, 0x9419) - -/* DES instruction for encryption and decryption */ -AVR_INSN (des, "E", "10010100EEEE1011", 1, AVR_ISA_DES, 0x940B) - diff --git a/include/opcode/bfin.h b/include/opcode/bfin.h deleted file mode 100755 index 26f0193..0000000 --- a/include/opcode/bfin.h +++ /dev/null @@ -1,1761 +0,0 @@ -/* bfin.h -- Header file for ADI Blackfin opcode table - Copyright 2005, 2010, 2011 Free Software Foundation, Inc. - - This file is part of GDB, GAS, and the GNU binutils. - - GDB, GAS, and the GNU binutils are free software; you can redistribute - them and/or modify them under the terms of the GNU General Public - License as published by the Free Software Foundation; either version 3, - or (at your option) any later version. - - GDB, GAS, and the GNU binutils are distributed in the hope that they - will be useful, but WITHOUT ANY WARRANTY; without even the implied - warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See - the GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this file; see the file COPYING3. If not, write to the Free - Software Foundation, 51 Franklin Street - Fifth Floor, Boston, - MA 02110-1301, USA. */ - -#ifndef OPCODE_BFIN_H -#define OPCODE_BFIN_H - -/* Common to all DSP32 instructions. */ -#define BIT_MULTI_INS 0x0800 - -/* This just sets the multi instruction bit of a DSP32 instruction. */ -#define SET_MULTI_INSTRUCTION_BIT(x) x->value |= BIT_MULTI_INS; - - -/* DSP instructions (32 bit) */ - -/* mmod field. */ -#define M_S2RND 1 -#define M_T 2 -#define M_W32 3 -#define M_FU 4 -#define M_TFU 6 -#define M_IS 8 -#define M_ISS2 9 -#define M_IH 11 -#define M_IU 12 - -static inline int is_macmod_pmove (int x) -{ - return (x == 0) || (x == M_IS) || (x == M_FU) || (x == M_S2RND) - || (x == M_ISS2) || (x == M_IU); -} - -static inline int is_macmod_hmove (int x) -{ - return (x == 0) || (x == M_IS) || (x == M_FU) || (x == M_IU) || (x == M_T) - || (x == M_TFU) || (x == M_S2RND) || (x == M_ISS2) || (x == M_IH); -} - -static inline int is_macmod_signed (int x) -{ - return (x == 0) || (x == M_IS) || (x == M_T) || (x == M_S2RND) - || (x == M_ISS2) || (x == M_IH) || (x == M_W32); -} - -/* dsp32mac -+----+----+---+---|---+----+----+---|---+---+---+---|---+---+---+---+ -| 1 | 1 | 0 | 0 |.M.| 0 | 0 |.mmod..........|.MM|.P.|.w1|.op1...| -|.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1......| -+----+----+---+---|---+----+----+---|---+---+---+---|---+---+---+---+ -*/ - -typedef struct -{ - unsigned long opcode; - int bits_src1; - int mask_src1; - int bits_src0; - int mask_src0; - int bits_dst; - int mask_dst; - int bits_h10; - int mask_h10; - int bits_h00; - int mask_h00; - int bits_op0; - int mask_op0; - int bits_w0; - int mask_w0; - int bits_h11; - int mask_h11; - int bits_h01; - int mask_h01; - int bits_op1; - int mask_op1; - int bits_w1; - int mask_w1; - int bits_P; - int mask_P; - int bits_MM; - int mask_MM; - int bits_mmod; - int mask_mmod; - int bits_code2; - int mask_code2; - int bits_M; - int mask_M; - int bits_code; - int mask_code; -} DSP32Mac; - -#define DSP32Mac_opcode 0xc0000000 -#define DSP32Mac_src1_bits 0 -#define DSP32Mac_src1_mask 0x7 -#define DSP32Mac_src0_bits 3 -#define DSP32Mac_src0_mask 0x7 -#define DSP32Mac_dst_bits 6 -#define DSP32Mac_dst_mask 0x7 -#define DSP32Mac_h10_bits 9 -#define DSP32Mac_h10_mask 0x1 -#define DSP32Mac_h00_bits 10 -#define DSP32Mac_h00_mask 0x1 -#define DSP32Mac_op0_bits 11 -#define DSP32Mac_op0_mask 0x3 -#define DSP32Mac_w0_bits 13 -#define DSP32Mac_w0_mask 0x1 -#define DSP32Mac_h11_bits 14 -#define DSP32Mac_h11_mask 0x1 -#define DSP32Mac_h01_bits 15 -#define DSP32Mac_h01_mask 0x1 -#define DSP32Mac_op1_bits 16 -#define DSP32Mac_op1_mask 0x3 -#define DSP32Mac_w1_bits 18 -#define DSP32Mac_w1_mask 0x1 -#define DSP32Mac_p_bits 19 -#define DSP32Mac_p_mask 0x1 -#define DSP32Mac_MM_bits 20 -#define DSP32Mac_MM_mask 0x1 -#define DSP32Mac_mmod_bits 21 -#define DSP32Mac_mmod_mask 0xf -#define DSP32Mac_code2_bits 25 -#define DSP32Mac_code2_mask 0x3 -#define DSP32Mac_M_bits 27 -#define DSP32Mac_M_mask 0x1 -#define DSP32Mac_code_bits 28 -#define DSP32Mac_code_mask 0xf - -#define init_DSP32Mac \ -{ \ - DSP32Mac_opcode, \ - DSP32Mac_src1_bits, DSP32Mac_src1_mask, \ - DSP32Mac_src0_bits, DSP32Mac_src0_mask, \ - DSP32Mac_dst_bits, DSP32Mac_dst_mask, \ - DSP32Mac_h10_bits, DSP32Mac_h10_mask, \ - DSP32Mac_h00_bits, DSP32Mac_h00_mask, \ - DSP32Mac_op0_bits, DSP32Mac_op0_mask, \ - DSP32Mac_w0_bits, DSP32Mac_w0_mask, \ - DSP32Mac_h11_bits, DSP32Mac_h11_mask, \ - DSP32Mac_h01_bits, DSP32Mac_h01_mask, \ - DSP32Mac_op1_bits, DSP32Mac_op1_mask, \ - DSP32Mac_w1_bits, DSP32Mac_w1_mask, \ - DSP32Mac_p_bits, DSP32Mac_p_mask, \ - DSP32Mac_MM_bits, DSP32Mac_MM_mask, \ - DSP32Mac_mmod_bits, DSP32Mac_mmod_mask, \ - DSP32Mac_code2_bits, DSP32Mac_code2_mask, \ - DSP32Mac_M_bits, DSP32Mac_M_mask, \ - DSP32Mac_code_bits, DSP32Mac_code_mask \ -}; - -/* dsp32mult -+----+----+---+---|---+----+----+---|---+---+---+---|---+---+---+---+ -| 1 | 1 | 0 | 0 |.M.| 0 | 1 |.mmod..........|.MM|.P.|.w1|.op1...| -|.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1......| -+----+----+---+---|---+----+----+---|---+---+---+---|---+---+---+---+ -*/ - -typedef DSP32Mac DSP32Mult; -#define DSP32Mult_opcode 0xc2000000 - -#define init_DSP32Mult \ -{ \ - DSP32Mult_opcode, \ - DSP32Mac_src1_bits, DSP32Mac_src1_mask, \ - DSP32Mac_src0_bits, DSP32Mac_src0_mask, \ - DSP32Mac_dst_bits, DSP32Mac_dst_mask, \ - DSP32Mac_h10_bits, DSP32Mac_h10_mask, \ - DSP32Mac_h00_bits, DSP32Mac_h00_mask, \ - DSP32Mac_op0_bits, DSP32Mac_op0_mask, \ - DSP32Mac_w0_bits, DSP32Mac_w0_mask, \ - DSP32Mac_h11_bits, DSP32Mac_h11_mask, \ - DSP32Mac_h01_bits, DSP32Mac_h01_mask, \ - DSP32Mac_op1_bits, DSP32Mac_op1_mask, \ - DSP32Mac_w1_bits, DSP32Mac_w1_mask, \ - DSP32Mac_p_bits, DSP32Mac_p_mask, \ - DSP32Mac_MM_bits, DSP32Mac_MM_mask, \ - DSP32Mac_mmod_bits, DSP32Mac_mmod_mask, \ - DSP32Mac_code2_bits, DSP32Mac_code2_mask, \ - DSP32Mac_M_bits, DSP32Mac_M_mask, \ - DSP32Mac_code_bits, DSP32Mac_code_mask \ -}; - -/* dsp32alu -+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ -| 1 | 1 | 0 | 0 |.M.| 1 | 0 | - | - | - |.HL|.aopcde............| -|.aop...|.s.|.x.|.dst0......|.dst1......|.src0......|.src1......| -+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ -*/ - -typedef struct -{ - unsigned long opcode; - int bits_src1; - int mask_src1; - int bits_src0; - int mask_src0; - int bits_dst1; - int mask_dst1; - int bits_dst0; - int mask_dst0; - int bits_x; - int mask_x; - int bits_s; - int mask_s; - int bits_aop; - int mask_aop; - int bits_aopcde; - int mask_aopcde; - int bits_HL; - int mask_HL; - int bits_dontcare; - int mask_dontcare; - int bits_code2; - int mask_code2; - int bits_M; - int mask_M; - int bits_code; - int mask_code; -} DSP32Alu; - -#define DSP32Alu_opcode 0xc4000000 -#define DSP32Alu_src1_bits 0 -#define DSP32Alu_src1_mask 0x7 -#define DSP32Alu_src0_bits 3 -#define DSP32Alu_src0_mask 0x7 -#define DSP32Alu_dst1_bits 6 -#define DSP32Alu_dst1_mask 0x7 -#define DSP32Alu_dst0_bits 9 -#define DSP32Alu_dst0_mask 0x7 -#define DSP32Alu_x_bits 12 -#define DSP32Alu_x_mask 0x1 -#define DSP32Alu_s_bits 13 -#define DSP32Alu_s_mask 0x1 -#define DSP32Alu_aop_bits 14 -#define DSP32Alu_aop_mask 0x3 -#define DSP32Alu_aopcde_bits 16 -#define DSP32Alu_aopcde_mask 0x1f -#define DSP32Alu_HL_bits 21 -#define DSP32Alu_HL_mask 0x1 -#define DSP32Alu_dontcare_bits 22 -#define DSP32Alu_dontcare_mask 0x7 -#define DSP32Alu_code2_bits 25 -#define DSP32Alu_code2_mask 0x3 -#define DSP32Alu_M_bits 27 -#define DSP32Alu_M_mask 0x1 -#define DSP32Alu_code_bits 28 -#define DSP32Alu_code_mask 0xf - -#define init_DSP32Alu \ -{ \ - DSP32Alu_opcode, \ - DSP32Alu_src1_bits, DSP32Alu_src1_mask, \ - DSP32Alu_src0_bits, DSP32Alu_src0_mask, \ - DSP32Alu_dst1_bits, DSP32Alu_dst1_mask, \ - DSP32Alu_dst0_bits, DSP32Alu_dst0_mask, \ - DSP32Alu_x_bits, DSP32Alu_x_mask, \ - DSP32Alu_s_bits, DSP32Alu_s_mask, \ - DSP32Alu_aop_bits, DSP32Alu_aop_mask, \ - DSP32Alu_aopcde_bits, DSP32Alu_aopcde_mask, \ - DSP32Alu_HL_bits, DSP32Alu_HL_mask, \ - DSP32Alu_dontcare_bits, DSP32Alu_dontcare_mask, \ - DSP32Alu_code2_bits, DSP32Alu_code2_mask, \ - DSP32Alu_M_bits, DSP32Alu_M_mask, \ - DSP32Alu_code_bits, DSP32Alu_code_mask \ -}; - -/* dsp32shift -+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ -| 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 0 | - | - |.sopcde............| -|.sop...|.HLs...|.dst0......| - | - | - |.src0......|.src1......| -+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ -*/ - -typedef struct -{ - unsigned long opcode; - int bits_src1; - int mask_src1; - int bits_src0; - int mask_src0; - int bits_dst1; - int mask_dst1; - int bits_dst0; - int mask_dst0; - int bits_HLs; - int mask_HLs; - int bits_sop; - int mask_sop; - int bits_sopcde; - int mask_sopcde; - int bits_dontcare; - int mask_dontcare; - int bits_code2; - int mask_code2; - int bits_M; - int mask_M; - int bits_code; - int mask_code; -} DSP32Shift; - -#define DSP32Shift_opcode 0xc6000000 -#define DSP32Shift_src1_bits 0 -#define DSP32Shift_src1_mask 0x7 -#define DSP32Shift_src0_bits 3 -#define DSP32Shift_src0_mask 0x7 -#define DSP32Shift_dst1_bits 6 -#define DSP32Shift_dst1_mask 0x7 -#define DSP32Shift_dst0_bits 9 -#define DSP32Shift_dst0_mask 0x7 -#define DSP32Shift_HLs_bits 12 -#define DSP32Shift_HLs_mask 0x3 -#define DSP32Shift_sop_bits 14 -#define DSP32Shift_sop_mask 0x3 -#define DSP32Shift_sopcde_bits 16 -#define DSP32Shift_sopcde_mask 0x1f -#define DSP32Shift_dontcare_bits 21 -#define DSP32Shift_dontcare_mask 0x3 -#define DSP32Shift_code2_bits 23 -#define DSP32Shift_code2_mask 0xf -#define DSP32Shift_M_bits 27 -#define DSP32Shift_M_mask 0x1 -#define DSP32Shift_code_bits 28 -#define DSP32Shift_code_mask 0xf - -#define init_DSP32Shift \ -{ \ - DSP32Shift_opcode, \ - DSP32Shift_src1_bits, DSP32Shift_src1_mask, \ - DSP32Shift_src0_bits, DSP32Shift_src0_mask, \ - DSP32Shift_dst1_bits, DSP32Shift_dst1_mask, \ - DSP32Shift_dst0_bits, DSP32Shift_dst0_mask, \ - DSP32Shift_HLs_bits, DSP32Shift_HLs_mask, \ - DSP32Shift_sop_bits, DSP32Shift_sop_mask, \ - DSP32Shift_sopcde_bits, DSP32Shift_sopcde_mask, \ - DSP32Shift_dontcare_bits, DSP32Shift_dontcare_mask, \ - DSP32Shift_code2_bits, DSP32Shift_code2_mask, \ - DSP32Shift_M_bits, DSP32Shift_M_mask, \ - DSP32Shift_code_bits, DSP32Shift_code_mask \ -}; - -/* dsp32shiftimm -+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ -| 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 1 | - | - |.sopcde............| -|.sop...|.HLs...|.dst0......|.immag.................|.src1......| -+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ -*/ - -typedef struct -{ - unsigned long opcode; - int bits_src1; - int mask_src1; - int bits_immag; - int mask_immag; - int bits_dst0; - int mask_dst0; - int bits_HLs; - int mask_HLs; - int bits_sop; - int mask_sop; - int bits_sopcde; - int mask_sopcde; - int bits_dontcare; - int mask_dontcare; - int bits_code2; - int mask_code2; - int bits_M; - int mask_M; - int bits_code; - int mask_code; -} DSP32ShiftImm; - -#define DSP32ShiftImm_opcode 0xc6800000 -#define DSP32ShiftImm_src1_bits 0 -#define DSP32ShiftImm_src1_mask 0x7 -#define DSP32ShiftImm_immag_bits 3 -#define DSP32ShiftImm_immag_mask 0x3f -#define DSP32ShiftImm_dst0_bits 9 -#define DSP32ShiftImm_dst0_mask 0x7 -#define DSP32ShiftImm_HLs_bits 12 -#define DSP32ShiftImm_HLs_mask 0x3 -#define DSP32ShiftImm_sop_bits 14 -#define DSP32ShiftImm_sop_mask 0x3 -#define DSP32ShiftImm_sopcde_bits 16 -#define DSP32ShiftImm_sopcde_mask 0x1f -#define DSP32ShiftImm_dontcare_bits 21 -#define DSP32ShiftImm_dontcare_mask 0x3 -#define DSP32ShiftImm_code2_bits 23 -#define DSP32ShiftImm_code2_mask 0xf -#define DSP32ShiftImm_M_bits 27 -#define DSP32ShiftImm_M_mask 0x1 -#define DSP32ShiftImm_code_bits 28 -#define DSP32ShiftImm_code_mask 0xf - -#define init_DSP32ShiftImm \ -{ \ - DSP32ShiftImm_opcode, \ - DSP32ShiftImm_src1_bits, DSP32ShiftImm_src1_mask, \ - DSP32ShiftImm_immag_bits, DSP32ShiftImm_immag_mask, \ - DSP32ShiftImm_dst0_bits, DSP32ShiftImm_dst0_mask, \ - DSP32ShiftImm_HLs_bits, DSP32ShiftImm_HLs_mask, \ - DSP32ShiftImm_sop_bits, DSP32ShiftImm_sop_mask, \ - DSP32ShiftImm_sopcde_bits, DSP32ShiftImm_sopcde_mask, \ - DSP32ShiftImm_dontcare_bits, DSP32ShiftImm_dontcare_mask, \ - DSP32ShiftImm_code2_bits, DSP32ShiftImm_code2_mask, \ - DSP32ShiftImm_M_bits, DSP32ShiftImm_M_mask, \ - DSP32ShiftImm_code_bits, DSP32ShiftImm_code_mask \ -}; - -/* LOAD / STORE */ - -/* LDSTidxI -+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ -| 1 | 1 | 1 | 0 | 0 | 1 |.W.|.Z.|.sz....|.ptr.......|.reg.......| -|.offset........................................................| -+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ -*/ - -typedef struct -{ - unsigned long opcode; - int bits_offset; - int mask_offset; - int bits_reg; - int mask_reg; - int bits_ptr; - int mask_ptr; - int bits_sz; - int mask_sz; - int bits_Z; - int mask_Z; - int bits_W; - int mask_W; - int bits_code; - int mask_code; -} LDSTidxI; - -#define LDSTidxI_opcode 0xe4000000 -#define LDSTidxI_offset_bits 0 -#define LDSTidxI_offset_mask 0xffff -#define LDSTidxI_reg_bits 16 -#define LDSTidxI_reg_mask 0x7 -#define LDSTidxI_ptr_bits 19 -#define LDSTidxI_ptr_mask 0x7 -#define LDSTidxI_sz_bits 22 -#define LDSTidxI_sz_mask 0x3 -#define LDSTidxI_Z_bits 24 -#define LDSTidxI_Z_mask 0x1 -#define LDSTidxI_W_bits 25 -#define LDSTidxI_W_mask 0x1 -#define LDSTidxI_code_bits 26 -#define LDSTidxI_code_mask 0x3f - -#define init_LDSTidxI \ -{ \ - LDSTidxI_opcode, \ - LDSTidxI_offset_bits, LDSTidxI_offset_mask, \ - LDSTidxI_reg_bits, LDSTidxI_reg_mask, \ - LDSTidxI_ptr_bits, LDSTidxI_ptr_mask, \ - LDSTidxI_sz_bits, LDSTidxI_sz_mask, \ - LDSTidxI_Z_bits, LDSTidxI_Z_mask, \ - LDSTidxI_W_bits, LDSTidxI_W_mask, \ - LDSTidxI_code_bits, LDSTidxI_code_mask \ -}; - - -/* LDST -+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ -| 1 | 0 | 0 | 1 |.sz....|.W.|.aop...|.Z.|.ptr.......|.reg.......| -+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ -*/ - -typedef struct -{ - unsigned short opcode; - int bits_reg; - int mask_reg; - int bits_ptr; - int mask_ptr; - int bits_Z; - int mask_Z; - int bits_aop; - int mask_aop; - int bits_W; - int mask_W; - int bits_sz; - int mask_sz; - int bits_code; - int mask_code; -} LDST; - -#define LDST_opcode 0x9000 -#define LDST_reg_bits 0 -#define LDST_reg_mask 0x7 -#define LDST_ptr_bits 3 -#define LDST_ptr_mask 0x7 -#define LDST_Z_bits 6 -#define LDST_Z_mask 0x1 -#define LDST_aop_bits 7 -#define LDST_aop_mask 0x3 -#define LDST_W_bits 9 -#define LDST_W_mask 0x1 -#define LDST_sz_bits 10 -#define LDST_sz_mask 0x3 -#define LDST_code_bits 12 -#define LDST_code_mask 0xf - -#define init_LDST \ -{ \ - LDST_opcode, \ - LDST_reg_bits, LDST_reg_mask, \ - LDST_ptr_bits, LDST_ptr_mask, \ - LDST_Z_bits, LDST_Z_mask, \ - LDST_aop_bits, LDST_aop_mask, \ - LDST_W_bits, LDST_W_mask, \ - LDST_sz_bits, LDST_sz_mask, \ - LDST_code_bits, LDST_code_mask \ -}; - -/* LDSTii -+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ -| 1 | 0 | 1 |.W.|.op....|.offset........|.ptr.......|.reg.......| -+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ -*/ - -typedef struct -{ - unsigned short opcode; - int bits_reg; - int mask_reg; - int bits_ptr; - int mask_ptr; - int bits_offset; - int mask_offset; - int bits_op; - int mask_op; - int bits_W; - int mask_W; - int bits_code; - int mask_code; -} LDSTii; - -#define LDSTii_opcode 0xa000 -#define LDSTii_reg_bit 0 -#define LDSTii_reg_mask 0x7 -#define LDSTii_ptr_bit 3 -#define LDSTii_ptr_mask 0x7 -#define LDSTii_offset_bit 6 -#define LDSTii_offset_mask 0xf -#define LDSTii_op_bit 10 -#define LDSTii_op_mask 0x3 -#define LDSTii_W_bit 12 -#define LDSTii_W_mask 0x1 -#define LDSTii_code_bit 13 -#define LDSTii_code_mask 0x7 - -#define init_LDSTii \ -{ \ - LDSTii_opcode, \ - LDSTii_reg_bit, LDSTii_reg_mask, \ - LDSTii_ptr_bit, LDSTii_ptr_mask, \ - LDSTii_offset_bit, LDSTii_offset_mask, \ - LDSTii_op_bit, LDSTii_op_mask, \ - LDSTii_W_bit, LDSTii_W_mask, \ - LDSTii_code_bit, LDSTii_code_mask \ -}; - - -/* LDSTiiFP -+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ -| 1 | 0 | 1 | 1 | 1 | 0 |.W.|.offset............|.reg...........| -+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ -*/ - -typedef struct -{ - unsigned short opcode; - int bits_reg; - int mask_reg; - int bits_offset; - int mask_offset; - int bits_W; - int mask_W; - int bits_code; - int mask_code; -} LDSTiiFP; - -#define LDSTiiFP_opcode 0xb800 -#define LDSTiiFP_reg_bits 0 -#define LDSTiiFP_reg_mask 0xf -#define LDSTiiFP_offset_bits 4 -#define LDSTiiFP_offset_mask 0x1f -#define LDSTiiFP_W_bits 9 -#define LDSTiiFP_W_mask 0x1 -#define LDSTiiFP_code_bits 10 -#define LDSTiiFP_code_mask 0x3f - -#define init_LDSTiiFP \ -{ \ - LDSTiiFP_opcode, \ - LDSTiiFP_reg_bits, LDSTiiFP_reg_mask, \ - LDSTiiFP_offset_bits, LDSTiiFP_offset_mask, \ - LDSTiiFP_W_bits, LDSTiiFP_W_mask, \ - LDSTiiFP_code_bits, LDSTiiFP_code_mask \ -}; - -/* dspLDST -+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ -| 1 | 0 | 0 | 1 | 1 | 1 |.W.|.aop...|.m.....|.i.....|.reg.......| -+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ -*/ - -typedef struct -{ - unsigned short opcode; - int bits_reg; - int mask_reg; - int bits_i; - int mask_i; - int bits_m; - int mask_m; - int bits_aop; - int mask_aop; - int bits_W; - int mask_W; - int bits_code; - int mask_code; -} DspLDST; - -#define DspLDST_opcode 0x9c00 -#define DspLDST_reg_bits 0 -#define DspLDST_reg_mask 0x7 -#define DspLDST_i_bits 3 -#define DspLDST_i_mask 0x3 -#define DspLDST_m_bits 5 -#define DspLDST_m_mask 0x3 -#define DspLDST_aop_bits 7 -#define DspLDST_aop_mask 0x3 -#define DspLDST_W_bits 9 -#define DspLDST_W_mask 0x1 -#define DspLDST_code_bits 10 -#define DspLDST_code_mask 0x3f - -#define init_DspLDST \ -{ \ - DspLDST_opcode, \ - DspLDST_reg_bits, DspLDST_reg_mask, \ - DspLDST_i_bits, DspLDST_i_mask, \ - DspLDST_m_bits, DspLDST_m_mask, \ - DspLDST_aop_bits, DspLDST_aop_mask, \ - DspLDST_W_bits, DspLDST_W_mask, \ - DspLDST_code_bits, DspLDST_code_mask \ -}; - - -/* LDSTpmod -+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ -| 1 | 0 | 0 | 0 |.W.|.aop...|.reg.......|.idx.......|.ptr.......| -+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ -*/ - -typedef struct -{ - unsigned short opcode; - int bits_ptr; - int mask_ptr; - int bits_idx; - int mask_idx; - int bits_reg; - int mask_reg; - int bits_aop; - int mask_aop; - int bits_W; - int mask_W; - int bits_code; - int mask_code; -} LDSTpmod; - -#define LDSTpmod_opcode 0x8000 -#define LDSTpmod_ptr_bits 0 -#define LDSTpmod_ptr_mask 0x7 -#define LDSTpmod_idx_bits 3 -#define LDSTpmod_idx_mask 0x7 -#define LDSTpmod_reg_bits 6 -#define LDSTpmod_reg_mask 0x7 -#define LDSTpmod_aop_bits 9 -#define LDSTpmod_aop_mask 0x3 -#define LDSTpmod_W_bits 11 -#define LDSTpmod_W_mask 0x1 -#define LDSTpmod_code_bits 12 -#define LDSTpmod_code_mask 0xf - -#define init_LDSTpmod \ -{ \ - LDSTpmod_opcode, \ - LDSTpmod_ptr_bits, LDSTpmod_ptr_mask, \ - LDSTpmod_idx_bits, LDSTpmod_idx_mask, \ - LDSTpmod_reg_bits, LDSTpmod_reg_mask, \ - LDSTpmod_aop_bits, LDSTpmod_aop_mask, \ - LDSTpmod_W_bits, LDSTpmod_W_mask, \ - LDSTpmod_code_bits, LDSTpmod_code_mask \ -}; - - -/* LOGI2op -+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ -| 0 | 1 | 0 | 0 | 1 |.opc.......|.src...............|.dst.......| -+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ -*/ - -typedef struct -{ - unsigned short opcode; - int bits_dst; - int mask_dst; - int bits_src; - int mask_src; - int bits_opc; - int mask_opc; - int bits_code; - int mask_code; -} LOGI2op; - -#define LOGI2op_opcode 0x4800 -#define LOGI2op_dst_bits 0 -#define LOGI2op_dst_mask 0x7 -#define LOGI2op_src_bits 3 -#define LOGI2op_src_mask 0x1f -#define LOGI2op_opc_bits 8 -#define LOGI2op_opc_mask 0x7 -#define LOGI2op_code_bits 11 -#define LOGI2op_code_mask 0x1f - -#define init_LOGI2op \ -{ \ - LOGI2op_opcode, \ - LOGI2op_dst_bits, LOGI2op_dst_mask, \ - LOGI2op_src_bits, LOGI2op_src_mask, \ - LOGI2op_opc_bits, LOGI2op_opc_mask, \ - LOGI2op_code_bits, LOGI2op_code_mask \ -}; - - -/* ALU2op -+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ -| 0 | 1 | 0 | 0 | 0 | 0 |.opc...........|.src.......|.dst.......| -+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ -*/ - -typedef struct -{ - unsigned short opcode; - int bits_dst; - int mask_dst; - int bits_src; - int mask_src; - int bits_opc; - int mask_opc; - int bits_code; - int mask_code; -} ALU2op; - -#define ALU2op_opcode 0x4000 -#define ALU2op_dst_bits 0 -#define ALU2op_dst_mask 0x7 -#define ALU2op_src_bits 3 -#define ALU2op_src_mask 0x7 -#define ALU2op_opc_bits 6 -#define ALU2op_opc_mask 0xf -#define ALU2op_code_bits 10 -#define ALU2op_code_mask 0x3f - -#define init_ALU2op \ -{ \ - ALU2op_opcode, \ - ALU2op_dst_bits, ALU2op_dst_mask, \ - ALU2op_src_bits, ALU2op_src_mask, \ - ALU2op_opc_bits, ALU2op_opc_mask, \ - ALU2op_code_bits, ALU2op_code_mask \ -}; - - -/* BRCC -+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ -| 0 | 0 | 0 | 1 |.T.|.B.|.offset................................| -+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ -*/ - -typedef struct -{ - unsigned short opcode; - int bits_offset; - int mask_offset; - int bits_B; - int mask_B; - int bits_T; - int mask_T; - int bits_code; - int mask_code; -} BRCC; - -#define BRCC_opcode 0x1000 -#define BRCC_offset_bits 0 -#define BRCC_offset_mask 0x3ff -#define BRCC_B_bits 10 -#define BRCC_B_mask 0x1 -#define BRCC_T_bits 11 -#define BRCC_T_mask 0x1 -#define BRCC_code_bits 12 -#define BRCC_code_mask 0xf - -#define init_BRCC \ -{ \ - BRCC_opcode, \ - BRCC_offset_bits, BRCC_offset_mask, \ - BRCC_B_bits, BRCC_B_mask, \ - BRCC_T_bits, BRCC_T_mask, \ - BRCC_code_bits, BRCC_code_mask \ -}; - - -/* UJUMP -+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ -| 0 | 0 | 1 | 0 |.offset........................................| -+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ -*/ - -typedef struct -{ - unsigned short opcode; - int bits_offset; - int mask_offset; - int bits_code; - int mask_code; -} UJump; - -#define UJump_opcode 0x2000 -#define UJump_offset_bits 0 -#define UJump_offset_mask 0xfff -#define UJump_code_bits 12 -#define UJump_code_mask 0xf - -#define init_UJump \ -{ \ - UJump_opcode, \ - UJump_offset_bits, UJump_offset_mask, \ - UJump_code_bits, UJump_code_mask \ -}; - - -/* ProgCtrl -+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ -| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.prgfunc.......|.poprnd........| -+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ -*/ - -typedef struct -{ - unsigned short opcode; - int bits_poprnd; - int mask_poprnd; - int bits_prgfunc; - int mask_prgfunc; - int bits_code; - int mask_code; -} ProgCtrl; - -#define ProgCtrl_opcode 0x0000 -#define ProgCtrl_poprnd_bits 0 -#define ProgCtrl_poprnd_mask 0xf -#define ProgCtrl_prgfunc_bits 4 -#define ProgCtrl_prgfunc_mask 0xf -#define ProgCtrl_code_bits 8 -#define ProgCtrl_code_mask 0xff - -#define init_ProgCtrl \ -{ \ - ProgCtrl_opcode, \ - ProgCtrl_poprnd_bits, ProgCtrl_poprnd_mask, \ - ProgCtrl_prgfunc_bits, ProgCtrl_prgfunc_mask, \ - ProgCtrl_code_bits, ProgCtrl_code_mask \ -}; - -/* CALLa -+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ -| 1 | 1 | 1 | 0 | 0 | 0 | 1 |.S.|.msw...........................| -|.lsw...........................................................| -+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ -*/ - - -typedef struct -{ - unsigned long opcode; - int bits_addr; - int mask_addr; - int bits_S; - int mask_S; - int bits_code; - int mask_code; -} CALLa; - -#define CALLa_opcode 0xe2000000 -#define CALLa_addr_bits 0 -#define CALLa_addr_mask 0xffffff -#define CALLa_S_bits 24 -#define CALLa_S_mask 0x1 -#define CALLa_code_bits 25 -#define CALLa_code_mask 0x7f - -#define init_CALLa \ -{ \ - CALLa_opcode, \ - CALLa_addr_bits, CALLa_addr_mask, \ - CALLa_S_bits, CALLa_S_mask, \ - CALLa_code_bits, CALLa_code_mask \ -}; - - -/* pseudoDEBUG -+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ -| 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |.fn....|.grp.......|.reg.......| -+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ -*/ - -typedef struct -{ - unsigned short opcode; - int bits_reg; - int mask_reg; - int bits_grp; - int mask_grp; - int bits_fn; - int mask_fn; - int bits_code; - int mask_code; -} PseudoDbg; - -#define PseudoDbg_opcode 0xf800 -#define PseudoDbg_reg_bits 0 -#define PseudoDbg_reg_mask 0x7 -#define PseudoDbg_grp_bits 3 -#define PseudoDbg_grp_mask 0x7 -#define PseudoDbg_fn_bits 6 -#define PseudoDbg_fn_mask 0x3 -#define PseudoDbg_code_bits 8 -#define PseudoDbg_code_mask 0xff - -#define init_PseudoDbg \ -{ \ - PseudoDbg_opcode, \ - PseudoDbg_reg_bits, PseudoDbg_reg_mask, \ - PseudoDbg_grp_bits, PseudoDbg_grp_mask, \ - PseudoDbg_fn_bits, PseudoDbg_fn_mask, \ - PseudoDbg_code_bits, PseudoDbg_code_mask \ -}; - -/* PseudoDbg_assert -+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ -| 1 | 1 | 1 | 1 | 0 | - | - | - | dbgop |.grp.......|.regtest...| -|.expected......................................................| -+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ -*/ - -typedef struct -{ - unsigned long opcode; - int bits_expected; - int mask_expected; - int bits_regtest; - int mask_regtest; - int bits_grp; - int mask_grp; - int bits_dbgop; - int mask_dbgop; - int bits_dontcare; - int mask_dontcare; - int bits_code; - int mask_code; -} PseudoDbg_Assert; - -#define PseudoDbg_Assert_opcode 0xf0000000 -#define PseudoDbg_Assert_expected_bits 0 -#define PseudoDbg_Assert_expected_mask 0xffff -#define PseudoDbg_Assert_regtest_bits 16 -#define PseudoDbg_Assert_regtest_mask 0x7 -#define PseudoDbg_Assert_grp_bits 19 -#define PseudoDbg_Assert_grp_mask 0x7 -#define PseudoDbg_Assert_dbgop_bits 22 -#define PseudoDbg_Assert_dbgop_mask 0x3 -#define PseudoDbg_Assert_dontcare_bits 24 -#define PseudoDbg_Assert_dontcare_mask 0x7 -#define PseudoDbg_Assert_code_bits 27 -#define PseudoDbg_Assert_code_mask 0x1f - -#define init_PseudoDbg_Assert \ -{ \ - PseudoDbg_Assert_opcode, \ - PseudoDbg_Assert_expected_bits, PseudoDbg_Assert_expected_mask, \ - PseudoDbg_Assert_regtest_bits, PseudoDbg_Assert_regtest_mask, \ - PseudoDbg_Assert_grp_bits, PseudoDbg_Assert_grp_mask, \ - PseudoDbg_Assert_dbgop_bits, PseudoDbg_Assert_dbgop_mask, \ - PseudoDbg_Assert_dontcare_bits, PseudoDbg_Assert_dontcare_mask, \ - PseudoDbg_Assert_code_bits, PseudoDbg_Assert_code_mask \ -}; - -/* pseudoChr -+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ -| 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |.ch............................| -+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ -*/ - -typedef struct -{ - unsigned short opcode; - int bits_ch; - int mask_ch; - int bits_code; - int mask_code; -} PseudoChr; - -#define PseudoChr_opcode 0xf900 -#define PseudoChr_ch_bits 0 -#define PseudoChr_ch_mask 0xff -#define PseudoChr_code_bits 8 -#define PseudoChr_code_mask 0xff - -#define init_PseudoChr \ -{ \ - PseudoChr_opcode, \ - PseudoChr_ch_bits, PseudoChr_ch_mask, \ - PseudoChr_code_bits, PseudoChr_code_mask \ -}; - -/* CaCTRL -+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ -| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |.a.|.op....|.reg.......| -+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ -*/ - -typedef struct -{ - unsigned short opcode; - int bits_reg; - int mask_reg; - int bits_op; - int mask_op; - int bits_a; - int mask_a; - int bits_code; - int mask_code; -} CaCTRL; - -#define CaCTRL_opcode 0x0240 -#define CaCTRL_reg_bits 0 -#define CaCTRL_reg_mask 0x7 -#define CaCTRL_op_bits 3 -#define CaCTRL_op_mask 0x3 -#define CaCTRL_a_bits 5 -#define CaCTRL_a_mask 0x1 -#define CaCTRL_code_bits 6 -#define CaCTRL_code_mask 0x3fff - -#define init_CaCTRL \ -{ \ - CaCTRL_opcode, \ - CaCTRL_reg_bits, CaCTRL_reg_mask, \ - CaCTRL_op_bits, CaCTRL_op_mask, \ - CaCTRL_a_bits, CaCTRL_a_mask, \ - CaCTRL_code_bits, CaCTRL_code_mask \ -}; - -/* PushPopMultiple -+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ -| 0 | 0 | 0 | 0 | 0 | 1 | 0 |.d.|.p.|.W.|.dr........|.pr........| -+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ -*/ - -typedef struct -{ - unsigned short opcode; - int bits_pr; - int mask_pr; - int bits_dr; - int mask_dr; - int bits_W; - int mask_W; - int bits_p; - int mask_p; - int bits_d; - int mask_d; - int bits_code; - int mask_code; -} PushPopMultiple; - -#define PushPopMultiple_opcode 0x0400 -#define PushPopMultiple_pr_bits 0 -#define PushPopMultiple_pr_mask 0x7 -#define PushPopMultiple_dr_bits 3 -#define PushPopMultiple_dr_mask 0x7 -#define PushPopMultiple_W_bits 6 -#define PushPopMultiple_W_mask 0x1 -#define PushPopMultiple_p_bits 7 -#define PushPopMultiple_p_mask 0x1 -#define PushPopMultiple_d_bits 8 -#define PushPopMultiple_d_mask 0x1 -#define PushPopMultiple_code_bits 8 -#define PushPopMultiple_code_mask 0x1 - -#define init_PushPopMultiple \ -{ \ - PushPopMultiple_opcode, \ - PushPopMultiple_pr_bits, PushPopMultiple_pr_mask, \ - PushPopMultiple_dr_bits, PushPopMultiple_dr_mask, \ - PushPopMultiple_W_bits, PushPopMultiple_W_mask, \ - PushPopMultiple_p_bits, PushPopMultiple_p_mask, \ - PushPopMultiple_d_bits, PushPopMultiple_d_mask, \ - PushPopMultiple_code_bits, PushPopMultiple_code_mask \ -}; - -/* PushPopReg -+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ -| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |.W.|.grp.......|.reg.......| -+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ -*/ - -typedef struct -{ - unsigned short opcode; - int bits_reg; - int mask_reg; - int bits_grp; - int mask_grp; - int bits_W; - int mask_W; - int bits_code; - int mask_code; -} PushPopReg; - -#define PushPopReg_opcode 0x0100 -#define PushPopReg_reg_bits 0 -#define PushPopReg_reg_mask 0x7 -#define PushPopReg_grp_bits 3 -#define PushPopReg_grp_mask 0x7 -#define PushPopReg_W_bits 6 -#define PushPopReg_W_mask 0x1 -#define PushPopReg_code_bits 7 -#define PushPopReg_code_mask 0x1ff - -#define init_PushPopReg \ -{ \ - PushPopReg_opcode, \ - PushPopReg_reg_bits, PushPopReg_reg_mask, \ - PushPopReg_grp_bits, PushPopReg_grp_mask, \ - PushPopReg_W_bits, PushPopReg_W_mask, \ - PushPopReg_code_bits, PushPopReg_code_mask, \ -}; - -/* linkage -+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ -| 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.R.| -|.framesize.....................................................| -+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ -*/ - -typedef struct -{ - unsigned long opcode; - int bits_framesize; - int mask_framesize; - int bits_R; - int mask_R; - int bits_code; - int mask_code; -} Linkage; - -#define Linkage_opcode 0xe8000000 -#define Linkage_framesize_bits 0 -#define Linkage_framesize_mask 0xffff -#define Linkage_R_bits 16 -#define Linkage_R_mask 0x1 -#define Linkage_code_bits 17 -#define Linkage_code_mask 0x7fff - -#define init_Linkage \ -{ \ - Linkage_opcode, \ - Linkage_framesize_bits, Linkage_framesize_mask, \ - Linkage_R_bits, Linkage_R_mask, \ - Linkage_code_bits, Linkage_code_mask \ -}; - -/* LoopSetup -+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ -| 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 |.rop...|.c.|.soffset.......| -|.reg...........| - | - |.eoffset...............................| -+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ -*/ - -typedef struct -{ - unsigned long opcode; - int bits_eoffset; - int mask_eoffset; - int bits_dontcare; - int mask_dontcare; - int bits_reg; - int mask_reg; - int bits_soffset; - int mask_soffset; - int bits_c; - int mask_c; - int bits_rop; - int mask_rop; - int bits_code; - int mask_code; -} LoopSetup; - -#define LoopSetup_opcode 0xe0800000 -#define LoopSetup_eoffset_bits 0 -#define LoopSetup_eoffset_mask 0x3ff -#define LoopSetup_dontcare_bits 10 -#define LoopSetup_dontcare_mask 0x3 -#define LoopSetup_reg_bits 12 -#define LoopSetup_reg_mask 0xf -#define LoopSetup_soffset_bits 16 -#define LoopSetup_soffset_mask 0xf -#define LoopSetup_c_bits 20 -#define LoopSetup_c_mask 0x1 -#define LoopSetup_rop_bits 21 -#define LoopSetup_rop_mask 0x3 -#define LoopSetup_code_bits 23 -#define LoopSetup_code_mask 0x1ff - -#define init_LoopSetup \ -{ \ - LoopSetup_opcode, \ - LoopSetup_eoffset_bits, LoopSetup_eoffset_mask, \ - LoopSetup_dontcare_bits, LoopSetup_dontcare_mask, \ - LoopSetup_reg_bits, LoopSetup_reg_mask, \ - LoopSetup_soffset_bits, LoopSetup_soffset_mask, \ - LoopSetup_c_bits, LoopSetup_c_mask, \ - LoopSetup_rop_bits, LoopSetup_rop_mask, \ - LoopSetup_code_bits, LoopSetup_code_mask \ -}; - -/* LDIMMhalf -+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ -| 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 |.Z.|.H.|.S.|.grp...|.reg.......| -|.hword.........................................................| -+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ -*/ - -typedef struct -{ - unsigned long opcode; - int bits_hword; - int mask_hword; - int bits_reg; - int mask_reg; - int bits_grp; - int mask_grp; - int bits_S; - int mask_S; - int bits_H; - int mask_H; - int bits_Z; - int mask_Z; - int bits_code; - int mask_code; -} LDIMMhalf; - -#define LDIMMhalf_opcode 0xe1000000 -#define LDIMMhalf_hword_bits 0 -#define LDIMMhalf_hword_mask 0xffff -#define LDIMMhalf_reg_bits 16 -#define LDIMMhalf_reg_mask 0x7 -#define LDIMMhalf_grp_bits 19 -#define LDIMMhalf_grp_mask 0x3 -#define LDIMMhalf_S_bits 21 -#define LDIMMhalf_S_mask 0x1 -#define LDIMMhalf_H_bits 22 -#define LDIMMhalf_H_mask 0x1 -#define LDIMMhalf_Z_bits 23 -#define LDIMMhalf_Z_mask 0x1 -#define LDIMMhalf_code_bits 24 -#define LDIMMhalf_code_mask 0xff - -#define init_LDIMMhalf \ -{ \ - LDIMMhalf_opcode, \ - LDIMMhalf_hword_bits, LDIMMhalf_hword_mask, \ - LDIMMhalf_reg_bits, LDIMMhalf_reg_mask, \ - LDIMMhalf_grp_bits, LDIMMhalf_grp_mask, \ - LDIMMhalf_S_bits, LDIMMhalf_S_mask, \ - LDIMMhalf_H_bits, LDIMMhalf_H_mask, \ - LDIMMhalf_Z_bits, LDIMMhalf_Z_mask, \ - LDIMMhalf_code_bits, LDIMMhalf_code_mask \ -}; - - -/* CC2dreg -+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ -| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |.op....|.reg.......| -+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ -*/ - -typedef struct -{ - unsigned short opcode; - int bits_reg; - int mask_reg; - int bits_op; - int mask_op; - int bits_code; - int mask_code; -} CC2dreg; - -#define CC2dreg_opcode 0x0200 -#define CC2dreg_reg_bits 0 -#define CC2dreg_reg_mask 0x7 -#define CC2dreg_op_bits 3 -#define CC2dreg_op_mask 0x3 -#define CC2dreg_code_bits 5 -#define CC2dreg_code_mask 0x7fff - -#define init_CC2dreg \ -{ \ - CC2dreg_opcode, \ - CC2dreg_reg_bits, CC2dreg_reg_mask, \ - CC2dreg_op_bits, CC2dreg_op_mask, \ - CC2dreg_code_bits, CC2dreg_code_mask \ -}; - - -/* PTR2op -+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ -| 0 | 1 | 0 | 0 | 0 | 1 | 0 |.opc.......|.src.......|.dst.......| -+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ -*/ - -typedef struct -{ - unsigned short opcode; - int bits_dst; - int mask_dst; - int bits_src; - int mask_src; - int bits_opc; - int mask_opc; - int bits_code; - int mask_code; -} PTR2op; - -#define PTR2op_opcode 0x4400 -#define PTR2op_dst_bits 0 -#define PTR2op_dst_mask 0x7 -#define PTR2op_src_bits 3 -#define PTR2op_src_mask 0x7 -#define PTR2op_opc_bits 6 -#define PTR2op_opc_mask 0x7 -#define PTR2op_code_bits 9 -#define PTR2op_code_mask 0x7f - -#define init_PTR2op \ -{ \ - PTR2op_opcode, \ - PTR2op_dst_bits, PTR2op_dst_mask, \ - PTR2op_src_bits, PTR2op_src_mask, \ - PTR2op_opc_bits, PTR2op_opc_mask, \ - PTR2op_code_bits, PTR2op_code_mask \ -}; - - -/* COMP3op -+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ -| 0 | 1 | 0 | 1 |.opc.......|.dst.......|.src1......|.src0......| -+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ -*/ - -typedef struct -{ - unsigned short opcode; - int bits_src0; - int mask_src0; - int bits_src1; - int mask_src1; - int bits_dst; - int mask_dst; - int bits_opc; - int mask_opc; - int bits_code; - int mask_code; -} COMP3op; - -#define COMP3op_opcode 0x5000 -#define COMP3op_src0_bits 0 -#define COMP3op_src0_mask 0x7 -#define COMP3op_src1_bits 3 -#define COMP3op_src1_mask 0x7 -#define COMP3op_dst_bits 6 -#define COMP3op_dst_mask 0x7 -#define COMP3op_opc_bits 9 -#define COMP3op_opc_mask 0x7 -#define COMP3op_code_bits 12 -#define COMP3op_code_mask 0xf - -#define init_COMP3op \ -{ \ - COMP3op_opcode, \ - COMP3op_src0_bits, COMP3op_src0_mask, \ - COMP3op_src1_bits, COMP3op_src1_mask, \ - COMP3op_dst_bits, COMP3op_dst_mask, \ - COMP3op_opc_bits, COMP3op_opc_mask, \ - COMP3op_code_bits, COMP3op_code_mask \ -}; - -/* ccMV -+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ -| 0 | 0 | 0 | 0 | 0 | 1 | 1 |.T.|.d.|.s.|.dst.......|.src.......| -+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ -*/ - -typedef struct -{ - unsigned short opcode; - int bits_src; - int mask_src; - int bits_dst; - int mask_dst; - int bits_s; - int mask_s; - int bits_d; - int mask_d; - int bits_T; - int mask_T; - int bits_code; - int mask_code; -} CCmv; - -#define CCmv_opcode 0x0600 -#define CCmv_src_bits 0 -#define CCmv_src_mask 0x7 -#define CCmv_dst_bits 3 -#define CCmv_dst_mask 0x7 -#define CCmv_s_bits 6 -#define CCmv_s_mask 0x1 -#define CCmv_d_bits 7 -#define CCmv_d_mask 0x1 -#define CCmv_T_bits 8 -#define CCmv_T_mask 0x1 -#define CCmv_code_bits 9 -#define CCmv_code_mask 0x7f - -#define init_CCmv \ -{ \ - CCmv_opcode, \ - CCmv_src_bits, CCmv_src_mask, \ - CCmv_dst_bits, CCmv_dst_mask, \ - CCmv_s_bits, CCmv_s_mask, \ - CCmv_d_bits, CCmv_d_mask, \ - CCmv_T_bits, CCmv_T_mask, \ - CCmv_code_bits, CCmv_code_mask \ -}; - - -/* CCflag -+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ -| 0 | 0 | 0 | 0 | 1 |.I.|.opc.......|.G.|.y.........|.x.........| -+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ -*/ - -typedef struct -{ - unsigned short opcode; - int bits_x; - int mask_x; - int bits_y; - int mask_y; - int bits_G; - int mask_G; - int bits_opc; - int mask_opc; - int bits_I; - int mask_I; - int bits_code; - int mask_code; -} CCflag; - -#define CCflag_opcode 0x0800 -#define CCflag_x_bits 0 -#define CCflag_x_mask 0x7 -#define CCflag_y_bits 3 -#define CCflag_y_mask 0x7 -#define CCflag_G_bits 6 -#define CCflag_G_mask 0x1 -#define CCflag_opc_bits 7 -#define CCflag_opc_mask 0x7 -#define CCflag_I_bits 10 -#define CCflag_I_mask 0x1 -#define CCflag_code_bits 11 -#define CCflag_code_mask 0x1f - -#define init_CCflag \ -{ \ - CCflag_opcode, \ - CCflag_x_bits, CCflag_x_mask, \ - CCflag_y_bits, CCflag_y_mask, \ - CCflag_G_bits, CCflag_G_mask, \ - CCflag_opc_bits, CCflag_opc_mask, \ - CCflag_I_bits, CCflag_I_mask, \ - CCflag_code_bits, CCflag_code_mask, \ -}; - - -/* CC2stat -+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ -| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |.D.|.op....|.cbit..............| -+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ -*/ - -typedef struct -{ - unsigned short opcode; - int bits_cbit; - int mask_cbit; - int bits_op; - int mask_op; - int bits_D; - int mask_D; - int bits_code; - int mask_code; -} CC2stat; - -#define CC2stat_opcode 0x0300 -#define CC2stat_cbit_bits 0 -#define CC2stat_cbit_mask 0x1f -#define CC2stat_op_bits 5 -#define CC2stat_op_mask 0x3 -#define CC2stat_D_bits 7 -#define CC2stat_D_mask 0x1 -#define CC2stat_code_bits 8 -#define CC2stat_code_mask 0xff - -#define init_CC2stat \ -{ \ - CC2stat_opcode, \ - CC2stat_cbit_bits, CC2stat_cbit_mask, \ - CC2stat_op_bits, CC2stat_op_mask, \ - CC2stat_D_bits, CC2stat_D_mask, \ - CC2stat_code_bits, CC2stat_code_mask \ -}; - - -/* REGMV -+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ -| 0 | 0 | 1 | 1 |.gd........|.gs........|.dst.......|.src.......| -+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ -*/ - -typedef struct -{ - unsigned short opcode; - int bits_src; - int mask_src; - int bits_dst; - int mask_dst; - int bits_gs; - int mask_gs; - int bits_gd; - int mask_gd; - int bits_code; - int mask_code; -} RegMv; - -#define RegMv_opcode 0x3000 -#define RegMv_src_bits 0 -#define RegMv_src_mask 0x7 -#define RegMv_dst_bits 3 -#define RegMv_dst_mask 0x7 -#define RegMv_gs_bits 6 -#define RegMv_gs_mask 0x7 -#define RegMv_gd_bits 9 -#define RegMv_gd_mask 0x7 -#define RegMv_code_bits 12 -#define RegMv_code_mask 0xf - -#define init_RegMv \ -{ \ - RegMv_opcode, \ - RegMv_src_bits, RegMv_src_mask, \ - RegMv_dst_bits, RegMv_dst_mask, \ - RegMv_gs_bits, RegMv_gs_mask, \ - RegMv_gd_bits, RegMv_gd_mask, \ - RegMv_code_bits, RegMv_code_mask \ -}; - - -/* COMPI2opD -+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ -| 0 | 1 | 1 | 0 | 0 |.op|.isrc......................|.dst.......| -+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ -*/ - -typedef struct -{ - unsigned short opcode; - int bits_dst; - int mask_dst; - int bits_src; - int mask_src; - int bits_op; - int mask_op; - int bits_code; - int mask_code; -} COMPI2opD; - -#define COMPI2opD_opcode 0x6000 -#define COMPI2opD_dst_bits 0 -#define COMPI2opD_dst_mask 0x7 -#define COMPI2opD_src_bits 3 -#define COMPI2opD_src_mask 0x7f -#define COMPI2opD_op_bits 10 -#define COMPI2opD_op_mask 0x1 -#define COMPI2opD_code_bits 11 -#define COMPI2opD_code_mask 0x1f - -#define init_COMPI2opD \ -{ \ - COMPI2opD_opcode, \ - COMPI2opD_dst_bits, COMPI2opD_dst_mask, \ - COMPI2opD_src_bits, COMPI2opD_src_mask, \ - COMPI2opD_op_bits, COMPI2opD_op_mask, \ - COMPI2opD_code_bits, COMPI2opD_code_mask \ -}; - -/* COMPI2opP -+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ -| 0 | 1 | 1 | 0 | 1 |.op|.src.......................|.dst.......| -+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ -*/ - -typedef COMPI2opD COMPI2opP; - -#define COMPI2opP_opcode 0x6800 -#define COMPI2opP_dst_bits 0 -#define COMPI2opP_dst_mask 0x7 -#define COMPI2opP_src_bits 3 -#define COMPI2opP_src_mask 0x7f -#define COMPI2opP_op_bits 10 -#define COMPI2opP_op_mask 0x1 -#define COMPI2opP_code_bits 11 -#define COMPI2opP_code_mask 0x1f - -#define init_COMPI2opP \ -{ \ - COMPI2opP_opcode, \ - COMPI2opP_dst_bits, COMPI2opP_dst_mask, \ - COMPI2opP_src_bits, COMPI2opP_src_mask, \ - COMPI2opP_op_bits, COMPI2opP_op_mask, \ - COMPI2opP_code_bits, COMPI2opP_code_mask \ -}; - - -/* dagMODim -+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ -| 1 | 0 | 0 | 1 | 1 | 1 | 1 | 0 |.br| 1 | 1 |.op|.m.....|.i.....| -+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ -*/ - -typedef struct -{ - unsigned short opcode; - int bits_i; - int mask_i; - int bits_m; - int mask_m; - int bits_op; - int mask_op; - int bits_code2; - int mask_code2; - int bits_br; - int mask_br; - int bits_code; - int mask_code; -} DagMODim; - -#define DagMODim_opcode 0x9e60 -#define DagMODim_i_bits 0 -#define DagMODim_i_mask 0x3 -#define DagMODim_m_bits 2 -#define DagMODim_m_mask 0x3 -#define DagMODim_op_bits 4 -#define DagMODim_op_mask 0x1 -#define DagMODim_code2_bits 5 -#define DagMODim_code2_mask 0x3 -#define DagMODim_br_bits 7 -#define DagMODim_br_mask 0x1 -#define DagMODim_code_bits 8 -#define DagMODim_code_mask 0xff - -#define init_DagMODim \ -{ \ - DagMODim_opcode, \ - DagMODim_i_bits, DagMODim_i_mask, \ - DagMODim_m_bits, DagMODim_m_mask, \ - DagMODim_op_bits, DagMODim_op_mask, \ - DagMODim_code2_bits, DagMODim_code2_mask, \ - DagMODim_br_bits, DagMODim_br_mask, \ - DagMODim_code_bits, DagMODim_code_mask \ -}; - -/* dagMODik -+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ -| 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |.op....|.i.....| -+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ -*/ - -typedef struct -{ - unsigned short opcode; - int bits_i; - int mask_i; - int bits_op; - int mask_op; - int bits_code; - int mask_code; -} DagMODik; - -#define DagMODik_opcode 0x9f60 -#define DagMODik_i_bits 0 -#define DagMODik_i_mask 0x3 -#define DagMODik_op_bits 2 -#define DagMODik_op_mask 0x3 -#define DagMODik_code_bits 3 -#define DagMODik_code_mask 0xfff - -#define init_DagMODik \ -{ \ - DagMODik_opcode, \ - DagMODik_i_bits, DagMODik_i_mask, \ - DagMODik_op_bits, DagMODik_op_mask, \ - DagMODik_code_bits, DagMODik_code_mask \ -}; - -#endif diff --git a/include/opcode/cgen.h b/include/opcode/cgen.h deleted file mode 100644 index b7e82d4..0000000 --- a/include/opcode/cgen.h +++ /dev/null @@ -1,1480 +0,0 @@ -/* Header file for targets using CGEN: Cpu tools GENerator. - - Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005, 2009, 2010 - Free Software Foundation, Inc. - - This file is part of GDB, the GNU debugger, and the GNU Binutils. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License along - with this program; if not, write to the Free Software Foundation, Inc., - 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ - -#ifndef OPCODE_CGEN_H -#define OPCODE_CGEN_H - -#include "symcat.h" -#include "cgen/bitset.h" - -/* ??? IWBN to replace bfd in the name. */ -#include "bfd_stdint.h" - -/* ??? This file requires bfd.h but only to get bfd_vma. - Seems like an awful lot to require just to get such a fundamental type. - Perhaps the definition of bfd_vma can be moved outside of bfd.h. - Or perhaps one could duplicate its definition in another file. - Until such time, this file conditionally compiles definitions that require - bfd_vma using __BFD_H_SEEN__. */ - -/* Enums must be defined before they can be used. - Allow them to be used in struct definitions, even though the enum must - be defined elsewhere. - If CGEN_ARCH isn't defined, this file is being included by something other - than <arch>-desc.h. */ - -/* Prepend the arch name, defined in <arch>-desc.h, and _cgen_ to symbol S. - The lack of spaces in the arg list is important for non-stdc systems. - This file is included by <arch>-desc.h. - It can be included independently of <arch>-desc.h, in which case the arch - dependent portions will be declared as "unknown_cgen_foo". */ - -#ifndef CGEN_SYM -#define CGEN_SYM(s) CONCAT3 (unknown,_cgen_,s) -#endif - -/* This file contains the static (unchanging) pieces and as much other stuff - as we can reasonably put here. It's generally cleaner to put stuff here - rather than having it machine generated if possible. */ - -/* The assembler syntax is made up of expressions (duh...). - At the lowest level the values are mnemonics, register names, numbers, etc. - Above that are subexpressions, if any (an example might be the - "effective address" in m68k cpus). Subexpressions are wip. - At the second highest level are the insns themselves. Above that are - pseudo-insns, synthetic insns, and macros, if any. */ - -/* Lots of cpu's have a fixed insn size, or one which rarely changes, - and it's generally easier to handle these by treating the insn as an - integer type, rather than an array of characters. So we allow targets - to control this. When an integer type the value is in host byte order, - when an array of characters the value is in target byte order. */ - -typedef unsigned int CGEN_INSN_INT; -typedef int64_t CGEN_INSN_LGSINT; /* large/long SINT */ -typedef uint64_t CGEN_INSN_LGUINT; /* large/long UINT */ - -#if CGEN_INT_INSN_P -typedef CGEN_INSN_INT CGEN_INSN_BYTES; -typedef CGEN_INSN_INT *CGEN_INSN_BYTES_PTR; -#else -typedef unsigned char *CGEN_INSN_BYTES; -typedef unsigned char *CGEN_INSN_BYTES_PTR; -#endif - -#ifdef __GNUC__ -#define CGEN_INLINE __inline__ -#else -#define CGEN_INLINE -#endif - -enum cgen_endian -{ - CGEN_ENDIAN_UNKNOWN, - CGEN_ENDIAN_LITTLE, - CGEN_ENDIAN_BIG -}; - -/* Forward decl. */ - -typedef struct cgen_insn CGEN_INSN; - -/* Opaque pointer version for use by external world. */ - -typedef struct cgen_cpu_desc *CGEN_CPU_DESC; - -/* Attributes. - Attributes are used to describe various random things associated with - an object (ifield, hardware, operand, insn, whatever) and are specified - as name/value pairs. - Integer attributes computed at compile time are currently all that's - supported, though adding string attributes and run-time computation is - straightforward. Integer attribute values are always host int's - (signed or unsigned). For portability, this means 32 bits. - Integer attributes are further categorized as boolean, bitset, integer, - and enum types. Boolean attributes appear frequently enough that they're - recorded in one host int. This limits the maximum number of boolean - attributes to 32, though that's a *lot* of attributes. */ - -/* Type of attribute values. */ - -typedef CGEN_BITSET CGEN_ATTR_VALUE_BITSET_TYPE; -typedef int CGEN_ATTR_VALUE_ENUM_TYPE; -typedef union -{ - CGEN_ATTR_VALUE_BITSET_TYPE bitset; - CGEN_ATTR_VALUE_ENUM_TYPE nonbitset; -} CGEN_ATTR_VALUE_TYPE; - -/* Struct to record attribute information. */ - -typedef struct -{ - /* Boolean attributes. */ - unsigned int bool_; - /* Non-boolean integer attributes. */ - CGEN_ATTR_VALUE_TYPE nonbool[1]; -} CGEN_ATTR; - -/* Define a structure member for attributes with N non-boolean entries. - There is no maximum number of non-boolean attributes. - There is a maximum of 32 boolean attributes (since they are all recorded - in one host int). */ - -#define CGEN_ATTR_TYPE(n) \ -struct { unsigned int bool_; \ - CGEN_ATTR_VALUE_TYPE nonbool[(n) ? (n) : 1]; } - -/* Return the boolean attributes. */ - -#define CGEN_ATTR_BOOLS(a) ((a)->bool_) - -/* Non-boolean attribute numbers are offset by this much. */ - -#define CGEN_ATTR_NBOOL_OFFSET 32 - -/* Given a boolean attribute number, return its mask. */ - -#define CGEN_ATTR_MASK(attr) (1 << (attr)) - -/* Return the value of boolean attribute ATTR in ATTRS. */ - -#define CGEN_BOOL_ATTR(attrs, attr) ((CGEN_ATTR_MASK (attr) & (attrs)) != 0) - -/* Return value of attribute ATTR in ATTR_TABLE for OBJ. - OBJ is a pointer to the entity that has the attributes - (??? not used at present but is reserved for future purposes - eventually - the goal is to allow recording attributes in source form and computing - them lazily at runtime, not sure of the details yet). */ - -#define CGEN_ATTR_VALUE(obj, attr_table, attr) \ -((unsigned int) (attr) < CGEN_ATTR_NBOOL_OFFSET \ - ? ((CGEN_ATTR_BOOLS (attr_table) & CGEN_ATTR_MASK (attr)) != 0) \ - : ((attr_table)->nonbool[(attr) - CGEN_ATTR_NBOOL_OFFSET].nonbitset)) -#define CGEN_BITSET_ATTR_VALUE(obj, attr_table, attr) \ - ((attr_table)->nonbool[(attr) - CGEN_ATTR_NBOOL_OFFSET].bitset) - -/* Attribute name/value tables. - These are used to assist parsing of descriptions at run-time. */ - -typedef struct -{ - const char * name; - unsigned value; -} CGEN_ATTR_ENTRY; - -/* For each domain (ifld,hw,operand,insn), list of attributes. */ - -typedef struct -{ - const char * name; - const CGEN_ATTR_ENTRY * dfault; - const CGEN_ATTR_ENTRY * vals; -} CGEN_ATTR_TABLE; - -/* Instruction set variants. */ - -typedef struct { - const char *name; - - /* Default instruction size (in bits). - This is used by the assembler when it encounters an unknown insn. */ - unsigned int default_insn_bitsize; - - /* Base instruction size (in bits). - For non-LIW cpus this is generally the length of the smallest insn. - For LIW cpus its wip (work-in-progress). For the m32r its 32. */ - unsigned int base_insn_bitsize; - - /* Minimum/maximum instruction size (in bits). */ - unsigned int min_insn_bitsize; - unsigned int max_insn_bitsize; -} CGEN_ISA; - -/* Machine variants. */ - -typedef struct { - const char *name; - /* The argument to bfd_arch_info->scan. */ - const char *bfd_name; - /* one of enum mach_attr */ - int num; - /* parameter from mach->cpu */ - unsigned int insn_chunk_bitsize; -} CGEN_MACH; - -/* Parse result (also extraction result). - - The result of parsing an insn is stored here. - To generate the actual insn, this is passed to the insert handler. - When printing an insn, the result of extraction is stored here. - To print the insn, this is passed to the print handler. - - It is machine generated so we don't define it here, - but we do need a forward decl for the handler fns. - - There is one member for each possible field in the insn. - The type depends on the field. - Also recorded here is the computed length of the insn for architectures - where it varies. -*/ - -typedef struct cgen_fields CGEN_FIELDS; - -/* Total length of the insn, as recorded in the `fields' struct. */ -/* ??? The field insert handler has lots of opportunities for optimization - if it ever gets inlined. On architectures where insns all have the same - size, may wish to detect that and make this macro a constant - to allow - further optimizations. */ - -#define CGEN_FIELDS_BITSIZE(fields) ((fields)->length) - -/* Extraction support for variable length insn sets. */ - -/* When disassembling we don't know the number of bytes to read at the start. - So the first CGEN_BASE_INSN_SIZE bytes are read at the start and the rest - are read when needed. This struct controls this. It is basically the - disassemble_info stuff, except that we provide a cache for values already - read (since bytes can typically be read several times to fetch multiple - operands that may be in them), and that extraction of fields is needed - in contexts other than disassembly. */ - -typedef struct { - /* A pointer to the disassemble_info struct. - We don't require dis-asm.h so we use void * for the type here. - If NULL, BYTES is full of valid data (VALID == -1). */ - void *dis_info; - /* Points to a working buffer of sufficient size. */ - unsigned char *insn_bytes; - /* Mask of bytes that are valid in INSN_BYTES. */ - unsigned int valid; -} CGEN_EXTRACT_INFO; - -/* Associated with each insn or expression is a set of "handlers" for - performing operations like parsing, printing, etc. These require a bfd_vma - value to be passed around but we don't want all applications to need bfd.h. - So this stuff is only provided if bfd.h has been included. */ - -/* Parse handler. - CD is a cpu table descriptor. - INSN is a pointer to a struct describing the insn being parsed. - STRP is a pointer to a pointer to the text being parsed. - FIELDS is a pointer to a cgen_fields struct in which the results are placed. - If the expression is successfully parsed, *STRP is updated. - If not it is left alone. - The result is NULL if success or an error message. */ -typedef const char * (cgen_parse_fn) - (CGEN_CPU_DESC, const CGEN_INSN *insn_, - const char **strp_, CGEN_FIELDS *fields_); - -/* Insert handler. - CD is a cpu table descriptor. - INSN is a pointer to a struct describing the insn being parsed. - FIELDS is a pointer to a cgen_fields struct from which the values - are fetched. - INSNP is a pointer to a buffer in which to place the insn. - PC is the pc value of the insn. - The result is an error message or NULL if success. */ - -#ifdef __BFD_H_SEEN__ -typedef const char * (cgen_insert_fn) - (CGEN_CPU_DESC, const CGEN_INSN *insn_, - CGEN_FIELDS *fields_, CGEN_INSN_BYTES_PTR insnp_, - bfd_vma pc_); -#else -typedef const char * (cgen_insert_fn) (); -#endif - -/* Extract handler. - CD is a cpu table descriptor. - INSN is a pointer to a struct describing the insn being parsed. - The second argument is a pointer to a struct controlling extraction - (only used for variable length insns). - EX_INFO is a pointer to a struct for controlling reading of further - bytes for the insn. - BASE_INSN is the first CGEN_BASE_INSN_SIZE bytes (host order). - FIELDS is a pointer to a cgen_fields struct in which the results are placed. - PC is the pc value of the insn. - The result is the length of the insn in bits or zero if not recognized. */ - -#ifdef __BFD_H_SEEN__ -typedef int (cgen_extract_fn) - (CGEN_CPU_DESC, const CGEN_INSN *insn_, - CGEN_EXTRACT_INFO *ex_info_, CGEN_INSN_INT base_insn_, - CGEN_FIELDS *fields_, bfd_vma pc_); -#else -typedef int (cgen_extract_fn) (); -#endif - -/* Print handler. - CD is a cpu table descriptor. - INFO is a pointer to the disassembly info. - Eg: disassemble_info. It's defined as `PTR' so this file can be included - without dis-asm.h. - INSN is a pointer to a struct describing the insn being printed. - FIELDS is a pointer to a cgen_fields struct. - PC is the pc value of the insn. - LEN is the length of the insn, in bits. */ - -#ifdef __BFD_H_SEEN__ -typedef void (cgen_print_fn) - (CGEN_CPU_DESC, void * info_, const CGEN_INSN *insn_, - CGEN_FIELDS *fields_, bfd_vma pc_, int len_); -#else -typedef void (cgen_print_fn) (); -#endif - -/* Parse/insert/extract/print handlers. - - Indices into the handler tables. - We could use pointers here instead, but 90% of them are generally identical - and that's a lot of redundant data. Making these unsigned char indices - into tables of pointers saves a bit of space. - Using indices also keeps assembler code out of the disassembler and - vice versa. */ - -struct cgen_opcode_handler -{ - unsigned char parse, insert, extract, print; -}; - -/* Assembler interface. - - The interface to the assembler is intended to be clean in the sense that - libopcodes.a is a standalone entity and could be used with any assembler. - Not that one would necessarily want to do that but rather that it helps - keep a clean interface. The interface will obviously be slanted towards - GAS, but at least it's a start. - ??? Note that one possible user of the assembler besides GAS is GDB. - - Parsing is controlled by the assembler which calls - CGEN_SYM (assemble_insn). If it can parse and build the entire insn - it doesn't call back to the assembler. If it needs/wants to call back - to the assembler, cgen_parse_operand_fn is called which can either - - - return a number to be inserted in the insn - - return a "register" value to be inserted - (the register might not be a register per pe) - - queue the argument and return a marker saying the expression has been - queued (eg: a fix-up) - - return an error message indicating the expression wasn't recognizable - - The result is an error message or NULL for success. - The parsed value is stored in the bfd_vma *. */ - -/* Values for indicating what the caller wants. */ - -enum cgen_parse_operand_type -{ - CGEN_PARSE_OPERAND_INIT, - CGEN_PARSE_OPERAND_INTEGER, - CGEN_PARSE_OPERAND_ADDRESS, - CGEN_PARSE_OPERAND_SYMBOLIC -}; - -/* Values for indicating what was parsed. */ - -enum cgen_parse_operand_result -{ - CGEN_PARSE_OPERAND_RESULT_NUMBER, - CGEN_PARSE_OPERAND_RESULT_REGISTER, - CGEN_PARSE_OPERAND_RESULT_QUEUED, - CGEN_PARSE_OPERAND_RESULT_ERROR -}; - -#ifdef __BFD_H_SEEN__ /* Don't require bfd.h unnecessarily. */ -typedef const char * (cgen_parse_operand_fn) - (CGEN_CPU_DESC, - enum cgen_parse_operand_type, const char **, int, int, - enum cgen_parse_operand_result *, bfd_vma *); -#else -typedef const char * (cgen_parse_operand_fn) (); -#endif - -/* Set the cgen_parse_operand_fn callback. */ - -extern void cgen_set_parse_operand_fn - (CGEN_CPU_DESC, cgen_parse_operand_fn); - -/* Called before trying to match a table entry with the insn. */ - -extern void cgen_init_parse_operand (CGEN_CPU_DESC); - -/* Operand values (keywords, integers, symbols, etc.) */ - -/* Types of assembler elements. */ - -enum cgen_asm_type -{ - CGEN_ASM_NONE, CGEN_ASM_KEYWORD, CGEN_ASM_MAX -}; - -#ifndef CGEN_ARCH -enum cgen_hw_type { CGEN_HW_MAX }; -#endif - -/* List of hardware elements. */ - -typedef struct -{ - char *name; - enum cgen_hw_type type; - /* There is currently no example where both index specs and value specs - are required, so for now both are clumped under "asm_data". */ - enum cgen_asm_type asm_type; - void *asm_data; -#ifndef CGEN_HW_NBOOL_ATTRS -#define CGEN_HW_NBOOL_ATTRS 1 -#endif - CGEN_ATTR_TYPE (CGEN_HW_NBOOL_ATTRS) attrs; -#define CGEN_HW_ATTRS(hw) (&(hw)->attrs) -} CGEN_HW_ENTRY; - -/* Return value of attribute ATTR in HW. */ - -#define CGEN_HW_ATTR_VALUE(hw, attr) \ -CGEN_ATTR_VALUE ((hw), CGEN_HW_ATTRS (hw), (attr)) - -/* Table of hardware elements for selected mach, computed at runtime. - enum cgen_hw_type is an index into this table (specifically `entries'). */ - -typedef struct { - /* Pointer to null terminated table of all compiled in entries. */ - const CGEN_HW_ENTRY *init_entries; - unsigned int entry_size; /* since the attribute member is variable sized */ - /* Array of all entries, initial and run-time added. */ - const CGEN_HW_ENTRY **entries; - /* Number of elements in `entries'. */ - unsigned int num_entries; - /* For now, xrealloc is called each time a new entry is added at runtime. - ??? May wish to keep track of some slop to reduce the number of calls to - xrealloc, except that there's unlikely to be many and not expected to be - in speed critical code. */ -} CGEN_HW_TABLE; - -extern const CGEN_HW_ENTRY * cgen_hw_lookup_by_name - (CGEN_CPU_DESC, const char *); -extern const CGEN_HW_ENTRY * cgen_hw_lookup_by_num - (CGEN_CPU_DESC, unsigned int); - -/* This struct is used to describe things like register names, etc. */ - -typedef struct cgen_keyword_entry -{ - /* Name (as in register name). */ - char * name; - - /* Value (as in register number). - The value cannot be -1 as that is used to indicate "not found". - IDEA: Have "FUNCTION" attribute? [function is called to fetch value]. */ - int value; - - /* Attributes. - This should, but technically needn't, appear last. It is a variable sized - array in that one architecture may have 1 nonbool attribute and another - may have more. Having this last means the non-architecture specific code - needn't care. The goal is to eventually record - attributes in their raw form, evaluate them at run-time, and cache the - values, so this worry will go away anyway. */ - /* ??? Moving this last should be done by treating keywords like insn lists - and moving the `next' fields into a CGEN_KEYWORD_LIST struct. */ - /* FIXME: Not used yet. */ -#ifndef CGEN_KEYWORD_NBOOL_ATTRS -#define CGEN_KEYWORD_NBOOL_ATTRS 1 -#endif - CGEN_ATTR_TYPE (CGEN_KEYWORD_NBOOL_ATTRS) attrs; - - /* ??? Putting these here means compiled in entries can't be const. - Not a really big deal, but something to consider. */ - /* Next name hash table entry. */ - struct cgen_keyword_entry *next_name; - /* Next value hash table entry. */ - struct cgen_keyword_entry *next_value; -} CGEN_KEYWORD_ENTRY; - -/* Top level struct for describing a set of related keywords - (e.g. register names). - - This struct supports run-time entry of new values, and hashed lookups. */ - -typedef struct cgen_keyword -{ - /* Pointer to initial [compiled in] values. */ - CGEN_KEYWORD_ENTRY *init_entries; - - /* Number of entries in `init_entries'. */ - unsigned int num_init_entries; - - /* Hash table used for name lookup. */ - CGEN_KEYWORD_ENTRY **name_hash_table; - - /* Hash table used for value lookup. */ - CGEN_KEYWORD_ENTRY **value_hash_table; - - /* Number of entries in the hash_tables. */ - unsigned int hash_table_size; - - /* Pointer to null keyword "" entry if present. */ - const CGEN_KEYWORD_ENTRY *null_entry; - - /* String containing non-alphanumeric characters used - in keywords. - At present, the highest number of entries used is 1. */ - char nonalpha_chars[8]; -} CGEN_KEYWORD; - -/* Structure used for searching. */ - -typedef struct -{ - /* Table being searched. */ - const CGEN_KEYWORD *table; - - /* Specification of what is being searched for. */ - const char *spec; - - /* Current index in hash table. */ - unsigned int current_hash; - - /* Current element in current hash chain. */ - CGEN_KEYWORD_ENTRY *current_entry; -} CGEN_KEYWORD_SEARCH; - -/* Lookup a keyword from its name. */ - -const CGEN_KEYWORD_ENTRY *cgen_keyword_lookup_name - (CGEN_KEYWORD *, const char *); - -/* Lookup a keyword from its value. */ - -const CGEN_KEYWORD_ENTRY *cgen_keyword_lookup_value - (CGEN_KEYWORD *, int); - -/* Add a keyword. */ - -void cgen_keyword_add (CGEN_KEYWORD *, CGEN_KEYWORD_ENTRY *); - -/* Keyword searching. - This can be used to retrieve every keyword, or a subset. */ - -CGEN_KEYWORD_SEARCH cgen_keyword_search_init - (CGEN_KEYWORD *, const char *); -const CGEN_KEYWORD_ENTRY *cgen_keyword_search_next - (CGEN_KEYWORD_SEARCH *); - -/* Operand value support routines. */ - -extern const char *cgen_parse_keyword - (CGEN_CPU_DESC, const char **, CGEN_KEYWORD *, long *); -#ifdef __BFD_H_SEEN__ /* Don't require bfd.h unnecessarily. */ -extern const char *cgen_parse_signed_integer - (CGEN_CPU_DESC, const char **, int, long *); -extern const char *cgen_parse_unsigned_integer - (CGEN_CPU_DESC, const char **, int, unsigned long *); -extern const char *cgen_parse_address - (CGEN_CPU_DESC, const char **, int, int, - enum cgen_parse_operand_result *, bfd_vma *); -extern const char *cgen_validate_signed_integer - (long, long, long); -extern const char *cgen_validate_unsigned_integer - (unsigned long, unsigned long, unsigned long); -#endif - -/* Operand modes. */ - -/* ??? This duplicates the values in arch.h. Revisit. - These however need the CGEN_ prefix [as does everything in this file]. */ -/* ??? Targets may need to add their own modes so we may wish to move this - to <arch>-opc.h, or add a hook. */ - -enum cgen_mode { - CGEN_MODE_VOID, /* ??? rename simulator's VM to VOID? */ - CGEN_MODE_BI, CGEN_MODE_QI, CGEN_MODE_HI, CGEN_MODE_SI, CGEN_MODE_DI, - CGEN_MODE_UBI, CGEN_MODE_UQI, CGEN_MODE_UHI, CGEN_MODE_USI, CGEN_MODE_UDI, - CGEN_MODE_SF, CGEN_MODE_DF, CGEN_MODE_XF, CGEN_MODE_TF, - CGEN_MODE_TARGET_MAX, - CGEN_MODE_INT, CGEN_MODE_UINT, - CGEN_MODE_MAX -}; - -/* FIXME: Until simulator is updated. */ - -#define CGEN_MODE_VM CGEN_MODE_VOID - -/* Operands. */ - -#ifndef CGEN_ARCH -enum cgen_operand_type { CGEN_OPERAND_MAX }; -#endif - -/* "nil" indicator for the operand instance table */ -#define CGEN_OPERAND_NIL CGEN_OPERAND_MAX - -/* A tree of these structs represents the multi-ifield - structure of an operand's hw-index value, if it exists. */ - -struct cgen_ifld; - -typedef struct cgen_maybe_multi_ifield -{ - int count; /* 0: indexed by single cgen_ifld (possibly null: dead entry); - n: indexed by array of more cgen_maybe_multi_ifields. */ - union - { - const void *p; - const struct cgen_maybe_multi_ifield * multi; - const struct cgen_ifld * leaf; - } val; -} -CGEN_MAYBE_MULTI_IFLD; - -/* This struct defines each entry in the operand table. */ - -typedef struct -{ - /* Name as it appears in the syntax string. */ - char *name; - - /* Operand type. */ - enum cgen_operand_type type; - - /* The hardware element associated with this operand. */ - enum cgen_hw_type hw_type; - - /* FIXME: We don't yet record ifield definitions, which we should. - When we do it might make sense to delete start/length (since they will - be duplicated in the ifield's definition) and replace them with a - pointer to the ifield entry. */ - - /* Bit position. - This is just a hint, and may be unused in more complex operands. - May be unused for a modifier. */ - unsigned char start; - - /* The number of bits in the operand. - This is just a hint, and may be unused in more complex operands. - May be unused for a modifier. */ - unsigned char length; - - /* The (possibly-multi) ifield used as an index for this operand, if it - is indexed by a field at all. This substitutes / extends the start and - length fields above, but unsure at this time whether they are used - anywhere. */ - CGEN_MAYBE_MULTI_IFLD index_fields; -#if 0 /* ??? Interesting idea but relocs tend to get too complicated, - and ABI dependent, for simple table lookups to work. */ - /* Ideally this would be the internal (external?) reloc type. */ - int reloc_type; -#endif - - /* Attributes. - This should, but technically needn't, appear last. It is a variable sized - array in that one architecture may have 1 nonbool attribute and another - may have more. Having this last means the non-architecture specific code - needn't care, now or tomorrow. The goal is to eventually record - attributes in their raw form, evaluate them at run-time, and cache the - values, so this worry will go away anyway. */ -#ifndef CGEN_OPERAND_NBOOL_ATTRS -#define CGEN_OPERAND_NBOOL_ATTRS 1 -#endif - CGEN_ATTR_TYPE (CGEN_OPERAND_NBOOL_ATTRS) attrs; -#define CGEN_OPERAND_ATTRS(operand) (&(operand)->attrs) -} CGEN_OPERAND; - -/* Return value of attribute ATTR in OPERAND. */ - -#define CGEN_OPERAND_ATTR_VALUE(operand, attr) \ -CGEN_ATTR_VALUE ((operand), CGEN_OPERAND_ATTRS (operand), (attr)) - -/* Table of operands for selected mach/isa, computed at runtime. - enum cgen_operand_type is an index into this table (specifically - `entries'). */ - -typedef struct { - /* Pointer to null terminated table of all compiled in entries. */ - const CGEN_OPERAND *init_entries; - unsigned int entry_size; /* since the attribute member is variable sized */ - /* Array of all entries, initial and run-time added. */ - const CGEN_OPERAND **entries; - /* Number of elements in `entries'. */ - unsigned int num_entries; - /* For now, xrealloc is called each time a new entry is added at runtime. - ??? May wish to keep track of some slop to reduce the number of calls to - xrealloc, except that there's unlikely to be many and not expected to be - in speed critical code. */ -} CGEN_OPERAND_TABLE; - -extern const CGEN_OPERAND * cgen_operand_lookup_by_name - (CGEN_CPU_DESC, const char *); -extern const CGEN_OPERAND * cgen_operand_lookup_by_num - (CGEN_CPU_DESC, int); - -/* Instruction operand instances. - - For each instruction, a list of the hardware elements that are read and - written are recorded. */ - -/* The type of the instance. */ - -enum cgen_opinst_type { - /* End of table marker. */ - CGEN_OPINST_END = 0, - CGEN_OPINST_INPUT, CGEN_OPINST_OUTPUT -}; - -typedef struct -{ - /* Input or output indicator. */ - enum cgen_opinst_type type; - - /* Name of operand. */ - const char *name; - - /* The hardware element referenced. */ - enum cgen_hw_type hw_type; - - /* The mode in which the operand is being used. */ - enum cgen_mode mode; - - /* The operand table entry CGEN_OPERAND_NIL if there is none - (i.e. an explicit hardware reference). */ - enum cgen_operand_type op_type; - - /* If `operand' is "nil", the index (e.g. into array of registers). */ - int index; - - /* Attributes. - ??? This perhaps should be a real attribute struct but there's - no current need, so we save a bit of space and just have a set of - flags. The interface is such that this can easily be made attributes - should it prove useful. */ - unsigned int attrs; -#define CGEN_OPINST_ATTRS(opinst) ((opinst)->attrs) -/* Return value of attribute ATTR in OPINST. */ -#define CGEN_OPINST_ATTR(opinst, attr) \ -((CGEN_OPINST_ATTRS (opinst) & (attr)) != 0) -/* Operand is conditionally referenced (read/written). */ -#define CGEN_OPINST_COND_REF 1 -} CGEN_OPINST; - -/* Syntax string. - - Each insn format and subexpression has one of these. - - The syntax "string" consists of characters (n > 0 && n < 128), and operand - values (n >= 128), and is terminated by 0. Operand values are 128 + index - into the operand table. The operand table doesn't exist in C, per se, as - the data is recorded in the parse/insert/extract/print switch statements. */ - -/* This should be at least as large as necessary for any target. */ -#define CGEN_MAX_SYNTAX_ELEMENTS 48 - -/* A target may know its own precise maximum. Assert that it falls below - the above limit. */ -#ifdef CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS -#if CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS > CGEN_MAX_SYNTAX_ELEMENTS -#error "CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS too high - enlarge CGEN_MAX_SYNTAX_ELEMENTS" -#endif -#endif - -typedef unsigned short CGEN_SYNTAX_CHAR_TYPE; - -typedef struct -{ - CGEN_SYNTAX_CHAR_TYPE syntax[CGEN_MAX_SYNTAX_ELEMENTS]; -} CGEN_SYNTAX; - -#define CGEN_SYNTAX_STRING(syn) (syn->syntax) -#define CGEN_SYNTAX_CHAR_P(c) ((c) < 128) -#define CGEN_SYNTAX_CHAR(c) ((unsigned char)c) -#define CGEN_SYNTAX_FIELD(c) ((c) - 128) -#define CGEN_SYNTAX_MAKE_FIELD(c) ((c) + 128) - -/* ??? I can't currently think of any case where the mnemonic doesn't come - first [and if one ever doesn't building the hash tables will be tricky]. - However, we treat mnemonics as just another operand of the instruction. - A value of 1 means "this is where the mnemonic appears". 1 isn't - special other than it's a non-printable ASCII char. */ - -#define CGEN_SYNTAX_MNEMONIC 1 -#define CGEN_SYNTAX_MNEMONIC_P(ch) ((ch) == CGEN_SYNTAX_MNEMONIC) - -/* Instruction fields. - - ??? We currently don't allow adding fields at run-time. - Easy to fix when needed. */ - -typedef struct cgen_ifld { - /* Enum of ifield. */ - int num; -#define CGEN_IFLD_NUM(f) ((f)->num) - - /* Name of the field, distinguishes it from all other fields. */ - const char *name; -#define CGEN_IFLD_NAME(f) ((f)->name) - - /* Default offset, in bits, from the start of the insn to the word - containing the field. */ - int word_offset; -#define CGEN_IFLD_WORD_OFFSET(f) ((f)->word_offset) - - /* Default length of the word containing the field. */ - int word_size; -#define CGEN_IFLD_WORD_SIZE(f) ((f)->word_size) - - /* Default starting bit number. - Whether lsb=0 or msb=0 is determined by CGEN_INSN_LSB0_P. */ - int start; -#define CGEN_IFLD_START(f) ((f)->start) - - /* Length of the field, in bits. */ - int length; -#define CGEN_IFLD_LENGTH(f) ((f)->length) - -#ifndef CGEN_IFLD_NBOOL_ATTRS -#define CGEN_IFLD_NBOOL_ATTRS 1 -#endif - CGEN_ATTR_TYPE (CGEN_IFLD_NBOOL_ATTRS) attrs; -#define CGEN_IFLD_ATTRS(f) (&(f)->attrs) -} CGEN_IFLD; - -/* Return value of attribute ATTR in IFLD. */ -#define CGEN_IFLD_ATTR_VALUE(ifld, attr) \ -CGEN_ATTR_VALUE ((ifld), CGEN_IFLD_ATTRS (ifld), (attr)) - -/* Instruction data. */ - -/* Instruction formats. - - Instructions are grouped by format. Associated with an instruction is its - format. Each insn's opcode table entry contains a format table entry. - ??? There is usually very few formats compared with the number of insns, - so one can reduce the size of the opcode table by recording the format table - as a separate entity. Given that we currently don't, format table entries - are also distinguished by their operands. This increases the size of the - table, but reduces the number of tables. It's all minutiae anyway so it - doesn't really matter [at this point in time]. - - ??? Support for variable length ISA's is wip. */ - -/* Accompanying each iformat description is a list of its fields. */ - -typedef struct { - const CGEN_IFLD *ifld; -#define CGEN_IFMT_IFLD_IFLD(ii) ((ii)->ifld) -} CGEN_IFMT_IFLD; - -/* This should be at least as large as necessary for any target. */ -#define CGEN_MAX_IFMT_OPERANDS 16 - -/* A target may know its own precise maximum. Assert that it falls below - the above limit. */ -#ifdef CGEN_ACTUAL_MAX_IFMT_OPERANDS -#if CGEN_ACTUAL_MAX_IFMT_OPERANDS > CGEN_MAX_IFMT_OPERANDS -#error "CGEN_ACTUAL_MAX_IFMT_OPERANDS too high - enlarge CGEN_MAX_IFMT_OPERANDS" -#endif -#endif - - -typedef struct -{ - /* Length that MASK and VALUE have been calculated to - [VALUE is recorded elsewhere]. - Normally it is base_insn_bitsize. On [V]LIW architectures where the base - insn size may be larger than the size of an insn, this field is less than - base_insn_bitsize. */ - unsigned char mask_length; -#define CGEN_IFMT_MASK_LENGTH(ifmt) ((ifmt)->mask_length) - - /* Total length of instruction, in bits. */ - unsigned char length; -#define CGEN_IFMT_LENGTH(ifmt) ((ifmt)->length) - - /* Mask to apply to the first MASK_LENGTH bits. - Each insn's value is stored with the insn. - The first step in recognizing an insn for disassembly is - (opcode & mask) == value. */ - CGEN_INSN_INT mask; -#define CGEN_IFMT_MASK(ifmt) ((ifmt)->mask) - - /* Instruction fields. - +1 for trailing NULL. */ - CGEN_IFMT_IFLD iflds[CGEN_MAX_IFMT_OPERANDS + 1]; -#define CGEN_IFMT_IFLDS(ifmt) ((ifmt)->iflds) -} CGEN_IFMT; - -/* Instruction values. */ - -typedef struct -{ - /* The opcode portion of the base insn. */ - CGEN_INSN_INT base_value; - -#ifdef CGEN_MAX_EXTRA_OPCODE_OPERANDS - /* Extra opcode values beyond base_value. */ - unsigned long ifield_values[CGEN_MAX_EXTRA_OPCODE_OPERANDS]; -#endif -} CGEN_IVALUE; - -/* Instruction opcode table. - This contains the syntax and format data of an instruction. */ - -/* ??? Some ports already have an opcode table yet still need to use the rest - of what cgen_insn has. Plus keeping the opcode data with the operand - instance data can create a pretty big file. So we keep them separately. - Not sure this is a good idea in the long run. */ - -typedef struct -{ - /* Indices into parse/insert/extract/print handler tables. */ - struct cgen_opcode_handler handlers; -#define CGEN_OPCODE_HANDLERS(opc) (& (opc)->handlers) - - /* Syntax string. */ - CGEN_SYNTAX syntax; -#define CGEN_OPCODE_SYNTAX(opc) (& (opc)->syntax) - - /* Format entry. */ - const CGEN_IFMT *format; -#define CGEN_OPCODE_FORMAT(opc) ((opc)->format) -#define CGEN_OPCODE_MASK_BITSIZE(opc) CGEN_IFMT_MASK_LENGTH (CGEN_OPCODE_FORMAT (opc)) -#define CGEN_OPCODE_BITSIZE(opc) CGEN_IFMT_LENGTH (CGEN_OPCODE_FORMAT (opc)) -#define CGEN_OPCODE_IFLDS(opc) CGEN_IFMT_IFLDS (CGEN_OPCODE_FORMAT (opc)) - - /* Instruction opcode value. */ - CGEN_IVALUE value; -#define CGEN_OPCODE_VALUE(opc) (& (opc)->value) -#define CGEN_OPCODE_BASE_VALUE(opc) (CGEN_OPCODE_VALUE (opc)->base_value) -#define CGEN_OPCODE_BASE_MASK(opc) CGEN_IFMT_MASK (CGEN_OPCODE_FORMAT (opc)) -} CGEN_OPCODE; - -/* Instruction attributes. - This is made a published type as applications can cache a pointer to - the attributes for speed. */ - -#ifndef CGEN_INSN_NBOOL_ATTRS -#define CGEN_INSN_NBOOL_ATTRS 1 -#endif -typedef CGEN_ATTR_TYPE (CGEN_INSN_NBOOL_ATTRS) CGEN_INSN_ATTR_TYPE; - -/* Enum of architecture independent attributes. */ - -#ifndef CGEN_ARCH -/* ??? Numbers here are recorded in two places. */ -typedef enum cgen_insn_attr { - CGEN_INSN_ALIAS = 0 -} CGEN_INSN_ATTR; -#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) ((attrs)->bool_ & (1 << CGEN_INSN_ALIAS)) -#endif - -/* This struct defines each entry in the instruction table. */ - -typedef struct -{ - /* Each real instruction is enumerated. */ - /* ??? This may go away in time. */ - int num; -#define CGEN_INSN_NUM(insn) ((insn)->base->num) - - /* Name of entry (that distinguishes it from all other entries). */ - /* ??? If mnemonics have operands, try to print full mnemonic. */ - const char *name; -#define CGEN_INSN_NAME(insn) ((insn)->base->name) - - /* Mnemonic. This is used when parsing and printing the insn. - In the case of insns that have operands on the mnemonics, this is - only the constant part. E.g. for conditional execution of an `add' insn, - where the full mnemonic is addeq, addne, etc., and the condition is - treated as an operand, this is only "add". */ - const char *mnemonic; -#define CGEN_INSN_MNEMONIC(insn) ((insn)->base->mnemonic) - - /* Total length of instruction, in bits. */ - int bitsize; -#define CGEN_INSN_BITSIZE(insn) ((insn)->base->bitsize) - -#if 0 /* ??? Disabled for now as there is a problem with embedded newlines - and the table is already pretty big. Should perhaps be moved - to a file of its own. */ - /* Semantics, as RTL. */ - /* ??? Plain text or bytecodes? */ - /* ??? Note that the operand instance table could be computed at run-time - if we parse this and cache the results. Something to eventually do. */ - const char *rtx; -#define CGEN_INSN_RTX(insn) ((insn)->base->rtx) -#endif - - /* Attributes. - This must appear last. It is a variable sized array in that one - architecture may have 1 nonbool attribute and another may have more. - Having this last means the non-architecture specific code needn't - care. The goal is to eventually record attributes in their raw form, - evaluate them at run-time, and cache the values, so this worry will go - away anyway. */ - CGEN_INSN_ATTR_TYPE attrs; -#define CGEN_INSN_ATTRS(insn) (&(insn)->base->attrs) -/* Return value of attribute ATTR in INSN. */ -#define CGEN_INSN_ATTR_VALUE(insn, attr) \ -CGEN_ATTR_VALUE ((insn), CGEN_INSN_ATTRS (insn), (attr)) -#define CGEN_INSN_BITSET_ATTR_VALUE(insn, attr) \ - CGEN_BITSET_ATTR_VALUE ((insn), CGEN_INSN_ATTRS (insn), (attr)) -} CGEN_IBASE; - -/* Return non-zero if INSN is the "invalid" insn marker. */ - -#define CGEN_INSN_INVALID_P(insn) (CGEN_INSN_MNEMONIC (insn) == 0) - -/* Main struct contain instruction information. - BASE is always present, the rest is present only if asked for. */ - -struct cgen_insn -{ - /* ??? May be of use to put a type indicator here. - Then this struct could different info for different classes of insns. */ - /* ??? A speedup can be had by moving `base' into this struct. - Maybe later. */ - const CGEN_IBASE *base; - const CGEN_OPCODE *opcode; - const CGEN_OPINST *opinst; - - /* Regex to disambiguate overloaded opcodes */ - void *rx; -#define CGEN_INSN_RX(insn) ((insn)->rx) -#define CGEN_MAX_RX_ELEMENTS (CGEN_MAX_SYNTAX_ELEMENTS * 5) -}; - -/* Instruction lists. - This is used for adding new entries and for creating the hash lists. */ - -typedef struct cgen_insn_list -{ - struct cgen_insn_list *next; - const CGEN_INSN *insn; -} CGEN_INSN_LIST; - -/* Table of instructions. */ - -typedef struct -{ - const CGEN_INSN *init_entries; - unsigned int entry_size; /* since the attribute member is variable sized */ - unsigned int num_init_entries; - CGEN_INSN_LIST *new_entries; -} CGEN_INSN_TABLE; - -/* Return number of instructions. This includes any added at run-time. */ - -extern int cgen_insn_count (CGEN_CPU_DESC); -extern int cgen_macro_insn_count (CGEN_CPU_DESC); - -/* Macros to access the other insn elements not recorded in CGEN_IBASE. */ - -/* Fetch INSN's operand instance table. */ -/* ??? Doesn't handle insns added at runtime. */ -#define CGEN_INSN_OPERANDS(insn) ((insn)->opinst) - -/* Return INSN's opcode table entry. */ -#define CGEN_INSN_OPCODE(insn) ((insn)->opcode) - -/* Return INSN's handler data. */ -#define CGEN_INSN_HANDLERS(insn) CGEN_OPCODE_HANDLERS (CGEN_INSN_OPCODE (insn)) - -/* Return INSN's syntax. */ -#define CGEN_INSN_SYNTAX(insn) CGEN_OPCODE_SYNTAX (CGEN_INSN_OPCODE (insn)) - -/* Return size of base mask in bits. */ -#define CGEN_INSN_MASK_BITSIZE(insn) \ - CGEN_OPCODE_MASK_BITSIZE (CGEN_INSN_OPCODE (insn)) - -/* Return mask of base part of INSN. */ -#define CGEN_INSN_BASE_MASK(insn) \ - CGEN_OPCODE_BASE_MASK (CGEN_INSN_OPCODE (insn)) - -/* Return value of base part of INSN. */ -#define CGEN_INSN_BASE_VALUE(insn) \ - CGEN_OPCODE_BASE_VALUE (CGEN_INSN_OPCODE (insn)) - -/* Standard way to test whether INSN is supported by MACH. - MACH is one of enum mach_attr. - The "|1" is because the base mach is always selected. */ -#define CGEN_INSN_MACH_HAS_P(insn, mach) \ -((CGEN_INSN_ATTR_VALUE ((insn), CGEN_INSN_MACH) & ((1 << (mach)) | 1)) != 0) - -/* Macro instructions. - Macro insns aren't real insns, they map to one or more real insns. - E.g. An architecture's "nop" insn may actually be an "mv r0,r0" or - some such. - - Macro insns can expand to nothing (e.g. a nop that is optimized away). - This is useful in multi-insn macros that build a constant in a register. - Of course this isn't the default behaviour and must be explicitly enabled. - - Assembly of macro-insns is relatively straightforward. Disassembly isn't. - However, disassembly of at least some kinds of macro insns is important - in order that the disassembled code preserve the readability of the original - insn. What is attempted here is to disassemble all "simple" macro-insns, - where "simple" is currently defined to mean "expands to one real insn". - - Simple macro-insns are handled specially. They are emitted as ALIAS's - of real insns. This simplifies their handling since there's usually more - of them than any other kind of macro-insn, and proper disassembly of them - falls out for free. */ - -/* For each macro-insn there may be multiple expansion possibilities, - depending on the arguments. This structure is accessed via the `data' - member of CGEN_INSN. */ - -typedef struct cgen_minsn_expansion { - /* Function to do the expansion. - If the expansion fails (e.g. "no match") NULL is returned. - Space for the expansion is obtained with malloc. - It is up to the caller to free it. */ - const char * (* fn) - (const struct cgen_minsn_expansion *, - const char *, const char **, int *, - CGEN_OPERAND **); -#define CGEN_MIEXPN_FN(ex) ((ex)->fn) - - /* Instruction(s) the macro expands to. - The format of STR is defined by FN. - It is typically the assembly code of the real insn, but it could also be - the original Scheme expression or a tokenized form of it (with FN being - an appropriate interpreter). */ - const char * str; -#define CGEN_MIEXPN_STR(ex) ((ex)->str) -} CGEN_MINSN_EXPANSION; - -/* Normal expander. - When supported, this function will convert the input string to another - string and the parser will be invoked recursively. The output string - may contain further macro invocations. */ - -extern const char * cgen_expand_macro_insn - (CGEN_CPU_DESC, const struct cgen_minsn_expansion *, - const char *, const char **, int *, CGEN_OPERAND **); - -/* The assembler insn table is hashed based on some function of the mnemonic - (the actually hashing done is up to the target, but we provide a few - examples like the first letter or a function of the entire mnemonic). */ - -extern CGEN_INSN_LIST * cgen_asm_lookup_insn - (CGEN_CPU_DESC, const char *); -#define CGEN_ASM_LOOKUP_INSN(cd, string) cgen_asm_lookup_insn ((cd), (string)) -#define CGEN_ASM_NEXT_INSN(insn) ((insn)->next) - -/* The disassembler insn table is hashed based on some function of machine - instruction (the actually hashing done is up to the target). */ - -extern CGEN_INSN_LIST * cgen_dis_lookup_insn - (CGEN_CPU_DESC, const char *, CGEN_INSN_INT); -/* FIXME: delete these two */ -#define CGEN_DIS_LOOKUP_INSN(cd, buf, value) cgen_dis_lookup_insn ((cd), (buf), (value)) -#define CGEN_DIS_NEXT_INSN(insn) ((insn)->next) - -/* The CPU description. - A copy of this is created when the cpu table is "opened". - All global state information is recorded here. - Access macros are provided for "public" members. */ - -typedef struct cgen_cpu_desc -{ - /* Bitmap of selected machine(s) (a la BFD machine number). */ - int machs; - - /* Bitmap of selected isa(s). */ - CGEN_BITSET *isas; -#define CGEN_CPU_ISAS(cd) ((cd)->isas) - - /* Current endian. */ - enum cgen_endian endian; -#define CGEN_CPU_ENDIAN(cd) ((cd)->endian) - - /* Current insn endian. */ - enum cgen_endian insn_endian; -#define CGEN_CPU_INSN_ENDIAN(cd) ((cd)->insn_endian) - - /* Word size (in bits). */ - /* ??? Or maybe maximum word size - might we ever need to allow a cpu table - to be opened for both sparc32/sparc64? - ??? Another alternative is to create a table of selected machs and - lazily fetch the data from there. */ - unsigned int word_bitsize; - - /* Instruction chunk size (in bits), for purposes of endianness - conversion. */ - unsigned int insn_chunk_bitsize; - - /* Indicator if sizes are unknown. - This is used by default_insn_bitsize,base_insn_bitsize if there is a - difference between the selected isa's. */ -#define CGEN_SIZE_UNKNOWN 65535 - - /* Default instruction size (in bits). - This is used by the assembler when it encounters an unknown insn. */ - unsigned int default_insn_bitsize; - - /* Base instruction size (in bits). - For non-LIW cpus this is generally the length of the smallest insn. - For LIW cpus its wip (work-in-progress). For the m32r its 32. */ - unsigned int base_insn_bitsize; - - /* Minimum/maximum instruction size (in bits). */ - unsigned int min_insn_bitsize; - unsigned int max_insn_bitsize; - - /* Instruction set variants. */ - const CGEN_ISA *isa_table; - - /* Machine variants. */ - const CGEN_MACH *mach_table; - - /* Hardware elements. */ - CGEN_HW_TABLE hw_table; - - /* Instruction fields. */ - const CGEN_IFLD *ifld_table; - - /* Operands. */ - CGEN_OPERAND_TABLE operand_table; - - /* Main instruction table. */ - CGEN_INSN_TABLE insn_table; -#define CGEN_CPU_INSN_TABLE(cd) (& (cd)->insn_table) - - /* Macro instructions are defined separately and are combined with real - insns during hash table computation. */ - CGEN_INSN_TABLE macro_insn_table; - - /* Copy of CGEN_INT_INSN_P. */ - int int_insn_p; - - /* Called to rebuild the tables after something has changed. */ - void (*rebuild_tables) (CGEN_CPU_DESC); - - /* Operand parser callback. */ - cgen_parse_operand_fn * parse_operand_fn; - - /* Parse/insert/extract/print cover fns for operands. */ - const char * (*parse_operand) - (CGEN_CPU_DESC, int opindex_, const char **, CGEN_FIELDS *fields_); -#ifdef __BFD_H_SEEN__ - const char * (*insert_operand) - (CGEN_CPU_DESC, int opindex_, CGEN_FIELDS *fields_, - CGEN_INSN_BYTES_PTR, bfd_vma pc_); - int (*extract_operand) - (CGEN_CPU_DESC, int opindex_, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, - CGEN_FIELDS *fields_, bfd_vma pc_); - void (*print_operand) - (CGEN_CPU_DESC, int opindex_, void * info_, CGEN_FIELDS * fields_, - void const *attrs_, bfd_vma pc_, int length_); -#else - const char * (*insert_operand) (); - int (*extract_operand) (); - void (*print_operand) (); -#endif -#define CGEN_CPU_PARSE_OPERAND(cd) ((cd)->parse_operand) -#define CGEN_CPU_INSERT_OPERAND(cd) ((cd)->insert_operand) -#define CGEN_CPU_EXTRACT_OPERAND(cd) ((cd)->extract_operand) -#define CGEN_CPU_PRINT_OPERAND(cd) ((cd)->print_operand) - - /* Size of CGEN_FIELDS struct. */ - unsigned int sizeof_fields; -#define CGEN_CPU_SIZEOF_FIELDS(cd) ((cd)->sizeof_fields) - - /* Set the bitsize field. */ - void (*set_fields_bitsize) (CGEN_FIELDS *fields_, int size_); -#define CGEN_CPU_SET_FIELDS_BITSIZE(cd) ((cd)->set_fields_bitsize) - - /* CGEN_FIELDS accessors. */ - int (*get_int_operand) - (CGEN_CPU_DESC, int opindex_, const CGEN_FIELDS *fields_); - void (*set_int_operand) - (CGEN_CPU_DESC, int opindex_, CGEN_FIELDS *fields_, int value_); -#ifdef __BFD_H_SEEN__ - bfd_vma (*get_vma_operand) - (CGEN_CPU_DESC, int opindex_, const CGEN_FIELDS *fields_); - void (*set_vma_operand) - (CGEN_CPU_DESC, int opindex_, CGEN_FIELDS *fields_, bfd_vma value_); -#else - long (*get_vma_operand) (); - void (*set_vma_operand) (); -#endif -#define CGEN_CPU_GET_INT_OPERAND(cd) ((cd)->get_int_operand) -#define CGEN_CPU_SET_INT_OPERAND(cd) ((cd)->set_int_operand) -#define CGEN_CPU_GET_VMA_OPERAND(cd) ((cd)->get_vma_operand) -#define CGEN_CPU_SET_VMA_OPERAND(cd) ((cd)->set_vma_operand) - - /* Instruction parse/insert/extract/print handlers. */ - /* FIXME: make these types uppercase. */ - cgen_parse_fn * const *parse_handlers; - cgen_insert_fn * const *insert_handlers; - cgen_extract_fn * const *extract_handlers; - cgen_print_fn * const *print_handlers; -#define CGEN_PARSE_FN(cd, insn) (cd->parse_handlers[(insn)->opcode->handlers.parse]) -#define CGEN_INSERT_FN(cd, insn) (cd->insert_handlers[(insn)->opcode->handlers.insert]) -#define CGEN_EXTRACT_FN(cd, insn) (cd->extract_handlers[(insn)->opcode->handlers.extract]) -#define CGEN_PRINT_FN(cd, insn) (cd->print_handlers[(insn)->opcode->handlers.print]) - - /* Return non-zero if insn should be added to hash table. */ - int (* asm_hash_p) (const CGEN_INSN *); - - /* Assembler hash function. */ - unsigned int (* asm_hash) (const char *); - - /* Number of entries in assembler hash table. */ - unsigned int asm_hash_size; - - /* Return non-zero if insn should be added to hash table. */ - int (* dis_hash_p) (const CGEN_INSN *); - - /* Disassembler hash function. */ - unsigned int (* dis_hash) (const char *, CGEN_INSN_INT); - - /* Number of entries in disassembler hash table. */ - unsigned int dis_hash_size; - - /* Assembler instruction hash table. */ - CGEN_INSN_LIST **asm_hash_table; - CGEN_INSN_LIST *asm_hash_table_entries; - - /* Disassembler instruction hash table. */ - CGEN_INSN_LIST **dis_hash_table; - CGEN_INSN_LIST *dis_hash_table_entries; - - /* This field could be turned into a bitfield if room for other flags is needed. */ - unsigned int signed_overflow_ok_p; - -} CGEN_CPU_TABLE; - -/* wip */ -#ifndef CGEN_WORD_ENDIAN -#define CGEN_WORD_ENDIAN(cd) CGEN_CPU_ENDIAN (cd) -#endif -#ifndef CGEN_INSN_WORD_ENDIAN -#define CGEN_INSN_WORD_ENDIAN(cd) CGEN_CPU_INSN_ENDIAN (cd) -#endif - -/* Prototypes of major functions. */ -/* FIXME: Move more CGEN_SYM-defined functions into CGEN_CPU_DESC. - Not the init fns though, as that would drag in things that mightn't be - used and might not even exist. */ - -/* Argument types to cpu_open. */ - -enum cgen_cpu_open_arg { - CGEN_CPU_OPEN_END, - /* Select instruction set(s), arg is bitmap or 0 meaning "unspecified". */ - CGEN_CPU_OPEN_ISAS, - /* Select machine(s), arg is bitmap or 0 meaning "unspecified". */ - CGEN_CPU_OPEN_MACHS, - /* Select machine, arg is mach's bfd name. - Multiple machines can be specified by repeated use. */ - CGEN_CPU_OPEN_BFDMACH, - /* Select endian, arg is CGEN_ENDIAN_*. */ - CGEN_CPU_OPEN_ENDIAN -}; - -/* Open a cpu descriptor table for use. - ??? We only support ISO C stdargs here, not K&R. - Laziness, plus experiment to see if anything requires K&R - eventually - K&R will no longer be supported - e.g. GDB is currently trying this. */ - -extern CGEN_CPU_DESC CGEN_SYM (cpu_open) (enum cgen_cpu_open_arg, ...); - -/* Cover fn to handle simple case. */ - -extern CGEN_CPU_DESC CGEN_SYM (cpu_open_1) - (const char *mach_name_, enum cgen_endian endian_); - -/* Close it. */ - -extern void CGEN_SYM (cpu_close) (CGEN_CPU_DESC); - -/* Initialize the opcode table for use. - Called by init_asm/init_dis. */ - -extern void CGEN_SYM (init_opcode_table) (CGEN_CPU_DESC cd_); - -/* build the insn selection regex. - called by init_opcode_table */ - -extern char * CGEN_SYM(build_insn_regex) (CGEN_INSN *insn_); - -/* Initialize the ibld table for use. - Called by init_asm/init_dis. */ - -extern void CGEN_SYM (init_ibld_table) (CGEN_CPU_DESC cd_); - -/* Initialize an cpu table for assembler or disassembler use. - These must be called immediately after cpu_open. */ - -extern void CGEN_SYM (init_asm) (CGEN_CPU_DESC); -extern void CGEN_SYM (init_dis) (CGEN_CPU_DESC); - -/* Initialize the operand instance table for use. */ - -extern void CGEN_SYM (init_opinst_table) (CGEN_CPU_DESC cd_); - -/* Assemble an instruction. */ - -extern const CGEN_INSN * CGEN_SYM (assemble_insn) - (CGEN_CPU_DESC, const char *, CGEN_FIELDS *, - CGEN_INSN_BYTES_PTR, char **); - -extern const CGEN_KEYWORD CGEN_SYM (operand_mach); -extern int CGEN_SYM (get_mach) (const char *); - -/* Operand index computation. */ -extern const CGEN_INSN * cgen_lookup_insn - (CGEN_CPU_DESC, const CGEN_INSN * insn_, - CGEN_INSN_INT int_value_, unsigned char *bytes_value_, - int length_, CGEN_FIELDS *fields_, int alias_p_); -extern void cgen_get_insn_operands - (CGEN_CPU_DESC, const CGEN_INSN * insn_, - const CGEN_FIELDS *fields_, int *indices_); -extern const CGEN_INSN * cgen_lookup_get_insn_operands - (CGEN_CPU_DESC, const CGEN_INSN *insn_, - CGEN_INSN_INT int_value_, unsigned char *bytes_value_, - int length_, int *indices_, CGEN_FIELDS *fields_); - -/* Cover fns to bfd_get/set. */ - -extern CGEN_INSN_INT cgen_get_insn_value - (CGEN_CPU_DESC, unsigned char *, int); -extern void cgen_put_insn_value - (CGEN_CPU_DESC, unsigned char *, int, CGEN_INSN_INT); - -/* Read in a cpu description file. - ??? For future concerns, including adding instructions to the assembler/ - disassembler at run-time. */ - -extern const char * cgen_read_cpu_file (CGEN_CPU_DESC, const char * filename_); - -/* Allow signed overflow of instruction fields. */ -extern void cgen_set_signed_overflow_ok (CGEN_CPU_DESC); - -/* Generate an error message if a signed field in an instruction overflows. */ -extern void cgen_clear_signed_overflow_ok (CGEN_CPU_DESC); - -/* Will an error message be generated if a signed field in an instruction overflows ? */ -extern unsigned int cgen_signed_overflow_ok_p (CGEN_CPU_DESC); - -#endif /* OPCODE_CGEN_H */ diff --git a/include/opcode/convex.h b/include/opcode/convex.h deleted file mode 100644 index 4643f5e..0000000 --- a/include/opcode/convex.h +++ /dev/null @@ -1,1708 +0,0 @@ -/* Information for instruction disassembly on the Convex. - Copyright 1989, 1993, 2002, 2010 Free Software Foundation, Inc. - - This file is part of GDB. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, - MA 02110-1301, USA. */ - -#define xxx 0 -#define rrr 1 -#define rr 2 -#define rxr 3 -#define r 4 -#define nops 5 -#define nr 6 -#define pcrel 7 -#define lr 8 -#define rxl 9 -#define rlr 10 -#define rrl 11 -#define iml 12 -#define imr 13 -#define a1r 14 -#define a1l 15 -#define a2r 16 -#define a2l 17 -#define a3 18 -#define a4 19 -#define a5 20 -#define V 1 -#define S 2 -#define VM 3 -#define A 4 -#define VL 5 -#define VS 6 -#define VLS 7 -#define PSW 8 -/* Prevent an error during "make depend". */ -#if !defined (PC) -#define PC 9 -#endif -#define ITR 10 -#define VV 11 -#define ITSR 12 -#define TOC 13 -#define CIR 14 -#define TTR 15 -#define VMU 16 -#define VML 17 -#define ICR 18 -#define TCPU 19 -#define CPUID 20 -#define TID 21 - -const char *op[] = { - "", - "v0\0v1\0v2\0v3\0v4\0v5\0v6\0v7", - "s0\0s1\0s2\0s3\0s4\0s5\0s6\0s7", - "vm", - "sp\0a1\0a2\0a3\0a4\0a5\0ap\0fp", - "vl", - "vs", - "vls", - "psw", - "pc", - "itr", - "vv", - "itsr", - "toc", - "cir", - "ttr", - "vmu", - "vml", - "icr", - "tcpu", - "cpuid", - "tid", -}; - -const struct formstr format0[] = { - {0,0,rrr,V,S,S}, /* mov */ - {0,0,rrr,S,S,V}, /* mov */ - {1,1,rrr,V,V,V}, /* merg.t */ - {2,1,rrr,V,V,V}, /* mask.t */ - {1,2,rrr,V,S,V}, /* merg.f */ - {2,2,rrr,V,S,V}, /* mask.f */ - {1,1,rrr,V,S,V}, /* merg.t */ - {2,1,rrr,V,S,V}, /* mask.t */ - {3,3,rrr,V,V,V}, /* mul.s */ - {3,4,rrr,V,V,V}, /* mul.d */ - {4,3,rrr,V,V,V}, /* div.s */ - {4,4,rrr,V,V,V}, /* div.d */ - {3,3,rrr,V,S,V}, /* mul.s */ - {3,4,rrr,V,S,V}, /* mul.d */ - {4,3,rrr,V,S,V}, /* div.s */ - {4,4,rrr,V,S,V}, /* div.d */ - {5,0,rrr,V,V,V}, /* and */ - {6,0,rrr,V,V,V}, /* or */ - {7,0,rrr,V,V,V}, /* xor */ - {8,0,rrr,V,V,V}, /* shf */ - {5,0,rrr,V,S,V}, /* and */ - {6,0,rrr,V,S,V}, /* or */ - {7,0,rrr,V,S,V}, /* xor */ - {8,0,rrr,V,S,V}, /* shf */ - {9,3,rrr,V,V,V}, /* add.s */ - {9,4,rrr,V,V,V}, /* add.d */ - {10,3,rrr,V,V,V}, /* sub.s */ - {10,4,rrr,V,V,V}, /* sub.d */ - {9,3,rrr,V,S,V}, /* add.s */ - {9,4,rrr,V,S,V}, /* add.d */ - {10,3,rrr,V,S,V}, /* sub.s */ - {10,4,rrr,V,S,V}, /* sub.d */ - {9,5,rrr,V,V,V}, /* add.b */ - {9,6,rrr,V,V,V}, /* add.h */ - {9,7,rrr,V,V,V}, /* add.w */ - {9,8,rrr,V,V,V}, /* add.l */ - {9,5,rrr,V,S,V}, /* add.b */ - {9,6,rrr,V,S,V}, /* add.h */ - {9,7,rrr,V,S,V}, /* add.w */ - {9,8,rrr,V,S,V}, /* add.l */ - {10,5,rrr,V,V,V}, /* sub.b */ - {10,6,rrr,V,V,V}, /* sub.h */ - {10,7,rrr,V,V,V}, /* sub.w */ - {10,8,rrr,V,V,V}, /* sub.l */ - {10,5,rrr,V,S,V}, /* sub.b */ - {10,6,rrr,V,S,V}, /* sub.h */ - {10,7,rrr,V,S,V}, /* sub.w */ - {10,8,rrr,V,S,V}, /* sub.l */ - {3,5,rrr,V,V,V}, /* mul.b */ - {3,6,rrr,V,V,V}, /* mul.h */ - {3,7,rrr,V,V,V}, /* mul.w */ - {3,8,rrr,V,V,V}, /* mul.l */ - {3,5,rrr,V,S,V}, /* mul.b */ - {3,6,rrr,V,S,V}, /* mul.h */ - {3,7,rrr,V,S,V}, /* mul.w */ - {3,8,rrr,V,S,V}, /* mul.l */ - {4,5,rrr,V,V,V}, /* div.b */ - {4,6,rrr,V,V,V}, /* div.h */ - {4,7,rrr,V,V,V}, /* div.w */ - {4,8,rrr,V,V,V}, /* div.l */ - {4,5,rrr,V,S,V}, /* div.b */ - {4,6,rrr,V,S,V}, /* div.h */ - {4,7,rrr,V,S,V}, /* div.w */ - {4,8,rrr,V,S,V}, /* div.l */ -}; - -const struct formstr format1[] = { - {11,0,xxx,0,0,0}, /* exit */ - {12,0,a3,0,0,0}, /* jmp */ - {13,2,a3,0,0,0}, /* jmpi.f */ - {13,1,a3,0,0,0}, /* jmpi.t */ - {14,2,a3,0,0,0}, /* jmpa.f */ - {14,1,a3,0,0,0}, /* jmpa.t */ - {15,2,a3,0,0,0}, /* jmps.f */ - {15,1,a3,0,0,0}, /* jmps.t */ - {16,0,a3,0,0,0}, /* tac */ - {17,0,a1r,A,0,0}, /* ldea */ - {18,8,a1l,VLS,0,0}, /* ld.l */ - {18,9,a1l,VM,0,0}, /* ld.x */ - {19,0,a3,0,0,0}, /* tas */ - {20,0,a3,0,0,0}, /* pshea */ - {21,8,a2l,VLS,0,0}, /* st.l */ - {21,9,a2l,VM,0,0}, /* st.x */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {22,0,a3,0,0,0}, /* call */ - {23,0,a3,0,0,0}, /* calls */ - {24,0,a3,0,0,0}, /* callq */ - {25,0,a1r,A,0,0}, /* pfork */ - {26,5,a2r,S,0,0}, /* ste.b */ - {26,6,a2r,S,0,0}, /* ste.h */ - {26,7,a2r,S,0,0}, /* ste.w */ - {26,8,a2r,S,0,0}, /* ste.l */ - {18,5,a1r,A,0,0}, /* ld.b */ - {18,6,a1r,A,0,0}, /* ld.h */ - {18,7,a1r,A,0,0}, /* ld.w */ - {27,7,a1r,A,0,0}, /* incr.w */ - {21,5,a2r,A,0,0}, /* st.b */ - {21,6,a2r,A,0,0}, /* st.h */ - {21,7,a2r,A,0,0}, /* st.w */ - {27,8,a1r,S,0,0}, /* incr.l */ - {18,5,a1r,S,0,0}, /* ld.b */ - {18,6,a1r,S,0,0}, /* ld.h */ - {18,7,a1r,S,0,0}, /* ld.w */ - {18,8,a1r,S,0,0}, /* ld.l */ - {21,5,a2r,S,0,0}, /* st.b */ - {21,6,a2r,S,0,0}, /* st.h */ - {21,7,a2r,S,0,0}, /* st.w */ - {21,8,a2r,S,0,0}, /* st.l */ - {18,5,a1r,V,0,0}, /* ld.b */ - {18,6,a1r,V,0,0}, /* ld.h */ - {18,7,a1r,V,0,0}, /* ld.w */ - {18,8,a1r,V,0,0}, /* ld.l */ - {21,5,a2r,V,0,0}, /* st.b */ - {21,6,a2r,V,0,0}, /* st.h */ - {21,7,a2r,V,0,0}, /* st.w */ - {21,8,a2r,V,0,0}, /* st.l */ -}; - -const struct formstr format2[] = { - {28,5,rr,A,A,0}, /* cvtw.b */ - {28,6,rr,A,A,0}, /* cvtw.h */ - {29,7,rr,A,A,0}, /* cvtb.w */ - {30,7,rr,A,A,0}, /* cvth.w */ - {28,5,rr,S,S,0}, /* cvtw.b */ - {28,6,rr,S,S,0}, /* cvtw.h */ - {29,7,rr,S,S,0}, /* cvtb.w */ - {30,7,rr,S,S,0}, /* cvth.w */ - {28,3,rr,S,S,0}, /* cvtw.s */ - {31,7,rr,S,S,0}, /* cvts.w */ - {32,3,rr,S,S,0}, /* cvtd.s */ - {31,4,rr,S,S,0}, /* cvts.d */ - {31,8,rr,S,S,0}, /* cvts.l */ - {32,8,rr,S,S,0}, /* cvtd.l */ - {33,3,rr,S,S,0}, /* cvtl.s */ - {33,4,rr,S,S,0}, /* cvtl.d */ - {34,0,rr,A,A,0}, /* ldpa */ - {8,0,nr,A,0,0}, /* shf */ - {18,6,nr,A,0,0}, /* ld.h */ - {18,7,nr,A,0,0}, /* ld.w */ - {33,7,rr,S,S,0}, /* cvtl.w */ - {28,8,rr,S,S,0}, /* cvtw.l */ - {35,1,rr,S,S,0}, /* plc.t */ - {36,0,rr,S,S,0}, /* tzc */ - {37,6,rr,A,A,0}, /* eq.h */ - {37,7,rr,A,A,0}, /* eq.w */ - {37,6,nr,A,0,0}, /* eq.h */ - {37,7,nr,A,0,0}, /* eq.w */ - {37,5,rr,S,S,0}, /* eq.b */ - {37,6,rr,S,S,0}, /* eq.h */ - {37,7,rr,S,S,0}, /* eq.w */ - {37,8,rr,S,S,0}, /* eq.l */ - {38,6,rr,A,A,0}, /* leu.h */ - {38,7,rr,A,A,0}, /* leu.w */ - {38,6,nr,A,0,0}, /* leu.h */ - {38,7,nr,A,0,0}, /* leu.w */ - {38,5,rr,S,S,0}, /* leu.b */ - {38,6,rr,S,S,0}, /* leu.h */ - {38,7,rr,S,S,0}, /* leu.w */ - {38,8,rr,S,S,0}, /* leu.l */ - {39,6,rr,A,A,0}, /* ltu.h */ - {39,7,rr,A,A,0}, /* ltu.w */ - {39,6,nr,A,0,0}, /* ltu.h */ - {39,7,nr,A,0,0}, /* ltu.w */ - {39,5,rr,S,S,0}, /* ltu.b */ - {39,6,rr,S,S,0}, /* ltu.h */ - {39,7,rr,S,S,0}, /* ltu.w */ - {39,8,rr,S,S,0}, /* ltu.l */ - {40,6,rr,A,A,0}, /* le.h */ - {40,7,rr,A,A,0}, /* le.w */ - {40,6,nr,A,0,0}, /* le.h */ - {40,7,nr,A,0,0}, /* le.w */ - {40,5,rr,S,S,0}, /* le.b */ - {40,6,rr,S,S,0}, /* le.h */ - {40,7,rr,S,S,0}, /* le.w */ - {40,8,rr,S,S,0}, /* le.l */ - {41,6,rr,A,A,0}, /* lt.h */ - {41,7,rr,A,A,0}, /* lt.w */ - {41,6,nr,A,0,0}, /* lt.h */ - {41,7,nr,A,0,0}, /* lt.w */ - {41,5,rr,S,S,0}, /* lt.b */ - {41,6,rr,S,S,0}, /* lt.h */ - {41,7,rr,S,S,0}, /* lt.w */ - {41,8,rr,S,S,0}, /* lt.l */ - {9,7,rr,S,A,0}, /* add.w */ - {8,0,rr,A,A,0}, /* shf */ - {0,0,rr,A,A,0}, /* mov */ - {0,0,rr,S,A,0}, /* mov */ - {0,7,rr,S,S,0}, /* mov.w */ - {8,0,rr,S,S,0}, /* shf */ - {0,0,rr,S,S,0}, /* mov */ - {0,0,rr,A,S,0}, /* mov */ - {5,0,rr,A,A,0}, /* and */ - {6,0,rr,A,A,0}, /* or */ - {7,0,rr,A,A,0}, /* xor */ - {42,0,rr,A,A,0}, /* not */ - {5,0,rr,S,S,0}, /* and */ - {6,0,rr,S,S,0}, /* or */ - {7,0,rr,S,S,0}, /* xor */ - {42,0,rr,S,S,0}, /* not */ - {40,3,rr,S,S,0}, /* le.s */ - {40,4,rr,S,S,0}, /* le.d */ - {41,3,rr,S,S,0}, /* lt.s */ - {41,4,rr,S,S,0}, /* lt.d */ - {9,3,rr,S,S,0}, /* add.s */ - {9,4,rr,S,S,0}, /* add.d */ - {10,3,rr,S,S,0}, /* sub.s */ - {10,4,rr,S,S,0}, /* sub.d */ - {37,3,rr,S,S,0}, /* eq.s */ - {37,4,rr,S,S,0}, /* eq.d */ - {43,6,rr,A,A,0}, /* neg.h */ - {43,7,rr,A,A,0}, /* neg.w */ - {3,3,rr,S,S,0}, /* mul.s */ - {3,4,rr,S,S,0}, /* mul.d */ - {4,3,rr,S,S,0}, /* div.s */ - {4,4,rr,S,S,0}, /* div.d */ - {9,6,rr,A,A,0}, /* add.h */ - {9,7,rr,A,A,0}, /* add.w */ - {9,6,nr,A,0,0}, /* add.h */ - {9,7,nr,A,0,0}, /* add.w */ - {9,5,rr,S,S,0}, /* add.b */ - {9,6,rr,S,S,0}, /* add.h */ - {9,7,rr,S,S,0}, /* add.w */ - {9,8,rr,S,S,0}, /* add.l */ - {10,6,rr,A,A,0}, /* sub.h */ - {10,7,rr,A,A,0}, /* sub.w */ - {10,6,nr,A,0,0}, /* sub.h */ - {10,7,nr,A,0,0}, /* sub.w */ - {10,5,rr,S,S,0}, /* sub.b */ - {10,6,rr,S,S,0}, /* sub.h */ - {10,7,rr,S,S,0}, /* sub.w */ - {10,8,rr,S,S,0}, /* sub.l */ - {3,6,rr,A,A,0}, /* mul.h */ - {3,7,rr,A,A,0}, /* mul.w */ - {3,6,nr,A,0,0}, /* mul.h */ - {3,7,nr,A,0,0}, /* mul.w */ - {3,5,rr,S,S,0}, /* mul.b */ - {3,6,rr,S,S,0}, /* mul.h */ - {3,7,rr,S,S,0}, /* mul.w */ - {3,8,rr,S,S,0}, /* mul.l */ - {4,6,rr,A,A,0}, /* div.h */ - {4,7,rr,A,A,0}, /* div.w */ - {4,6,nr,A,0,0}, /* div.h */ - {4,7,nr,A,0,0}, /* div.w */ - {4,5,rr,S,S,0}, /* div.b */ - {4,6,rr,S,S,0}, /* div.h */ - {4,7,rr,S,S,0}, /* div.w */ - {4,8,rr,S,S,0}, /* div.l */ -}; - -const struct formstr format3[] = { - {32,3,rr,V,V,0}, /* cvtd.s */ - {31,4,rr,V,V,0}, /* cvts.d */ - {33,4,rr,V,V,0}, /* cvtl.d */ - {32,8,rr,V,V,0}, /* cvtd.l */ - {0,0,rrl,S,S,VM}, /* mov */ - {0,0,rlr,S,VM,S}, /* mov */ - {0,0,0,0,0,0}, - {44,0,rr,S,S,0}, /* lop */ - {36,0,rr,V,V,0}, /* tzc */ - {44,0,rr,V,V,0}, /* lop */ - {0,0,0,0,0,0}, - {42,0,rr,V,V,0}, /* not */ - {8,0,rr,S,V,0}, /* shf */ - {35,1,rr,V,V,0}, /* plc.t */ - {45,2,rr,V,V,0}, /* cprs.f */ - {45,1,rr,V,V,0}, /* cprs.t */ - {37,3,rr,V,V,0}, /* eq.s */ - {37,4,rr,V,V,0}, /* eq.d */ - {43,3,rr,V,V,0}, /* neg.s */ - {43,4,rr,V,V,0}, /* neg.d */ - {37,3,rr,S,V,0}, /* eq.s */ - {37,4,rr,S,V,0}, /* eq.d */ - {43,3,rr,S,S,0}, /* neg.s */ - {43,4,rr,S,S,0}, /* neg.d */ - {40,3,rr,V,V,0}, /* le.s */ - {40,4,rr,V,V,0}, /* le.d */ - {41,3,rr,V,V,0}, /* lt.s */ - {41,4,rr,V,V,0}, /* lt.d */ - {40,3,rr,S,V,0}, /* le.s */ - {40,4,rr,S,V,0}, /* le.d */ - {41,3,rr,S,V,0}, /* lt.s */ - {41,4,rr,S,V,0}, /* lt.d */ - {37,5,rr,V,V,0}, /* eq.b */ - {37,6,rr,V,V,0}, /* eq.h */ - {37,7,rr,V,V,0}, /* eq.w */ - {37,8,rr,V,V,0}, /* eq.l */ - {37,5,rr,S,V,0}, /* eq.b */ - {37,6,rr,S,V,0}, /* eq.h */ - {37,7,rr,S,V,0}, /* eq.w */ - {37,8,rr,S,V,0}, /* eq.l */ - {40,5,rr,V,V,0}, /* le.b */ - {40,6,rr,V,V,0}, /* le.h */ - {40,7,rr,V,V,0}, /* le.w */ - {40,8,rr,V,V,0}, /* le.l */ - {40,5,rr,S,V,0}, /* le.b */ - {40,6,rr,S,V,0}, /* le.h */ - {40,7,rr,S,V,0}, /* le.w */ - {40,8,rr,S,V,0}, /* le.l */ - {41,5,rr,V,V,0}, /* lt.b */ - {41,6,rr,V,V,0}, /* lt.h */ - {41,7,rr,V,V,0}, /* lt.w */ - {41,8,rr,V,V,0}, /* lt.l */ - {41,5,rr,S,V,0}, /* lt.b */ - {41,6,rr,S,V,0}, /* lt.h */ - {41,7,rr,S,V,0}, /* lt.w */ - {41,8,rr,S,V,0}, /* lt.l */ - {43,5,rr,V,V,0}, /* neg.b */ - {43,6,rr,V,V,0}, /* neg.h */ - {43,7,rr,V,V,0}, /* neg.w */ - {43,8,rr,V,V,0}, /* neg.l */ - {43,5,rr,S,S,0}, /* neg.b */ - {43,6,rr,S,S,0}, /* neg.h */ - {43,7,rr,S,S,0}, /* neg.w */ - {43,8,rr,S,S,0}, /* neg.l */ -}; - -const struct formstr format4[] = { - {46,0,nops,0,0,0}, /* nop */ - {47,0,pcrel,0,0,0}, /* br */ - {48,2,pcrel,0,0,0}, /* bri.f */ - {48,1,pcrel,0,0,0}, /* bri.t */ - {49,2,pcrel,0,0,0}, /* bra.f */ - {49,1,pcrel,0,0,0}, /* bra.t */ - {50,2,pcrel,0,0,0}, /* brs.f */ - {50,1,pcrel,0,0,0}, /* brs.t */ -}; - -const struct formstr format5[] = { - {51,5,rr,V,V,0}, /* ldvi.b */ - {51,6,rr,V,V,0}, /* ldvi.h */ - {51,7,rr,V,V,0}, /* ldvi.w */ - {51,8,rr,V,V,0}, /* ldvi.l */ - {28,3,rr,V,V,0}, /* cvtw.s */ - {31,7,rr,V,V,0}, /* cvts.w */ - {28,8,rr,V,V,0}, /* cvtw.l */ - {33,7,rr,V,V,0}, /* cvtl.w */ - {52,5,rxr,V,V,0}, /* stvi.b */ - {52,6,rxr,V,V,0}, /* stvi.h */ - {52,7,rxr,V,V,0}, /* stvi.w */ - {52,8,rxr,V,V,0}, /* stvi.l */ - {52,5,rxr,S,V,0}, /* stvi.b */ - {52,6,rxr,S,V,0}, /* stvi.h */ - {52,7,rxr,S,V,0}, /* stvi.w */ - {52,8,rxr,S,V,0}, /* stvi.l */ -}; - -const struct formstr format6[] = { - {53,0,r,A,0,0}, /* ldsdr */ - {54,0,r,A,0,0}, /* ldkdr */ - {55,3,r,S,0,0}, /* ln.s */ - {55,4,r,S,0,0}, /* ln.d */ - {56,0,nops,0,0,0}, /* patu */ - {57,0,r,A,0,0}, /* pate */ - {58,0,nops,0,0,0}, /* pich */ - {59,0,nops,0,0,0}, /* plch */ - {0,0,lr,PSW,A,0}, /* mov */ - {0,0,rxl,A,PSW,0}, /* mov */ - {0,0,lr,PC,A,0}, /* mov */ - {60,0,r,S,0,0}, /* idle */ - {0,0,lr,ITR,S,0}, /* mov */ - {0,0,rxl,S,ITR,0}, /* mov */ - {0,0,0,0,0,0}, - {0,0,rxl,S,ITSR,0}, /* mov */ - {61,0,nops,0,0,0}, /* rtnq */ - {62,0,nops,0,0,0}, /* cfork */ - {63,0,nops,0,0,0}, /* rtn */ - {64,0,nops,0,0,0}, /* wfork */ - {65,0,nops,0,0,0}, /* join */ - {66,0,nops,0,0,0}, /* rtnc */ - {67,3,r,S,0,0}, /* exp.s */ - {67,4,r,S,0,0}, /* exp.d */ - {68,3,r,S,0,0}, /* sin.s */ - {68,4,r,S,0,0}, /* sin.d */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {69,3,r,S,0,0}, /* cos.s */ - {69,4,r,S,0,0}, /* cos.d */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {70,7,r,A,0,0}, /* psh.w */ - {0,0,0,0,0,0}, - {71,7,r,A,0,0}, /* pop.w */ - {0,0,0,0,0,0}, - {70,7,r,S,0,0}, /* psh.w */ - {70,8,r,S,0,0}, /* psh.l */ - {71,7,r,S,0,0}, /* pop.w */ - {71,8,r,S,0,0}, /* pop.l */ - {72,0,nops,0,0,0}, /* eni */ - {73,0,nops,0,0,0}, /* dsi */ - {74,0,nops,0,0,0}, /* bkpt */ - {75,0,nops,0,0,0}, /* msync */ - {76,0,r,S,0,0}, /* mski */ - {77,0,r,S,0,0}, /* xmti */ - {0,0,rxl,S,VV,0}, /* mov */ - {78,0,nops,0,0,0}, /* tstvv */ - {0,0,lr,VS,A,0}, /* mov */ - {0,0,rxl,A,VS,0}, /* mov */ - {0,0,lr,VL,A,0}, /* mov */ - {0,0,rxl,A,VL,0}, /* mov */ - {0,7,lr,VS,S,0}, /* mov.w */ - {0,7,rxl,S,VS,0}, /* mov.w */ - {0,7,lr,VL,S,0}, /* mov.w */ - {0,7,rxl,S,VL,0}, /* mov.w */ - {79,0,r,A,0,0}, /* diag */ - {80,0,nops,0,0,0}, /* pbkpt */ - {81,3,r,S,0,0}, /* sqrt.s */ - {81,4,r,S,0,0}, /* sqrt.d */ - {82,0,nops,0,0,0}, /* casr */ - {0,0,0,0,0,0}, - {83,3,r,S,0,0}, /* atan.s */ - {83,4,r,S,0,0}, /* atan.d */ -}; - -const struct formstr format7[] = { - {84,5,r,V,0,0}, /* sum.b */ - {84,6,r,V,0,0}, /* sum.h */ - {84,7,r,V,0,0}, /* sum.w */ - {84,8,r,V,0,0}, /* sum.l */ - {85,0,r,V,0,0}, /* all */ - {86,0,r,V,0,0}, /* any */ - {87,0,r,V,0,0}, /* parity */ - {0,0,0,0,0,0}, - {88,5,r,V,0,0}, /* max.b */ - {88,6,r,V,0,0}, /* max.h */ - {88,7,r,V,0,0}, /* max.w */ - {88,8,r,V,0,0}, /* max.l */ - {89,5,r,V,0,0}, /* min.b */ - {89,6,r,V,0,0}, /* min.h */ - {89,7,r,V,0,0}, /* min.w */ - {89,8,r,V,0,0}, /* min.l */ - {84,3,r,V,0,0}, /* sum.s */ - {84,4,r,V,0,0}, /* sum.d */ - {90,3,r,V,0,0}, /* prod.s */ - {90,4,r,V,0,0}, /* prod.d */ - {88,3,r,V,0,0}, /* max.s */ - {88,4,r,V,0,0}, /* max.d */ - {89,3,r,V,0,0}, /* min.s */ - {89,4,r,V,0,0}, /* min.d */ - {90,5,r,V,0,0}, /* prod.b */ - {90,6,r,V,0,0}, /* prod.h */ - {90,7,r,V,0,0}, /* prod.w */ - {90,8,r,V,0,0}, /* prod.l */ - {35,2,lr,VM,S,0}, /* plc.f */ - {35,1,lr,VM,S,0}, /* plc.t */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, -}; - -const struct formstr formatx[] = { - {0,0,0,0,0,0}, -}; - -const struct formstr format1a[] = { - {91,0,imr,A,0,0}, /* halt */ - {92,0,a4,0,0,0}, /* sysc */ - {18,6,imr,A,0,0}, /* ld.h */ - {18,7,imr,A,0,0}, /* ld.w */ - {5,0,imr,A,0,0}, /* and */ - {6,0,imr,A,0,0}, /* or */ - {7,0,imr,A,0,0}, /* xor */ - {8,0,imr,A,0,0}, /* shf */ - {9,6,imr,A,0,0}, /* add.h */ - {9,7,imr,A,0,0}, /* add.w */ - {10,6,imr,A,0,0}, /* sub.h */ - {10,7,imr,A,0,0}, /* sub.w */ - {3,6,imr,A,0,0}, /* mul.h */ - {3,7,imr,A,0,0}, /* mul.w */ - {4,6,imr,A,0,0}, /* div.h */ - {4,7,imr,A,0,0}, /* div.w */ - {18,7,iml,VL,0,0}, /* ld.w */ - {18,7,iml,VS,0,0}, /* ld.w */ - {0,0,0,0,0,0}, - {8,7,imr,S,0,0}, /* shf.w */ - {93,0,a5,0,0,0}, /* trap */ - {0,0,0,0,0,0}, - {37,6,imr,A,0,0}, /* eq.h */ - {37,7,imr,A,0,0}, /* eq.w */ - {38,6,imr,A,0,0}, /* leu.h */ - {38,7,imr,A,0,0}, /* leu.w */ - {39,6,imr,A,0,0}, /* ltu.h */ - {39,7,imr,A,0,0}, /* ltu.w */ - {40,6,imr,A,0,0}, /* le.h */ - {40,7,imr,A,0,0}, /* le.w */ - {41,6,imr,A,0,0}, /* lt.h */ - {41,7,imr,A,0,0}, /* lt.w */ -}; - -const struct formstr format1b[] = { - {18,4,imr,S,0,0}, /* ld.d */ - {18,10,imr,S,0,0}, /* ld.u */ - {18,8,imr,S,0,0}, /* ld.l */ - {18,7,imr,S,0,0}, /* ld.w */ - {5,0,imr,S,0,0}, /* and */ - {6,0,imr,S,0,0}, /* or */ - {7,0,imr,S,0,0}, /* xor */ - {8,0,imr,S,0,0}, /* shf */ - {9,6,imr,S,0,0}, /* add.h */ - {9,7,imr,S,0,0}, /* add.w */ - {10,6,imr,S,0,0}, /* sub.h */ - {10,7,imr,S,0,0}, /* sub.w */ - {3,6,imr,S,0,0}, /* mul.h */ - {3,7,imr,S,0,0}, /* mul.w */ - {4,6,imr,S,0,0}, /* div.h */ - {4,7,imr,S,0,0}, /* div.w */ - {9,3,imr,S,0,0}, /* add.s */ - {10,3,imr,S,0,0}, /* sub.s */ - {3,3,imr,S,0,0}, /* mul.s */ - {4,3,imr,S,0,0}, /* div.s */ - {40,3,imr,S,0,0}, /* le.s */ - {41,3,imr,S,0,0}, /* lt.s */ - {37,6,imr,S,0,0}, /* eq.h */ - {37,7,imr,S,0,0}, /* eq.w */ - {38,6,imr,S,0,0}, /* leu.h */ - {38,7,imr,S,0,0}, /* leu.w */ - {39,6,imr,S,0,0}, /* ltu.h */ - {39,7,imr,S,0,0}, /* ltu.w */ - {40,6,imr,S,0,0}, /* le.h */ - {40,7,imr,S,0,0}, /* le.w */ - {41,6,imr,S,0,0}, /* lt.h */ - {41,7,imr,S,0,0}, /* lt.w */ -}; - -const struct formstr e0_format0[] = { - {10,3,rrr,S,V,V}, /* sub.s */ - {10,4,rrr,S,V,V}, /* sub.d */ - {4,3,rrr,S,V,V}, /* div.s */ - {4,4,rrr,S,V,V}, /* div.d */ - {10,11,rrr,S,V,V}, /* sub.s.f */ - {10,12,rrr,S,V,V}, /* sub.d.f */ - {4,11,rrr,S,V,V}, /* div.s.f */ - {4,12,rrr,S,V,V}, /* div.d.f */ - {3,11,rrr,V,V,V}, /* mul.s.f */ - {3,12,rrr,V,V,V}, /* mul.d.f */ - {4,11,rrr,V,V,V}, /* div.s.f */ - {4,12,rrr,V,V,V}, /* div.d.f */ - {3,11,rrr,V,S,V}, /* mul.s.f */ - {3,12,rrr,V,S,V}, /* mul.d.f */ - {4,11,rrr,V,S,V}, /* div.s.f */ - {4,12,rrr,V,S,V}, /* div.d.f */ - {5,2,rrr,V,V,V}, /* and.f */ - {6,2,rrr,V,V,V}, /* or.f */ - {7,2,rrr,V,V,V}, /* xor.f */ - {8,2,rrr,V,V,V}, /* shf.f */ - {5,2,rrr,V,S,V}, /* and.f */ - {6,2,rrr,V,S,V}, /* or.f */ - {7,2,rrr,V,S,V}, /* xor.f */ - {8,2,rrr,V,S,V}, /* shf.f */ - {9,11,rrr,V,V,V}, /* add.s.f */ - {9,12,rrr,V,V,V}, /* add.d.f */ - {10,11,rrr,V,V,V}, /* sub.s.f */ - {10,12,rrr,V,V,V}, /* sub.d.f */ - {9,11,rrr,V,S,V}, /* add.s.f */ - {9,12,rrr,V,S,V}, /* add.d.f */ - {10,11,rrr,V,S,V}, /* sub.s.f */ - {10,12,rrr,V,S,V}, /* sub.d.f */ - {9,13,rrr,V,V,V}, /* add.b.f */ - {9,14,rrr,V,V,V}, /* add.h.f */ - {9,15,rrr,V,V,V}, /* add.w.f */ - {9,16,rrr,V,V,V}, /* add.l.f */ - {9,13,rrr,V,S,V}, /* add.b.f */ - {9,14,rrr,V,S,V}, /* add.h.f */ - {9,15,rrr,V,S,V}, /* add.w.f */ - {9,16,rrr,V,S,V}, /* add.l.f */ - {10,13,rrr,V,V,V}, /* sub.b.f */ - {10,14,rrr,V,V,V}, /* sub.h.f */ - {10,15,rrr,V,V,V}, /* sub.w.f */ - {10,16,rrr,V,V,V}, /* sub.l.f */ - {10,13,rrr,V,S,V}, /* sub.b.f */ - {10,14,rrr,V,S,V}, /* sub.h.f */ - {10,15,rrr,V,S,V}, /* sub.w.f */ - {10,16,rrr,V,S,V}, /* sub.l.f */ - {3,13,rrr,V,V,V}, /* mul.b.f */ - {3,14,rrr,V,V,V}, /* mul.h.f */ - {3,15,rrr,V,V,V}, /* mul.w.f */ - {3,16,rrr,V,V,V}, /* mul.l.f */ - {3,13,rrr,V,S,V}, /* mul.b.f */ - {3,14,rrr,V,S,V}, /* mul.h.f */ - {3,15,rrr,V,S,V}, /* mul.w.f */ - {3,16,rrr,V,S,V}, /* mul.l.f */ - {4,13,rrr,V,V,V}, /* div.b.f */ - {4,14,rrr,V,V,V}, /* div.h.f */ - {4,15,rrr,V,V,V}, /* div.w.f */ - {4,16,rrr,V,V,V}, /* div.l.f */ - {4,13,rrr,V,S,V}, /* div.b.f */ - {4,14,rrr,V,S,V}, /* div.h.f */ - {4,15,rrr,V,S,V}, /* div.w.f */ - {4,16,rrr,V,S,V}, /* div.l.f */ -}; - -const struct formstr e0_format1[] = { - {0,0,0,0,0,0}, - {94,0,a3,0,0,0}, /* tst */ - {95,0,a3,0,0,0}, /* lck */ - {96,0,a3,0,0,0}, /* ulk */ - {17,0,a1r,S,0,0}, /* ldea */ - {97,0,a1r,A,0,0}, /* spawn */ - {98,0,a1r,A,0,0}, /* ldcmr */ - {99,0,a2r,A,0,0}, /* stcmr */ - {100,0,a1r,A,0,0}, /* popr */ - {101,0,a2r,A,0,0}, /* pshr */ - {102,7,a1r,A,0,0}, /* rcvr.w */ - {103,7,a2r,A,0,0}, /* matm.w */ - {104,7,a2r,A,0,0}, /* sndr.w */ - {104,8,a2r,S,0,0}, /* sndr.l */ - {102,8,a1r,S,0,0}, /* rcvr.l */ - {103,8,a2r,S,0,0}, /* matm.l */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {105,7,a2r,A,0,0}, /* putr.w */ - {105,8,a2r,S,0,0}, /* putr.l */ - {106,7,a1r,A,0,0}, /* getr.w */ - {106,8,a1r,S,0,0}, /* getr.l */ - {26,13,a2r,S,0,0}, /* ste.b.f */ - {26,14,a2r,S,0,0}, /* ste.h.f */ - {26,15,a2r,S,0,0}, /* ste.w.f */ - {26,16,a2r,S,0,0}, /* ste.l.f */ - {107,7,a2r,A,0,0}, /* matr.w */ - {108,7,a2r,A,0,0}, /* mat.w */ - {109,7,a1r,A,0,0}, /* get.w */ - {110,7,a1r,A,0,0}, /* rcv.w */ - {0,0,0,0,0,0}, - {111,7,a1r,A,0,0}, /* inc.w */ - {112,7,a2r,A,0,0}, /* put.w */ - {113,7,a2r,A,0,0}, /* snd.w */ - {107,8,a2r,S,0,0}, /* matr.l */ - {108,8,a2r,S,0,0}, /* mat.l */ - {109,8,a1r,S,0,0}, /* get.l */ - {110,8,a1r,S,0,0}, /* rcv.l */ - {0,0,0,0,0,0}, - {111,8,a1r,S,0,0}, /* inc.l */ - {112,8,a2r,S,0,0}, /* put.l */ - {113,8,a2r,S,0,0}, /* snd.l */ - {18,13,a1r,V,0,0}, /* ld.b.f */ - {18,14,a1r,V,0,0}, /* ld.h.f */ - {18,15,a1r,V,0,0}, /* ld.w.f */ - {18,16,a1r,V,0,0}, /* ld.l.f */ - {21,13,a2r,V,0,0}, /* st.b.f */ - {21,14,a2r,V,0,0}, /* st.h.f */ - {21,15,a2r,V,0,0}, /* st.w.f */ - {21,16,a2r,V,0,0}, /* st.l.f */ -}; - -const struct formstr e0_format2[] = { - {28,5,rr,V,V,0}, /* cvtw.b */ - {28,6,rr,V,V,0}, /* cvtw.h */ - {29,7,rr,V,V,0}, /* cvtb.w */ - {30,7,rr,V,V,0}, /* cvth.w */ - {28,13,rr,V,V,0}, /* cvtw.b.f */ - {28,14,rr,V,V,0}, /* cvtw.h.f */ - {29,15,rr,V,V,0}, /* cvtb.w.f */ - {30,15,rr,V,V,0}, /* cvth.w.f */ - {31,8,rr,V,V,0}, /* cvts.l */ - {32,7,rr,V,V,0}, /* cvtd.w */ - {33,3,rr,V,V,0}, /* cvtl.s */ - {28,4,rr,V,V,0}, /* cvtw.d */ - {31,16,rr,V,V,0}, /* cvts.l.f */ - {32,15,rr,V,V,0}, /* cvtd.w.f */ - {33,11,rr,V,V,0}, /* cvtl.s.f */ - {28,12,rr,V,V,0}, /* cvtw.d.f */ - {114,0,rr,S,S,0}, /* enal */ - {8,7,rr,S,S,0}, /* shf.w */ - {115,0,rr,S,S,0}, /* enag */ - {0,0,0,0,0,0}, - {28,4,rr,S,S,0}, /* cvtw.d */ - {32,7,rr,S,S,0}, /* cvtd.w */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {116,3,rr,S,S,0}, /* frint.s */ - {116,4,rr,S,S,0}, /* frint.d */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {116,3,rr,V,V,0}, /* frint.s */ - {116,4,rr,V,V,0}, /* frint.d */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {116,11,rr,V,V,0}, /* frint.s.f */ - {116,12,rr,V,V,0}, /* frint.d.f */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {81,3,rr,V,V,0}, /* sqrt.s */ - {81,4,rr,V,V,0}, /* sqrt.d */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {81,11,rr,V,V,0}, /* sqrt.s.f */ - {81,12,rr,V,V,0}, /* sqrt.d.f */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, -}; - -const struct formstr e0_format3[] = { - {32,11,rr,V,V,0}, /* cvtd.s.f */ - {31,12,rr,V,V,0}, /* cvts.d.f */ - {33,12,rr,V,V,0}, /* cvtl.d.f */ - {32,16,rr,V,V,0}, /* cvtd.l.f */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {36,2,rr,V,V,0}, /* tzc.f */ - {44,2,rr,V,V,0}, /* lop.f */ - {117,2,rr,V,V,0}, /* xpnd.f */ - {42,2,rr,V,V,0}, /* not.f */ - {8,2,rr,S,V,0}, /* shf.f */ - {35,17,rr,V,V,0}, /* plc.t.f */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {37,11,rr,V,V,0}, /* eq.s.f */ - {37,12,rr,V,V,0}, /* eq.d.f */ - {43,11,rr,V,V,0}, /* neg.s.f */ - {43,12,rr,V,V,0}, /* neg.d.f */ - {37,11,rr,S,V,0}, /* eq.s.f */ - {37,12,rr,S,V,0}, /* eq.d.f */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {40,11,rr,V,V,0}, /* le.s.f */ - {40,12,rr,V,V,0}, /* le.d.f */ - {41,11,rr,V,V,0}, /* lt.s.f */ - {41,12,rr,V,V,0}, /* lt.d.f */ - {40,11,rr,S,V,0}, /* le.s.f */ - {40,12,rr,S,V,0}, /* le.d.f */ - {41,11,rr,S,V,0}, /* lt.s.f */ - {41,12,rr,S,V,0}, /* lt.d.f */ - {37,13,rr,V,V,0}, /* eq.b.f */ - {37,14,rr,V,V,0}, /* eq.h.f */ - {37,15,rr,V,V,0}, /* eq.w.f */ - {37,16,rr,V,V,0}, /* eq.l.f */ - {37,13,rr,S,V,0}, /* eq.b.f */ - {37,14,rr,S,V,0}, /* eq.h.f */ - {37,15,rr,S,V,0}, /* eq.w.f */ - {37,16,rr,S,V,0}, /* eq.l.f */ - {40,13,rr,V,V,0}, /* le.b.f */ - {40,14,rr,V,V,0}, /* le.h.f */ - {40,15,rr,V,V,0}, /* le.w.f */ - {40,16,rr,V,V,0}, /* le.l.f */ - {40,13,rr,S,V,0}, /* le.b.f */ - {40,14,rr,S,V,0}, /* le.h.f */ - {40,15,rr,S,V,0}, /* le.w.f */ - {40,16,rr,S,V,0}, /* le.l.f */ - {41,13,rr,V,V,0}, /* lt.b.f */ - {41,14,rr,V,V,0}, /* lt.h.f */ - {41,15,rr,V,V,0}, /* lt.w.f */ - {41,16,rr,V,V,0}, /* lt.l.f */ - {41,13,rr,S,V,0}, /* lt.b.f */ - {41,14,rr,S,V,0}, /* lt.h.f */ - {41,15,rr,S,V,0}, /* lt.w.f */ - {41,16,rr,S,V,0}, /* lt.l.f */ - {43,13,rr,V,V,0}, /* neg.b.f */ - {43,14,rr,V,V,0}, /* neg.h.f */ - {43,15,rr,V,V,0}, /* neg.w.f */ - {43,16,rr,V,V,0}, /* neg.l.f */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, -}; - -const struct formstr e0_format4[] = { - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, -}; - -const struct formstr e0_format5[] = { - {51,13,rr,V,V,0}, /* ldvi.b.f */ - {51,14,rr,V,V,0}, /* ldvi.h.f */ - {51,15,rr,V,V,0}, /* ldvi.w.f */ - {51,16,rr,V,V,0}, /* ldvi.l.f */ - {28,11,rr,V,V,0}, /* cvtw.s.f */ - {31,15,rr,V,V,0}, /* cvts.w.f */ - {28,16,rr,V,V,0}, /* cvtw.l.f */ - {33,15,rr,V,V,0}, /* cvtl.w.f */ - {52,13,rxr,V,V,0}, /* stvi.b.f */ - {52,14,rxr,V,V,0}, /* stvi.h.f */ - {52,15,rxr,V,V,0}, /* stvi.w.f */ - {52,16,rxr,V,V,0}, /* stvi.l.f */ - {52,13,rxr,S,V,0}, /* stvi.b.f */ - {52,14,rxr,S,V,0}, /* stvi.h.f */ - {52,15,rxr,S,V,0}, /* stvi.w.f */ - {52,16,rxr,S,V,0}, /* stvi.l.f */ -}; - -const struct formstr e0_format6[] = { - {0,0,rxl,S,CIR,0}, /* mov */ - {0,0,lr,CIR,S,0}, /* mov */ - {0,0,lr,TOC,S,0}, /* mov */ - {0,0,lr,CPUID,S,0}, /* mov */ - {0,0,rxl,S,TTR,0}, /* mov */ - {0,0,lr,TTR,S,0}, /* mov */ - {118,0,nops,0,0,0}, /* ctrsl */ - {119,0,nops,0,0,0}, /* ctrsg */ - {0,0,rxl,S,VMU,0}, /* mov */ - {0,0,lr,VMU,S,0}, /* mov */ - {0,0,rxl,S,VML,0}, /* mov */ - {0,0,lr,VML,S,0}, /* mov */ - {0,0,rxl,S,ICR,0}, /* mov */ - {0,0,lr,ICR,S,0}, /* mov */ - {0,0,rxl,S,TCPU,0}, /* mov */ - {0,0,lr,TCPU,S,0}, /* mov */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {120,0,nops,0,0,0}, /* stop */ - {0,0,0,0,0,0}, - {0,0,rxl,S,TID,0}, /* mov */ - {0,0,lr,TID,S,0}, /* mov */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, -}; - -const struct formstr e0_format7[] = { - {84,13,r,V,0,0}, /* sum.b.f */ - {84,14,r,V,0,0}, /* sum.h.f */ - {84,15,r,V,0,0}, /* sum.w.f */ - {84,16,r,V,0,0}, /* sum.l.f */ - {85,2,r,V,0,0}, /* all.f */ - {86,2,r,V,0,0}, /* any.f */ - {87,2,r,V,0,0}, /* parity.f */ - {0,0,0,0,0,0}, - {88,13,r,V,0,0}, /* max.b.f */ - {88,14,r,V,0,0}, /* max.h.f */ - {88,15,r,V,0,0}, /* max.w.f */ - {88,16,r,V,0,0}, /* max.l.f */ - {89,13,r,V,0,0}, /* min.b.f */ - {89,14,r,V,0,0}, /* min.h.f */ - {89,15,r,V,0,0}, /* min.w.f */ - {89,16,r,V,0,0}, /* min.l.f */ - {84,11,r,V,0,0}, /* sum.s.f */ - {84,12,r,V,0,0}, /* sum.d.f */ - {90,11,r,V,0,0}, /* prod.s.f */ - {90,12,r,V,0,0}, /* prod.d.f */ - {88,11,r,V,0,0}, /* max.s.f */ - {88,12,r,V,0,0}, /* max.d.f */ - {89,11,r,V,0,0}, /* min.s.f */ - {89,12,r,V,0,0}, /* min.d.f */ - {90,13,r,V,0,0}, /* prod.b.f */ - {90,14,r,V,0,0}, /* prod.h.f */ - {90,15,r,V,0,0}, /* prod.w.f */ - {90,16,r,V,0,0}, /* prod.l.f */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, -}; - -const struct formstr e1_format0[] = { - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {10,18,rrr,S,V,V}, /* sub.s.t */ - {10,19,rrr,S,V,V}, /* sub.d.t */ - {4,18,rrr,S,V,V}, /* div.s.t */ - {4,19,rrr,S,V,V}, /* div.d.t */ - {3,18,rrr,V,V,V}, /* mul.s.t */ - {3,19,rrr,V,V,V}, /* mul.d.t */ - {4,18,rrr,V,V,V}, /* div.s.t */ - {4,19,rrr,V,V,V}, /* div.d.t */ - {3,18,rrr,V,S,V}, /* mul.s.t */ - {3,19,rrr,V,S,V}, /* mul.d.t */ - {4,18,rrr,V,S,V}, /* div.s.t */ - {4,19,rrr,V,S,V}, /* div.d.t */ - {5,1,rrr,V,V,V}, /* and.t */ - {6,1,rrr,V,V,V}, /* or.t */ - {7,1,rrr,V,V,V}, /* xor.t */ - {8,1,rrr,V,V,V}, /* shf.t */ - {5,1,rrr,V,S,V}, /* and.t */ - {6,1,rrr,V,S,V}, /* or.t */ - {7,1,rrr,V,S,V}, /* xor.t */ - {8,1,rrr,V,S,V}, /* shf.t */ - {9,18,rrr,V,V,V}, /* add.s.t */ - {9,19,rrr,V,V,V}, /* add.d.t */ - {10,18,rrr,V,V,V}, /* sub.s.t */ - {10,19,rrr,V,V,V}, /* sub.d.t */ - {9,18,rrr,V,S,V}, /* add.s.t */ - {9,19,rrr,V,S,V}, /* add.d.t */ - {10,18,rrr,V,S,V}, /* sub.s.t */ - {10,19,rrr,V,S,V}, /* sub.d.t */ - {9,20,rrr,V,V,V}, /* add.b.t */ - {9,21,rrr,V,V,V}, /* add.h.t */ - {9,22,rrr,V,V,V}, /* add.w.t */ - {9,23,rrr,V,V,V}, /* add.l.t */ - {9,20,rrr,V,S,V}, /* add.b.t */ - {9,21,rrr,V,S,V}, /* add.h.t */ - {9,22,rrr,V,S,V}, /* add.w.t */ - {9,23,rrr,V,S,V}, /* add.l.t */ - {10,20,rrr,V,V,V}, /* sub.b.t */ - {10,21,rrr,V,V,V}, /* sub.h.t */ - {10,22,rrr,V,V,V}, /* sub.w.t */ - {10,23,rrr,V,V,V}, /* sub.l.t */ - {10,20,rrr,V,S,V}, /* sub.b.t */ - {10,21,rrr,V,S,V}, /* sub.h.t */ - {10,22,rrr,V,S,V}, /* sub.w.t */ - {10,23,rrr,V,S,V}, /* sub.l.t */ - {3,20,rrr,V,V,V}, /* mul.b.t */ - {3,21,rrr,V,V,V}, /* mul.h.t */ - {3,22,rrr,V,V,V}, /* mul.w.t */ - {3,23,rrr,V,V,V}, /* mul.l.t */ - {3,20,rrr,V,S,V}, /* mul.b.t */ - {3,21,rrr,V,S,V}, /* mul.h.t */ - {3,22,rrr,V,S,V}, /* mul.w.t */ - {3,23,rrr,V,S,V}, /* mul.l.t */ - {4,20,rrr,V,V,V}, /* div.b.t */ - {4,21,rrr,V,V,V}, /* div.h.t */ - {4,22,rrr,V,V,V}, /* div.w.t */ - {4,23,rrr,V,V,V}, /* div.l.t */ - {4,20,rrr,V,S,V}, /* div.b.t */ - {4,21,rrr,V,S,V}, /* div.h.t */ - {4,22,rrr,V,S,V}, /* div.w.t */ - {4,23,rrr,V,S,V}, /* div.l.t */ -}; - -const struct formstr e1_format1[] = { - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {26,20,a2r,S,0,0}, /* ste.b.t */ - {26,21,a2r,S,0,0}, /* ste.h.t */ - {26,22,a2r,S,0,0}, /* ste.w.t */ - {26,23,a2r,S,0,0}, /* ste.l.t */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {18,20,a1r,V,0,0}, /* ld.b.t */ - {18,21,a1r,V,0,0}, /* ld.h.t */ - {18,22,a1r,V,0,0}, /* ld.w.t */ - {18,23,a1r,V,0,0}, /* ld.l.t */ - {21,20,a2r,V,0,0}, /* st.b.t */ - {21,21,a2r,V,0,0}, /* st.h.t */ - {21,22,a2r,V,0,0}, /* st.w.t */ - {21,23,a2r,V,0,0}, /* st.l.t */ -}; - -const struct formstr e1_format2[] = { - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {28,20,rr,V,V,0}, /* cvtw.b.t */ - {28,21,rr,V,V,0}, /* cvtw.h.t */ - {29,22,rr,V,V,0}, /* cvtb.w.t */ - {30,22,rr,V,V,0}, /* cvth.w.t */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {31,23,rr,V,V,0}, /* cvts.l.t */ - {32,22,rr,V,V,0}, /* cvtd.w.t */ - {33,18,rr,V,V,0}, /* cvtl.s.t */ - {28,19,rr,V,V,0}, /* cvtw.d.t */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {116,18,rr,V,V,0}, /* frint.s.t */ - {116,19,rr,V,V,0}, /* frint.d.t */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {81,18,rr,V,V,0}, /* sqrt.s.t */ - {81,19,rr,V,V,0}, /* sqrt.d.t */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, -}; - -const struct formstr e1_format3[] = { - {32,18,rr,V,V,0}, /* cvtd.s.t */ - {31,19,rr,V,V,0}, /* cvts.d.t */ - {33,19,rr,V,V,0}, /* cvtl.d.t */ - {32,23,rr,V,V,0}, /* cvtd.l.t */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {36,1,rr,V,V,0}, /* tzc.t */ - {44,1,rr,V,V,0}, /* lop.t */ - {117,1,rr,V,V,0}, /* xpnd.t */ - {42,1,rr,V,V,0}, /* not.t */ - {8,1,rr,S,V,0}, /* shf.t */ - {35,24,rr,V,V,0}, /* plc.t.t */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {37,18,rr,V,V,0}, /* eq.s.t */ - {37,19,rr,V,V,0}, /* eq.d.t */ - {43,18,rr,V,V,0}, /* neg.s.t */ - {43,19,rr,V,V,0}, /* neg.d.t */ - {37,18,rr,S,V,0}, /* eq.s.t */ - {37,19,rr,S,V,0}, /* eq.d.t */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {40,18,rr,V,V,0}, /* le.s.t */ - {40,19,rr,V,V,0}, /* le.d.t */ - {41,18,rr,V,V,0}, /* lt.s.t */ - {41,19,rr,V,V,0}, /* lt.d.t */ - {40,18,rr,S,V,0}, /* le.s.t */ - {40,19,rr,S,V,0}, /* le.d.t */ - {41,18,rr,S,V,0}, /* lt.s.t */ - {41,19,rr,S,V,0}, /* lt.d.t */ - {37,20,rr,V,V,0}, /* eq.b.t */ - {37,21,rr,V,V,0}, /* eq.h.t */ - {37,22,rr,V,V,0}, /* eq.w.t */ - {37,23,rr,V,V,0}, /* eq.l.t */ - {37,20,rr,S,V,0}, /* eq.b.t */ - {37,21,rr,S,V,0}, /* eq.h.t */ - {37,22,rr,S,V,0}, /* eq.w.t */ - {37,23,rr,S,V,0}, /* eq.l.t */ - {40,20,rr,V,V,0}, /* le.b.t */ - {40,21,rr,V,V,0}, /* le.h.t */ - {40,22,rr,V,V,0}, /* le.w.t */ - {40,23,rr,V,V,0}, /* le.l.t */ - {40,20,rr,S,V,0}, /* le.b.t */ - {40,21,rr,S,V,0}, /* le.h.t */ - {40,22,rr,S,V,0}, /* le.w.t */ - {40,23,rr,S,V,0}, /* le.l.t */ - {41,20,rr,V,V,0}, /* lt.b.t */ - {41,21,rr,V,V,0}, /* lt.h.t */ - {41,22,rr,V,V,0}, /* lt.w.t */ - {41,23,rr,V,V,0}, /* lt.l.t */ - {41,20,rr,S,V,0}, /* lt.b.t */ - {41,21,rr,S,V,0}, /* lt.h.t */ - {41,22,rr,S,V,0}, /* lt.w.t */ - {41,23,rr,S,V,0}, /* lt.l.t */ - {43,20,rr,V,V,0}, /* neg.b.t */ - {43,21,rr,V,V,0}, /* neg.h.t */ - {43,22,rr,V,V,0}, /* neg.w.t */ - {43,23,rr,V,V,0}, /* neg.l.t */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, -}; - -const struct formstr e1_format4[] = { - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, -}; - -const struct formstr e1_format5[] = { - {51,20,rr,V,V,0}, /* ldvi.b.t */ - {51,21,rr,V,V,0}, /* ldvi.h.t */ - {51,22,rr,V,V,0}, /* ldvi.w.t */ - {51,23,rr,V,V,0}, /* ldvi.l.t */ - {28,18,rr,V,V,0}, /* cvtw.s.t */ - {31,22,rr,V,V,0}, /* cvts.w.t */ - {28,23,rr,V,V,0}, /* cvtw.l.t */ - {33,22,rr,V,V,0}, /* cvtl.w.t */ - {52,20,rxr,V,V,0}, /* stvi.b.t */ - {52,21,rxr,V,V,0}, /* stvi.h.t */ - {52,22,rxr,V,V,0}, /* stvi.w.t */ - {52,23,rxr,V,V,0}, /* stvi.l.t */ - {52,20,rxr,S,V,0}, /* stvi.b.t */ - {52,21,rxr,S,V,0}, /* stvi.h.t */ - {52,22,rxr,S,V,0}, /* stvi.w.t */ - {52,23,rxr,S,V,0}, /* stvi.l.t */ -}; - -const struct formstr e1_format6[] = { - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, -}; - -const struct formstr e1_format7[] = { - {84,20,r,V,0,0}, /* sum.b.t */ - {84,21,r,V,0,0}, /* sum.h.t */ - {84,22,r,V,0,0}, /* sum.w.t */ - {84,23,r,V,0,0}, /* sum.l.t */ - {85,1,r,V,0,0}, /* all.t */ - {86,1,r,V,0,0}, /* any.t */ - {87,1,r,V,0,0}, /* parity.t */ - {0,0,0,0,0,0}, - {88,20,r,V,0,0}, /* max.b.t */ - {88,21,r,V,0,0}, /* max.h.t */ - {88,22,r,V,0,0}, /* max.w.t */ - {88,23,r,V,0,0}, /* max.l.t */ - {89,20,r,V,0,0}, /* min.b.t */ - {89,21,r,V,0,0}, /* min.h.t */ - {89,22,r,V,0,0}, /* min.w.t */ - {89,23,r,V,0,0}, /* min.l.t */ - {84,18,r,V,0,0}, /* sum.s.t */ - {84,19,r,V,0,0}, /* sum.d.t */ - {90,18,r,V,0,0}, /* prod.s.t */ - {90,19,r,V,0,0}, /* prod.d.t */ - {88,18,r,V,0,0}, /* max.s.t */ - {88,19,r,V,0,0}, /* max.d.t */ - {89,18,r,V,0,0}, /* min.s.t */ - {89,19,r,V,0,0}, /* min.d.t */ - {90,20,r,V,0,0}, /* prod.b.t */ - {90,21,r,V,0,0}, /* prod.h.t */ - {90,22,r,V,0,0}, /* prod.w.t */ - {90,23,r,V,0,0}, /* prod.l.t */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, -}; - -char *lop[] = { - "mov", /* 0 */ - "merg", /* 1 */ - "mask", /* 2 */ - "mul", /* 3 */ - "div", /* 4 */ - "and", /* 5 */ - "or", /* 6 */ - "xor", /* 7 */ - "shf", /* 8 */ - "add", /* 9 */ - "sub", /* 10 */ - "exit", /* 11 */ - "jmp", /* 12 */ - "jmpi", /* 13 */ - "jmpa", /* 14 */ - "jmps", /* 15 */ - "tac", /* 16 */ - "ldea", /* 17 */ - "ld", /* 18 */ - "tas", /* 19 */ - "pshea", /* 20 */ - "st", /* 21 */ - "call", /* 22 */ - "calls", /* 23 */ - "callq", /* 24 */ - "pfork", /* 25 */ - "ste", /* 26 */ - "incr", /* 27 */ - "cvtw", /* 28 */ - "cvtb", /* 29 */ - "cvth", /* 30 */ - "cvts", /* 31 */ - "cvtd", /* 32 */ - "cvtl", /* 33 */ - "ldpa", /* 34 */ - "plc", /* 35 */ - "tzc", /* 36 */ - "eq", /* 37 */ - "leu", /* 38 */ - "ltu", /* 39 */ - "le", /* 40 */ - "lt", /* 41 */ - "not", /* 42 */ - "neg", /* 43 */ - "lop", /* 44 */ - "cprs", /* 45 */ - "nop", /* 46 */ - "br", /* 47 */ - "bri", /* 48 */ - "bra", /* 49 */ - "brs", /* 50 */ - "ldvi", /* 51 */ - "stvi", /* 52 */ - "ldsdr", /* 53 */ - "ldkdr", /* 54 */ - "ln", /* 55 */ - "patu", /* 56 */ - "pate", /* 57 */ - "pich", /* 58 */ - "plch", /* 59 */ - "idle", /* 60 */ - "rtnq", /* 61 */ - "cfork", /* 62 */ - "rtn", /* 63 */ - "wfork", /* 64 */ - "join", /* 65 */ - "rtnc", /* 66 */ - "exp", /* 67 */ - "sin", /* 68 */ - "cos", /* 69 */ - "psh", /* 70 */ - "pop", /* 71 */ - "eni", /* 72 */ - "dsi", /* 73 */ - "bkpt", /* 74 */ - "msync", /* 75 */ - "mski", /* 76 */ - "xmti", /* 77 */ - "tstvv", /* 78 */ - "diag", /* 79 */ - "pbkpt", /* 80 */ - "sqrt", /* 81 */ - "casr", /* 82 */ - "atan", /* 83 */ - "sum", /* 84 */ - "all", /* 85 */ - "any", /* 86 */ - "parity", /* 87 */ - "max", /* 88 */ - "min", /* 89 */ - "prod", /* 90 */ - "halt", /* 91 */ - "sysc", /* 92 */ - "trap", /* 93 */ - "tst", /* 94 */ - "lck", /* 95 */ - "ulk", /* 96 */ - "spawn", /* 97 */ - "ldcmr", /* 98 */ - "stcmr", /* 99 */ - "popr", /* 100 */ - "pshr", /* 101 */ - "rcvr", /* 102 */ - "matm", /* 103 */ - "sndr", /* 104 */ - "putr", /* 105 */ - "getr", /* 106 */ - "matr", /* 107 */ - "mat", /* 108 */ - "get", /* 109 */ - "rcv", /* 110 */ - "inc", /* 111 */ - "put", /* 112 */ - "snd", /* 113 */ - "enal", /* 114 */ - "enag", /* 115 */ - "frint", /* 116 */ - "xpnd", /* 117 */ - "ctrsl", /* 118 */ - "ctrsg", /* 119 */ - "stop", /* 120 */ -}; - -char *rop[] = { - "", /* 0 */ - ".t", /* 1 */ - ".f", /* 2 */ - ".s", /* 3 */ - ".d", /* 4 */ - ".b", /* 5 */ - ".h", /* 6 */ - ".w", /* 7 */ - ".l", /* 8 */ - ".x", /* 9 */ - ".u", /* 10 */ - ".s.f", /* 11 */ - ".d.f", /* 12 */ - ".b.f", /* 13 */ - ".h.f", /* 14 */ - ".w.f", /* 15 */ - ".l.f", /* 16 */ - ".t.f", /* 17 */ - ".s.t", /* 18 */ - ".d.t", /* 19 */ - ".b.t", /* 20 */ - ".h.t", /* 21 */ - ".w.t", /* 22 */ - ".l.t", /* 23 */ - ".t.t", /* 24 */ -}; diff --git a/include/opcode/cr16.h b/include/opcode/cr16.h deleted file mode 100644 index 1f1191d..0000000 --- a/include/opcode/cr16.h +++ /dev/null @@ -1,451 +0,0 @@ -/* cr16.h -- Header file for CR16 opcode and register tables. - Copyright 2007, 2008, 2010, 2013 Free Software Foundation, Inc. - Contributed by M R Swami Reddy - - This file is part of GAS, GDB and the GNU binutils. - - GAS, GDB, and GNU binutils is free software; you can redistribute it - and/or modify it under the terms of the GNU General Public License as - published by the Free Software Foundation; either version 3, or (at your - option) any later version. - - GAS, GDB, and GNU binutils are distributed in the hope that they will be - useful, but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software Foundation, - Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ - -#ifndef _CR16_H_ -#define _CR16_H_ - -/* CR16 core Registers : - The enums are used as indices to CR16 registers table (cr16_regtab). - Therefore, order MUST be preserved. */ - -typedef enum -{ - /* 16-bit general purpose registers. */ - r0, r1, r2, r3, - r4, r5, r6, r7, - r8, r9, r10, r11, - r12_L = 12, r13_L = 13, ra = 14, sp_L = 15, - - /* 32-bit general purpose registers. */ - r12 = 12, r13 = 13, r14 = 14, r15 = 15, - era = 14, sp = 15, RA, - - /* Not a register. */ - nullregister, - MAX_REG -} -reg; - -/* CR16 processor registers and special registers : - The enums are used as indices to CR16 processor registers table - (cr16_pregtab). Therefore, order MUST be preserved. */ - -typedef enum -{ - /* processor registers. */ - dbs = MAX_REG, - dsr, dcrl, dcrh, - car0l, car0h, car1l, car1h, - cfg, psr, intbasel, intbaseh, - ispl, isph, uspl, usph, - dcr = dcrl, - car0 = car0l, - car1 = car1l, - intbase = intbasel, - isp = ispl, - usp = uspl, - /* Not a processor register. */ - nullpregister = usph + 1, - MAX_PREG -} -preg; - -/* CR16 Register types. */ - -typedef enum -{ - CR16_R_REGTYPE, /* r<N> */ - CR16_RP_REGTYPE, /* reg pair */ - CR16_P_REGTYPE /* Processor register */ -} -reg_type; - -/* CR16 argument types : - The argument types correspond to instructions operands - - Argument types : - r - register - rp - register pair - c - constant - i - immediate - idxr - index with register - idxrp - index with register pair - rbase - register base - rpbase - register pair base - pr - processor register. */ - -typedef enum -{ - arg_r, - arg_c, - arg_cr, - arg_crp, - arg_ic, - arg_icr, - arg_idxr, - arg_idxrp, - arg_rbase, - arg_rpbase, - arg_rp, - arg_pr, - arg_prp, - arg_cc, - arg_ra, - /* Not an argument. */ - nullargs -} -argtype; - -/* CR16 operand types:The operand types correspond to instructions operands. */ - -typedef enum -{ - dummy, - /* N-bit signed immediate. */ - imm3, imm4, imm5, imm6, imm16, imm20, imm32, - /* N-bit unsigned immediate. */ - uimm3, uimm3_1, uimm4, uimm4_1, uimm5, uimm16, uimm20, uimm32, - /* N-bit signed displacement. */ - disps5, disps17, disps25, - /* N-bit unsigned displacement. */ - dispe9, - /* N-bit absolute address. */ - abs20, abs24, - /* Register relative. */ - rra, rbase, rbase_disps20, rbase_dispe20, - /* Register pair relative. */ - rpbase_disps0, rpbase_dispe4, rpbase_disps4, rpbase_disps16, - rpbase_disps20, rpbase_dispe20, - /* Register index. */ - rindex7_abs20, rindex8_abs20, - /* Register pair index. */ - rpindex_disps0, rpindex_disps14, rpindex_disps20, - /* register. */ - regr, - /* register pair. */ - regp, - /* processor register. */ - pregr, - /* processor register 32 bit. */ - pregrp, - /* condition code - 4 bit. */ - cc, - /* Not an operand. */ - nulloperand, - /* Maximum supported operand. */ - MAX_OPRD -} -operand_type; - -/* CR16 instruction types. */ - -#define NO_TYPE_INS 0 -#define ARITH_INS 1 -#define LD_STOR_INS 2 -#define BRANCH_INS 3 -#define ARITH_BYTE_INS 4 -#define SHIFT_INS 5 -#define BRANCH_NEQ_INS 6 -#define LD_STOR_INS_INC 7 -#define STOR_IMM_INS 8 -#define CSTBIT_INS 9 - -/* Maximum value supported for instruction types. */ -#define CR16_INS_MAX (1 << 4) -/* Mask to record an instruction type. */ -#define CR16_INS_MASK (CR16_INS_MAX - 1) -/* Return instruction type, given instruction's attributes. */ -#define CR16_INS_TYPE(attr) ((attr) & CR16_INS_MASK) - -/* Indicates whether this instruction has a register list as parameter. */ -#define REG_LIST CR16_INS_MAX - -/* The operands in binary and assembly are placed in reverse order. - load - (REVERSE_MATCH)/store - (! REVERSE_MATCH). */ -#define REVERSE_MATCH (1 << 5) - -/* Printing formats, where the instruction prefix isn't consecutive. */ -#define FMT_1 (1 << 9) /* 0xF0F00000 */ -#define FMT_2 (1 << 10) /* 0xFFF0FF00 */ -#define FMT_3 (1 << 11) /* 0xFFF00F00 */ -#define FMT_4 (1 << 12) /* 0xFFF0F000 */ -#define FMT_5 (1 << 13) /* 0xFFF0FFF0 */ -#define FMT_CR16 (FMT_1 | FMT_2 | FMT_3 | FMT_4 | FMT_5) - -/* Indicates whether this instruction can be relaxed. */ -#define RELAXABLE (1 << 14) - -/* Indicates that instruction uses user registers (and not - general-purpose registers) as operands. */ -#define USER_REG (1 << 15) - - -/* Instruction shouldn't allow 'sp' usage. */ -#define NO_SP (1 << 17) - -/* Instruction shouldn't allow to push a register which is used as a rptr. */ -#define NO_RPTR (1 << 18) - -/* Maximum operands per instruction. */ -#define MAX_OPERANDS 5 -/* Maximum register name length. */ -#define MAX_REGNAME_LEN 10 -/* Maximum instruction length. */ -#define MAX_INST_LEN 256 - - -/* Values defined for the flags field of a struct operand_entry. */ - -/* Operand must be an unsigned number. */ -#define OP_UNSIGNED (1 << 0) -/* Operand must be a signed number. */ -#define OP_SIGNED (1 << 1) -/* Operand must be a negative number. */ -#define OP_NEG (1 << 2) -/* A special load/stor 4-bit unsigned displacement operand. */ -#define OP_DEC (1 << 3) -/* Operand must be an even number. */ -#define OP_EVEN (1 << 4) -/* Operand is shifted right. */ -#define OP_SHIFT (1 << 5) -/* Operand is shifted right and decremented. */ -#define OP_SHIFT_DEC (1 << 6) -/* Operand has reserved escape sequences. */ -#define OP_ESC (1 << 7) -/* Operand must be a ABS20 number. */ -#define OP_ABS20 (1 << 8) -/* Operand must be a ABS24 number. */ -#define OP_ABS24 (1 << 9) -/* Operand has reserved escape sequences type 1. */ -#define OP_ESC1 (1 << 10) - -/* Single operand description. */ - -typedef struct -{ - /* Operand type. */ - operand_type op_type; - /* Operand location within the opcode. */ - unsigned int shift; -} -operand_desc; - -/* Instruction data structure used in instruction table. */ - -typedef struct -{ - /* Name. */ - const char *mnemonic; - /* Size (in words). */ - unsigned int size; - /* Constant prefix (matched by the disassembler). */ - unsigned long match; /* ie opcode */ - /* Match size (in bits). */ - /* MASK: if( (i & match_bits) == match ) then match */ - int match_bits; - /* Attributes. */ - unsigned int flags; - /* Operands (always last, so unreferenced operands are initialized). */ - operand_desc operands[MAX_OPERANDS]; -} -inst; - -/* Data structure for a single instruction's arguments (Operands). */ - -typedef struct -{ - /* Register or base register. */ - reg r; - /* Register pair register. */ - reg rp; - /* Index register. */ - reg i_r; - /* Processor register. */ - preg pr; - /* Processor register. 32 bit */ - preg prp; - /* Constant/immediate/absolute value. */ - long constant; - /* CC code. */ - unsigned int cc; - /* Scaled index mode. */ - unsigned int scale; - /* Argument type. */ - argtype type; - /* Size of the argument (in bits) required to represent. */ - int size; - /* The type of the expression. */ - unsigned char X_op; -} -argument; - -/* Internal structure to hold the various entities - corresponding to the current assembling instruction. */ - -typedef struct -{ - /* Number of arguments. */ - int nargs; - /* The argument data structure for storing args (operands). */ - argument arg[MAX_OPERANDS]; -/* The following fields are required only by CR16-assembler. */ -#ifdef TC_CR16 - /* Expression used for setting the fixups (if any). */ - expressionS exp; - bfd_reloc_code_real_type rtype; -#endif /* TC_CR16 */ - /* Instruction size (in bytes). */ - int size; -} -ins; - -/* Structure to hold information about predefined operands. */ - -typedef struct -{ - /* Size (in bits). */ - unsigned int bit_size; - /* Argument type. */ - argtype arg_type; - /* One bit syntax flags. */ - int flags; -} -operand_entry; - -/* Structure to hold trap handler information. */ - -typedef struct -{ - /* Trap name. */ - char *name; - /* Index in dispatch table. */ - unsigned int entry; -} -trap_entry; - -/* Structure to hold information about predefined registers. */ - -typedef struct -{ - /* Name (string representation). */ - char *name; - /* Value (enum representation). */ - union - { - /* Register. */ - reg reg_val; - /* processor register. */ - preg preg_val; - } value; - /* Register image. */ - int image; - /* Register type. */ - reg_type type; -} -reg_entry; - -/* CR16 opcode table. */ -extern const inst cr16_instruction[]; -extern const unsigned int cr16_num_opcodes; -#define NUMOPCODES cr16_num_opcodes - -/* CR16 operands table. */ -extern const operand_entry cr16_optab[]; -extern const unsigned int cr16_num_optab; - -/* CR16 registers table. */ -extern const reg_entry cr16_regtab[]; -extern const unsigned int cr16_num_regs; -#define NUMREGS cr16_num_regs - -/* CR16 register pair table. */ -extern const reg_entry cr16_regptab[]; -extern const unsigned int cr16_num_regps; -#define NUMREGPS cr16_num_regps - -/* CR16 processor registers table. */ -extern const reg_entry cr16_pregtab[]; -extern const unsigned int cr16_num_pregs; -#define NUMPREGS cr16_num_pregs - -/* CR16 processor registers - 32 bit table. */ -extern const reg_entry cr16_pregptab[]; -extern const unsigned int cr16_num_pregps; -#define NUMPREGPS cr16_num_pregps - -/* CR16 trap/interrupt table. */ -extern const trap_entry cr16_traps[]; -extern const unsigned int cr16_num_traps; -#define NUMTRAPS cr16_num_traps - -/* CR16 CC - codes bit table. */ -extern const char * cr16_b_cond_tab[]; -extern const unsigned int cr16_num_cc; -#define NUMCC cr16_num_cc; - - -/* Table of instructions with no operands. */ -extern const char * cr16_no_op_insn[]; - -/* Current instruction we're assembling. */ -extern const inst *instruction; - -/* A macro for representing the instruction "constant" opcode, that is, - the FIXED part of the instruction. The "constant" opcode is represented - as a 32-bit unsigned long, where OPC is expanded (by a left SHIFT) - over that range. */ -#define BIN(OPC,SHIFT) (OPC << SHIFT) - -/* Is the current instruction type is TYPE ? */ -#define IS_INSN_TYPE(TYPE) \ - (CR16_INS_TYPE (instruction->flags) == TYPE) - -/* Is the current instruction mnemonic is MNEMONIC ? */ -#define IS_INSN_MNEMONIC(MNEMONIC) \ - (strcmp (instruction->mnemonic, MNEMONIC) == 0) - -/* Does the current instruction has register list ? */ -#define INST_HAS_REG_LIST \ - (instruction->flags & REG_LIST) - - -/* Utility macros for string comparison. */ -#define streq(a, b) (strcmp (a, b) == 0) -#define strneq(a, b, c) (strncmp (a, b, c) == 0) - -/* Long long type handling. */ -/* Replace all appearances of 'long long int' with LONGLONG. */ -typedef long long int LONGLONG; -typedef unsigned long long ULONGLONG; - -/* Data types for opcode handling. */ -typedef unsigned long dwordU; -typedef unsigned short wordU; - -/* Globals to store opcode data and build the instruction. */ -extern wordU cr16_words[3]; -extern ULONGLONG cr16_allWords; -extern ins cr16_currInsn; - -/* Prototypes for function in cr16-dis.c. */ -extern void cr16_make_instruction (void); -extern int cr16_match_opcode (void); - -#endif /* _CR16_H_ */ diff --git a/include/opcode/cris.h b/include/opcode/cris.h deleted file mode 100644 index e57a882..0000000 --- a/include/opcode/cris.h +++ /dev/null @@ -1,367 +0,0 @@ -/* cris.h -- Header file for CRIS opcode and register tables. - Copyright (C) 2000, 2001, 2004, 2010 Free Software Foundation, Inc. - Contributed by Axis Communications AB, Lund, Sweden. - Originally written for GAS 1.38.1 by Mikael Asker. - Updated, BFDized and GNUified by Hans-Peter Nilsson. - - This file is part of GAS, GDB and the GNU binutils. - - GAS, GDB, and GNU binutils is free software; you can redistribute it - and/or modify it under the terms of the GNU General Public License as - published by the Free Software Foundation; either version 3, or (at your - option) any later version. - - GAS, GDB, and GNU binutils are distributed in the hope that they will be - useful, but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, - MA 02110-1301, USA. */ - -#ifndef __CRIS_H_INCLUDED_ -#define __CRIS_H_INCLUDED_ - -#if !defined(__STDC__) && !defined(const) -#define const -#endif - - -/* Registers. */ -#define MAX_REG (15) -#define REG_SP (14) -#define REG_PC (15) - -/* CPU version control of disassembly and assembly of instructions. - May affect how the instruction is assembled, at least the size of - immediate operands. */ -enum cris_insn_version_usage -{ - /* Any version. */ - cris_ver_version_all=0, - - /* Indeterminate (intended for disassembly only, or obsolete). */ - cris_ver_warning, - - /* Only for v0..3 (Etrax 1..4). */ - cris_ver_v0_3, - - /* Only for v3 or higher (ETRAX 4 and beyond). */ - cris_ver_v3p, - - /* Only for v8 (Etrax 100). */ - cris_ver_v8, - - /* Only for v8 or higher (ETRAX 100, ETRAX 100 LX). */ - cris_ver_v8p, - - /* Only for v0..10. FIXME: Not sure what to do with this. */ - cris_ver_sim_v0_10, - - /* Only for v0..10. */ - cris_ver_v0_10, - - /* Only for v3..10. (ETRAX 4, ETRAX 100 and ETRAX 100 LX). */ - cris_ver_v3_10, - - /* Only for v8..10 (ETRAX 100 and ETRAX 100 LX). */ - cris_ver_v8_10, - - /* Only for v10 (ETRAX 100 LX) and same series. */ - cris_ver_v10, - - /* Only for v10 (ETRAX 100 LX) and same series. */ - cris_ver_v10p, - - /* Only for v32 or higher (codename GUINNESS). - Of course some or all these of may change to cris_ver_v32p if/when - there's a new revision. */ - cris_ver_v32p -}; - - -/* Special registers. */ -struct cris_spec_reg -{ - const char *const name; - unsigned int number; - - /* The size of the register. */ - unsigned int reg_size; - - /* What CPU version the special register of that name is implemented - in. If cris_ver_warning, emit an unimplemented-warning. */ - enum cris_insn_version_usage applicable_version; - - /* There might be a specific warning for using a special register - here. */ - const char *const warning; -}; -extern const struct cris_spec_reg cris_spec_regs[]; - - -/* Support registers (kind of special too, but not named as such). */ -struct cris_support_reg -{ - const char *const name; - unsigned int number; -}; -extern const struct cris_support_reg cris_support_regs[]; - -struct cris_cond15 -{ - /* The name of the condition. */ - const char *const name; - - /* What CPU version this condition name applies to. */ - enum cris_insn_version_usage applicable_version; -}; -extern const struct cris_cond15 cris_conds15[]; - -/* Opcode-dependent constants. */ -#define AUTOINCR_BIT (0x04) - -/* Prefixes. */ -#define BDAP_QUICK_OPCODE (0x0100) -#define BDAP_QUICK_Z_BITS (0x0e00) - -#define BIAP_OPCODE (0x0540) -#define BIAP_Z_BITS (0x0a80) - -#define DIP_OPCODE (0x0970) -#define DIP_Z_BITS (0xf280) - -#define BDAP_INDIR_LOW (0x40) -#define BDAP_INDIR_LOW_Z (0x80) -#define BDAP_INDIR_HIGH (0x09) -#define BDAP_INDIR_HIGH_Z (0x02) - -#define BDAP_INDIR_OPCODE (BDAP_INDIR_HIGH * 0x0100 + BDAP_INDIR_LOW) -#define BDAP_INDIR_Z_BITS (BDAP_INDIR_HIGH_Z * 0x100 + BDAP_INDIR_LOW_Z) -#define BDAP_PC_LOW (BDAP_INDIR_LOW + REG_PC) -#define BDAP_INCR_HIGH (BDAP_INDIR_HIGH + AUTOINCR_BIT) - -/* No prefix must have this code for its "match" bits in the - opcode-table. "BCC .+2" will do nicely. */ -#define NO_CRIS_PREFIX 0 - -/* Definitions for condition codes. */ -#define CC_CC 0x0 -#define CC_HS 0x0 -#define CC_CS 0x1 -#define CC_LO 0x1 -#define CC_NE 0x2 -#define CC_EQ 0x3 -#define CC_VC 0x4 -#define CC_VS 0x5 -#define CC_PL 0x6 -#define CC_MI 0x7 -#define CC_LS 0x8 -#define CC_HI 0x9 -#define CC_GE 0xA -#define CC_LT 0xB -#define CC_GT 0xC -#define CC_LE 0xD -#define CC_A 0xE -#define CC_EXT 0xF - -/* A table of strings "cc", "cs"... indexed with condition code - values as above. */ -extern const char *const cris_cc_strings[]; - -/* Bcc quick. */ -#define BRANCH_QUICK_LOW (0) -#define BRANCH_QUICK_HIGH (0) -#define BRANCH_QUICK_OPCODE (BRANCH_QUICK_HIGH * 0x0100 + BRANCH_QUICK_LOW) -#define BRANCH_QUICK_Z_BITS (0x0F00) - -/* BA quick. */ -#define BA_QUICK_HIGH (BRANCH_QUICK_HIGH + CC_A * 0x10) -#define BA_QUICK_OPCODE (BA_QUICK_HIGH * 0x100 + BRANCH_QUICK_LOW) - -/* Bcc [PC+]. */ -#define BRANCH_PC_LOW (0xFF) -#define BRANCH_INCR_HIGH (0x0D) -#define BA_PC_INCR_OPCODE \ - ((BRANCH_INCR_HIGH + CC_A * 0x10) * 0x0100 + BRANCH_PC_LOW) - -/* Jump. */ -/* Note that old versions generated special register 8 (in high bits) - and not-that-old versions recognized it as a jump-instruction. - That opcode now belongs to JUMPU. */ -#define JUMP_INDIR_OPCODE (0x0930) -#define JUMP_INDIR_Z_BITS (0xf2c0) -#define JUMP_PC_INCR_OPCODE \ - (JUMP_INDIR_OPCODE + AUTOINCR_BIT * 0x0100 + REG_PC) - -#define MOVE_M_TO_PREG_OPCODE 0x0a30 -#define MOVE_M_TO_PREG_ZBITS 0x01c0 - -/* BDAP.D N,PC. */ -#define MOVE_PC_INCR_OPCODE_PREFIX \ - (((BDAP_INCR_HIGH | (REG_PC << 4)) << 8) | BDAP_PC_LOW | (2 << 4)) -#define MOVE_PC_INCR_OPCODE_SUFFIX \ - (MOVE_M_TO_PREG_OPCODE | REG_PC | (AUTOINCR_BIT << 8)) - -#define JUMP_PC_INCR_OPCODE_V32 (0x0DBF) - -/* BA DWORD (V32). */ -#define BA_DWORD_OPCODE (0x0EBF) - -/* Nop. */ -#define NOP_OPCODE (0x050F) -#define NOP_Z_BITS (0xFFFF ^ NOP_OPCODE) - -#define NOP_OPCODE_V32 (0x05B0) -#define NOP_Z_BITS_V32 (0xFFFF ^ NOP_OPCODE_V32) - -/* For the compatibility mode, let's use "MOVE R0,P0". Doesn't affect - registers or flags. Unfortunately shuts off interrupts for one cycle - for < v32, but there doesn't seem to be any alternative without that - effect. */ -#define NOP_OPCODE_COMMON (0x630) -#define NOP_OPCODE_ZBITS_COMMON (0xffff & ~NOP_OPCODE_COMMON) - -/* LAPC.D */ -#define LAPC_DWORD_OPCODE (0x0D7F) -#define LAPC_DWORD_Z_BITS (0x0fff & ~LAPC_DWORD_OPCODE) - -/* Structure of an opcode table entry. */ -enum cris_imm_oprnd_size_type -{ - /* No size is applicable. */ - SIZE_NONE, - - /* Always 32 bits. */ - SIZE_FIX_32, - - /* Indicated by size of special register. */ - SIZE_SPEC_REG, - - /* Indicated by size field, signed. */ - SIZE_FIELD_SIGNED, - - /* Indicated by size field, unsigned. */ - SIZE_FIELD_UNSIGNED, - - /* Indicated by size field, no sign implied. */ - SIZE_FIELD -}; - -/* For GDB. FIXME: Is this the best way to handle opcode - interpretation? */ -enum cris_op_type -{ - cris_not_implemented_op = 0, - cris_abs_op, - cris_addi_op, - cris_asr_op, - cris_asrq_op, - cris_ax_ei_setf_op, - cris_bdap_prefix, - cris_biap_prefix, - cris_break_op, - cris_btst_nop_op, - cris_clearf_di_op, - cris_dip_prefix, - cris_dstep_logshift_mstep_neg_not_op, - cris_eight_bit_offset_branch_op, - cris_move_mem_to_reg_movem_op, - cris_move_reg_to_mem_movem_op, - cris_move_to_preg_op, - cris_muls_op, - cris_mulu_op, - cris_none_reg_mode_add_sub_cmp_and_or_move_op, - cris_none_reg_mode_clear_test_op, - cris_none_reg_mode_jump_op, - cris_none_reg_mode_move_from_preg_op, - cris_quick_mode_add_sub_op, - cris_quick_mode_and_cmp_move_or_op, - cris_quick_mode_bdap_prefix, - cris_reg_mode_add_sub_cmp_and_or_move_op, - cris_reg_mode_clear_op, - cris_reg_mode_jump_op, - cris_reg_mode_move_from_preg_op, - cris_reg_mode_test_op, - cris_scc_op, - cris_sixteen_bit_offset_branch_op, - cris_three_operand_add_sub_cmp_and_or_op, - cris_three_operand_bound_op, - cris_two_operand_bound_op, - cris_xor_op -}; - -struct cris_opcode -{ - /* The name of the insn. */ - const char *name; - - /* Bits that must be 1 for a match. */ - unsigned int match; - - /* Bits that must be 0 for a match. */ - unsigned int lose; - - /* See the table in "opcodes/cris-opc.c". */ - const char *args; - - /* Nonzero if this is a delayed branch instruction. */ - char delayed; - - /* Size of immediate operands. */ - enum cris_imm_oprnd_size_type imm_oprnd_size; - - /* Indicates which version this insn was first implemented in. */ - enum cris_insn_version_usage applicable_version; - - /* What kind of operation this is. */ - enum cris_op_type op; -}; -extern const struct cris_opcode cris_opcodes[]; - - -/* These macros are for the target-specific flags in disassemble_info - used at disassembly. */ - -/* This insn accesses memory. This flag is more trustworthy than - checking insn_type for "dis_dref" which does not work for - e.g. "JSR [foo]". */ -#define CRIS_DIS_FLAG_MEMREF (1 << 0) - -/* The "target" field holds a register number. */ -#define CRIS_DIS_FLAG_MEM_TARGET_IS_REG (1 << 1) - -/* The "target2" field holds a register number; add it to "target". */ -#define CRIS_DIS_FLAG_MEM_TARGET2_IS_REG (1 << 2) - -/* Yet another add-on: the register in "target2" must be multiplied - by 2 before adding to "target". */ -#define CRIS_DIS_FLAG_MEM_TARGET2_MULT2 (1 << 3) - -/* Yet another add-on: the register in "target2" must be multiplied - by 4 (mutually exclusive with .._MULT2). */ -#define CRIS_DIS_FLAG_MEM_TARGET2_MULT4 (1 << 4) - -/* The register in "target2" is an indirect memory reference (of the - register there), add to "target". Assumed size is dword (mutually - exclusive with .._MULT[24]). */ -#define CRIS_DIS_FLAG_MEM_TARGET2_MEM (1 << 5) - -/* Add-on to CRIS_DIS_FLAG_MEM_TARGET2_MEM; the memory access is "byte"; - sign-extended before adding to "target". */ -#define CRIS_DIS_FLAG_MEM_TARGET2_MEM_BYTE (1 << 6) - -/* Add-on to CRIS_DIS_FLAG_MEM_TARGET2_MEM; the memory access is "word"; - sign-extended before adding to "target". */ -#define CRIS_DIS_FLAG_MEM_TARGET2_MEM_WORD (1 << 7) - -#endif /* __CRIS_H_INCLUDED_ */ - -/* - * Local variables: - * eval: (c-set-style "gnu") - * indent-tabs-mode: t - * End: - */ diff --git a/include/opcode/crx.h b/include/opcode/crx.h deleted file mode 100644 index 6081ea3..0000000 --- a/include/opcode/crx.h +++ /dev/null @@ -1,419 +0,0 @@ -/* crx.h -- Header file for CRX opcode and register tables. - Copyright 2004, 2010, 2012 Free Software Foundation, Inc. - Contributed by Tomer Levi, NSC, Israel. - Originally written for GAS 2.12 by Tomer Levi, NSC, Israel. - Updates, BFDizing, GNUifying and ELF support by Tomer Levi. - - This file is part of GAS, GDB and the GNU binutils. - - GAS, GDB, and GNU binutils is free software; you can redistribute it - and/or modify it under the terms of the GNU General Public License as - published by the Free Software Foundation; either version 3, or (at your - option) any later version. - - GAS, GDB, and GNU binutils are distributed in the hope that they will be - useful, but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, - MA 02110-1301, USA. */ - -#ifndef _CRX_H_ -#define _CRX_H_ - -/* CRX core/debug Registers : - The enums are used as indices to CRX registers table (crx_regtab). - Therefore, order MUST be preserved. */ - -typedef enum - { - /* 32-bit general purpose registers. */ - r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, - r10, r11, r12, r13, r14, r15, ra, sp, - /* 32-bit user registers. */ - u0, u1, u2, u3, u4, u5, u6, u7, u8, u9, - u10, u11, u12, u13, u14, u15, ura, usp, - /* hi and lo registers. */ - hi, lo, - /* hi and lo user registers. */ - uhi, ulo, - /* Processor Status Register. */ - psr, - /* Interrupt Base Register. */ - intbase, - /* Interrupt Stack Pointer Register. */ - isp, - /* Configuration Register. */ - cfg, - /* Coprocessor Configuration Register. */ - cpcfg, - /* Coprocessor Enable Register. */ - cen, - /* Not a register. */ - nullregister, - MAX_REG - } -reg; - -/* CRX Coprocessor registers and special registers : - The enums are used as indices to CRX coprocessor registers table - (crx_copregtab). Therefore, order MUST be preserved. */ - -typedef enum - { - /* Coprocessor registers. */ - c0 = MAX_REG, c1, c2, c3, c4, c5, c6, c7, c8, - c9, c10, c11, c12, c13, c14, c15, - /* Coprocessor special registers. */ - cs0, cs1 ,cs2, cs3, cs4, cs5, cs6, cs7, cs8, - cs9, cs10, cs11, cs12, cs13, cs14, cs15, - /* Not a Coprocessor register. */ - nullcopregister, - MAX_COPREG - } -copreg; - -/* CRX Register types. */ - -typedef enum - { - CRX_R_REGTYPE, /* r<N> */ - CRX_U_REGTYPE, /* u<N> */ - CRX_C_REGTYPE, /* c<N> */ - CRX_CS_REGTYPE, /* cs<N> */ - CRX_CFG_REGTYPE /* configuration register */ - } -reg_type; - -/* CRX argument types : - The argument types correspond to instructions operands - - Argument types : - r - register - c - constant - i - immediate - idxr - index register - rbase - register base - s - star ('*') - copr - coprocessor register - copsr - coprocessor special register. */ - -typedef enum - { - arg_r, arg_c, arg_cr, arg_ic, arg_icr, arg_sc, - arg_idxr, arg_rbase, arg_copr, arg_copsr, - /* Not an argument. */ - nullargs - } -argtype; - -/* CRX operand types : - The operand types correspond to instructions operands. */ - -typedef enum - { - dummy, - /* 4-bit encoded constant. */ - cst4, - /* N-bit immediate. */ - i16, i32, - /* N-bit unsigned immediate. */ - ui3, ui4, ui5, ui16, - /* N-bit signed displacement. */ - disps9, disps17, disps25, disps32, - /* N-bit unsigned displacement. */ - dispu5, - /* N-bit escaped displacement. */ - dispe9, - /* N-bit absolute address. */ - abs16, abs32, - /* Register relative. */ - rbase, rbase_dispu4, - rbase_disps12, rbase_disps16, rbase_disps28, rbase_disps32, - /* Register index. */ - rindex_disps6, rindex_disps22, - /* 4-bit genaral-purpose register specifier. */ - regr, - /* 8-bit register address space. */ - regr8, - /* coprocessor register. */ - copregr, - /* coprocessor special register. */ - copsregr, - /* Not an operand. */ - nulloperand, - /* Maximum supported operand. */ - MAX_OPRD - } -operand_type; - -/* CRX instruction types. */ - -#define NO_TYPE_INS 0 -#define ARITH_INS 1 -#define LD_STOR_INS 2 -#define BRANCH_INS 3 -#define ARITH_BYTE_INS 4 -#define CMPBR_INS 5 -#define SHIFT_INS 6 -#define BRANCH_NEQ_INS 7 -#define LD_STOR_INS_INC 8 -#define STOR_IMM_INS 9 -#define CSTBIT_INS 10 -#define COP_BRANCH_INS 11 -#define COP_REG_INS 12 -#define COPS_REG_INS 13 -#define DCR_BRANCH_INS 14 - -/* Maximum value supported for instruction types. */ -#define CRX_INS_MAX (1 << 4) -/* Mask to record an instruction type. */ -#define CRX_INS_MASK (CRX_INS_MAX - 1) -/* Return instruction type, given instruction's attributes. */ -#define CRX_INS_TYPE(attr) ((attr) & CRX_INS_MASK) - -/* Indicates whether this instruction has a register list as parameter. */ -#define REG_LIST CRX_INS_MAX -/* The operands in binary and assembly are placed in reverse order. - load - (REVERSE_MATCH)/store - (! REVERSE_MATCH). */ -#define REVERSE_MATCH (1 << 5) - -/* Kind of displacement map used DISPU[BWD]4. */ -#define DISPUB4 (1 << 6) -#define DISPUW4 (1 << 7) -#define DISPUD4 (1 << 8) -#define DISPU4MAP (DISPUB4 | DISPUW4 | DISPUD4) - -/* Printing formats, where the instruction prefix isn't consecutive. */ -#define FMT_1 (1 << 9) /* 0xF0F00000 */ -#define FMT_2 (1 << 10) /* 0xFFF0FF00 */ -#define FMT_3 (1 << 11) /* 0xFFF00F00 */ -#define FMT_4 (1 << 12) /* 0xFFF0F000 */ -#define FMT_5 (1 << 13) /* 0xFFF0FFF0 */ -#define FMT_CRX (FMT_1 | FMT_2 | FMT_3 | FMT_4 | FMT_5) - -/* Indicates whether this instruction can be relaxed. */ -#define RELAXABLE (1 << 14) - -/* Indicates that instruction uses user registers (and not - general-purpose registers) as operands. */ -#define USER_REG (1 << 15) - -/* Indicates that instruction can perfom a cst4 mapping. */ -#define CST4MAP (1 << 16) - -/* Instruction shouldn't allow 'sp' usage. */ -#define NO_SP (1 << 17) - -/* Instruction shouldn't allow to push a register which is used as a rptr. */ -#define NO_RPTR (1 << 18) - -/* Maximum operands per instruction. */ -#define MAX_OPERANDS 5 -/* Maximum register name length. */ -#define MAX_REGNAME_LEN 10 -/* Maximum instruction length. */ -#define MAX_INST_LEN 256 - - -/* Values defined for the flags field of a struct operand_entry. */ - -/* Operand must be an unsigned number. */ -#define OP_UNSIGNED (1 << 0) -/* Operand must be a signed number. */ -#define OP_SIGNED (1 << 1) -/* A special arithmetic 4-bit constant operand. */ -#define OP_CST4 (1 << 2) -/* A special load/stor 4-bit unsigned displacement operand. */ -#define OP_DISPU4 (1 << 3) -/* Operand must be an even number. */ -#define OP_EVEN (1 << 4) -/* Operand is shifted right. */ -#define OP_SHIFT (1 << 5) -/* Operand is shifted right and decremented. */ -#define OP_SHIFT_DEC (1 << 6) -/* Operand has reserved escape sequences. */ -#define OP_ESC (1 << 7) -/* Operand is used only for the upper 64 KB (FFFF0000 to FFFFFFFF). */ -#define OP_UPPER_64KB (1 << 8) - -/* Single operand description. */ - -typedef struct - { - /* Operand type. */ - operand_type op_type; - /* Operand location within the opcode. */ - unsigned int shift; - } -operand_desc; - -/* Instruction data structure used in instruction table. */ - -typedef struct - { - /* Name. */ - const char *mnemonic; - /* Size (in words). */ - unsigned int size; - /* Constant prefix (matched by the disassembler). */ - unsigned long match; - /* Match size (in bits). */ - int match_bits; - /* Attributes. */ - unsigned int flags; - /* Operands (always last, so unreferenced operands are initialized). */ - operand_desc operands[MAX_OPERANDS]; - } -inst; - -/* Data structure for a single instruction's arguments (Operands). */ - -typedef struct - { - /* Register or base register. */ - reg r; - /* Index register. */ - reg i_r; - /* Coprocessor register. */ - copreg cr; - /* Constant/immediate/absolute value. */ - long constant; - /* Scaled index mode. */ - unsigned int scale; - /* Argument type. */ - argtype type; - /* Size of the argument (in bits) required to represent. */ - int size; - /* The type of the expression. */ - unsigned char X_op; - } -argument; - -/* Internal structure to hold the various entities - corresponding to the current assembling instruction. */ - -typedef struct - { - /* Number of arguments. */ - int nargs; - /* The argument data structure for storing args (operands). */ - argument arg[MAX_OPERANDS]; -/* The following fields are required only by CRX-assembler. */ -#ifdef TC_CRX - /* Expression used for setting the fixups (if any). */ - expressionS exp; - bfd_reloc_code_real_type rtype; -#endif /* TC_CRX */ - /* Instruction size (in bytes). */ - int size; - } -ins; - -/* Structure to hold information about predefined operands. */ - -typedef struct - { - /* Size (in bits). */ - unsigned int bit_size; - /* Argument type. */ - argtype arg_type; - /* One bit syntax flags. */ - int flags; - } -operand_entry; - -/* Structure to hold trap handler information. */ - -typedef struct - { - /* Trap name. */ - char *name; - /* Index in dispatch table. */ - unsigned int entry; - } -trap_entry; - -/* Structure to hold information about predefined registers. */ - -typedef struct - { - /* Name (string representation). */ - char *name; - /* Value (enum representation). */ - union - { - /* Register. */ - reg reg_val; - /* Coprocessor register. */ - copreg copreg_val; - } value; - /* Register image. */ - int image; - /* Register type. */ - reg_type type; - } -reg_entry; - -/* Structure to hold a cst4 operand mapping. */ - -/* CRX opcode table. */ -extern const inst crx_instruction[]; -extern const int crx_num_opcodes; -#define NUMOPCODES crx_num_opcodes - -/* CRX operands table. */ -extern const operand_entry crx_optab[]; - -/* CRX registers table. */ -extern const reg_entry crx_regtab[]; -extern const int crx_num_regs; -#define NUMREGS crx_num_regs - -/* CRX coprocessor registers table. */ -extern const reg_entry crx_copregtab[]; -extern const int crx_num_copregs; -#define NUMCOPREGS crx_num_copregs - -/* CRX trap/interrupt table. */ -extern const trap_entry crx_traps[]; -extern const int crx_num_traps; -#define NUMTRAPS crx_num_traps - -/* cst4 operand mapping. */ -extern const int cst4_map[]; -extern const int cst4_maps; - -/* Table of instructions with no operands. */ -extern const char* no_op_insn[]; - -/* Current instruction we're assembling. */ -extern const inst *instruction; - -/* A macro for representing the instruction "constant" opcode, that is, - the FIXED part of the instruction. The "constant" opcode is represented - as a 32-bit unsigned long, where OPC is expanded (by a left SHIFT) - over that range. */ -#define BIN(OPC,SHIFT) (OPC << SHIFT) - -/* Is the current instruction type is TYPE ? */ -#define IS_INSN_TYPE(TYPE) \ - (CRX_INS_TYPE(instruction->flags) == TYPE) - -/* Is the current instruction mnemonic is MNEMONIC ? */ -#define IS_INSN_MNEMONIC(MNEMONIC) \ - (strcmp(instruction->mnemonic,MNEMONIC) == 0) - -/* Does the current instruction has register list ? */ -#define INST_HAS_REG_LIST \ - (instruction->flags & REG_LIST) - -/* Long long type handling. */ -/* Replace all appearances of 'long long int' with LONGLONG. */ -typedef long long int LONGLONG; -typedef unsigned long long ULONGLONG; - -#endif /* _CRX_H_ */ diff --git a/include/opcode/d10v.h b/include/opcode/d10v.h deleted file mode 100644 index d0e115f..0000000 --- a/include/opcode/d10v.h +++ /dev/null @@ -1,209 +0,0 @@ -/* d10v.h -- Header file for D10V opcode table - Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2003, 2010 - Free Software Foundation, Inc. - Written by Martin Hunt (hunt@cygnus.com), Cygnus Support - - This file is part of GDB, GAS, and the GNU binutils. - - GDB, GAS, and the GNU binutils are free software; you can redistribute - them and/or modify them under the terms of the GNU General Public - License as published by the Free Software Foundation; either version 3, - or (at your option) any later version. - - GDB, GAS, and the GNU binutils are distributed in the hope that they - will be useful, but WITHOUT ANY WARRANTY; without even the implied - warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See - the GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this file; see the file COPYING3. If not, write to the Free - Software Foundation, 51 Franklin Street - Fifth Floor, Boston, - MA 02110-1301, USA. */ - -#ifndef D10V_H -#define D10V_H - -/* Format Specifier */ -#define FM00 0 -#define FM01 0x40000000 -#define FM10 0x80000000 -#define FM11 0xC0000000 - -#define NOP 0x5e00 -#define OPCODE_DIVS 0x14002800 - -/* The opcode table is an array of struct d10v_opcode. */ - -struct d10v_opcode -{ - /* The opcode name. */ - const char *name; - - /* the opcode format */ - int format; - - /* These numbers were picked so we can do if( i & SHORT_OPCODE) */ -#define SHORT_OPCODE 1 -#define LONG_OPCODE 8 -#define SHORT_2 1 /* short with 2 operands */ -#define SHORT_B 3 /* short with 8-bit branch */ -#define LONG_B 8 /* long with 16-bit branch */ -#define LONG_L 10 /* long with 3 operands */ -#define LONG_R 12 /* reserved */ - - /* just a placeholder for variable-length instructions */ - /* for example, "bra" will be a fake for "bra.s" and bra.l" */ - /* which will immediately follow in the opcode table. */ -#define OPCODE_FAKE 32 - - /* the number of cycles */ - int cycles; - - /* the execution unit(s) used */ - int unit; -#define EITHER 0 -#define IU 1 -#define MU 2 -#define BOTH 3 - - /* execution type; parallel or sequential */ - /* this field is used to decide if two instructions */ - /* can be executed in parallel */ - int exec_type; -#define PARONLY 1 /* parallel only */ -#define SEQ 2 /* must be sequential */ -#define PAR 4 /* may be parallel */ -#define BRANCH_LINK 8 /* subroutine call. must be aligned */ -#define RMEM 16 /* reads memory */ -#define WMEM 32 /* writes memory */ -#define RF0 64 /* reads f0 */ -#define WF0 128 /* modifies f0 */ -#define WCAR 256 /* write Carry */ -#define BRANCH 512 /* branch, no link */ -#define ALONE 1024 /* short but pack with a NOP if on asm line alone */ - - /* the opcode */ - long opcode; - - /* mask. if( (i & mask) == opcode ) then match */ - long mask; - - /* An array of operand codes. Each code is an index into the - operand table. They appear in the order which the operands must - appear in assembly code, and are terminated by a zero. */ - unsigned char operands[6]; -}; - -/* The table itself is sorted by major opcode number, and is otherwise - in the order in which the disassembler should consider - instructions. */ -extern const struct d10v_opcode d10v_opcodes[]; -extern const int d10v_num_opcodes; - -/* The operands table is an array of struct d10v_operand. */ -struct d10v_operand -{ - /* The number of bits in the operand. */ - int bits; - - /* How far the operand is left shifted in the instruction. */ - int shift; - - /* One bit syntax flags. */ - int flags; -}; - -/* Elements in the table are retrieved by indexing with values from - the operands field of the d10v_opcodes table. */ - -extern const struct d10v_operand d10v_operands[]; - -/* Values defined for the flags field of a struct d10v_operand. */ - -/* the operand must be an even number */ -#define OPERAND_EVEN (1) - -/* the operand must be an odd number */ -#define OPERAND_ODD (2) - -/* this is the destination register; it will be modified */ -/* this is used by the optimizer */ -#define OPERAND_DEST (4) - -/* number or symbol */ -#define OPERAND_NUM (8) - -/* address or label */ -#define OPERAND_ADDR (0x10) - -/* register */ -#define OPERAND_REG (0x20) - -/* postincrement + */ -#define OPERAND_PLUS (0x40) - -/* postdecrement - */ -#define OPERAND_MINUS (0x80) - -/* @ */ -#define OPERAND_ATSIGN (0x100) - -/* @( */ -#define OPERAND_ATPAR (0x200) - -/* accumulator 0 */ -#define OPERAND_ACC0 (0x400) - -/* accumulator 1 */ -#define OPERAND_ACC1 (0x800) - -/* f0 / f1 flag register */ -#define OPERAND_FFLAG (0x1000) - -/* c flag register */ -#define OPERAND_CFLAG (0x2000) - -/* control register */ -#define OPERAND_CONTROL (0x4000) - -/* predecrement mode '@-sp' */ -#define OPERAND_ATMINUS (0x8000) - -/* signed number */ -#define OPERAND_SIGNED (0x10000) - -/* special accumulator shifts need a 4-bit number */ -/* 1 <= x <= 16 */ -#define OPERAND_SHIFT (0x20000) - -/* general purpose register */ -#define OPERAND_GPR (0x40000) - -/* special imm3 values with range restricted to -2 <= imm3 <= 3 */ -/* needed for rac/rachi */ -#define RESTRICTED_NUM3 (0x80000) - -/* Pre-decrement is only supported for SP. */ -#define OPERAND_SP (0x100000) - -/* Post-decrement is not supported for SP. Like OPERAND_EVEN, and - unlike OPERAND_SP, this flag doesn't prevent the instruction from - matching, it only fails validation later on. */ -#define OPERAND_NOSP (0x200000) - -/* Structure to hold information about predefined registers. */ -struct pd_reg -{ - char *name; /* name to recognize */ - char *pname; /* name to print for this register */ - int value; -}; - -extern const struct pd_reg d10v_predefined_registers[]; -int d10v_reg_name_cnt (void); - -/* an expressionS only has one register type, so we fake it */ -/* by setting high bits to indicate type */ -#define REGISTER_MASK 0xFF - -#endif /* D10V_H */ diff --git a/include/opcode/d30v.h b/include/opcode/d30v.h deleted file mode 100644 index 62c041d..0000000 --- a/include/opcode/d30v.h +++ /dev/null @@ -1,288 +0,0 @@ -/* d30v.h -- Header file for D30V opcode table - Copyright 1997, 1998, 1999, 2000, 2001, 2003, 2010 - Free Software Foundation, Inc. - Written by Martin Hunt (hunt@cygnus.com), Cygnus Solutions - - This file is part of GDB, GAS, and the GNU binutils. - - GDB, GAS, and the GNU binutils are free software; you can redistribute - them and/or modify them under the terms of the GNU General Public - License as published by the Free Software Foundation; either version 3, - or (at your option) any later version. - - GDB, GAS, and the GNU binutils are distributed in the hope that they - will be useful, but WITHOUT ANY WARRANTY; without even the implied - warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See - the GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this file; see the file COPYING3. If not, write to the Free - Software Foundation, 51 Franklin Street - Fifth Floor, Boston, - MA 02110-1301, USA. */ - -#ifndef D30V_H -#define D30V_H - -#define NOP 0x00F00000 - -/* Structure to hold information about predefined registers. */ -struct pd_reg -{ - char *name; /* name to recognize */ - char *pname; /* name to print for this register */ - int value; -}; - -extern const struct pd_reg pre_defined_registers[]; -int reg_name_cnt (void); - -/* the number of control registers */ -#define MAX_CONTROL_REG 64 - -/* define the format specifiers */ -#define FM00 0 -#define FM01 0x80000000 -#define FM10 0x8000000000000000LL -#define FM11 0x8000000080000000LL - -/* define the opcode classes */ -#define BRA 0 -#define LOGIC 1 -#define IMEM 2 -#define IALU1 4 -#define IALU2 5 - -/* define the execution condition codes */ -#define ECC_AL 0 /* ALways (default) */ -#define ECC_TX 1 /* F0=True, F1=Don't care */ -#define ECC_FX 2 /* F0=False, F1=Don't care */ -#define ECC_XT 3 /* F0=Don't care, F1=True */ -#define ECC_XF 4 /* F0=Don't care, F1=False */ -#define ECC_TT 5 /* F0=True, F1=True */ -#define ECC_TF 6 /* F0=True, F1=False */ -#define ECC_RESERVED 7 /* reserved */ -#define ECC_MAX ECC_RESERVED - -extern const char *d30v_ecc_names[]; - -/* condition code table for CMP and CMPU */ -extern const char *d30v_cc_names[]; - -/* The opcode table is an array of struct d30v_opcode. */ -struct d30v_opcode -{ - /* The opcode name. */ - const char *name; - - /* the opcode */ - int op1; /* first part, "IALU1" for example */ - int op2; /* the rest of the opcode */ - - /* opcode format(s). These numbers correspond to entries */ - /* in the d30v_format_table */ - unsigned char format[4]; - -#define SHORT_M 1 -#define SHORT_M2 5 /* for ld2w and st2w */ -#define SHORT_A 9 -#define SHORT_B1 11 -#define SHORT_B2 12 -#define SHORT_B2r 13 -#define SHORT_B3 14 -#define SHORT_B3r 16 -#define SHORT_B3b 18 -#define SHORT_B3br 20 -#define SHORT_D1r 22 -#define SHORT_D2 24 -#define SHORT_D2r 26 -#define SHORT_D2Br 28 -#define SHORT_U 30 /* unary SHORT_A. ABS for example */ -#define SHORT_F 31 /* SHORT_A with flag registers */ -#define SHORT_AF 33 /* SHORT_A with only the first register a flag register */ -#define SHORT_T 35 /* for trap instruction */ -#define SHORT_A5 36 /* SHORT_A with a 5-bit immediate instead of 6 */ -#define SHORT_CMP 38 /* special form for CMPcc */ -#define SHORT_CMPU 40 /* special form for CMPUcc */ -#define SHORT_A1 42 /* special form of SHORT_A for MACa opcodes where a=1 */ -#define SHORT_AA 44 /* SHORT_A with the first register an accumulator */ -#define SHORT_RA 46 /* SHORT_A with the second register an accumulator */ -#define SHORT_MODINC 48 -#define SHORT_MODDEC 49 -#define SHORT_C1 50 -#define SHORT_C2 51 -#define SHORT_UF 52 -#define SHORT_A2 53 -#define SHORT_NONE 55 /* no operands */ -#define SHORT_AR 56 /* like SHORT_AA but only accept register as third parameter */ -#define LONG 57 -#define LONG_U 58 /* unary LONG */ -#define LONG_Ur 59 /* LONG pc-relative */ -#define LONG_CMP 60 /* special form for CMPcc and CMPUcc */ -#define LONG_M 61 /* Memory long for ldb, stb */ -#define LONG_M2 62 /* Memory long for ld2w, st2w */ -#define LONG_2 63 /* LONG with 2 operands; jmptnz */ -#define LONG_2r 64 /* LONG with 2 operands; bratnz */ -#define LONG_2b 65 /* LONG_2 with modifier of 3 */ -#define LONG_2br 66 /* LONG_2r with modifier of 3 */ -#define LONG_D 67 /* for DJMPI */ -#define LONG_Dr 68 /* for DBRAI */ -#define LONG_Dbr 69 /* for repeati */ - - /* the execution unit(s) used */ - int unit; -#define EITHER 0 -#define IU 1 -#define MU 2 -#define EITHER_BUT_PREFER_MU 3 - - /* this field is used to decide if two instructions */ - /* can be executed in parallel */ - long flags_used; - long flags_set; -#define FLAG_0 (1L<<0) -#define FLAG_1 (1L<<1) -#define FLAG_2 (1L<<2) -#define FLAG_3 (1L<<3) -#define FLAG_4 (1L<<4) /* S (saturation) */ -#define FLAG_5 (1L<<5) /* V (overflow) */ -#define FLAG_6 (1L<<6) /* VA (accumulated overflow) */ -#define FLAG_7 (1L<<7) /* C (carry/borrow) */ -#define FLAG_SM (1L<<8) /* SM (stack mode) */ -#define FLAG_RP (1L<<9) /* RP (repeat enable) */ -#define FLAG_CONTROL (1L<<10) /* control registers */ -#define FLAG_A0 (1L<<11) /* A0 */ -#define FLAG_A1 (1L<<12) /* A1 */ -#define FLAG_JMP (1L<<13) /* instruction is a branch */ -#define FLAG_JSR (1L<<14) /* subroutine call. must be aligned */ -#define FLAG_MEM (1L<<15) /* reads/writes memory */ -#define FLAG_NOT_WITH_ADDSUBppp (1L<<16) /* Old meaning: a 2 word 4 byter operation - New meaning: operation cannot be - combined in parallel with ADD/SUBppp. */ -#define FLAG_MUL16 (1L<<17) /* 16 bit multiply */ -#define FLAG_MUL32 (1L<<18) /* 32 bit multiply */ -#define FLAG_ADDSUBppp (1L<<19) /* ADDppp or SUBppp */ -#define FLAG_DELAY (1L<<20) /* This is a delayed branch or jump */ -#define FLAG_LKR (1L<<21) /* insn in left slot kills right slot */ -#define FLAG_CVVA (FLAG_5|FLAG_6|FLAG_7) -#define FLAG_C FLAG_7 -#define FLAG_ALL (FLAG_0 | \ - FLAG_1 | \ - FLAG_2 | \ - FLAG_3 | \ - FLAG_4 | \ - FLAG_5 | \ - FLAG_6 | \ - FLAG_7 | \ - FLAG_SM | \ - FLAG_RP | \ - FLAG_CONTROL) - - int reloc_flag; -#define RELOC_PCREL 1 -#define RELOC_ABS 2 -}; - -extern const struct d30v_opcode d30v_opcode_table[]; -extern const int d30v_num_opcodes; - -/* The operands table is an array of struct d30v_operand. */ -struct d30v_operand -{ - /* the length of the field */ - int length; - - /* The number of significant bits in the operand. */ - int bits; - - /* position relative to Ra */ - int position; - - /* syntax flags. */ - long flags; -}; -extern const struct d30v_operand d30v_operand_table[]; - -/* Values defined for the flags field of a struct d30v_operand. */ - -/* this is the destination register; it will be modified */ -/* this is used by the optimizer */ -#define OPERAND_DEST (1) - -/* number or symbol */ -#define OPERAND_NUM (2) - -/* address or label */ -#define OPERAND_ADDR (4) - -/* register */ -#define OPERAND_REG (8) - -/* postincrement + */ -#define OPERAND_PLUS (0x10) - -/* postdecrement - */ -#define OPERAND_MINUS (0x20) - -/* signed number */ -#define OPERAND_SIGNED (0x40) - -/* this operand must be shifted left by 3 */ -#define OPERAND_SHIFT (0x80) - -/* flag register */ -#define OPERAND_FLAG (0x100) - -/* control register */ -#define OPERAND_CONTROL (0x200) - -/* accumulator */ -#define OPERAND_ACC (0x400) - -/* @ */ -#define OPERAND_ATSIGN (0x800) - -/* @( */ -#define OPERAND_ATPAR (0x1000) - -/* predecrement mode '@-sp' */ -#define OPERAND_ATMINUS (0x2000) - -/* this operand changes the instruction name */ -/* for example, CPMcc, CMPUcc */ -#define OPERAND_NAME (0x4000) - -/* fake operand for mvtsys and mvfsys */ -#define OPERAND_SPECIAL (0x8000) - -/* let the optimizer know that two registers are affected */ -#define OPERAND_2REG (0x10000) - -/* This operand is pc-relative. Note that repeati can have two immediate - operands, one of which is pcrel, the other (the IMM6U one) is not. */ -#define OPERAND_PCREL (0x20000) - -/* The format table is an array of struct d30v_format. */ -struct d30v_format -{ - int form; /* SHORT_A, LONG, etc */ - int modifier; /* two bit modifier following opcode */ - unsigned char operands[5]; -}; -extern const struct d30v_format d30v_format_table[]; - - -/* an instruction is defined by an opcode and a format */ -/* for example, "add" has one opcode, but three different */ -/* formats, 2 SHORT_A forms and a LONG form. */ -struct d30v_insn -{ - struct d30v_opcode *op; /* pointer to an entry in the opcode table */ - struct d30v_format *form; /* pointer to an entry in the format table */ - int ecc; /* execution condition code */ -}; - -/* an expressionS only has one register type, so we fake it */ -/* by setting high bits to indicate type */ -#define REGISTER_MASK 0xFF - -#endif /* D30V_H */ diff --git a/include/opcode/dlx.h b/include/opcode/dlx.h deleted file mode 100644 index 54dadd0..0000000 --- a/include/opcode/dlx.h +++ /dev/null @@ -1,283 +0,0 @@ -/* Table of opcodes for the DLX microprocess. - Copyright 2002, 2010 Free Software Foundation, Inc. - - This file is part of GDB and GAS. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, - MA 02110-1301, USA. - - Initially created by Kuang Hwa Lin, 2002. */ - -/* Following are the function codes for the Special OP (ALU). */ -#define ALUOP 0x00000000 -#define SPECIALOP 0x00000000 - -#define NOPF 0x00000000 -#define SLLF 0x00000004 -#define SRLF 0x00000006 -#define SRAF 0x00000007 - -#define SEQUF 0x00000010 -#define SNEUF 0x00000011 -#define SLTUF 0x00000012 -#define SGTUF 0x00000013 -#define SLEUF 0x00000014 -#define SGEUF 0x00000015 - -#define ADDF 0x00000020 -#define ADDUF 0x00000021 -#define SUBF 0x00000022 -#define SUBUF 0x00000023 -#define ANDF 0x00000024 -#define ORF 0x00000025 -#define XORF 0x00000026 - -#define SEQF 0x00000028 -#define SNEF 0x00000029 -#define SLTF 0x0000002A -#define SGTF 0x0000002B -#define SLEF 0x0000002C -#define SGEF 0x0000002D - /* Following special functions was not mentioned in the - Hennessy's book but was implemented in the RTL. */ -#define MVTSF 0x00000030 -#define MVFSF 0x00000031 -#define BSWAPF 0x00000032 -#define LUTF 0x00000033 -/* Following special functions was mentioned in the - Hennessy's book but was not implemented in the RTL. */ -#define MULTF 0x00000005 -#define MULTUF 0x00000006 -#define DIVF 0x00000007 -#define DIVUF 0x00000008 - - -/* Following are the rest of the OPcodes: - JOP = (0x002 << 26), JALOP = (0x003 << 26), BEQOP = (0x004 << 26), BNEOP = (0x005 << 26) - ADDIOP = (0x008 << 26), ADDUIOP= (0x009 << 26), SUBIOP = (0x00A << 26), SUBUIOP= (0x00B << 26) - ANDIOP = (0x00C << 26), ORIOP = (0x00D << 26), XORIOP = (0x00E << 26), LHIOP = (0x00F << 26) - RFEOP = (0x010 << 26), TRAPOP = (0x011 << 26), JROP = (0x012 << 26), JALROP = (0x013 << 26) - BREAKOP= (0x014 << 26) - SEQIOP = (0x018 << 26), SNEIOP = (0x019 << 26), SLTIOP = (0x01A << 26), SGTIOP = (0x01B << 26) - SLEIOP = (0x01C << 26), SGEIOP = (0x01D << 26) - LBOP = (0x020 << 26), LHOP = (0x021 << 26), LWOP = (0x023 << 26), LBUOP = (0x024 << 26) - LHUOP = (0x025 << 26), SBOP = (0x028 << 26), SHOP = (0x029 << 26), SWOP = (0x02B << 26) - LSBUOP = (0x026 << 26), LSHU = (0x027 << 26), LSW = (0x02C << 26), - SEQUIOP= (0x030 << 26), SNEUIOP= (0x031 << 26), SLTUIOP= (0x032 << 26), SGTUIOP= (0x033 << 26) - SLEUIOP= (0x034 << 26), SGEUIOP= (0x035 << 26) - SLLIOP = (0x036 << 26), SRLIOP = (0x037 << 26), SRAIOP = (0x038 << 26). */ -#define JOP 0x08000000 -#define JALOP 0x0c000000 -#define BEQOP 0x10000000 -#define BNEOP 0x14000000 - -#define ADDIOP 0x20000000 -#define ADDUIOP 0x24000000 -#define SUBIOP 0x28000000 -#define SUBUIOP 0x2c000000 -#define ANDIOP 0x30000000 -#define ORIOP 0x34000000 -#define XORIOP 0x38000000 -#define LHIOP 0x3c000000 -#define RFEOP 0x40000000 -#define TRAPOP 0x44000000 -#define JROP 0x48000000 -#define JALROP 0x4c000000 -#define BREAKOP 0x50000000 - -#define SEQIOP 0x60000000 -#define SNEIOP 0x64000000 -#define SLTIOP 0x68000000 -#define SGTIOP 0x6c000000 -#define SLEIOP 0x70000000 -#define SGEIOP 0x74000000 - -#define LBOP 0x80000000 -#define LHOP 0x84000000 -#define LWOP 0x8c000000 -#define LBUOP 0x90000000 -#define LHUOP 0x94000000 -#define LDSTBU -#define LDSTHU -#define SBOP 0xa0000000 -#define SHOP 0xa4000000 -#define SWOP 0xac000000 -#define LDST - -#define SEQUIOP 0xc0000000 -#define SNEUIOP 0xc4000000 -#define SLTUIOP 0xc8000000 -#define SGTUIOP 0xcc000000 -#define SLEUIOP 0xd0000000 -#define SGEUIOP 0xd4000000 - -#define SLLIOP 0xd8000000 -#define SRLIOP 0xdc000000 -#define SRAIOP 0xe0000000 - -/* Following 3 ops was added to provide the MP atonmic operation. */ -#define LSBUOP 0x98000000 -#define LSHUOP 0x9c000000 -#define LSWOP 0xb0000000 - -/* Following opcode was defined in the Hennessy's book as - "normal" opcode but was implemented in the RTL as special - functions. */ -#if 0 -#define MVTSOP 0x50000000 -#define MVFSOP 0x54000000 -#endif - -struct dlx_opcode -{ - /* Name of the instruction. */ - char *name; - - /* Opcode word. */ - unsigned long opcode; - - /* A string of characters which describe the operands. - Valid characters are: - , Itself. The character appears in the assembly code. - a rs1 The register number is in bits 21-25 of the instruction. - b rs2/rd The register number is in bits 16-20 of the instruction. - c rd. The register number is in bits 11-15 of the instruction. - f FUNC bits 0-10 of the instruction. - i An immediate operand is in bits 0-16 of the instruction. 0 extended - I An immediate operand is in bits 0-16 of the instruction. sign extended - d An 16 bit PC relative displacement. - D An immediate operand is in bits 0-25 of the instruction. - N No opperands needed, for nops. - P it can be a register or a 16 bit operand. */ - char *args; -}; - -static const struct dlx_opcode dlx_opcodes[] = - { - /* Arithmetic and Logic R-TYPE instructions. */ - { "nop", (ALUOP|NOPF), "N" }, /* NOP */ - { "add", (ALUOP|ADDF), "c,a,b" }, /* Add */ - { "addu", (ALUOP|ADDUF), "c,a,b" }, /* Add Unsigned */ - { "sub", (ALUOP|SUBF), "c,a,b" }, /* SUB */ - { "subu", (ALUOP|SUBUF), "c,a,b" }, /* Sub Unsigned */ - { "mult", (ALUOP|MULTF), "c,a,b" }, /* MULTIPLY */ - { "multu", (ALUOP|MULTUF), "c,a,b" }, /* MULTIPLY Unsigned */ - { "div", (ALUOP|DIVF), "c,a,b" }, /* DIVIDE */ - { "divu", (ALUOP|DIVUF), "c,a,b" }, /* DIVIDE Unsigned */ - { "and", (ALUOP|ANDF), "c,a,b" }, /* AND */ - { "or", (ALUOP|ORF), "c,a,b" }, /* OR */ - { "xor", (ALUOP|XORF), "c,a,b" }, /* Exclusive OR */ - { "sll", (ALUOP|SLLF), "c,a,b" }, /* SHIFT LEFT LOGICAL */ - { "sra", (ALUOP|SRAF), "c,a,b" }, /* SHIFT RIGHT ARITHMETIC */ - { "srl", (ALUOP|SRLF), "c,a,b" }, /* SHIFT RIGHT LOGICAL */ - { "seq", (ALUOP|SEQF), "c,a,b" }, /* Set if equal */ - { "sne", (ALUOP|SNEF), "c,a,b" }, /* Set if not equal */ - { "slt", (ALUOP|SLTF), "c,a,b" }, /* Set if less */ - { "sgt", (ALUOP|SGTF), "c,a,b" }, /* Set if greater */ - { "sle", (ALUOP|SLEF), "c,a,b" }, /* Set if less or equal */ - { "sge", (ALUOP|SGEF), "c,a,b" }, /* Set if greater or equal */ - { "sequ", (ALUOP|SEQUF), "c,a,b" }, /* Set if equal unsigned */ - { "sneu", (ALUOP|SNEUF), "c,a,b" }, /* Set if not equal unsigned */ - { "sltu", (ALUOP|SLTUF), "c,a,b" }, /* Set if less unsigned */ - { "sgtu", (ALUOP|SGTUF), "c,a,b" }, /* Set if greater unsigned */ - { "sleu", (ALUOP|SLEUF), "c,a,b" }, /* Set if less or equal unsigned*/ - { "sgeu", (ALUOP|SGEUF), "c,a,b" }, /* Set if greater or equal */ - { "mvts", (ALUOP|MVTSF), "c,a" }, /* Move to special register */ - { "mvfs", (ALUOP|MVFSF), "c,a" }, /* Move from special register */ - { "bswap", (ALUOP|BSWAPF), "c,a,b" }, /* ??? Was not documented */ - { "lut", (ALUOP|LUTF), "c,a,b" }, /* ????? same as above */ - - /* Arithmetic and Logical Immediate I-TYPE instructions. */ - { "addi", ADDIOP, "b,a,I" }, /* Add Immediate */ - { "addui", ADDUIOP, "b,a,i" }, /* Add Usigned Immediate */ - { "subi", SUBIOP, "b,a,I" }, /* Sub Immediate */ - { "subui", SUBUIOP, "b,a,i" }, /* Sub Unsigned Immedated */ - { "andi", ANDIOP, "b,a,i" }, /* AND Immediate */ - { "ori", ORIOP, "b,a,i" }, /* OR Immediate */ - { "xori", XORIOP, "b,a,i" }, /* Exclusive OR Immediate */ - { "slli", SLLIOP, "b,a,i" }, /* SHIFT LEFT LOCICAL Immediate */ - { "srai", SRAIOP, "b,a,i" }, /* SHIFT RIGHT ARITH. Immediate */ - { "srli", SRLIOP, "b,a,i" }, /* SHIFT RIGHT LOGICAL Immediate*/ - { "seqi", SEQIOP, "b,a,i" }, /* Set if equal */ - { "snei", SNEIOP, "b,a,i" }, /* Set if not equal */ - { "slti", SLTIOP, "b,a,i" }, /* Set if less */ - { "sgti", SGTIOP, "b,a,i" }, /* Set if greater */ - { "slei", SLEIOP, "b,a,i" }, /* Set if less or equal */ - { "sgei", SGEIOP, "b,a,i" }, /* Set if greater or equal */ - { "sequi", SEQUIOP, "b,a,i" }, /* Set if equal */ - { "sneui", SNEUIOP, "b,a,i" }, /* Set if not equal */ - { "sltui", SLTUIOP, "b,a,i" }, /* Set if less */ - { "sgtui", SGTUIOP, "b,a,i" }, /* Set if greater */ - { "sleui", SLEUIOP, "b,a,i" }, /* Set if less or equal */ - { "sgeui", SGEUIOP, "b,a,i" }, /* Set if greater or equal */ - /* Macros for I type instructions. */ - { "mov", ADDIOP, "b,P" }, /* a move macro */ - { "movu", ADDUIOP, "b,P" }, /* a move macro, unsigned */ - -#if 0 - /* Move special. */ - { "mvts", MVTSOP, "b,a" }, /* Move From Integer to Special */ - { "mvfs", MVFSOP, "b,a" }, /* Move From Special to Integer */ -#endif - - /* Load high Immediate I-TYPE instruction. */ - { "lhi", LHIOP, "b,i" }, /* Load High Immediate */ - { "lui", LHIOP, "b,i" }, /* Load High Immediate */ - { "sethi", LHIOP, "b,i" }, /* Load High Immediate */ - - /* LOAD/STORE BYTE 8 bits I-TYPE. */ - { "lb", LBOP, "b,a,I" }, /* Load Byte */ - { "lbu", LBUOP, "b,a,I" }, /* Load Byte Unsigned */ - { "ldstbu", LSBUOP, "b,a,I" }, /* Load store Byte Unsigned */ - { "sb", SBOP, "b,a,I" }, /* Store Byte */ - - /* LOAD/STORE HALFWORD 16 bits. */ - { "lh", LHOP, "b,a,I" }, /* Load Halfword */ - { "lhu", LHUOP, "b,a,I" }, /* Load Halfword Unsigned */ - { "ldsthu", LSHUOP, "b,a,I" }, /* Load Store Halfword Unsigned */ - { "sh", SHOP, "b,a,I" }, /* Store Halfword */ - - /* LOAD/STORE WORD 32 bits. */ - { "lw", LWOP, "b,a,I" }, /* Load Word */ - { "sw", SWOP, "b,a,I" }, /* Store Word */ - { "ldstw", LSWOP, "b,a,I" }, /* Load Store Word */ - - /* Branch PC-relative, 16 bits offset. */ - { "beqz", BEQOP, "a,d" }, /* Branch if a == 0 */ - { "bnez", BNEOP, "a,d" }, /* Branch if a != 0 */ - { "beq", BEQOP, "a,d" }, /* Branch if a == 0 */ - { "bne", BNEOP, "a,d" }, /* Branch if a != 0 */ - - /* Jumps Trap and RFE J-TYPE. */ - { "j", JOP, "D" }, /* Jump, PC-relative 26 bits */ - { "jal", JALOP, "D" }, /* JAL, PC-relative 26 bits */ - { "break", BREAKOP, "D" }, /* break to OS */ - { "trap" , TRAPOP, "D" }, /* TRAP to OS */ - { "rfe", RFEOP, "N" }, /* Return From Exception */ - /* Macros. */ - { "call", JOP, "D" }, /* Jump, PC-relative 26 bits */ - - /* Jumps Trap and RFE I-TYPE. */ - { "jr", JROP, "a" }, /* Jump Register, Abs (32 bits) */ - { "jalr", JALROP, "a" }, /* JALR, Abs (32 bits) */ - /* Macros. */ - { "retr", JROP, "a" }, /* Jump Register, Abs (32 bits) */ - - { "", 0x0, "" } /* Dummy entry, not included in NUM_OPCODES. - This lets code examine entry i + 1 without - checking if we've run off the end of the table. */ - }; - -const unsigned int num_dlx_opcodes = (((sizeof dlx_opcodes) / (sizeof dlx_opcodes[0])) - 1); diff --git a/include/opcode/h8300.h b/include/opcode/h8300.h deleted file mode 100644 index 3296deb..0000000 --- a/include/opcode/h8300.h +++ /dev/null @@ -1,1892 +0,0 @@ -/* Opcode table for the H8/300 - Copyright 1991-2013 Free Software Foundation, Inc. - Written by Steve Chamberlain <sac@cygnus.com>. - - This file is part of GDB, the GNU Debugger and GAS, the GNU Assembler. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA - 02110-1301, USA. */ - -/* Instructions are stored as a sequence of nibbles. - If the nibble has value 15 or less than the representation is complete. - Otherwise, we record what it contains with several flags. */ - -typedef int op_type; - -enum h8_flags -{ - L_2 = 0x10, - L_3 = 0x20, - /* 3 bit constant, zero not accepted. */ - L_3NZ = 0x30, - L_4 = 0x40, - L_5 = 0x50, - L_8 = 0x60, - L_8U = 0x70, - L_16 = 0x80, - L_16U = 0x90, - L_24 = 0xA0, - L_32 = 0xB0, - L_P = 0xC0, - - /* Mask to isolate the L_x size bits. */ - SIZE = 0xF0, - - REG = 0x0100, - ABS = 0x0200, - MEMIND = 0x0300, - IMM = 0x0400, - DISP = 0x0500, - IND = 0x0600, - POSTINC = 0x0700, - POSTDEC = 0x0800, - PREINC = 0x0900, - PREDEC = 0x0A00, - PCREL = 0x0B00, - KBIT = 0x0C00, - DBIT = 0x0D00, - CONST_2 = 0x0E00, - CONST_4 = 0x0F00, - CONST_8 = 0x1000, - CONST_16 = 0x1100, - INDEXB = 0x1200, - INDEXW = 0x1300, - INDEXL = 0x1400, - PCIDXB = 0x1500, - PCIDXW = 0x1600, - PCIDXL = 0x1700, - VECIND = 0x1800, - LOWREG = 0x1900, - DATA = 0x2000, - - /* Synonyms. */ - INC = POSTINC, - DEC = PREDEC, - /* Control Registers. */ - CCR = 0x4000, - EXR = 0x4100, - MACH = 0x4200, - MACL = 0x4300, - RESERV1 = 0x4400, - RESERV2 = 0x4500, - VBR = 0x4600, - SBR = 0x4700, - MACREG = 0x4800, - CCR_EXR = 0x4900, - VBR_SBR = 0x4A00, - CC_EX_VB_SB = 0x4B00, - RESERV3 = 0x4C00, - RESERV4 = 0x4D00, - RESERV5 = 0x4E00, - RESERV6 = 0x4F00, - - /* Mask to isolate the addressing mode bits (REG .. PREDEC). */ - MODE = 0x7F00, - - CTRL = 0x4000, - - NO_SYMBOLS = 0x8000, - SRC = 0x10000, - DST = 0x20000, - OP3 = 0x40000, - MEMRELAX = 0x80000, /* Move insn which may relax. */ - - DISPREG = 0x100000, - IGNORE = 0x200000, - ABSJMP = 0x400000, - - B00 = 0x800000, /* Bit 0 must be low. */ - B01 = 0x1000000, /* Bit 0 must be high. */ - B10 = 0x2000000, /* Bit 1 must be low. */ - B11 = 0x4000000, /* Bit 1 must be high. */ - B20 = 0x8000000, /* Bit 2 must be low. */ - B21 = 0x10000000, /* Bit 2 must be high. */ - B30 = 0x20000000, /* Bit 3 must be low. */ - B31 = 0x40000000, /* Bit 3 must be high. */ - E = 0x80000000, /* End of nibble sequence. */ - - /* Immediates smaller than 8 bits are always unsigned. */ - IMM3 = IMM | L_3, - IMM4 = IMM | L_4, - IMM5 = IMM | L_5, - IMM3NZ = IMM | L_3NZ, - IMM2 = IMM | L_2, - - IMM8 = IMM | SRC | L_8, - IMM8U = IMM | SRC | L_8U, - IMM16 = IMM | SRC | L_16, - IMM16U = IMM | SRC | L_16U, - IMM32 = IMM | SRC | L_32, - - IMM3NZ_NS = IMM3NZ | NO_SYMBOLS, - IMM4_NS = IMM4 | NO_SYMBOLS, - IMM8U_NS = IMM8U | NO_SYMBOLS, - IMM16U_NS = IMM16U | NO_SYMBOLS, - - RD8 = DST | L_8 | REG, - RD16 = DST | L_16 | REG, - RD32 = DST | L_32 | REG, - R3_8 = OP3 | L_8 | REG, - R3_16 = OP3 | L_16 | REG, - R3_32 = OP3 | L_32 | REG, - RS8 = SRC | L_8 | REG, - RS16 = SRC | L_16 | REG, - RS32 = SRC | L_32 | REG, - - RSP = SRC | L_P | REG, - RDP = DST | L_P | REG, - - PCREL8 = PCREL | L_8, - PCREL16 = PCREL | L_16, - - OP3PCREL8 = OP3 | PCREL | L_8, - OP3PCREL16 = OP3 | PCREL | L_16, - - INDEXB16 = INDEXB | L_16, - INDEXW16 = INDEXW | L_16, - INDEXL16 = INDEXL | L_16, - INDEXB16D = INDEXB | L_16 | DST, - INDEXW16D = INDEXW | L_16 | DST, - INDEXL16D = INDEXL | L_16 | DST, - - INDEXB32 = INDEXB | L_32, - INDEXW32 = INDEXW | L_32, - INDEXL32 = INDEXL | L_32, - INDEXB32D = INDEXB | L_32 | DST, - INDEXW32D = INDEXW | L_32 | DST, - INDEXL32D = INDEXL | L_32 | DST, - - DISP2SRC = DISP | L_2 | SRC, - DISP16SRC = DISP | L_16 | SRC, - DISP32SRC = DISP | L_32 | SRC, - - DISP2DST = DISP | L_2 | DST, - DISP16DST = DISP | L_16 | DST, - DISP32DST = DISP | L_32 | DST, - - DSTDISPREG = DST | DISPREG, - SRCDISPREG = SRC | DISPREG, - - ABS8SRC = SRC | ABS | L_8, - ABS16SRC = SRC | ABS | L_16U, - ABS24SRC = SRC | ABS | L_24, - ABS32SRC = SRC | ABS | L_32, - - ABS8DST = DST | ABS | L_8, - ABS16DST = DST | ABS | L_16U, - ABS24DST = DST | ABS | L_24, - ABS32DST = DST | ABS | L_32, - - ABS8OP3 = OP3 | ABS | L_8, - ABS16OP3 = OP3 | ABS | L_16U, - ABS24OP3 = OP3 | ABS | L_24, - ABS32OP3 = OP3 | ABS | L_32, - - RDDEC = DST | DEC, - RSINC = SRC | INC, - RDINC = DST | INC, - - RSPOSTINC = SRC | POSTINC, - RDPOSTINC = DST | POSTINC, - RSPREINC = SRC | PREINC, - RDPREINC = DST | PREINC, - RSPOSTDEC = SRC | POSTDEC, - RDPOSTDEC = DST | POSTDEC, - RSPREDEC = SRC | PREDEC, - RDPREDEC = DST | PREDEC, - - RSIND = SRC | IND, - RDIND = DST | IND, - R3_IND = OP3 | IND, - -#define MS32 (SRC | L_32 | MACREG) -#define MD32 (DST | L_32 | MACREG) - -#if 1 - OR8 = RS8, /* ??? OR as in One Register. */ - OR16 = RS16, - OR32 = RS32, -#else - OR8 = RD8, - OR16 = RD16, - OR32 = RD32 -#endif -}; - -enum ctrlreg -{ - C_CCR = 0, - C_EXR = 1, - C_MACH = 2, - C_MACL = 3, - C_VBR = 6, - C_SBR = 7 -}; - -enum {MAX_CODE_NIBBLES = 33}; - -struct code -{ - op_type nib[MAX_CODE_NIBBLES]; -}; - -struct arg -{ - op_type nib[3]; -}; - -/* Availability of instructions on processor models. */ -enum h8_model -{ - AV_H8, - AV_H8H, - AV_H8S, - AV_H8SX -}; - -struct h8_opcode -{ - int how; - enum h8_model available; - int time; - char *name; - struct arg args; - struct code data; -}; - -#ifdef DEFINE_TABLE - -#define DATA2 DATA, DATA -#define DATA3 DATA, DATA, DATA -#define DATA5 DATA, DATA, DATA, DATA, DATA -#define DATA7 DATA, DATA, DATA, DATA, DATA, DATA, DATA - -#define IMM8LIST IMM8, DATA -#define IMM16LIST IMM16, DATA3 -#define IMM16ULIST IMM16U, DATA3 -#define IMM24LIST IMM24, DATA5 -#define IMM32LIST IMM32, DATA7 - -#define DISP16LIST DISP | L_16, DATA3 -#define DISP24LIST DISP | L_24, DATA5 -#define DISP32LIST DISP | L_32, DATA7 - -#define ABS8LIST ABS | L_8, DATA -#define ABS16LIST ABS | L_16U, DATA3 -#define ABS24LIST ABS | L_24, DATA5 -#define ABS32LIST ABS | L_32, DATA7 - -#define DSTABS8LIST DST | ABS | L_8, DATA -#define DSTABS16LIST DST | ABS | L_16U, DATA3 -#define DSTABS24LIST DST | ABS | L_24, DATA5 -#define DSTABS32LIST DST | ABS | L_32, DATA7 - -#define OP3ABS8LIST OP3 | ABS | L_8, DATA -#define OP3ABS16LIST OP3 | ABS | L_16, DATA3 -#define OP3ABS24LIST OP3 | ABS | L_24, DATA5 -#define OP3ABS32LIST OP3 | ABS | L_32, DATA7 - -#define DSTDISP16LIST DST | DISP | L_16, DATA3 -#define DSTDISP24LIST DST | DISP | L_24, DATA5 -#define DSTDISP32LIST DST | DISP | L_32, DATA7 - -#define A16LIST L_16, DATA3 -#define A24LIST L_24, DATA5 -#define A32LIST L_32, DATA7 - -/* Extended Operand Prefixes: */ - -#define PREFIX_010 0x0, 0x1, 0x0 -#define PREFIX_015 0x0, 0x1, 0x5 -#define PREFIX_017 0x0, 0x1, 0x7 - -#define PREFIX_0100 0x0, 0x1, 0x0, 0x0 -#define PREFIX_010_D2 0x0, 0x1, 0x0, B30 | B21 | DISP2SRC -#define PREFIX_0101 0x0, 0x1, 0x0, 0x1 -#define PREFIX_0102 0x0, 0x1, 0x0, 0x2 -#define PREFIX_0103 0x0, 0x1, 0x0, 0x3 -#define PREFIX_0104 0x0, 0x1, 0x0, 0x4 -#define PREFIX_0105 0x0, 0x1, 0x0, 0x5 -#define PREFIX_0106 0x0, 0x1, 0x0, 0x6 -#define PREFIX_0107 0x0, 0x1, 0x0, 0x7 -#define PREFIX_0108 0x0, 0x1, 0x0, 0x8 -#define PREFIX_0109 0x0, 0x1, 0x0, 0x9 -#define PREFIX_010A 0x0, 0x1, 0x0, 0xa -#define PREFIX_010D 0x0, 0x1, 0x0, 0xd -#define PREFIX_010E 0x0, 0x1, 0x0, 0xe - -#define PREFIX_0150 0x0, 0x1, 0x5, 0x0 -#define PREFIX_015_D2 0x0, 0x1, 0x5, B30 | B21 | DISP2SRC -#define PREFIX_0151 0x0, 0x1, 0x5, 0x1 -#define PREFIX_0152 0x0, 0x1, 0x5, 0x2 -#define PREFIX_0153 0x0, 0x1, 0x5, 0x3 -#define PREFIX_0154 0x0, 0x1, 0x5, 0x4 -#define PREFIX_0155 0x0, 0x1, 0x5, 0x5 -#define PREFIX_0156 0x0, 0x1, 0x5, 0x6 -#define PREFIX_0157 0x0, 0x1, 0x5, 0x7 -#define PREFIX_0158 0x0, 0x1, 0x5, 0x8 -#define PREFIX_0159 0x0, 0x1, 0x5, 0x9 -#define PREFIX_015A 0x0, 0x1, 0x5, 0xa -#define PREFIX_015D 0x0, 0x1, 0x5, 0xd -#define PREFIX_015E 0x0, 0x1, 0x5, 0xe -#define PREFIX_015F 0x0, 0x1, 0x5, 0xf - -#define PREFIX_0170 0x0, 0x1, 0x7, 0x0 -#define PREFIX_017_D2S 0x0, 0x1, 0x7, B30 | B21 | DISP2SRC -#define PREFIX_017_D2D 0x0, 0x1, 0x7, B30 | B21 | DISP2DST -#define PREFIX_0171 0x0, 0x1, 0x7, 0x1 -#define PREFIX_0172 0x0, 0x1, 0x7, 0x2 -#define PREFIX_0173 0x0, 0x1, 0x7, 0x3 -#define PREFIX_0174 0x0, 0x1, 0x7, 0x4 -#define PREFIX_0175 0x0, 0x1, 0x7, 0x5 -#define PREFIX_0176 0x0, 0x1, 0x7, 0x6 -#define PREFIX_0177 0x0, 0x1, 0x7, 0x7 -#define PREFIX_0178 0x0, 0x1, 0x7, 0x8 -#define PREFIX_0179 0x0, 0x1, 0x7, 0x9 -#define PREFIX_017A 0x0, 0x1, 0x7, 0xa -#define PREFIX_017D 0x0, 0x1, 0x7, 0xd -#define PREFIX_017E 0x0, 0x1, 0x7, 0xe -#define PREFIX_017F 0x0, 0x1, 0x7, 0xf - -#define PREFIX_6A15 0x6, 0xa, 0x1, 0x5 -#define PREFIX_6A35 0x6, 0xa, 0x3, 0x5 -#define PREFIX_6B15 0x6, 0xb, 0x1, 0x5 -#define PREFIX_6B35 0x6, 0xb, 0x3, 0x5 - -#define PREFIX_78R4 0x7, 0x8, B31 | DISPREG, 0x4 -#define PREFIX_78R5 0x7, 0x8, B31 | DISPREG, 0x5 -#define PREFIX_78R6 0x7, 0x8, B31 | DISPREG, 0x6 -#define PREFIX_78R7 0x7, 0x8, B31 | DISPREG, 0x7 - -#define PREFIX_78R4W 0x7, 0x8, B30 | DISPREG, 0x4 -#define PREFIX_78R5W 0x7, 0x8, B30 | DISPREG, 0x5 -#define PREFIX_78R6W 0x7, 0x8, B30 | DISPREG, 0x6 -#define PREFIX_78R7W 0x7, 0x8, B30 | DISPREG, 0x7 - -#define PREFIX_78R4WD 0x7, 0x8, B30 | DSTDISPREG, 0x4 -#define PREFIX_78R5WD 0x7, 0x8, B30 | DSTDISPREG, 0x5 -#define PREFIX_78R6WD 0x7, 0x8, B30 | DSTDISPREG, 0x6 -#define PREFIX_78R7WD 0x7, 0x8, B30 | DSTDISPREG, 0x7 - -#define PREFIX_7974 0x7, 0x9, 0x7, 0x4 -#define PREFIX_7A74 0x7, 0xa, 0x7, 0x4 -#define PREFIX_7A7C 0x7, 0xa, 0x7, 0xc - - -/* Source standard fragment: */ -#define FROM_IND 0, RSIND -#define FROM_POSTINC 8, RSPOSTINC -#define FROM_POSTDEC 10, RSPOSTDEC -#define FROM_PREINC 9, RSPREINC -#define FROM_PREDEC 11, RSPREDEC -#define FROM_DISP2 B30 | B20 | DISP2SRC, DISPREG -#define FROM_DISP16 12, B30 | DISPREG -#define FROM_DISP32 12, B31 | DISPREG -#define FROM_DISP16B 13, B30 | DISPREG -#define FROM_DISP16W 14, B30 | DISPREG -#define FROM_DISP16L 15, B30 | DISPREG -#define FROM_DISP32B 13, B31 | DISPREG -#define FROM_DISP32W 14, B31 | DISPREG -#define FROM_DISP32L 15, B31 | DISPREG -#define FROM_ABS16 4, B30 | IGNORE -#define FROM_ABS32 4, B31 | IGNORE - -/* Destination standard fragment: */ -#define TO_IND 0, RDIND -#define TO_IND_MOV 0, RDIND | B30 -#define TO_POSTINC 8, RDPOSTINC -#define TO_POSTINC_MOV 8, RDPOSTINC | B30 -#define TO_POSTDEC 10, RDPOSTDEC -#define TO_POSTDEC_MOV 10, RDPOSTDEC | B30 -#define TO_PREINC 9, RDPREINC -#define TO_PREINC_MOV 9, RDPREINC | B30 -#define TO_PREDEC 11, RDPREDEC -#define TO_PREDEC_MOV 11, RDPREDEC | B30 -#define TO_DISP2 B30 | B20 | DISP2DST, DSTDISPREG -#define TO_DISP2_MOV B30 | B20 | DISP2DST, DSTDISPREG | B30 -#define TO_DISP16 12, B30 | DSTDISPREG -#define TO_DISP32 12, B31 | DSTDISPREG -#define TO_DISP16B 13, B30 | DSTDISPREG -#define TO_DISP16W 14, B30 | DSTDISPREG -#define TO_DISP16L 15, B30 | DSTDISPREG -#define TO_DISP32B 13, B31 | DSTDISPREG -#define TO_DISP32W 14, B31 | DSTDISPREG -#define TO_DISP32L 15, B31 | DSTDISPREG -#define TO_ABS16 4, B30 | IGNORE -#define TO_ABS32 4, B31 | IGNORE - -/* Source fragment for three-word instruction: */ -#define TFROM_IND 6, 9, B30 | RSIND, 12 -#define TFROM_DISP2 6, 9, B30 | DISPREG, 12 -#define TFROM_ABS16 6, 11, B30 | B20 | B10 | IGNORE, 12, ABS16LIST -#define TFROM_ABS32 6, 11, B30 | B20 | B11 | IGNORE, 12, ABS32LIST -#define TFROM_POSTINC 6, 13, B30 | RSPOSTINC, 12 -#define TFROM_PREINC 6, 13, B30 | RSPREINC, 12 -#define TFROM_POSTDEC 6, 13, B30 | RSPOSTDEC, 12 -#define TFROM_PREDEC 6, 13, B30 | RSPREDEC, 12 -#define TFROM_DISP16 6, 15, B30 | DISPREG, 12, DISP16LIST -#define TFROM_DISP32 6, 11, 2, 12, DISP32LIST -#define TFROM_DISP16B 6, 15, B30 | DISPREG, 12, DISP16LIST -#define TFROM_DISP16W 6, 15, B30 | DISPREG, 12, DISP16LIST -#define TFROM_DISP16L 6, 15, B30 | DISPREG, 12, DISP16LIST -#define TFROM_DISP32B 6, 11, 2, 12, DISP32LIST -#define TFROM_DISP32W 6, 11, 2, 12, DISP32LIST -#define TFROM_DISP32L 6, 11, 2, 12, DISP32LIST -#define TFROM_ABS16W 6, 11, 1, 12, ABS16LIST -#define TFROM_ABS32W 6, 11, 3, 12, ABS32LIST - -/* Source fragment for three-word instruction: */ -#define TFROM_IND_B 6, 8, B30 | RSIND, 12 -#define TFROM_ABS16_B 6, 10, B30 | B20 | B10 | IGNORE, 12, ABS16LIST -#define TFROM_ABS32_B 6, 10, B30 | B20 | B11 | IGNORE, 12, ABS32LIST - -#define TFROM_DISP2_B 6, 8, B30 | DISPREG, 12 -#define TFROM_POSTINC_B 6, 12, B30 | RSPOSTINC, 12 -#define TFROM_PREINC_B 6, 12, B30 | RSPREINC, 12 -#define TFROM_POSTDEC_B 6, 12, B30 | RSPOSTDEC, 12 -#define TFROM_PREDEC_B 6, 12, B30 | RSPREDEC, 12 -#define TFROM_DISP16_B 6, 14, B30 | DISPREG, 12, DISP16LIST -#define TFROM_DISP32_B 6, 10, 2, 12, DISP32LIST -#define TFROM_DISP16B_B 6, 14, B30 | DISPREG, 12, DISP16LIST -#define TFROM_DISP16W_B 6, 14, B30 | DISPREG, 12, DISP16LIST -#define TFROM_DISP16L_B 6, 14, B30 | DISPREG, 12, DISP16LIST -#define TFROM_DISP32B_B 6, 10, 2, 12, DISP32LIST -#define TFROM_DISP32W_B 6, 10, 2, 12, DISP32LIST -#define TFROM_DISP32L_B 6, 10, 2, 12, DISP32LIST - -#define TFROM_ABS16W_B 6, 10, 1, 12, ABS16LIST -#define TFROM_ABS32W_B 6, 10, 3, 12, ABS32LIST - -/* Extended Operand Class Expanders: */ - -#define MOVFROM_STD(CODE, PREFIX, NAME, SRC, SRC_INFIX) \ - {CODE, AV_H8SX, 0, NAME, {{SRC, RDIND, E}}, {{PREFIX, SRC_INFIX, TO_IND_MOV, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, SRC_INFIX, TO_POSTINC_MOV, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, SRC_INFIX, TO_POSTDEC_MOV, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC, E}}, {{PREFIX, SRC_INFIX, TO_PREINC_MOV, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC, E}}, {{PREFIX, SRC_INFIX, TO_PREDEC_MOV, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST, E}}, {{PREFIX, SRC_INFIX, TO_DISP2_MOV, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}}, {{PREFIX, SRC_INFIX, TO_DISP16, DSTDISP16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}}, {{PREFIX, SRC_INFIX, TO_DISP32, DSTDISP32LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, SRC_INFIX, TO_DISP16B, DSTDISP16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}}, {{PREFIX, SRC_INFIX, TO_DISP16W, DSTDISP16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}}, {{PREFIX, SRC_INFIX, TO_DISP16L, DSTDISP16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{PREFIX, SRC_INFIX, TO_DISP32B, DSTDISP32LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{PREFIX, SRC_INFIX, TO_DISP32W, DSTDISP32LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{PREFIX, SRC_INFIX, TO_DISP32L, DSTDISP32LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, ABS16DST, E}}, {{PREFIX, SRC_INFIX, TO_ABS16, DSTABS16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, ABS32DST, E}}, {{PREFIX, SRC_INFIX, TO_ABS32, DSTABS32LIST, E}}} - -#define MOVFROM_AD(CODE, PREFIX, NAME, SRC, SRC_INFIX, SRC_SUFFIX) \ - {CODE, AV_H8SX, 0, NAME, {{SRC, RDIND, E}}, {{PREFIX, SRC_INFIX, TO_IND_MOV, SRC_SUFFIX, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, SRC_INFIX, TO_POSTINC_MOV, SRC_SUFFIX, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, SRC_INFIX, TO_POSTDEC_MOV, SRC_SUFFIX, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC, E}}, {{PREFIX, SRC_INFIX, TO_PREINC_MOV, SRC_SUFFIX, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC, E}}, {{PREFIX, SRC_INFIX, TO_PREDEC_MOV, SRC_SUFFIX, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST, E}}, {{PREFIX, SRC_INFIX, TO_DISP2_MOV, SRC_SUFFIX, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}}, {{PREFIX, SRC_INFIX, TO_DISP16, SRC_SUFFIX, DSTDISP16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}}, {{PREFIX, SRC_INFIX, TO_DISP32, SRC_SUFFIX, DSTDISP32LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, SRC_INFIX, TO_DISP16B, SRC_SUFFIX, DSTDISP16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}}, {{PREFIX, SRC_INFIX, TO_DISP16W, SRC_SUFFIX, DSTDISP16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}}, {{PREFIX, SRC_INFIX, TO_DISP16L, SRC_SUFFIX, DSTDISP16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{PREFIX, SRC_INFIX, TO_DISP32B, SRC_SUFFIX, DSTDISP32LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{PREFIX, SRC_INFIX, TO_DISP32W, SRC_SUFFIX, DSTDISP32LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{PREFIX, SRC_INFIX, TO_DISP32L, SRC_SUFFIX, DSTDISP32LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, ABS16DST, E}}, {{PREFIX, SRC_INFIX, TO_ABS16, SRC_SUFFIX, DSTABS16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, ABS32DST, E}}, {{PREFIX, SRC_INFIX, TO_ABS32, SRC_SUFFIX, DSTABS32LIST, E}}} - -#define MOVFROM_IMM8(CODE, PREFIX, NAME, SRC) \ - {CODE, AV_H8SX, 0, NAME, {{SRC, RDIND, E}}, {{PREFIX, 0, RDIND, IMM8LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, 8, RDPOSTINC, IMM8LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, 10, RDPOSTDEC, IMM8LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC, E}}, {{PREFIX, 9, RDPREINC, IMM8LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC, E}}, {{PREFIX, 11, RDPREDEC, IMM8LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST, E}}, {{PREFIX, B30 | B20 | DISP2DST, DSTDISPREG, IMM8LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}}, {{PREFIX, 12, B30 | DSTDISPREG, IMM8LIST, DSTDISP16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}}, {{PREFIX, 12, B31 | DSTDISPREG, IMM8LIST, DSTDISP32LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, 13, B30 | DSTDISPREG, IMM8LIST, DSTDISP16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}}, {{PREFIX, 14, B30 | DSTDISPREG, IMM8LIST, DSTDISP16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}}, {{PREFIX, 15, B30 | DSTDISPREG, IMM8LIST, DSTDISP16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{PREFIX, 13, B31 | DSTDISPREG, IMM8LIST, DSTDISP32LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{PREFIX, 14, B31 | DSTDISPREG, IMM8LIST, DSTDISP32LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{PREFIX, 15, B31 | DSTDISPREG, IMM8LIST, DSTDISP32LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, ABS16DST, E}}, {{PREFIX, 4, B30 | IGNORE, IMM8LIST, DSTABS16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, ABS32DST, E}}, {{PREFIX, 4, B31 | IGNORE, IMM8LIST, DSTABS32LIST, E}}} - -#define MOVFROM_IMM(CODE, PREFIX, NAME, SRC, LIST) \ - {CODE, AV_H8SX, 0, NAME, {{SRC, RDIND, E}}, {{PREFIX, LIST, 0, RDIND, DATA2, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, LIST, 8, RDPOSTINC, DATA2, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, LIST, 10, RDPOSTDEC, DATA2, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC, E}}, {{PREFIX, LIST, 9, RDPREINC, DATA2, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC, E}}, {{PREFIX, LIST, 11, RDPREDEC, DATA2, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST, E}}, {{PREFIX, LIST, B30 | B20 | DISP2DST, DSTDISPREG, DATA2, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}}, {{PREFIX, LIST, 12, B30 | DSTDISPREG, DATA2, DSTDISP16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}}, {{PREFIX, LIST, 12, B31 | DSTDISPREG, DATA2, DSTDISP32LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, LIST, 13, B30 | DSTDISPREG, DATA2, DSTDISP16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}}, {{PREFIX, LIST, 14, B30 | DSTDISPREG, DATA2, DSTDISP16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}}, {{PREFIX, LIST, 15, B30 | DSTDISPREG, DATA2, DSTDISP16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{PREFIX, LIST, 13, B31 | DSTDISPREG, DATA2, DSTDISP32LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{PREFIX, LIST, 14, B31 | DSTDISPREG, DATA2, DSTDISP32LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{PREFIX, LIST, 15, B31 | DSTDISPREG, DATA2, DSTDISP32LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, ABS16DST, E}}, {{PREFIX, LIST, 4, B30 | IGNORE, DATA2, DSTABS16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, ABS32DST, E}}, {{PREFIX, LIST, 4, B31 | IGNORE, DATA2, DSTABS32LIST, E}}} - -#define MOVFROM_REG_BW(CODE, NAME, SRC, PREFIX, OP1, OP2, OP3, OP4, RELAX16) \ - {CODE, AV_H8, 4, NAME, {{SRC, RDIND, E}}, {{ 6, OP1, B31 | RDIND, SRC, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, 3, 6, OP3, B31 | RDPOSTINC, SRC, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, 1, 6, OP3, B31 | RDPOSTDEC, SRC, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC, E}}, {{PREFIX, 2, 6, OP3, B31 | RDPREINC, SRC, E}}}, \ - {CODE, AV_H8, 6, NAME, {{SRC, RDPREDEC, E}}, {{ 6, OP3, B31 | RDPREDEC, SRC, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST, E}}, {{PREFIX, B30 | B20 | DISP2DST, 6, OP1, B31 | DSTDISPREG, SRC, E}}}, \ - {CODE, AV_H8, 6, NAME, {{SRC, DISP16DST, E}}, {{ 6, OP4, B31 | DSTDISPREG, SRC, DSTDISP16LIST, E}}}, \ - {CODE, AV_H8, 6, NAME, {{SRC, DISP32DST, E}}, {{7, 8, B30 | DSTDISPREG, 0, 6, OP2, 10, SRC, MEMRELAX | DSTDISP32LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, 1, 6, OP4, B31 | DSTDISPREG, SRC, DSTDISP16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}}, {{PREFIX, 2, 6, OP4, B31 | DSTDISPREG, SRC, DSTDISP16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}}, {{PREFIX, 3, 6, OP4, B31 | DSTDISPREG, SRC, DSTDISP16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{7, 8, B30 | DSTDISPREG, 1, 6, OP2, 10, SRC, DSTDISP32LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{7, 8, B30 | DSTDISPREG, 2, 6, OP2, 10, SRC, DSTDISP32LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{7, 8, B30 | DSTDISPREG, 3, 6, OP2, 10, SRC, DSTDISP32LIST, E}}}, \ - {CODE, AV_H8, 4, NAME, {{SRC, ABS16DST, E}}, {{ 6, OP2, 8, SRC, RELAX16 | DSTABS16LIST, E}}}, \ - {CODE, AV_H8, 6, NAME, {{SRC, ABS32DST, E}}, {{ 6, OP2, 10, SRC, MEMRELAX | DSTABS32LIST, E}}} - -#define MOVTO_REG_BW(CODE, NAME, DST, PREFIX, OP1, OP2, OP3, OP4, RELAX16) \ - {CODE, AV_H8, 4, NAME, {{RSIND, DST, E}}, {{ 6, OP1, B30 | RSIND, DST, E}}}, \ - {CODE, AV_H8, 6, NAME, {{RSPOSTINC, DST, E}}, {{ 6, OP3, B30 | RSPOSTINC, DST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{RSPOSTDEC, DST, E}}, {{PREFIX, 2, 6, OP3, B30 | RSPOSTDEC, DST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{RSPREINC, DST, E}}, {{PREFIX, 1, 6, OP3, B30 | RSPREINC, DST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{RSPREDEC, DST, E}}, {{PREFIX, 3, 6, OP3, B30 | RSPREDEC, DST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{DISP2SRC, DST, E}}, {{PREFIX, B30 | B20 | DISP2SRC, 6, OP1, B30 | DISPREG, DST, E}}}, \ - {CODE, AV_H8, 6, NAME, {{DISP16SRC, DST, E}}, {{ 6, OP4, B30 | DISPREG, DST, DISP16LIST, E}}}, \ - {CODE, AV_H8, 6, NAME, {{DISP32SRC, DST, E}}, {{7, 8, B30 | DISPREG, 0, 6, OP2, 2, DST, MEMRELAX | DISP32LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{INDEXB16, DST, E}}, {{PREFIX, 1, 6, OP4, B30 | DISPREG, DST, DISP16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{INDEXW16, DST, E}}, {{PREFIX, 2, 6, OP4, B30 | DISPREG, DST, DISP16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{INDEXL16, DST, E}}, {{PREFIX, 3, 6, OP4, B30 | DISPREG, DST, DISP16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{INDEXB32, DST, E}}, {{7, 8, B30 | DISPREG, 1, 6, OP2, 2, DST, DISP32LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{INDEXW32, DST, E}}, {{7, 8, B30 | DISPREG, 2, 6, OP2, 2, DST, DISP32LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{INDEXL32, DST, E}}, {{7, 8, B30 | DISPREG, 3, 6, OP2, 2, DST, DISP32LIST, E}}}, \ - {CODE, AV_H8, 4, NAME, {{ABS16SRC, DST, E}}, {{ 6, OP2, 0, DST, RELAX16 | ABS16LIST, E}}}, \ - {CODE, AV_H8, 6, NAME, {{ABS32SRC, DST, E}}, {{ 6, OP2, 2, DST, MEMRELAX | ABS32LIST, E}}} - -/* Expansion macros for two-word (plus data) instructions. */ - -/* Expansion from one source to "standard" destinations. */ -#define EXPAND2_STD_SRC(CODE, WEIGHT, NAME, SRC, PREFIX, NIB1, NIB2) \ - {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, TO_POSTINC, NIB1, NIB2, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, TO_POSTDEC, NIB1, NIB2, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC, E}}, {{PREFIX, TO_PREINC, NIB1, NIB2, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC, E}}, {{PREFIX, TO_PREDEC, NIB1, NIB2, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST, E}}, {{PREFIX, TO_DISP2, NIB1, NIB2, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}}, {{PREFIX, TO_DISP16, NIB1, NIB2, DSTDISP16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}}, {{PREFIX, TO_DISP32, NIB1, NIB2, DSTDISP32LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, TO_DISP16B, NIB1, NIB2, DSTDISP16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}}, {{PREFIX, TO_DISP16W, NIB1, NIB2, DSTDISP16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}}, {{PREFIX, TO_DISP16L, NIB1, NIB2, DSTDISP16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{PREFIX, TO_DISP32B, NIB1, NIB2, DSTDISP32LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{PREFIX, TO_DISP32W, NIB1, NIB2, DSTDISP32LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{PREFIX, TO_DISP32L, NIB1, NIB2, DSTDISP32LIST, E}}} - -/* Expansion from one destination to "standard" sources. */ -#define EXPAND2_STD_DST(CODE, WEIGHT, NAME, DST, PREFIX, NIB1, NIB2) \ - {CODE, AV_H8SX, 0, NAME, {{RSPOSTINC, DST, E}}, {{PREFIX, FROM_POSTINC, NIB1, NIB2, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{RSPOSTDEC, DST, E}}, {{PREFIX, FROM_POSTDEC, NIB1, NIB2, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{RSPREINC, DST, E}}, {{PREFIX, FROM_PREINC, NIB1, NIB2, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{RSPREDEC, DST, E}}, {{PREFIX, FROM_PREDEC, NIB1, NIB2, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{DISP2SRC, DST, E}}, {{PREFIX, FROM_DISP2, NIB1, NIB2, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{DISP16SRC, DST, E}}, {{PREFIX, FROM_DISP16, NIB1, NIB2, DISP16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{DISP32SRC, DST, E}}, {{PREFIX, FROM_DISP32, NIB1, NIB2, DISP32LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{INDEXB16, DST, E}}, {{PREFIX, FROM_DISP16B, NIB1, NIB2, DISP16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{INDEXW16, DST, E}}, {{PREFIX, FROM_DISP16W, NIB1, NIB2, DISP16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{INDEXL16, DST, E}}, {{PREFIX, FROM_DISP16L, NIB1, NIB2, DISP16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{INDEXB32, DST, E}}, {{PREFIX, FROM_DISP32B, NIB1, NIB2, DISP32LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{INDEXW32, DST, E}}, {{PREFIX, FROM_DISP32W, NIB1, NIB2, DISP32LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{INDEXL32, DST, E}}, {{PREFIX, FROM_DISP32L, NIB1, NIB2, DISP32LIST, E}}} - -/* Expansion from immediate source to "standard" destinations. */ -#define EXPAND2_STD_IMM(CODE, WEIGHT, NAME, SRC, PREFIX, OPCODE, IGN, IMMLIST) \ - {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, TO_POSTINC, OPCODE, IGN, IMMLIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, TO_POSTDEC, OPCODE, IGN, IMMLIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC, E}}, {{PREFIX, TO_PREINC, OPCODE, IGN, IMMLIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC, E}}, {{PREFIX, TO_PREDEC, OPCODE, IGN, IMMLIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST, E}}, {{PREFIX, TO_DISP2, OPCODE, IGN, IMMLIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}}, {{PREFIX, TO_DISP16, OPCODE, IGN, DSTDISP16LIST, IMMLIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}}, {{PREFIX, TO_DISP32, OPCODE, IGN, DSTDISP32LIST, IMMLIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, TO_DISP16B, OPCODE, IGN, DSTDISP16LIST, IMMLIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}}, {{PREFIX, TO_DISP16W, OPCODE, IGN, DSTDISP16LIST, IMMLIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}}, {{PREFIX, TO_DISP16L, OPCODE, IGN, DSTDISP16LIST, IMMLIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{PREFIX, TO_DISP32B, OPCODE, IGN, DSTDISP32LIST, IMMLIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{PREFIX, TO_DISP32W, OPCODE, IGN, DSTDISP32LIST, IMMLIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{PREFIX, TO_DISP32L, OPCODE, IGN, DSTDISP32LIST, IMMLIST, E}}} - -/* Expansion from abs/disp source to "standard" destinations. */ -#define EXPAND2_STD_ABSDISP(CODE, WEIGHT, NAME, SRC, PREFIX, DSTLIST, NIB1, NIB2) \ - {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, DSTLIST, TO_POSTINC, NIB1, NIB2, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, DSTLIST, TO_POSTDEC, NIB1, NIB2, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC, E}}, {{PREFIX, DSTLIST, TO_PREINC, NIB1, NIB2, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC, E}}, {{PREFIX, DSTLIST, TO_PREDEC, NIB1, NIB2, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST, E}}, {{PREFIX, DSTLIST, TO_DISP2, NIB1, NIB2, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}}, {{PREFIX, DSTLIST, TO_DISP16, NIB1, NIB2, DSTDISP16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}}, {{PREFIX, DSTLIST, TO_DISP32, NIB1, NIB2, DSTDISP32LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, DSTLIST, TO_DISP16B, NIB1, NIB2, DSTDISP16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}}, {{PREFIX, DSTLIST, TO_DISP16W, NIB1, NIB2, DSTDISP16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}}, {{PREFIX, DSTLIST, TO_DISP16L, NIB1, NIB2, DSTDISP16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{PREFIX, DSTLIST, TO_DISP32B, NIB1, NIB2, DSTDISP32LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{PREFIX, DSTLIST, TO_DISP32W, NIB1, NIB2, DSTDISP32LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{PREFIX, DSTLIST, TO_DISP32L, NIB1, NIB2, DSTDISP32LIST, E}}} - -/* Expansion from ind source to "standard" destinations. */ -#define EXPAND2_STD_IND(CODE, WEIGHT, NAME, OPCODE, BIT) \ - {CODE, AV_H8SX, 0, NAME, {{RSIND, RDPOSTINC, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_POSTINC, OPCODE, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{RSIND, RDPOSTDEC, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_POSTDEC, OPCODE, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{RSIND, RDPREINC, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_PREINC, OPCODE, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{RSIND, RDPREDEC, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_PREDEC, OPCODE, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{RSIND, DISP2DST, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_DISP2, OPCODE, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{RSIND, DISP16DST, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_DISP16, OPCODE, IGNORE, DSTDISP16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{RSIND, DISP32DST, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_DISP32, OPCODE, IGNORE, DSTDISP32LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{RSIND, INDEXB16D, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_DISP16B, OPCODE, IGNORE, DSTDISP16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{RSIND, INDEXW16D, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_DISP16W, OPCODE, IGNORE, DSTDISP16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{RSIND, INDEXL16D, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_DISP16L, OPCODE, IGNORE, DSTDISP16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{RSIND, INDEXB32D, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_DISP32B, OPCODE, IGNORE, DSTDISP32LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{RSIND, INDEXW32D, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_DISP32W, OPCODE, IGNORE, DSTDISP32LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{RSIND, INDEXL32D, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_DISP32L, OPCODE, IGNORE, DSTDISP32LIST, E}}} - -/* Expansion macros for three word (plus data) instructions. */ - -#define EXPAND3_STD_SRC(CODE, WEIGHT, NAME, SRC, PREFIX, INFIX, OPCODE) \ - {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, INFIX, 8, RDPOSTINC, OPCODE, B30 | IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, INFIX, 10, RDPOSTDEC, OPCODE, B30 | IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC, E}}, {{PREFIX, INFIX, 9, RDPREINC, OPCODE, B30 | IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC, E}}, {{PREFIX, INFIX, 11, RDPREDEC, OPCODE, B30 | IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST, E}}, {{PREFIX, INFIX, B30 | B20 | DISP2DST, DSTDISPREG, OPCODE, B30 | IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}}, {{PREFIX, INFIX, 12, B30 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}}, {{PREFIX, INFIX, 12, B31 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP32LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, INFIX, 13, B30 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}}, {{PREFIX, INFIX, 14, B30 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}}, {{PREFIX, INFIX, 15, B30 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{PREFIX, INFIX, 13, B31 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP32LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{PREFIX, INFIX, 14, B31 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP32LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{PREFIX, INFIX, 15, B31 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP32LIST, E}}} - -#define EXPAND3_L_SRC(CODE, WEIGHT, NAME, SRC, PREFIX, INFIX, OPCODE) \ - {CODE, AV_H8SX, 0, NAME, {{SRC, RDIND, E}}, {{PREFIX, INFIX, 0, RDIND, OPCODE, B30 | IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, INFIX, 8, RDPOSTINC, OPCODE, B30 | IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, INFIX, 10, RDPOSTDEC, OPCODE, B30 | IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC, E}}, {{PREFIX, INFIX, 9, RDPREINC, OPCODE, B30 | IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC, E}}, {{PREFIX, INFIX, 11, RDPREDEC, OPCODE, B30 | IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST, E}}, {{PREFIX, INFIX, B30 | B20 | DISP2DST, DSTDISPREG, OPCODE, B30 | IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}}, {{PREFIX, INFIX, 12, B30 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}}, {{PREFIX, INFIX, 12, B31 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP32LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, INFIX, 13, B30 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}}, {{PREFIX, INFIX, 14, B30 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}}, {{PREFIX, INFIX, 15, B30 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{PREFIX, INFIX, 13, B31 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP32LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{PREFIX, INFIX, 14, B31 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP32LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{PREFIX, INFIX, 15, B31 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP32LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, ABS16DST, E}}, {{PREFIX, INFIX, 4, B30 | IGNORE, OPCODE, B30 | IGNORE, DSTABS16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, ABS32DST, E}}, {{PREFIX, INFIX, 4, B31 | IGNORE, OPCODE, B30 | IGNORE, DSTABS32LIST, E}}} - - -#define EXPAND_STD_MATRIX_L(CODE, NAME, OPCODE) \ - EXPAND3_L_SRC (CODE, 6, NAME, RSIND, PREFIX_0104, TFROM_IND, OPCODE), \ - EXPAND3_L_SRC (CODE, 6, NAME, RSPOSTINC, PREFIX_0104, TFROM_POSTINC, OPCODE), \ - EXPAND3_L_SRC (CODE, 6, NAME, RSPOSTDEC, PREFIX_0106, TFROM_POSTDEC, OPCODE), \ - EXPAND3_L_SRC (CODE, 6, NAME, RSPREINC, PREFIX_0105, TFROM_PREINC, OPCODE), \ - EXPAND3_L_SRC (CODE, 6, NAME, RSPREDEC, PREFIX_0107, TFROM_PREDEC, OPCODE), \ - EXPAND3_L_SRC (CODE, 6, NAME, DISP2SRC, PREFIX_010_D2, TFROM_DISP2, OPCODE), \ - EXPAND3_L_SRC (CODE, 6, NAME, DISP16SRC, PREFIX_0104, TFROM_DISP16, OPCODE), \ - EXPAND3_L_SRC (CODE, 6, NAME, DISP32SRC, PREFIX_78R4, TFROM_DISP32, OPCODE), \ - EXPAND3_L_SRC (CODE, 6, NAME, INDEXB16, PREFIX_0105, TFROM_DISP16B, OPCODE), \ - EXPAND3_L_SRC (CODE, 6, NAME, INDEXW16, PREFIX_0106, TFROM_DISP16W, OPCODE), \ - EXPAND3_L_SRC (CODE, 6, NAME, INDEXL16, PREFIX_0107, TFROM_DISP16L, OPCODE), \ - EXPAND3_L_SRC (CODE, 6, NAME, INDEXB32, PREFIX_78R5, TFROM_DISP32B, OPCODE), \ - EXPAND3_L_SRC (CODE, 6, NAME, INDEXW32, PREFIX_78R6, TFROM_DISP32W, OPCODE), \ - EXPAND3_L_SRC (CODE, 6, NAME, INDEXL32, PREFIX_78R7, TFROM_DISP32L, OPCODE), \ - EXPAND3_L_SRC (CODE, 6, NAME, ABS16SRC, PREFIX_0104, TFROM_ABS16, OPCODE), \ - EXPAND3_L_SRC (CODE, 6, NAME, ABS32SRC, PREFIX_0104, TFROM_ABS32, OPCODE) - - -#define EXPAND_STD_MATRIX_W(CODE, NAME, OPCODE) \ - EXPAND3_L_SRC (CODE, 4, NAME, RSPOSTINC, PREFIX_0154, TFROM_POSTINC, OPCODE), \ - EXPAND3_L_SRC (CODE, 4, NAME, RSPOSTDEC, PREFIX_0156, TFROM_POSTDEC, OPCODE), \ - EXPAND3_L_SRC (CODE, 4, NAME, RSPREINC, PREFIX_0155, TFROM_PREINC, OPCODE), \ - EXPAND3_L_SRC (CODE, 4, NAME, RSPREDEC, PREFIX_0157, TFROM_PREDEC, OPCODE), \ - EXPAND3_L_SRC (CODE, 4, NAME, DISP2SRC, PREFIX_015_D2, TFROM_DISP2, OPCODE), \ - EXPAND3_L_SRC (CODE, 4, NAME, DISP16SRC, PREFIX_0154, TFROM_DISP16, OPCODE), \ - EXPAND3_L_SRC (CODE, 4, NAME, DISP32SRC, PREFIX_78R4W, TFROM_DISP32, OPCODE), \ - EXPAND3_L_SRC (CODE, 4, NAME, INDEXB16, PREFIX_0155, TFROM_DISP16B, OPCODE), \ - EXPAND3_L_SRC (CODE, 4, NAME, INDEXW16, PREFIX_0156, TFROM_DISP16W, OPCODE), \ - EXPAND3_L_SRC (CODE, 4, NAME, INDEXL16, PREFIX_0157, TFROM_DISP16L, OPCODE), \ - EXPAND3_L_SRC (CODE, 4, NAME, INDEXB32, PREFIX_78R5W, TFROM_DISP32B, OPCODE), \ - EXPAND3_L_SRC (CODE, 4, NAME, INDEXW32, PREFIX_78R6W, TFROM_DISP32W, OPCODE), \ - EXPAND3_L_SRC (CODE, 4, NAME, INDEXL32, PREFIX_78R7W, TFROM_DISP32L, OPCODE) - -#define EXPAND_STD_MATRIX_B(CODE, NAME, OPCODE) \ - EXPAND3_L_SRC (CODE, 4, NAME, RSPOSTINC, PREFIX_0174, TFROM_POSTINC_B, OPCODE), \ - EXPAND3_L_SRC (CODE, 4, NAME, RSPOSTDEC, PREFIX_0176, TFROM_POSTDEC_B, OPCODE), \ - EXPAND3_L_SRC (CODE, 4, NAME, RSPREINC, PREFIX_0175, TFROM_PREINC_B, OPCODE), \ - EXPAND3_L_SRC (CODE, 4, NAME, RSPREDEC, PREFIX_0177, TFROM_PREDEC_B, OPCODE), \ - EXPAND3_L_SRC (CODE, 4, NAME, DISP2SRC, PREFIX_017_D2S, TFROM_DISP2_B, OPCODE), \ - EXPAND3_L_SRC (CODE, 4, NAME, DISP16SRC, PREFIX_0174, TFROM_DISP16_B, OPCODE), \ - EXPAND3_L_SRC (CODE, 4, NAME, DISP32SRC, PREFIX_78R4W, TFROM_DISP32_B, OPCODE), \ - EXPAND3_L_SRC (CODE, 4, NAME, INDEXB16, PREFIX_0175, TFROM_DISP16B_B, OPCODE), \ - EXPAND3_L_SRC (CODE, 4, NAME, INDEXW16, PREFIX_0176, TFROM_DISP16W_B, OPCODE), \ - EXPAND3_L_SRC (CODE, 4, NAME, INDEXL16, PREFIX_0177, TFROM_DISP16L_B, OPCODE), \ - EXPAND3_L_SRC (CODE, 4, NAME, INDEXB32, PREFIX_78R5W, TFROM_DISP32B_B, OPCODE), \ - EXPAND3_L_SRC (CODE, 4, NAME, INDEXW32, PREFIX_78R6W, TFROM_DISP32W_B, OPCODE), \ - EXPAND3_L_SRC (CODE, 4, NAME, INDEXL32, PREFIX_78R7W, TFROM_DISP32L_B, OPCODE) - - -/* Use the expansion macros to fill out the opcode table. */ - -#define EXPAND_FROM_REG8(CODE, NAME, OP1, OP2, OP3) \ - {CODE, AV_H8SX, 0, NAME, {{RS8, RDIND, E}}, {{0x7, 0xd, B30 | RDIND, IGNORE, OP1, OP2, RS8, IGNORE, E}}}, \ - EXPAND2_STD_SRC (CODE, 2, NAME, RS8, PREFIX_0179, OP3, RS8), \ - {CODE, AV_H8SX, 0, NAME, {{RS8, ABS8DST, E}}, {{0x7, 0xf, DSTABS8LIST, OP1, OP2, RS8, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{RS8, ABS16DST, E}}, {{0x6, 0xa, 0x1, B31 | IGNORE, DSTABS16LIST, OP1, OP2, RS8, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{RS8, ABS32DST, E}}, {{0x6, 0xa, 0x3, B31 | IGNORE, DSTABS32LIST, OP1, OP2, RS8, IGNORE, E}}} - -#define EXPAND_TO_REG8(CODE, NAME, OP1, OP2, OP3) \ - {CODE, AV_H8SX, 0, NAME, {{RSIND, RD8, E}}, {{0x7, 0xc, B30 | RSIND, IGNORE, OP1, OP2, IGNORE, RD8, E}}}, \ - EXPAND2_STD_DST (CODE, 2, NAME, RD8, PREFIX_017A, OP3, RD8), \ - {CODE, AV_H8SX, 0, NAME, {{ABS8SRC, RD8, E}}, {{0x7, 0xe, ABS8LIST, OP1, OP2, IGNORE, RD8, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, RD8, E}}, {{0x6, 0xa, 0x1, B30 | IGNORE, ABS16LIST, OP1, OP2, IGNORE, RD8, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, RD8, E}}, {{0x6, 0xa, 0x3, B30 | IGNORE, ABS32LIST, OP1, OP2, IGNORE, RD8, E}}} - -#define EXPAND_FROM_IND8(CODE, NAME, OPCODE) \ - {CODE, AV_H8SX, 0, NAME, {{RSIND, RDIND, E}}, {{0x7, 0xc, B30 | RSIND, 0x5, TO_IND, OPCODE, IGNORE, E}}}, \ - EXPAND2_STD_IND (CODE, 2, NAME, OPCODE, B30), \ - {CODE, AV_H8SX, 0, NAME, {{RSIND, ABS16DST, E}}, {{0x7, 0xc, B30 | RSIND, 0x5, TO_ABS16, OPCODE, IGNORE, DSTABS16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{RSIND, ABS32DST, E}}, {{0x7, 0xc, B30 | RSIND, 0x5, TO_ABS32, OPCODE, IGNORE, DSTABS32LIST, E}}} - -#define EXPAND_FROM_ABS16_B(CODE, NAME, OPCODE) \ - {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, RDIND, E}}, {{PREFIX_6A15, ABS16LIST, TO_IND, OPCODE, IGNORE, E}}}, \ - EXPAND2_STD_ABSDISP (CODE, 2, NAME, ABS16SRC, PREFIX_6A15, ABS16LIST, OPCODE, IGNORE), \ - {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, ABS16DST, E}}, {{PREFIX_6A15, ABS16LIST, TO_ABS16, OPCODE, IGNORE, DSTABS16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, ABS32DST, E}}, {{PREFIX_6A15, ABS16LIST, TO_ABS32, OPCODE, IGNORE, DSTABS32LIST, E}}} - -#define EXPAND_FROM_ABS32_B(CODE, NAME, OPCODE) \ - {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, RDIND, E}}, {{PREFIX_6A35, ABS32LIST, TO_IND, OPCODE, IGNORE, E}}}, \ - EXPAND2_STD_ABSDISP (CODE, 2, NAME, ABS32SRC, PREFIX_6A35, ABS32LIST, OPCODE, IGNORE), \ - {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, ABS16DST, E}}, {{PREFIX_6A35, ABS32LIST, TO_ABS16, OPCODE, IGNORE, DSTABS16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, ABS32DST, E}}, {{PREFIX_6A35, ABS32LIST, TO_ABS32, OPCODE, IGNORE, DSTABS32LIST, E}}} - -#define EXPAND_FROM_IMM16_W(CODE, NAME, OPCODE) \ - {CODE, AV_H8SX, 0, NAME, {{IMM16, RDIND, E}}, {{PREFIX_015E, TO_IND, OPCODE, IGNORE, IMM16LIST, E}}}, \ - EXPAND2_STD_IMM (CODE, 2, NAME, IMM16, PREFIX_015E, OPCODE, IGNORE, IMM16LIST), \ - {CODE, AV_H8SX, 0, NAME, {{IMM16, ABS16DST, E}}, {{PREFIX_015E, TO_ABS16, OPCODE, IGNORE, DSTABS16LIST, IMM16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{IMM16, ABS32DST, E}}, {{PREFIX_015E, TO_ABS32, OPCODE, IGNORE, DSTABS32LIST, IMM16LIST, E}}} - -#define EXPAND_FROM_REG16(CODE, NAME, OP1, OP2, OP3) \ - {CODE, AV_H8, 2, NAME, {{RS16, RDIND, E}}, {{0x7, 0xd, B31 | RDIND, IGNORE, OP1, OP2, RS16, IGNORE, E}}}, \ - EXPAND2_STD_SRC (CODE, 2, NAME, RS16, PREFIX_0159, OP3, RS16), \ - {CODE, AV_H8SX, 0, NAME, {{RS16, ABS16DST, E}}, {{0x6, 0xb, 0x1, B31 | IGNORE, DSTABS16LIST, OP1, OP2, RS16, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{RS16, ABS32DST, E}}, {{0x6, 0xb, 0x3, B31 | IGNORE, DSTABS32LIST, OP1, OP2, RS16, IGNORE, E}}} - -#define EXPAND_TO_REG16(CODE, NAME, OP1, OP2, OP3) \ - {CODE, AV_H8SX, 0, NAME, {{RSIND, RD16, E}}, {{0x7, 0xc, B31 | RSIND, IGNORE, OP1, OP2, IGNORE, RD16, E}}}, \ - EXPAND2_STD_DST (CODE, 2, NAME, RD16, PREFIX_015A, OP3, RD16), \ - {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, RD16, E}}, {{0x6, 0xb, 0x1, B30 | IGNORE, ABS16LIST, OP1, OP2, IGNORE, RD16, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, RD16, E}}, {{0x6, 0xb, 0x3, B30 | IGNORE, ABS32LIST, OP1, OP2, IGNORE, RD16, E}}} - -#define EXPAND_FROM_IND16(CODE, NAME, OPCODE) \ - {CODE, AV_H8SX, 0, NAME, {{RSIND, RDIND, E}}, {{0x7, 0xc, B31 | RSIND, 0x5, TO_IND, OPCODE, IGNORE, E}}}, \ - EXPAND2_STD_IND (CODE, 2, NAME, OPCODE, B31), \ - {CODE, AV_H8SX, 0, NAME, {{RSIND, ABS16DST, E}}, {{0x7, 0xc, B31 | RSIND, 0x5, TO_ABS16, OPCODE, IGNORE, DSTABS16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{RSIND, ABS32DST, E}}, {{0x7, 0xc, B31 | RSIND, 0x5, TO_ABS32, OPCODE, IGNORE, DSTABS32LIST, E}}} - -#define EXPAND_FROM_ABS16_W(CODE, NAME, OPCODE) \ - {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, RDIND, E}}, {{PREFIX_6B15, ABS16LIST, TO_IND, OPCODE, IGNORE, E}}}, \ - EXPAND2_STD_ABSDISP (CODE, 2, NAME, ABS16SRC, PREFIX_6B15, ABS16LIST, OPCODE, IGNORE), \ - {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, ABS16DST, E}}, {{PREFIX_6B15, ABS16LIST, TO_ABS16, OPCODE, IGNORE, DSTABS16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, ABS32DST, E}}, {{PREFIX_6B15, ABS16LIST, TO_ABS32, OPCODE, IGNORE, DSTABS32LIST, E}}} - -#define EXPAND_FROM_ABS32_W(CODE, NAME, OPCODE) \ - {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, RDIND, E}}, {{PREFIX_6B35, ABS32LIST, TO_IND, OPCODE, IGNORE, E}}}, \ - EXPAND2_STD_ABSDISP (CODE, 2, NAME, ABS32SRC, PREFIX_6B35, ABS32LIST, OPCODE, IGNORE), \ - {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, ABS16DST, E}}, {{PREFIX_6B35, ABS32LIST, TO_ABS16, OPCODE, IGNORE, DSTABS16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, ABS32DST, E}}, {{PREFIX_6B35, ABS32LIST, TO_ABS32, OPCODE, IGNORE, DSTABS32LIST, E}}} - -#define EXPAND_FROM_IMM16_L(CODE, NAME, OPCODE) \ - {CODE, AV_H8SX, 0, NAME, {{IMM16U_NS, RDIND, E}}, {{PREFIX_010E, TO_IND, OPCODE, B30 | IGNORE, IMM16ULIST, E}}}, \ - EXPAND2_STD_IMM (CODE, 2, NAME, IMM16U_NS, PREFIX_010E, OPCODE, B30 | IGNORE, IMM16ULIST), \ - {CODE, AV_H8SX, 0, NAME, {{IMM16U_NS, ABS16DST, E}}, {{PREFIX_010E, TO_ABS16, OPCODE, B30 | IGNORE, DSTABS16LIST, IMM16ULIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{IMM16U_NS, ABS32DST, E}}, {{PREFIX_010E, TO_ABS32, OPCODE, B30 | IGNORE, DSTABS32LIST, IMM16ULIST, E}}} - -#define EXPAND_FROM_IMM32_L(CODE, NAME, OPCODE) \ - {CODE, AV_H8SX, 0, NAME, {{IMM32, RDIND, E}}, {{PREFIX_010E, TO_IND, OPCODE, B31 | IGNORE, IMM32LIST, E}}}, \ - EXPAND2_STD_IMM (CODE, 2, NAME, IMM32, PREFIX_010E, OPCODE, B31 | IGNORE, IMM32LIST), \ - {CODE, AV_H8SX, 0, NAME, {{IMM32, ABS16DST, E}}, {{PREFIX_010E, TO_ABS16, OPCODE, B31 | IGNORE, DSTABS16LIST, IMM32LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{IMM32, ABS32DST, E}}, {{PREFIX_010E, TO_ABS32, OPCODE, B31 | IGNORE, DSTABS32LIST, IMM32LIST, E}}} - -#define EXPAND_FROM_REG32(CODE, NAME, OPCODE) \ - {CODE, AV_H8SX, 0, NAME, {{RS32, RDIND, E}}, {{PREFIX_0109, TO_IND, OPCODE, B30 | RS32, E}}}, \ - EXPAND2_STD_SRC (CODE, 2, NAME, RS32, PREFIX_0109, OPCODE, B30 | RS32), \ - {CODE, AV_H8SX, 0, NAME, {{RS32, ABS16DST, E}}, {{PREFIX_0109, TO_ABS16, OPCODE, B30 | RS32, DSTABS16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{RS32, ABS32DST, E}}, {{PREFIX_0109, TO_ABS32, OPCODE, B30 | RS32, DSTABS32LIST, E}}} - -#define EXPAND_TO_REG32(CODE, NAME, OPCODE) \ - {CODE, AV_H8SX, 0, NAME, {{RSIND, RD32, E}}, {{PREFIX_010A, FROM_IND, OPCODE, B30 | RD32, E}}}, \ - EXPAND2_STD_DST (CODE, 2, NAME, RD32, PREFIX_010A, OPCODE, B30 | RD32), \ - {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, RD32, E}}, {{PREFIX_010A, FROM_ABS16, OPCODE, B30 | RD32, ABS16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, RD32, E}}, {{PREFIX_010A, FROM_ABS32, OPCODE, B30 | RD32, ABS32LIST, E}}} - - -#define EXPAND_TWOOP_B(CODE, NAME, OP1, OP2, OP3, OP4, BIT) \ - {CODE, AV_H8SX, 0, NAME, {{IMM8, RDIND, E}}, {{0x7, 0xd, B30 | RDIND, IGNORE, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{IMM8, RDPOSTINC, E}}, {{PREFIX_0174, 0x6, 0xc, B30 | RDPOSTINC, B31 | B20 | IGNORE, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{IMM8, RDPOSTDEC, E}}, {{PREFIX_0176, 0x6, 0xc, B30 | RDPOSTDEC, B31 | B20 | IGNORE, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{IMM8, RDPREINC, E}}, {{PREFIX_0175, 0x6, 0xc, B30 | RDPREINC, B31 | B20 | IGNORE, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{IMM8, RDPREDEC, E}}, {{PREFIX_0177, 0x6, 0xc, B30 | RDPREDEC, B31 | B20 | IGNORE, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{IMM8, DISP2DST, E}}, {{PREFIX_017_D2D, 0x6, 0x8, B30 | DSTDISPREG, B31 | B20 | IGNORE, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{IMM8, DISP16DST, E}}, {{PREFIX_0174, 0x6, 0xe, B30 | DSTDISPREG, B31 | B20 | IGNORE, DSTDISP16LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{IMM8, DISP32DST, E}}, {{PREFIX_78R4WD, 0x6, 0xa, 2, B31 | B20 | IGNORE, DSTDISP32LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{IMM8, INDEXB16D, E}}, {{PREFIX_0175, 0x6, 0xe, B30 | DSTDISPREG, B31 | B20 | IGNORE, DSTDISP16LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{IMM8, INDEXW16D, E}}, {{PREFIX_0176, 0x6, 0xe, B30 | DSTDISPREG, B31 | B20 | IGNORE, DSTDISP16LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{IMM8, INDEXL16D, E}}, {{PREFIX_0177, 0x6, 0xe, B30 | DSTDISPREG, B31 | B20 | IGNORE, DSTDISP16LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{IMM8, INDEXB32D, E}}, {{PREFIX_78R5WD, 0x6, 0xa, 2, B31 | B20 | IGNORE, DSTDISP32LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{IMM8, INDEXW32D, E}}, {{PREFIX_78R6WD, 0x6, 0xa, 2, B31 | B20 | IGNORE, DSTDISP32LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{IMM8, INDEXL32D, E}}, {{PREFIX_78R7WD, 0x6, 0xa, 2, B31 | B20 | IGNORE, DSTDISP32LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{IMM8, ABS8DST, E}}, {{0x7, 0xf, DSTABS8LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{IMM8, ABS16DST, E}}, {{0x6, 0xa, 0x1, B31 | B20 | IGNORE, DSTABS16LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{IMM8, ABS32DST, E}}, {{0x6, 0xa, 0x3, B31 | B20 | IGNORE, DSTABS32LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ - {CODE, AV_H8, 2, NAME, {{RS8, RD8, E}}, {{OP2, OP3, RS8, RD8, E}}}, \ - EXPAND_FROM_REG8 (CODE, NAME, OP2, OP3, OP4), \ - EXPAND_TO_REG8 (CODE, NAME, OP2, OP3, OP4), \ - EXPAND_FROM_IND8 (CODE, NAME, OP4), \ - EXPAND_STD_MATRIX_B (CODE, NAME, OP4), \ - EXPAND_FROM_ABS16_B (CODE, NAME, OP4), \ - EXPAND_FROM_ABS32_B (CODE, NAME, OP4) - -#define EXPAND_TWOOP_W(CODE, NAME, OP1, OP2, OP3) \ - {CODE, AV_H8H, 6, NAME, {{IMM16, RD16, E}}, {{0x7, 0x9, OP3, RD16, IMM16LIST, E}}}, \ - EXPAND_FROM_IMM16_W (CODE, NAME, OP3), \ - EXPAND_FROM_REG16 (CODE, NAME, OP1, OP2, OP3), \ - EXPAND_TO_REG16 (CODE, NAME, OP1, OP2, OP3), \ - EXPAND_FROM_IND16 (CODE, NAME, OP3), \ - EXPAND_STD_MATRIX_W (CODE, NAME, OP3), \ - EXPAND_FROM_ABS16_W (CODE, NAME, OP3), \ - EXPAND_FROM_ABS32_W (CODE, NAME, OP3) - -#define EXPAND_TWOOP_L(CODE, NAME, OP1) \ - {CODE, AV_H8SX, 0, NAME, {{IMM16U_NS, RD32, E}}, {{0x7, 0xa, OP1, B31 | RD32, IMM16ULIST, E}}}, \ - {CODE, AV_H8H, 6, NAME, {{IMM32, RD32, E}}, {{0x7, 0xa, OP1, B30 | RD32, IMM32LIST, E}}}, \ - EXPAND_FROM_IMM16_L (CODE, NAME, OP1), \ - EXPAND_FROM_IMM32_L (CODE, NAME, OP1), \ - EXPAND_FROM_REG32 (CODE, NAME, OP1), \ - EXPAND_TO_REG32 (CODE, NAME, OP1), \ - EXPAND_STD_MATRIX_L (CODE, NAME, OP1) - - -/* Old expanders: */ - -#define BITOP(code, imm, name, op00, op01, op10, op11, op20, op21, op30, op4) \ - {code, AV_H8, 2, name, {{imm, RD8, E}}, {{op00, op01, imm, RD8, E}}}, \ - {code, AV_H8, 6, name, {{imm, RDIND, E}}, {{op10, op11, B30 | RDIND, 0, op00, op01, imm, 0, E}}}, \ - {code, AV_H8, 6, name, {{imm, ABS8DST, E}}, {{op20, op21, DSTABS8LIST, op00, op01, imm, 0, E}}}, \ - {code, AV_H8S, 6, name, {{imm, ABS16DST, E}}, {{0x6, 0xa, 0x1, op30, DST | MEMRELAX | ABS16LIST , op00, op01, imm, op4, E}}}, \ - {code, AV_H8S, 6, name, {{imm, ABS32DST, E}}, {{0x6, 0xa, 0x3, op30, DST | MEMRELAX | ABS32LIST , op00, op01, imm, op4, E}}} - -#define BITOP_B(code, imm, name, op00, op01, op10, op11, op20, op21, op30, op4) \ - {code, AV_H8SX, 0, name, {{imm, RDIND, E}}, {{op10, op11, B30 | RDIND, 0, op00, op01, imm, op4, E}}}, \ - {code, AV_H8SX, 0, name, {{imm, ABS8DST, E}}, {{op20, op21, DSTABS8LIST, op00, op01, imm, op4, E}}}, \ - {code, AV_H8SX, 0, name, {{imm, ABS16DST, E}}, {{0x6, 0xa, 0x1, op30, DST | ABS16LIST, op00, op01, imm, op4, E}}}, \ - {code, AV_H8SX, 0, name, {{imm, ABS32DST, E}}, {{0x6, 0xa, 0x3, op30, DST | ABS32LIST, op00, op01, imm, op4, E}}} - -#define EBITOP(code, imm, name, op00, op01, op10, op11, op20, op21, op30, op4) \ - BITOP(code, imm, name, op00+1, op01, op10, op11, op20, op21, op30, op4), \ - BITOP(code, RS8, name, op00, op01, op10, op11, op20, op21, op30, op4) - -#define EBITOP_B(code, imm, name, op00, op01, op10, op11, op20, op21, op30, op4) \ - BITOP_B(code, imm, name, op00+1, op01, op10, op11, op20, op21, op30, op4), \ - BITOP_B(code, RS8, name, op00, op01, op10, op11, op20, op21, op30, op4) - -#define WTWOP(code, name, op1, op2) \ - {code, AV_H8, 2, name, {{RS16, RD16, E}}, {{op1, op2, RS16, RD16, E}}} - -#define BRANCH(code, name, op) \ - {code, AV_H8H, 6, name, {{PCREL16, E}}, {{0x5, 0x8, op, 0x0, PCREL16, DATA3 | B00, E}}}, \ - {code, AV_H8, 4, name, {{PCREL8, E}}, {{0x4, op, PCREL8, DATA | B00, E}}} - - -#define UNOP(code, name, op1, op2) \ - {code, AV_H8, 2, name, {{OR8, E}}, {{op1, op2, 0, OR8, E}}} - -#define EXPAND_UNOP_STD_B(CODE, NAME, PREFIX, OP1, OP2, OP3) \ - {CODE, AV_H8, 2, NAME, {{OR8, E}}, {{ OP1, OP2, OP3, OR8, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{RSIND, E}}, {{ 7, 13, B30 | RSIND, IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{RSPOSTINC, E}}, {{PREFIX, 4, 6, 12, B30 | RSPOSTINC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{RSPOSTDEC, E}}, {{PREFIX, 6, 6, 12, B30 | RSPOSTDEC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{RSPREINC, E}}, {{PREFIX, 5, 6, 12, B30 | RSPREINC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{RSPREDEC, E}}, {{PREFIX, 7, 6, 12, B30 | RSPREDEC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{DISP2SRC, E}}, {{PREFIX, B30 | B21 | DISP2SRC, 6, 8, B30 | DISPREG, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{DISP16SRC, E}}, {{PREFIX, 4, 6, 14, B30 | DISPREG, B31 | IGNORE, DISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{DISP32SRC, E}}, {{7, 8, B30 | DISPREG, 4, 6, 10, 2, B31 | IGNORE, DISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{INDEXB16, E}}, {{PREFIX, 5, 6, 14, B30 | DISPREG, B31 | IGNORE, DISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{INDEXW16, E}}, {{PREFIX, 6, 6, 14, B30 | DISPREG, B31 | IGNORE, DISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{INDEXL16, E}}, {{PREFIX, 7, 6, 14, B30 | DISPREG, B31 | IGNORE, DISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{INDEXB32, E}}, {{7, 8, B30 | DISPREG, 5, 6, 10, 2, B31 | IGNORE, DISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{INDEXW32, E}}, {{7, 8, B30 | DISPREG, 6, 6, 10, 2, B31 | IGNORE, DISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{INDEXL32, E}}, {{7, 8, B30 | DISPREG, 7, 6, 10, 2, B31 | IGNORE, DISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{ABS8SRC, E}}, {{ 7, 15, ABS8LIST, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, E}}, {{ 6, 10, 1, B31 | IGNORE, ABS16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, E}}, {{ 6, 10, 3, B31 | IGNORE, ABS32LIST, OP1, OP2, OP3, IGNORE, E}}} - -#define EXPAND_UNOP_STD_W(CODE, NAME, PREFIX, OP1, OP2, OP3) \ - {CODE, AV_H8H, 2, NAME, {{OR16, E}}, {{ OP1, OP2, OP3, OR16, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{RSIND, E}}, {{ 7, 13, B31 | RSIND, IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{RSPOSTINC, E}}, {{PREFIX, 4, 6, 13, B30 | RSPOSTINC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{RSPOSTDEC, E}}, {{PREFIX, 6, 6, 13, B30 | RSPOSTDEC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{RSPREINC, E}}, {{PREFIX, 5, 6, 13, B30 | RSPREINC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{RSPREDEC, E}}, {{PREFIX, 7, 6, 13, B30 | RSPREDEC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{DISP2SRC, E}}, {{PREFIX, B30 | B21 | DISP2SRC, 6, 9, B30 | DISPREG, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{DISP16SRC, E}}, {{PREFIX, 4, 6, 15, B30 | DISPREG, B31 | IGNORE, DISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{DISP32SRC, E}}, {{7, 8, B30 | DISPREG, 4, 6, 11, 2, B31 | IGNORE, DISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{INDEXB16, E}}, {{PREFIX, 5, 6, 15, B30 | DISPREG, B31 | IGNORE, DISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{INDEXW16, E}}, {{PREFIX, 6, 6, 15, B30 | DISPREG, B31 | IGNORE, DISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{INDEXL16, E}}, {{PREFIX, 7, 6, 15, B30 | DISPREG, B31 | IGNORE, DISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{INDEXB32, E}}, {{7, 8, B30 | DISPREG, 5, 6, 11, 2, B31 | IGNORE, DISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{INDEXW32, E}}, {{7, 8, B30 | DISPREG, 6, 6, 11, 2, B31 | IGNORE, DISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{INDEXL32, E}}, {{7, 8, B30 | DISPREG, 7, 6, 11, 2, B31 | IGNORE, DISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, E}}, {{ 6, 11, 1, B31 | IGNORE, ABS16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, E}}, {{ 6, 11, 3, B31 | IGNORE, ABS32LIST, OP1, OP2, OP3, IGNORE, E}}} - -#define EXPAND_UNOP_STD_L(CODE, NAME, PREFIX, OP1, OP2, OP3) \ - {CODE, AV_H8H, 2, NAME, {{OR32, E}}, {{ OP1, OP2, OP3, B30 | OR32, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{RSIND, E}}, {{PREFIX, 4, 6, 9, B30 | RSIND, B31 | IGNORE, OP1, OP2, OP3, B30 | IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{RSPOSTINC, E}}, {{PREFIX, 4, 6, 13, B30 | RSPOSTINC, B31 | IGNORE, OP1, OP2, OP3, B30 | IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{RSPOSTDEC, E}}, {{PREFIX, 6, 6, 13, B30 | RSPOSTDEC, B31 | IGNORE, OP1, OP2, OP3, B30 | IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{RSPREINC, E}}, {{PREFIX, 5, 6, 13, B30 | RSPREINC, B31 | IGNORE, OP1, OP2, OP3, B30 | IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{RSPREDEC, E}}, {{PREFIX, 7, 6, 13, B30 | RSPREDEC, B31 | IGNORE, OP1, OP2, OP3, B30 | IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{DISP2SRC, E}}, {{PREFIX, B30 | B21 | DISP2SRC, 6, 9, B30 | DISPREG, B31 | IGNORE, OP1, OP2, OP3, B30 | IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{DISP16SRC, E}}, {{PREFIX, 4, 6, 15, B30 | DISPREG, B31 | IGNORE, DISP16LIST, OP1, OP2, OP3, B30 | IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{DISP32SRC, E}}, {{7, 8, B31 | DISPREG, 4, 6, 11, 2, B31 | IGNORE, DISP32LIST, OP1, OP2, OP3, B30 | IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{INDEXB16, E}}, {{PREFIX, 5, 6, 15, B30 | DISPREG, B31 | IGNORE, DISP16LIST, OP1, OP2, OP3, B30 | IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{INDEXW16, E}}, {{PREFIX, 6, 6, 15, B30 | DISPREG, B31 | IGNORE, DISP16LIST, OP1, OP2, OP3, B30 | IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{INDEXL16, E}}, {{PREFIX, 7, 6, 15, B30 | DISPREG, B31 | IGNORE, DISP16LIST, OP1, OP2, OP3, B30 | IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{INDEXB32, E}}, {{7, 8, B31 | DISPREG, 5, 6, 11, 2, B31 | IGNORE, DISP32LIST, OP1, OP2, OP3, B30 | IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{INDEXW32, E}}, {{7, 8, B31 | DISPREG, 6, 6, 11, 2, B31 | IGNORE, DISP32LIST, OP1, OP2, OP3, B30 | IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{INDEXL32, E}}, {{7, 8, B31 | DISPREG, 7, 6, 11, 2, B31 | IGNORE, DISP32LIST, OP1, OP2, OP3, B30 | IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, E}}, {{PREFIX, 4, 6, 11, 0, B31 | IGNORE, ABS16LIST, OP1, OP2, OP3, B30 | IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, E}}, {{PREFIX, 4, 6, 11, 2, B31 | IGNORE, ABS32LIST, OP1, OP2, OP3, B30 | IGNORE, E}}} - -#define EXPAND_UNOP_EXTENDED_B(CODE, NAME, CONST, PREFIX, OP1, OP2, OP3) \ - {CODE, AV_H8, 2, NAME, {{CONST, RD8, E}}, {{ OP1, OP2, OP3, RD8, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, RDIND, E}}, {{ 7, 13, B30 | RDIND, IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, RDPOSTINC, E}}, {{PREFIX, 4, 6, 12, B30 | RDPOSTINC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, RDPOSTDEC, E}}, {{PREFIX, 6, 6, 12, B30 | RDPOSTDEC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, RDPREINC, E}}, {{PREFIX, 5, 6, 12, B30 | RDPREINC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, RDPREDEC, E}}, {{PREFIX, 7, 6, 12, B30 | RDPREDEC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, DISP2DST, E}}, {{PREFIX, B30 | B21 | DISP2DST, 6, 8, B30 | DSTDISPREG, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, DISP16DST, E}}, {{PREFIX, 4, 6, 14, B30 | DSTDISPREG, B31 | IGNORE, DSTDISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, DISP32DST, E}}, {{7, 8, B30 | DSTDISPREG, 4, 6, 10, 2, B31 | IGNORE, DSTDISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXB16D, E}}, {{PREFIX, 5, 6, 14, B30 | DSTDISPREG, B31 | IGNORE, DSTDISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXW16D, E}}, {{PREFIX, 6, 6, 14, B30 | DSTDISPREG, B31 | IGNORE, DSTDISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXL16D, E}}, {{PREFIX, 7, 6, 14, B30 | DSTDISPREG, B31 | IGNORE, DSTDISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXB32D, E}}, {{7, 8, B30 | DSTDISPREG, 5, 6, 10, 2, B31 | IGNORE, DSTDISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXW32D, E}}, {{7, 8, B30 | DSTDISPREG, 6, 6, 10, 2, B31 | IGNORE, DSTDISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXL32D, E}}, {{7, 8, B30 | DSTDISPREG, 7, 6, 10, 2, B31 | IGNORE, DSTDISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, ABS8DST, E}}, {{ 7, 15, DSTABS8LIST, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, ABS16DST, E}}, {{ 6, 10, 1, B31 | IGNORE, DSTABS16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, ABS32DST, E}}, {{ 6, 10, 3, B31 | IGNORE, DSTABS32LIST, OP1, OP2, OP3, IGNORE, E}}} - -#define EXPAND_UNOP_EXTENDED_W(CODE, NAME, CONST, PREFIX, OP1, OP2, OP3) \ - {CODE, AV_H8, 2, NAME, {{CONST, RD16, E}}, {{ OP1, OP2, OP3, RD16, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, RDIND, E}}, {{ 7, 13, B31 | RDIND, IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, RDPOSTINC, E}}, {{PREFIX, 4, 6, 13, B30 | RDPOSTINC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, RDPOSTDEC, E}}, {{PREFIX, 6, 6, 13, B30 | RDPOSTDEC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, RDPREINC, E}}, {{PREFIX, 5, 6, 13, B30 | RDPREINC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, RDPREDEC, E}}, {{PREFIX, 7, 6, 13, B30 | RDPREDEC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, DISP2DST, E}}, {{PREFIX, B30 | B21 | DISP2DST, 6, 9, B30 | DSTDISPREG, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, DISP16DST, E}}, {{PREFIX, 4, 6, 15, B30 | DSTDISPREG, B31 | IGNORE, DSTDISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, DISP32DST, E}}, {{7, 8, B30 | DSTDISPREG, 4, 6, 11, 2, B31 | IGNORE, DSTDISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXB16D, E}}, {{PREFIX, 5, 6, 15, B30 | DSTDISPREG, B31 | IGNORE, DSTDISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXW16D, E}}, {{PREFIX, 6, 6, 15, B30 | DSTDISPREG, B31 | IGNORE, DSTDISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXL16D, E}}, {{PREFIX, 7, 6, 15, B30 | DSTDISPREG, B31 | IGNORE, DSTDISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXB32D, E}}, {{7, 8, B30 | DSTDISPREG, 5, 6, 11, 2, B31 | IGNORE, DSTDISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXW32D, E}}, {{7, 8, B30 | DSTDISPREG, 6, 6, 11, 2, B31 | IGNORE, DSTDISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXL32D, E}}, {{7, 8, B30 | DSTDISPREG, 7, 6, 11, 2, B31 | IGNORE, DSTDISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, ABS16DST, E}}, {{ 6, 11, 1, B31 | IGNORE, DSTABS16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, ABS32DST, E}}, {{ 6, 11, 3, B31 | IGNORE, DSTABS32LIST, OP1, OP2, OP3, IGNORE, E}}} - -#define EXPAND_UNOP_EXTENDED_L(CODE, NAME, CONST, PREFIX, OP1, OP2, OP3, BIT) \ - {CODE, AV_H8, 2, NAME, {{CONST, RD32, E}}, {{ OP1, OP2, OP3, BIT | RD32, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, RDIND, E}}, {{PREFIX, 4, 6, 9, B30 | RDIND, B31 | IGNORE, OP1, OP2, OP3, BIT | IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, RDPOSTINC, E}}, {{PREFIX, 4, 6, 13, B30 | RDPOSTINC, B31 | IGNORE, OP1, OP2, OP3, BIT | IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, RDPOSTDEC, E}}, {{PREFIX, 6, 6, 13, B30 | RDPOSTDEC, B31 | IGNORE, OP1, OP2, OP3, BIT | IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, RDPREINC, E}}, {{PREFIX, 5, 6, 13, B30 | RDPREINC, B31 | IGNORE, OP1, OP2, OP3, BIT | IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, RDPREDEC, E}}, {{PREFIX, 7, 6, 13, B30 | RDPREDEC, B31 | IGNORE, OP1, OP2, OP3, BIT | IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, DISP2DST, E}}, {{PREFIX, B30 | B21 | DISP2DST, 6, 9, B30 | DSTDISPREG, B31 | IGNORE, OP1, OP2, OP3, BIT | IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, DISP16DST, E}}, {{PREFIX, 4, 6, 15, B30 | DSTDISPREG, B31 | IGNORE, DSTDISP16LIST, OP1, OP2, OP3, BIT | IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, DISP32DST, E}}, {{7, 8, B31 | DSTDISPREG, 4, 6, 11, 2, B31 | IGNORE, DSTDISP32LIST, OP1, OP2, OP3, BIT | IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXB16D, E}}, {{PREFIX, 5, 6, 15, B30 | DSTDISPREG, B31 | IGNORE, DSTDISP16LIST, OP1, OP2, OP3, BIT | IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXW16D, E}}, {{PREFIX, 6, 6, 15, B30 | DSTDISPREG, B31 | IGNORE, DSTDISP16LIST, OP1, OP2, OP3, BIT | IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXL16D, E}}, {{PREFIX, 7, 6, 15, B30 | DSTDISPREG, B31 | IGNORE, DSTDISP16LIST, OP1, OP2, OP3, BIT | IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXB32D, E}}, {{7, 8, B31 | DSTDISPREG, 5, 6, 11, 2, B31 | IGNORE, DSTDISP32LIST, OP1, OP2, OP3, BIT | IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXW32D, E}}, {{7, 8, B31 | DSTDISPREG, 6, 6, 11, 2, B31 | IGNORE, DSTDISP32LIST, OP1, OP2, OP3, BIT | IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXL32D, E}}, {{7, 8, B31 | DSTDISPREG, 7, 6, 11, 2, B31 | IGNORE, DSTDISP32LIST, OP1, OP2, OP3, BIT | IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, ABS16DST, E}}, {{PREFIX, 4, 6, 11, 0, B31 | IGNORE, DSTABS16LIST, OP1, OP2, OP3, BIT | IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, ABS32DST, E}}, {{PREFIX, 4, 6, 11, 2, B31 | IGNORE, DSTABS32LIST, OP1, OP2, OP3, BIT | IGNORE, E}}} - -#define PREFIXLDC 0x0, 0x1, 0x4, B30 | CCR_EXR | DST -#define PREFIXSTC 0x0, 0x1, 0x4, B30 | CCR_EXR | SRC - -#define O(op, size) (op * 4 + size) -#define OP_SIZE(HOW) (HOW % 4) -#define OP_KIND(HOW) (HOW / 4) - -enum h8_asm_codes -{ - O_RECOMPILE = 0, - O_ADD, - O_ADDX, - O_AND, - O_BAND, - O_BRA, - O_BRAB, - O_BRAW, - O_BRAL, - O_BRAS, - O_BRABC, - O_BRABS, - O_BSRBC, - O_BSRBS, - O_BRN, - O_BHI, - O_BLS, - O_BCC, - O_BCS, - O_BNE, - O_BVC, - O_BVS, - O_BPL, - O_BMI, - O_BGE, - O_BLT, - O_BGT, - O_BLE, - O_ANDC, - O_BEQ, - O_BCLR, - O_BCLREQ, - O_BCLRNE, - O_BSETEQ, - O_BSETNE, - O_BFLD, - O_BFST, - O_BIAND, - O_BILD, - O_BIOR, - O_BIXOR, - O_BIST, - O_BISTZ, - O_BLD, - O_BNOT, - O_BOR, - O_BSET, - O_BSR, - O_BXOR, - O_CMP, - O_DAA, - O_DAS, - O_DEC, - O_DIVU, - O_DIVS, - O_DIVXU, - O_DIVXS, - O_INC, - O_LDC, - O_MOV, - O_MOVAB, - O_MOVAW, - O_MOVAL, - O_MOVMD, - O_MOVSD, - O_OR, - O_ROTL, - O_ROTR, - O_ROTXL, - O_ROTXR, - O_BPT, - O_SHAL, - O_SHAR, - O_SHLL, - O_SHLR, - O_SUB, - O_SUBS, - O_TRAPA, - O_XOR, - O_XORC, - O_BST, - O_BSTZ, - O_BTST, - O_EEPMOV, - O_EXTS, - O_EXTU, - O_JMP, - O_JSR, - O_MULU, - O_MULUU, - O_MULS, - O_MULSU, - O_MULXU, - O_MULXS, - O_NOP, - O_NOT, - O_ORC, - O_RTE, - O_RTEL, - O_STC, - O_SUBX, - O_NEG, - O_RTS, - O_RTSL, - O_SLEEP, - O_ILL, - O_ADDS, - O_SYSCALL, - O_TAS, - O_CLRMAC, - O_LDMAC, - O_MAC, - O_LDM, - O_STM, - O_STMAC, - O_LAST, - /* Change made for System Call processing. */ - O_SYS_CREAT, - O_SYS_OPEN, - O_SYS_READ, - O_SYS_WRITE, - O_SYS_LSEEK, - O_SYS_CLOSE, - O_SYS_STAT, - O_SYS_FSTAT, -/* Space reserved for future file I/O system calls. */ - O_SYS_CMDLINE - /* End of System Call specific Changes. */ -}; - -enum h8_size -{ - SB = 0, - SW = 1, - SL = 2, - SN = 3 -}; - - -/* FIXME: Lots of insns have "E, 0, 0, 0, 0" in the nibble code sequences. - Methinks the zeroes aren't necessary. Once confirmed, nuke 'em. */ - -struct h8_opcode h8_opcodes[] = -{ - {O (O_ADD, SB), AV_H8, 2, "add.b", {{IMM8, RD8, E}}, {{0x8, RD8, IMM8LIST, E}}}, - EXPAND_TWOOP_B (O (O_ADD, SB), "add.b", 0x8, 0x0, 0x8, 0x1, 0), - - {O (O_ADD, SW), AV_H8, 6, "add.w", {{RS16, RD16, E}}, {{0x0, 0x9, RS16, RD16, E}}}, - {O (O_ADD, SW), AV_H8SX, 0, "add.w", {{IMM3NZ_NS, RD16, E}}, {{0x0, 0xa, B30 | IMM3NZ, RD16, E}}}, - {O (O_ADD, SW), AV_H8SX, 0, "add.w", {{IMM3NZ_NS, RDIND, E}}, {{0x7, 0xd, B31 | RDIND, IGNORE, 0x0, 0xa, B30 | IMM3NZ, IGNORE, E}}}, - {O (O_ADD, SW), AV_H8SX, 0, "add.w", {{IMM3NZ_NS, ABS16DST, E}}, {{0x6, 0xb, 0x1, B31 | IGNORE, DSTABS16LIST, 0x0, 0xa, B30 | IMM3NZ, IGNORE, E}}}, - {O (O_ADD, SW), AV_H8SX, 0, "add.w", {{IMM3NZ_NS, ABS32DST, E}}, {{0x6, 0xb, 0x3, B31 | IGNORE, DSTABS32LIST, 0x0, 0xa, B30 | IMM3NZ, IGNORE, E}}}, - EXPAND_TWOOP_W (O (O_ADD, SW), "add.w", 0x0, 0x9, 0x1), - - {O (O_ADD, SL), AV_H8H, 6, "add.l", {{RS32, RD32, E}}, {{0x0, 0xa, B31 | RS32, B30 | RD32, E}}}, - {O (O_ADD, SL), AV_H8SX, 0, "add.l", {{IMM3NZ_NS, RD32, E}}, {{0x0, 0xa, B31 | IMM3NZ, B31 | RD32, E}}}, - EXPAND_TWOOP_L (O (O_ADD, SL), "add.l", 0x1), - - {O (O_ADDS, SL), AV_H8, 2, "adds", {{KBIT, RDP, E}}, {{0x0, 0xB,KBIT, RDP, E}}}, - - {O (O_ADDX, SB), AV_H8, 2, "addx", {{IMM8, RD8, E}}, {{0x9, RD8, IMM8LIST, E}}}, - {O (O_ADDX, SB), AV_H8SX, 0, "addx.b", {{IMM8, RDIND, E}}, {{0x7, 0xd, B30 | RDIND, IGNORE, 0x9, IGNORE, IMM8LIST, E}}}, - {O (O_ADDX, SB), AV_H8SX, 0, "addx.b", {{IMM8, RDPOSTDEC, E}}, {{PREFIX_0176, 0x6, 0xc, B30 | RDPOSTDEC, B31 | IGNORE, 0x9, IGNORE, IMM8LIST, E}}}, - {O (O_ADDX, SB), AV_H8, 2, "addx", {{RS8, RD8, E}}, {{0x0, 0xe, RS8, RD8, E}}}, - {O (O_ADDX, SB), AV_H8SX, 0, "addx.b", {{RS8, RDIND, E}}, {{0x7, 0xd, B30 | RDIND, IGNORE, 0x0, 0xe, RS8, IGNORE, E}}}, - {O (O_ADDX, SB), AV_H8SX, 0, "addx.b", {{RS8, RDPOSTDEC, E}}, {{PREFIX_0176, 0x6, 0xc, B30 | RDPOSTDEC, B31 | IGNORE, 0x0, 0xe, RS8, IGNORE, E}}}, - {O (O_ADDX, SB), AV_H8SX, 0, "addx.b", {{RSIND, RD8, E}}, {{0x7, 0xc, B30 | RSIND, IGNORE, 0x0, 0xe, IGNORE, RD8, E}}}, - {O (O_ADDX, SB), AV_H8SX, 0, "addx.b", {{RSPOSTDEC, RD8, E}}, {{PREFIX_0176, 0x6, 0xc, B30 | RSPOSTDEC, B30 | B20 | IGNORE, 0x0, 0xe, IGNORE, RD8, E}}}, - {O (O_ADDX, SB), AV_H8SX, 0, "addx.b", {{RSIND, RDIND, E}}, {{PREFIX_0174, 0x6, 0x8, B30 | RSIND, 0xd, 0x0, RDIND, 0x1, IGNORE, E}}}, - {O (O_ADDX, SB), AV_H8SX, 0, "addx.b", {{RSPOSTDEC, RDPOSTDEC, E}}, {{PREFIX_0176, 0x6, 0xc, B30 | RSPOSTDEC, 0xd, 0xa, RDPOSTDEC, 0x1, IGNORE, E}}}, - - {O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{IMM16, RD16, E}}, {{PREFIX_0151, 0x7, 0x9, 0x1, RD16, IMM16LIST, E}}}, - {O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{IMM16, RDIND, E}}, {{0x7, 0xd, B31 | RDIND, B01 | IGNORE, 0x7, 0x9, 0x1, IGNORE, IMM16LIST, E}}}, - {O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{IMM16, RDPOSTDEC, E}}, {{PREFIX_0156, 0x6, 0xd, B30 | RDPOSTDEC, B31 | B20 | B01 | IGNORE, 0x7, 0x9, 0x1, IGNORE, IMM16LIST, E}}}, - {O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{RS16, RD16, E}}, {{PREFIX_0151, 0x0, 0x9, RS16, RD16, E}}}, - {O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{RS16, RDIND, E}}, {{0x7, 0xd, B31 | RDIND, B01 | IGNORE, 0x0, 0x9, RS16, IGNORE, E}}}, - {O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{RS16, RDPOSTDEC, E}}, {{PREFIX_0156, 0x6, 0xd, B30 | RDPOSTDEC, B31 | B20 | B01 | IGNORE, 0x0, 0x9, RS16, IGNORE, E}}}, - {O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{RSIND, RD16, E}}, {{0x7, 0xc, B31 | RSIND, B01 | IGNORE, 0x0, 0x9, IGNORE, RD16, E}}}, - {O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{RSPOSTDEC, RD16, E}}, {{PREFIX_0156, 0x6, 0xd, B30 | RSPOSTDEC, B30 | B20 | B01 | IGNORE, 0x0, 0x9, IGNORE, RD16, E}}}, - {O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{RSIND, RDIND, E}}, {{PREFIX_0154, 0x6, 0x9, B30 | RSIND, 0xd, 0x0, RDIND, 0x1, IGNORE, E}}}, - {O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{RSPOSTDEC, RDPOSTDEC, E}}, {{PREFIX_0156, 0x6, 0xd, B30 | RSPOSTDEC, 0xd, 0xa, RDPOSTDEC, 0x1, IGNORE, E}}}, - - {O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{IMM32, RD32, E}}, {{PREFIX_0101, 0x7, 0xa, 0x1, RD32, IMM32LIST, E}}}, - {O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{IMM32, RDIND, E}}, {{PREFIX_0104, 0x6, 0x9, B30 | RDIND, B31 | B20 | B01 | IGNORE, 0x7, 0xa, 0x1, IGNORE, IMM32LIST, E}}}, - {O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{IMM32, RDPOSTDEC, E}}, {{PREFIX_0106, 0x6, 0xd, B30 | RDPOSTDEC, B31 | B20 | B01 | IGNORE, 0x7, 0xa, 0x1, IGNORE, IMM32LIST, E}}}, - {O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{RS32, RD32, E}}, {{PREFIX_0101, 0x0, 0xa, B31 | RS32, B30 | RD32, E}}}, - {O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{RS32, RDIND, E}}, {{PREFIX_0104, 0x6, 0x9, B30 | RDIND, B31 | B20 | B01 | IGNORE, 0x0, 0xa, B31 | RS32, B30 | IGNORE, E}}}, - {O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{RS32, RDPOSTDEC, E}}, {{PREFIX_0106, 0x6, 0xd, B30 | RDPOSTDEC, B31 | B20 | B01 | IGNORE, 0x0, 0xa, B31 | RS32, B30 | IGNORE, E}}}, - {O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{RSIND, RD32, E}}, {{PREFIX_0104, 0x6, 0x9, B30 | RSIND, B30 | B20 | B01 | IGNORE, 0x0, 0xa, B31 | IGNORE, B30 | RD32, E}}}, - {O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{RSPOSTDEC, RD32, E}}, {{PREFIX_0106, 0x6, 0xd, B30 | RSPOSTDEC, B30 | B20 | B01 | IGNORE, 0x0, 0xa, B31 | IGNORE, B30 | RD32, E}}}, - {O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{RSIND, RDIND, E}}, {{PREFIX_0104, 0x6, 0x9, B30 | RSIND, 0xd, 0x0, RDIND, 0x1, IGNORE, E}}}, - {O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{RSPOSTDEC, RDPOSTDEC, E}}, {{PREFIX_0106, 0x6, 0xd, B30 | RSPOSTDEC, 0xd, 0xa, RDPOSTDEC, 0x1, IGNORE, E}}}, - - {O (O_AND, SB), AV_H8, 2, "and.b", {{IMM8, RD8, E}}, {{0xe, RD8, IMM8LIST, E}}}, - EXPAND_TWOOP_B (O (O_AND, SB), "and.b", 0xe, 0x1, 0x6, 0x6, 0), - - {O (O_AND, SW), AV_H8, 2, "and.w", {{RS16, RD16, E}}, {{0x6, 0x6, RS16, RD16, E}}}, - EXPAND_TWOOP_W (O (O_AND, SW), "and.w", 0x6, 0x6, 0x6), - - {O (O_AND, SL), AV_H8H, 2, "and.l", {{RS32, RD32, E}}, {{0x0, 0x1, 0xF, 0x0, 0x6, 0x6, B30 | RS32, B30 | RD32, E}}}, - EXPAND_TWOOP_L (O (O_AND, SL), "and.l", 0x6), - - {O (O_ANDC, SB), AV_H8, 2, "andc", {{IMM8, CCR | DST, E}}, {{0x0, 0x6, IMM8LIST, E}}}, - {O (O_ANDC, SB), AV_H8S, 2, "andc", {{IMM8, EXR | DST, E}}, {{0x0, 0x1, 0x4, EXR | DST, 0x0, 0x6, IMM8LIST, E}}}, - - BRANCH (O (O_BRA, SB), "bra", 0x0), - - {O (O_BRAB, SB), AV_H8SX, 0, "bra", {{LOWREG | L_8, E}}, {{0x5, 0x9, LOWREG | L_8 | B30, 0x5, E}}}, - {O (O_BRAW, SW), AV_H8SX, 0, "bra", {{LOWREG | L_16, E}}, {{0x5, 0x9, LOWREG | L_16 | B30, 0x6, E}}}, - {O (O_BRAL, SL), AV_H8SX, 0, "bra", {{RS32, E}}, {{0x5, 0x9, RS32 | B30, 0x7, E}}}, - - {O (O_BRABC, SB), AV_H8SX, 0, "bra/bc", {{IMM3, RDIND, OP3PCREL8}}, {{0x7, 0xC, B30 | RDIND, 0x0, 0x4, B30 | IMM3, OP3PCREL8, DATA, E}}}, - {O (O_BRABC, SB), AV_H8SX, 0, "bra/bc", {{IMM3, ABS8DST, OP3PCREL8}}, {{0x7, 0xE, DSTABS8LIST, 0x4, B30 | IMM3, OP3PCREL8, DATA, E}}}, - {O (O_BRABC, SB), AV_H8SX, 0, "bra/bc", {{IMM3, ABS16DST, OP3PCREL8}}, {{0x6, 0xA, 0x1, 0x0, DSTABS16LIST, 0x4, B30 | IMM3, OP3PCREL8, DATA, E}}}, - {O (O_BRABC, SB), AV_H8SX, 0, "bra/bc", {{IMM3, ABS32DST, OP3PCREL8}}, {{0x6, 0xA, 0x3, 0x0, DSTABS32LIST, 0x4, B30 | IMM3, OP3PCREL8, DATA, E}}}, - {O (O_BRABS, SB), AV_H8SX, 0, "bra/bs", {{IMM3, RDIND, OP3PCREL8}}, {{0x7, 0xC, B30 | RDIND, 0x0, 0x4, B31 | IMM3, OP3PCREL8, DATA, E}}}, - {O (O_BRABS, SB), AV_H8SX, 0, "bra/bs", {{IMM3, ABS8DST, OP3PCREL8}}, {{0x7, 0xE, DSTABS8LIST, 0x4, B31 | IMM3, OP3PCREL8, DATA, E}}}, - {O (O_BRABS, SB), AV_H8SX, 0, "bra/bs", {{IMM3, ABS16DST, OP3PCREL8}}, {{0x6, 0xA, 0x1, 0x0, DSTABS16LIST, 0x4, B31 | IMM3, OP3PCREL8, DATA, E}}}, - {O (O_BRABS, SB), AV_H8SX, 0, "bra/bs", {{IMM3, ABS32DST, OP3PCREL8}}, {{0x6, 0xA, 0x3, 0x0, DSTABS32LIST, 0x4, B31 | IMM3, OP3PCREL8, DATA, E}}}, - {O (O_BRABC, SB), AV_H8SX, 0, "bra/bc", {{IMM3, RDIND, OP3PCREL16}}, {{0x7, 0xC, B30 | RDIND, 0x0, 0x5, 0x8, B30 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, - {O (O_BRABC, SB), AV_H8SX, 0, "bra/bc", {{IMM3, ABS8DST, OP3PCREL16}}, {{0x7, 0xE, DSTABS8LIST, 0x5, 0x8, B30 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, - {O (O_BRABC, SB), AV_H8SX, 0, "bra/bc", {{IMM3, ABS16DST, OP3PCREL16}}, {{0x6, 0xA, 0x1, 0x0, DSTABS16LIST, 0x5, 0x8, B30 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, - {O (O_BRABC, SB), AV_H8SX, 0, "bra/bc", {{IMM3, ABS32DST, OP3PCREL16}}, {{0x6, 0xA, 0x3, 0x0, DSTABS32LIST, 0x5, 0x8, B30 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, - {O (O_BRABS, SB), AV_H8SX, 0, "bra/bs", {{IMM3, RDIND, OP3PCREL16}}, {{0x7, 0xC, B30 | RDIND, 0x0, 0x5, 0x8, B31 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, - {O (O_BRABS, SB), AV_H8SX, 0, "bra/bs", {{IMM3, ABS8DST, OP3PCREL16}}, {{0x7, 0xE, DSTABS8LIST, 0x5, 0x8, B31 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, - {O (O_BRABS, SB), AV_H8SX, 0, "bra/bs", {{IMM3, ABS16DST, OP3PCREL16}}, {{0x6, 0xA, 0x1, 0x0, DSTABS16LIST, 0x5, 0x8, B31 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, - {O (O_BRABS, SB), AV_H8SX, 0, "bra/bs", {{IMM3, ABS32DST, OP3PCREL16}}, {{0x6, 0xA, 0x3, 0x0, DSTABS32LIST, 0x5, 0x8, B31 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, - - {O (O_BRAS, SB), AV_H8SX, 0, "bra/s", {{PCREL8, E}}, {{0x4, 0x0, PCREL8, DATA | B01, E}}}, - - {O (O_BSRBC, SB), AV_H8SX, 0, "bsr/bc", {{IMM3, RDIND, OP3PCREL16}}, {{0x7, 0xC, B30 | RDIND, 0x0, 0x5, 0xC, B30 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, - {O (O_BSRBC, SB), AV_H8SX, 0, "bsr/bc", {{IMM3, ABS8DST, OP3PCREL16}}, {{0x7, 0xE, DSTABS8LIST, 0x5, 0xC, B30 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, - {O (O_BSRBC, SB), AV_H8SX, 0, "bsr/bc", {{IMM3, ABS16DST, OP3PCREL16}}, {{0x6, 0xA, 0x1, 0x0, DSTABS16LIST, 0x5, 0xC, B30 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, - {O (O_BSRBC, SB), AV_H8SX, 0, "bsr/bc", {{IMM3, ABS32DST, OP3PCREL16}}, {{0x6, 0xA, 0x3, 0x0, DSTABS32LIST, 0x5, 0xC, B30 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, - {O (O_BSRBS, SB), AV_H8SX, 0, "bsr/bs", {{IMM3, RDIND, OP3PCREL16}}, {{0x7, 0xC, B30 | RDIND, 0x0, 0x5, 0xC, B31 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, - {O (O_BSRBS, SB), AV_H8SX, 0, "bsr/bs", {{IMM3, ABS8DST, OP3PCREL16}}, {{0x7, 0xE, DSTABS8LIST, 0x5, 0xC, B31 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, - {O (O_BSRBS, SB), AV_H8SX, 0, "bsr/bs", {{IMM3, ABS16DST, OP3PCREL16}}, {{0x6, 0xA, 0x1, 0x0, DSTABS16LIST, 0x5, 0xC, B31 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, - {O (O_BSRBS, SB), AV_H8SX, 0, "bsr/bs", {{IMM3, ABS32DST, OP3PCREL16}}, {{0x6, 0xA, 0x3, 0x0, DSTABS32LIST, 0x5, 0xC, B31 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, - - BRANCH (O (O_BRA, SB), "bt", 0x0), - BRANCH (O (O_BRN, SB), "brn", 0x1), - BRANCH (O (O_BRN, SB), "bf", 0x1), - BRANCH (O (O_BHI, SB), "bhi", 0x2), - BRANCH (O (O_BLS, SB), "bls", 0x3), - BRANCH (O (O_BCC, SB), "bcc", 0x4), - BRANCH (O (O_BCC, SB), "bhs", 0x4), - BRANCH (O (O_BCS, SB), "bcs", 0x5), - BRANCH (O (O_BCS, SB), "blo", 0x5), - BRANCH (O (O_BNE, SB), "bne", 0x6), - BRANCH (O (O_BEQ, SB), "beq", 0x7), - BRANCH (O (O_BVC, SB), "bvc", 0x8), - BRANCH (O (O_BVS, SB), "bvs", 0x9), - BRANCH (O (O_BPL, SB), "bpl", 0xA), - BRANCH (O (O_BMI, SB), "bmi", 0xB), - BRANCH (O (O_BGE, SB), "bge", 0xC), - BRANCH (O (O_BLT, SB), "blt", 0xD), - BRANCH (O (O_BGT, SB), "bgt", 0xE), - BRANCH (O (O_BLE, SB), "ble", 0xF), - - EBITOP (O (O_BCLR, SB), IMM3 | B30, "bclr", 0x6, 0x2, 0x7, 0xD, 0x7, 0xF, 0x8, 0), - BITOP (O (O_BAND, SB), IMM3 | B30, "band", 0x7, 0x6, 0x7, 0xC, 0x7, 0xE, 0x0, 0), - BITOP (O (O_BIAND, SB), IMM3 | B31, "biand", 0x7, 0x6, 0x7, 0xC, 0x7, 0xE, 0x0, 0), - BITOP (O (O_BILD, SB), IMM3 | B31, "bild", 0x7, 0x7, 0x7, 0xC, 0x7, 0xE, 0x0, 0), - BITOP (O (O_BIOR, SB), IMM3 | B31, "bior", 0x7, 0x4, 0x7, 0xC, 0x7, 0xE, 0x0, 0), - BITOP (O (O_BIST, SB), IMM3 | B31, "bist", 0x6, 0x7, 0x7, 0xD, 0x7, 0xF, 0x8, 0), - BITOP (O (O_BIXOR, SB), IMM3 | B31, "bixor", 0x7, 0x5, 0x7, 0xC, 0x7, 0xE, 0x0, 0), - BITOP (O (O_BLD, SB), IMM3 | B30, "bld", 0x7, 0x7, 0x7, 0xC, 0x7, 0xE, 0x0, 0), - EBITOP (O (O_BNOT, SB), IMM3 | B30, "bnot", 0x6, 0x1, 0x7, 0xD, 0x7, 0xF, 0x8, 0), - BITOP (O (O_BOR, SB), IMM3 | B30, "bor", 0x7, 0x4, 0x7, 0xC, 0x7, 0xE, 0x0, 0), - EBITOP (O (O_BSET, SB), IMM3 | B30, "bset", 0x6, 0x0, 0x7, 0xD, 0x7, 0xF, 0x8, 0), - BITOP (O (O_BST, SB), IMM3 | B30, "bst", 0x6, 0x7, 0x7, 0xD, 0x7, 0xF, 0x8, 0), - EBITOP (O (O_BTST, SB), IMM3 | B30, "btst", 0x6, 0x3, 0x7, 0xC, 0x7, 0xE, 0x0, 0), - BITOP (O (O_BXOR, SB), IMM3 | B30, "bxor", 0x7, 0x5, 0x7, 0xC, 0x7, 0xE, 0x0, 0), - - EBITOP_B (O (O_BCLREQ, SB), IMM3 | B30, "bclr/eq", 0x6, 0x2, 0x7, 0xD, 0x7, 0xF, 0x8, 0x7), - EBITOP_B (O (O_BCLRNE, SB), IMM3 | B30, "bclr/ne", 0x6, 0x2, 0x7, 0xD, 0x7, 0xF, 0x8, 0x6), - EBITOP_B (O (O_BSETEQ, SB), IMM3 | B30, "bset/eq", 0x6, 0x0, 0x7, 0xD, 0x7, 0xF, 0x8, 0x7), - EBITOP_B (O (O_BSETNE, SB), IMM3 | B30, "bset/ne", 0x6, 0x0, 0x7, 0xD, 0x7, 0xF, 0x8, 0x6), - BITOP_B (O (O_BISTZ, SB), IMM3 | B31, "bistz", 0x6, 0x7, 0x7, 0xD, 0x7, 0xF, 0x8, 0x7), - BITOP_B (O (O_BSTZ, SB), IMM3 | B30, "bstz", 0x6, 0x7, 0x7, 0xD, 0x7, 0xF, 0x8, 0x7), - - {O (O_BFLD, SB), AV_H8SX, 0, "bfld", {{IMM8, RDIND, R3_8}}, {{0x7, 0xC, B30 | RDIND, 0x0, 0xF, R3_8, IMM8LIST, E}}}, - {O (O_BFLD, SB), AV_H8SX, 0, "bfld", {{IMM8, ABS8DST, R3_8}}, {{0x7, 0xE, DSTABS8LIST, 0xF, R3_8, IMM8LIST, E}}}, - {O (O_BFLD, SB), AV_H8SX, 0, "bfld", {{IMM8, ABS16DST, R3_8}}, {{0x6, 0xA, 0x1, 0x0, DSTABS16LIST, 0xF, R3_8, IMM8LIST, E}}}, - {O (O_BFLD, SB), AV_H8SX, 0, "bfld", {{IMM8, ABS32DST, R3_8}}, {{0x6, 0xA, 0x3, 0x0, DSTABS32LIST, 0xF, R3_8, IMM8LIST, E}}}, - - /* Because the assembler treats SRC, DST and OP3 as ordinals, - I must designate the second argument, an immediate value, as DST. - May God have mercy on my soul. */ - {O (O_BFST, SB), AV_H8SX, 0, "bfst", {{RS8, DST | IMM8, R3_IND}}, {{0x7, 0xD, B30 | R3_IND, 0x0, 0xF, RS8, DST | IMM8LIST, E}}}, - {O (O_BFST, SB), AV_H8SX, 0, "bfst", {{RS8, DST | IMM8, ABS8OP3}}, {{0x7, 0xF, OP3ABS8LIST, 0xF, RS8, DST | IMM8LIST, E}}}, - {O (O_BFST, SB), AV_H8SX, 0, "bfst", {{RS8, DST | IMM8, ABS16OP3}}, {{0x6, 0xA, 0x1, 0x8, OP3ABS16LIST, 0xF, RS8, DST | IMM8LIST, E}}}, - {O (O_BFST, SB), AV_H8SX, 0, "bfst", {{RS8, DST | IMM8, ABS32OP3}}, {{0x6, 0xA, 0x3, 0x8, OP3ABS32LIST, 0xF, RS8, DST | IMM8LIST, E}}}, - - {O (O_BSR, SB), AV_H8, 6, "bsr", {{PCREL8, E}}, {{0x5, 0x5, PCREL8, DATA, E}}}, - {O (O_BSR, SB), AV_H8, 6, "bsr", {{PCREL16, E}}, {{0x5, 0xC, 0x0, 0x0, PCREL16, DATA3, E}}}, - {O (O_BSR, SB), AV_H8SX, 0, "bsr", {{LOWREG | L_8, E}}, {{0x5, 0xd, B30 | LOWREG | L_8, 0x5, E}}}, - {O (O_BSR, SW), AV_H8SX, 0, "bsr", {{LOWREG | L_16, E}}, {{0x5, 0xd, B30 | LOWREG | L_16, 0x6, E}}}, - {O (O_BSR, SL), AV_H8SX, 0, "bsr", {{OR32, E}}, {{0x5, 0xd, B30 | OR32, 0x7, E}}}, - - {O (O_CMP, SB), AV_H8, 2, "cmp.b", {{IMM8, RD8, E}}, {{0xa, RD8, IMM8LIST, E}}}, - EXPAND_TWOOP_B (O (O_CMP, SB), "cmp.b", 0xa, 0x1, 0xc, 0x2, B00), - - {O (O_CMP, SW), AV_H8, 2, "cmp.w", {{RS16, RD16, E}}, {{0x1, 0xd, RS16, RD16, E}}}, - {O (O_CMP, SW), AV_H8SX, 0, "cmp.w", {{IMM3NZ_NS, RD16, E}}, {{0x1, 0xf, B30 | IMM3NZ, RD16, E}}}, - {O (O_CMP, SW), AV_H8SX, 0, "cmp.w", {{IMM3NZ_NS, RDIND, E}}, {{0x7, 0xd, B31 | RDIND, IGNORE, 0x1, 0xf, B30 | IMM3NZ, IGNORE, E}}}, - {O (O_CMP, SW), AV_H8SX, 0, "cmp.w", {{IMM3NZ_NS, ABS16DST, E}}, {{0x6, 0xb, 0x1, B31 | IGNORE, DSTABS16LIST, 0x1, 0xf, B30 | IMM3NZ, IGNORE, E}}}, - {O (O_CMP, SW), AV_H8SX, 0, "cmp.w", {{IMM3NZ_NS, ABS32DST, E}}, {{0x6, 0xb, 0x3, B31 | IGNORE, DSTABS32LIST, 0x1, 0xf, B30 | IMM3NZ, IGNORE, E}}}, - EXPAND_TWOOP_W (O (O_CMP, SW), "cmp.w", 0x1, 0xd, 0x2), - - {O (O_CMP, SL), AV_H8H, 6, "cmp.l", {{RS32, RD32, E}}, {{0x1, 0xf, B31 | RS32, B30 | RD32, E}}}, - {O (O_CMP, SL), AV_H8SX, 0, "cmp.l", {{IMM3NZ_NS, RD32, E}}, {{0x1, 0xf, B31 | IMM3NZ, B31 | RD32, E}}}, - EXPAND_TWOOP_L (O (O_CMP, SL), "cmp.l", 0x2), - - UNOP (O (O_DAA, SB), "daa", 0x0, 0xF), - UNOP (O (O_DAS, SB), "das", 0x1, 0xF), - UNOP (O (O_DEC, SB), "dec.b", 0x1, 0xA), - - {O (O_DEC, SW), AV_H8H, 2, "dec.w", {{DBIT, RD16, E}}, {{0x1, 0xB, 0x5 | DBIT, RD16, E}}}, - {O (O_DEC, SL), AV_H8H, 2, "dec.l", {{DBIT, RD32, E}}, {{0x1, 0xB, 0x7 | DBIT, RD32 | B30, E}}}, - - {O (O_DIVS, SW), AV_H8SX, 0, "divs.w", {{IMM4, RD16, E}}, {{0x0, 0x1, 0xd, 0x6, 0x5, 0x1, IMM4, RD16, E}}}, - {O (O_DIVS, SW), AV_H8SX, 0, "divs.w", {{RS16, RD16, E}}, {{0x0, 0x1, 0xd, 0x2, 0x5, 0x1, RS16, RD16, E}}}, - {O (O_DIVS, SL), AV_H8SX, 0, "divs.l", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xd, 0x6, 0x5, 0x3, IMM4, B30 | RD32, E}}}, - {O (O_DIVS, SL), AV_H8SX, 0, "divs.l", {{RS32, RD32, E}}, {{0x0, 0x1, 0xd, 0x2, 0x5, 0x3, B30 | RS32, B30 | RD32, E}}}, - - {O (O_DIVU, SW), AV_H8SX, 0, "divu.w", {{IMM4, RD16, E}}, {{0x0, 0x1, 0xd, 0xe, 0x5, 0x1, IMM4, RD16, E}}}, - {O (O_DIVU, SW), AV_H8SX, 0, "divu.w", {{RS16, RD16, E}}, {{0x0, 0x1, 0xd, 0xa, 0x5, 0x1, RS16, RD16, E}}}, - {O (O_DIVU, SL), AV_H8SX, 0, "divu.l", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xd, 0xe, 0x5, 0x3, IMM4, B30 | RD32, E}}}, - {O (O_DIVU, SL), AV_H8SX, 0, "divu.l", {{RS32, RD32, E}}, {{0x0, 0x1, 0xd, 0xa, 0x5, 0x3, B30 | RS32, B30 | RD32, E}}}, - - {O (O_DIVXS, SB), AV_H8SX, 0, "divxs.b", {{IMM4, RD16, E}}, {{0x0, 0x1, 0xD, 0x4, 0x5, 0x1, IMM4, RD16, E}}}, - {O (O_DIVXS, SB), AV_H8H, 13, "divxs.b", {{RS8, RD16, E}}, {{0x0, 0x1, 0xD, 0x0, 0x5, 0x1, RS8, RD16, E}}}, - {O (O_DIVXS, SW), AV_H8SX, 0, "divxs.w", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xD, 0x4, 0x5, 0x3, IMM4, B30 | RD32, E}}}, - {O (O_DIVXS, SW), AV_H8H, 21, "divxs.w", {{RS16, RD32, E}}, {{0x0, 0x1, 0xD, 0x0, 0x5, 0x3, RS16, B30 | RD32, E}}}, - - {O (O_DIVXU, SB), AV_H8SX, 0, "divxu.b", {{IMM4, RD16, E}}, {{0x0, 0x1, 0xD, 0xC, 0x5, 0x1, IMM4, RD16, E}}}, - {O (O_DIVXU, SB), AV_H8, 13, "divxu.b", {{RS8, RD16, E}}, {{0x5, 0x1, RS8, RD16, E}}}, - {O (O_DIVXU, SW), AV_H8SX, 0, "divxu.w", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xD, 0xC, 0x5, 0x3, IMM4, B30 | RD32, E}}}, - {O (O_DIVXU, SW), AV_H8H, 21, "divxu.w", {{RS16, RD32, E}}, {{0x5, 0x3, RS16, B30 | RD32, E}}}, - - {O (O_EEPMOV, SB), AV_H8, 4, "eepmov.b", {{E}}, {{0x7, 0xB, 0x5, 0xC, 0x5, 0x9, 0x8, 0xF, E}}}, - {O (O_EEPMOV, SW), AV_H8H, 4, "eepmov.w", {{E}}, {{0x7, 0xB, 0xD, 0x4, 0x5, 0x9, 0x8, 0xF, E}}}, - - EXPAND_UNOP_STD_W (O (O_EXTS, SW), "exts.w", PREFIX_015, 0x1, 0x7, 0xd), - EXPAND_UNOP_STD_L (O (O_EXTS, SL), "exts.l", PREFIX_010, 0x1, 0x7, 0xf), - EXPAND_UNOP_EXTENDED_L (O (O_EXTS, SL), "exts.l", CONST_2, PREFIX_010, 0x1, 0x7, 0xe, 0), - EXPAND_UNOP_STD_W (O (O_EXTU, SW), "extu.w", PREFIX_015, 0x1, 0x7, 0x5), - EXPAND_UNOP_STD_L (O (O_EXTU, SL), "extu.l", PREFIX_010, 0x1, 0x7, 0x7), - EXPAND_UNOP_EXTENDED_L (O (O_EXTU, SL), "extu.l", CONST_2, PREFIX_010, 0x1, 0x7, 0x6, 0), - - UNOP (O (O_INC, SB), "inc", 0x0, 0xA), - - {O (O_INC, SW), AV_H8H, 2, "inc.w", {{DBIT, RD16, E}}, {{0x0, 0xB, 0x5 | DBIT, RD16, E}}}, - {O (O_INC, SL), AV_H8H, 2, "inc.l", {{DBIT, RD32, E}}, {{0x0, 0xB, 0x7 | DBIT, RD32 | B30, E}}}, - - {O (O_JMP, SN), AV_H8, 4, "jmp", {{RSIND, E}}, {{0x5, 0x9, B30 | RSIND, 0x0, E}}}, - {O (O_JMP, SN), AV_H8, 6, "jmp", {{ABSJMP | L_24, E}}, {{0x5, 0xA, SRC | ABSJMP | L_24, DATA5, E}}}, - - {O (O_JMP, SN), AV_H8SX, 0, "jmp", {{ABSJMP | L_32, E}}, {{0x5, 0x9, 0x0, 0x8, ABSJMP | L_32, DATA7, E}}}, - - {O (O_JMP, SN), AV_H8, 8, "jmp", {{MEMIND, E}}, {{0x5, 0xB, SRC | MEMIND, DATA, E}}}, - {O (O_JMP, SN), AV_H8SX, 0, "jmp", {{VECIND, E}}, {{0x5, 0x9, B31 | SRC | VECIND, DATA, E}}}, - - {O (O_JSR, SN), AV_H8, 6, "jsr", {{RSIND, E}}, {{0x5, 0xD, B30 | RSIND, 0x0, E}}}, - {O (O_JSR, SN), AV_H8, 8, "jsr", {{ABSJMP | L_24, E}}, {{0x5, 0xE, SRC | ABSJMP | L_24, DATA5, E}}}, - - {O (O_JSR, SN), AV_H8SX, 0, "jsr", {{ABSJMP | L_32, E}}, {{0x5, 0xD, 0x0, 0x8, ABSJMP | L_32, DATA7, E}}}, - - {O (O_JSR, SN), AV_H8, 8, "jsr", {{MEMIND, E}}, {{0x5, 0xF, SRC | MEMIND, DATA, E}}}, - {O (O_JSR, SN), AV_H8SX, 8, "jsr", {{VECIND, E}}, {{0x5, 0xD, SRC | VECIND, DATA, E}}}, - - {O (O_LDC, SB), AV_H8, 2, "ldc", {{IMM8, CCR | DST, E}}, {{ 0x0, 0x7, IMM8LIST, E}}}, - {O (O_LDC, SB), AV_H8S, 2, "ldc", {{IMM8, EXR | DST, E}}, {{0x0, 0x1, 0x4, EXR | DST, 0x0, 0x7, IMM8LIST, E}}}, - {O (O_LDC, SB), AV_H8, 2, "ldc", {{RS8, CCR | DST, E}}, {{0x0, 0x3, B30 | CCR | DST, RS8, E}}}, - {O (O_LDC, SB), AV_H8S, 2, "ldc", {{RS8, EXR | DST, E}}, {{0x0, 0x3, B30 | EXR | DST, RS8, E}}}, - {O (O_LDC, SW), AV_H8H, 2, "ldc", {{RSIND, CCR | DST, E}}, {{PREFIXLDC, 0x6, 0x9, B30 | RSIND, IGNORE, E}}}, - {O (O_LDC, SW), AV_H8S, 2, "ldc", {{RSIND, EXR | DST, E}}, {{PREFIXLDC, 0x6, 0x9, B30 | RSIND, IGNORE, E}}}, - {O (O_LDC, SW), AV_H8H, 2, "ldc", {{RSPOSTINC, CCR | DST, E}}, {{PREFIXLDC, 0x6, 0xD, B30 | RSPOSTINC, IGNORE, E}}}, - {O (O_LDC, SW), AV_H8S, 2, "ldc", {{RSPOSTINC, EXR | DST, E}}, {{PREFIXLDC, 0x6, 0xD, B30 | RSPOSTINC, IGNORE, E}}}, - {O (O_LDC, SW), AV_H8H, 2, "ldc", {{DISP16SRC, CCR | DST, E}}, {{PREFIXLDC, 0x6, 0xF, B30 | DISPREG, IGNORE, SRC | DISP16LIST, E}}}, - {O (O_LDC, SW), AV_H8S, 2, "ldc", {{DISP16SRC, EXR | DST, E}}, {{PREFIXLDC, 0x6, 0xF, B30 | DISPREG, IGNORE, SRC | DISP16LIST, E}}}, - {O (O_LDC, SW), AV_H8H, 2, "ldc", {{DISP32SRC, CCR | DST, E}}, {{PREFIXLDC, 0x7, 0x8, B30 | DISPREG, 0x0, 0x6, 0xB, 0x2, IGNORE, SRC | DISP32LIST, E}}}, - {O (O_LDC, SW), AV_H8S, 2, "ldc", {{DISP32SRC, EXR | DST, E}}, {{PREFIXLDC, 0x7, 0x8, B30 | DISPREG, 0x0, 0x6, 0xB, 0x2, IGNORE, SRC | DISP32LIST, E}}}, - {O (O_LDC, SW), AV_H8H, 2, "ldc", {{ABS16SRC, CCR | DST, E}}, {{PREFIXLDC, 0x6, 0xB, 0x0, IGNORE, SRC | ABS16LIST, E}}}, - {O (O_LDC, SW), AV_H8S, 2, "ldc", {{ABS16SRC, EXR | DST, E}}, {{PREFIXLDC, 0x6, 0xB, 0x0, IGNORE, SRC | ABS16LIST, E}}}, - {O (O_LDC, SW), AV_H8H, 2, "ldc", {{ABS32SRC, CCR | DST, E}}, {{PREFIXLDC, 0x6, 0xB, 0x2, IGNORE, SRC | MEMRELAX | ABS32LIST, E}}}, - {O (O_LDC, SW), AV_H8S, 2, "ldc", {{ABS32SRC, EXR | DST, E}}, {{PREFIXLDC, 0x6, 0xB, 0x2, IGNORE, SRC | MEMRELAX | ABS32LIST, E}}}, - - {O (O_LDC, SL), AV_H8SX, 0, "ldc", {{RS32, B30 | VBR_SBR | DST, E}}, {{0x0, 0x3, B30 | VBR_SBR | DST, RS32, E}}}, - - - {O (O_MOV, SB), AV_H8, 2, "mov.b", {{IMM8, RD8, E}}, {{0xF, RD8, IMM8LIST, E}}}, - {O (O_MOV, SB), AV_H8SX, 0, "mov.b", {{IMM4_NS, ABS16DST, E}}, {{0x6, 0xa, 0xd, IMM4, DSTABS16LIST, E}}}, - {O (O_MOV, SB), AV_H8SX, 0, "mov.b", {{IMM4_NS, ABS32DST, E}}, {{0x6, 0xa, 0xf, IMM4, DSTABS32LIST, E}}}, - MOVFROM_IMM8 (O (O_MOV, SB), PREFIX_017D, "mov.b", IMM8), - - {O (O_MOV, SB), AV_H8, 2, "mov.b", {{RS8, RD8, E}}, {{0x0, 0xC, RS8, RD8, E}}}, - MOVFROM_REG_BW (O (O_MOV, SB), "mov.b", RS8, PREFIX_017, 8, 10, 12, 14, MEMRELAX), - {O (O_MOV, SB), AV_H8, 4, "mov.b", {{RS8, ABS8DST, E}}, {{0x3, RS8, DSTABS8LIST, E}}}, - MOVTO_REG_BW (O (O_MOV, SB), "mov.b", RD8, PREFIX_017, 8, 10, 12, 14, MEMRELAX), - {O (O_MOV, SB), AV_H8, 4, "mov.b", {{ABS8SRC, RD8, E}}, {{0x2, RD8, ABS8LIST, E}}}, - - MOVFROM_STD (O (O_MOV, SB), PREFIX_0178, "mov.b", RSIND, FROM_IND), - MOVFROM_STD (O (O_MOV, SB), PREFIX_0178, "mov.b", RSPOSTINC, FROM_POSTINC), - MOVFROM_STD (O (O_MOV, SB), PREFIX_0178, "mov.b", RSPOSTDEC, FROM_POSTDEC), - MOVFROM_STD (O (O_MOV, SB), PREFIX_0178, "mov.b", RSPREINC, FROM_PREINC), - MOVFROM_STD (O (O_MOV, SB), PREFIX_0178, "mov.b", RSPREDEC, FROM_PREDEC), - MOVFROM_STD (O (O_MOV, SB), PREFIX_0178, "mov.b", DISP2SRC, FROM_DISP2), - MOVFROM_AD (O (O_MOV, SB), PREFIX_0178, "mov.b", DISP16SRC, FROM_DISP16, DISP16LIST), - MOVFROM_AD (O (O_MOV, SB), PREFIX_0178, "mov.b", DISP32SRC, FROM_DISP32, DISP32LIST), - MOVFROM_AD (O (O_MOV, SB), PREFIX_0178, "mov.b", INDEXB16, FROM_DISP16B, DISP16LIST), - MOVFROM_AD (O (O_MOV, SB), PREFIX_0178, "mov.b", INDEXW16, FROM_DISP16W, DISP16LIST), - MOVFROM_AD (O (O_MOV, SB), PREFIX_0178, "mov.b", INDEXL16, FROM_DISP16L, DISP16LIST), - MOVFROM_AD (O (O_MOV, SB), PREFIX_0178, "mov.b", INDEXB32, FROM_DISP32B, DISP32LIST), - MOVFROM_AD (O (O_MOV, SB), PREFIX_0178, "mov.b", INDEXW32, FROM_DISP32W, DISP32LIST), - MOVFROM_AD (O (O_MOV, SB), PREFIX_0178, "mov.b", INDEXL32, FROM_DISP32L, DISP32LIST), - MOVFROM_AD (O (O_MOV, SB), PREFIX_0178, "mov.b", ABS16SRC, FROM_ABS16, ABS16LIST), - MOVFROM_AD (O (O_MOV, SB), PREFIX_0178, "mov.b", ABS32SRC, FROM_ABS32, ABS32LIST), - - {O (O_MOV, SW), AV_H8SX, 0, "mov.w", {{IMM3NZ_NS, RD16, E}}, {{0x0, 0xf, B30 | IMM3NZ, RD16, E}}}, - {O (O_MOV, SW), AV_H8, 4, "mov.w", {{IMM16, RD16, E}}, {{0x7, 0x9, 0x0, RD16, IMM16LIST, E}}}, - {O (O_MOV, SW), AV_H8SX, 0, "mov.w", {{IMM4_NS, ABS16DST, E}}, {{0x6, 0xb, 0xd, IMM4, DSTABS16LIST, E}}}, - {O (O_MOV, SW), AV_H8SX, 0, "mov.w", {{IMM4_NS, ABS32DST, E}}, {{0x6, 0xb, 0xf, IMM4, DSTABS32LIST, E}}}, - - MOVFROM_IMM8 (O (O_MOV, SW), PREFIX_015D, "mov.w", IMM8U_NS), - MOVFROM_IMM (O (O_MOV, SW), PREFIX_7974, "mov.w", IMM16, IMM16LIST), - - {O (O_MOV, SW), AV_H8, 2, "mov.w", {{RS16, RD16, E}}, {{0x0, 0xD, RS16, RD16, E}}}, - MOVFROM_REG_BW (O (O_MOV, SW), "mov.w", RS16, PREFIX_015, 9, 11, 13, 15, 0), - MOVTO_REG_BW (O (O_MOV, SW), "mov.w", RD16, PREFIX_015, 9, 11, 13, 15, 0), - - MOVFROM_STD (O (O_MOV, SW), PREFIX_0158, "mov.w", RSIND, FROM_IND), - MOVFROM_STD (O (O_MOV, SW), PREFIX_0158, "mov.w", RSPOSTINC, FROM_POSTINC), - MOVFROM_STD (O (O_MOV, SW), PREFIX_0158, "mov.w", RSPOSTDEC, FROM_POSTDEC), - MOVFROM_STD (O (O_MOV, SW), PREFIX_0158, "mov.w", RSPREINC, FROM_PREINC), - MOVFROM_STD (O (O_MOV, SW), PREFIX_0158, "mov.w", RSPREDEC, FROM_PREDEC), - MOVFROM_STD (O (O_MOV, SW), PREFIX_0158, "mov.w", DISP2SRC, FROM_DISP2), - MOVFROM_AD (O (O_MOV, SW), PREFIX_0158, "mov.w", DISP16SRC, FROM_DISP16, DISP16LIST), - MOVFROM_AD (O (O_MOV, SW), PREFIX_0158, "mov.w", DISP32SRC, FROM_DISP32, DISP32LIST), - MOVFROM_AD (O (O_MOV, SW), PREFIX_0158, "mov.w", INDEXB16, FROM_DISP16B, DISP16LIST), - MOVFROM_AD (O (O_MOV, SW), PREFIX_0158, "mov.w", INDEXW16, FROM_DISP16W, DISP16LIST), - MOVFROM_AD (O (O_MOV, SW), PREFIX_0158, "mov.w", INDEXL16, FROM_DISP16L, DISP16LIST), - MOVFROM_AD (O (O_MOV, SW), PREFIX_0158, "mov.w", INDEXB32, FROM_DISP32B, DISP32LIST), - MOVFROM_AD (O (O_MOV, SW), PREFIX_0158, "mov.w", INDEXW32, FROM_DISP32W, DISP32LIST), - MOVFROM_AD (O (O_MOV, SW), PREFIX_0158, "mov.w", INDEXL32, FROM_DISP32L, DISP32LIST), - MOVFROM_AD (O (O_MOV, SW), PREFIX_0158, "mov.w", ABS16SRC, FROM_ABS16, ABS16LIST), - MOVFROM_AD (O (O_MOV, SW), PREFIX_0158, "mov.w", ABS32SRC, FROM_ABS32, ABS32LIST), - - {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{IMM3NZ_NS, RD32, E}}, {{0x0, 0xf, B31 | IMM3NZ, B31 | RD32, E}}}, - - MOVFROM_IMM8 (O (O_MOV, SL), PREFIX_010D, "mov.l", IMM8U_NS), - MOVFROM_IMM (O (O_MOV, SL), PREFIX_7A7C, "mov.l", IMM16U_NS, IMM16ULIST), - - {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{IMM16U_NS, RD32, E}}, {{0x7, 0xa, 0x0, B31 | RD32, IMM16ULIST, E}}}, - {O (O_MOV, SL), AV_H8H, 4, "mov.l", {{IMM32, RD32, E}}, {{0x7, 0xa, 0x0, B30 | RD32, IMM32LIST, E}}}, - - MOVFROM_IMM (O (O_MOV, SL), PREFIX_7A74, "mov.l", IMM32, IMM32LIST), - - {O (O_MOV, SL), AV_H8H, 2, "mov.l", {{RS32, RD32, E}}, {{0x0, 0xf, B31 | RS32, B30 | RD32, E}}}, - - {O (O_MOV, SL), AV_H8H, 6, "mov.l", {{RS32, RDIND, E}}, {{PREFIX_0100, 0x6, 0x9, B31 | RDIND, B30 | RS32, E}}}, - {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, RDPOSTINC, E}}, {{PREFIX_0103, 0x6, 0xd, B31 | RDPOSTINC, RS32, E}}}, - {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, RDPOSTDEC, E}}, {{PREFIX_0101, 0x6, 0xd, B31 | RDPOSTDEC, RS32, E}}}, - {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, RDPREINC, E}}, {{PREFIX_0102, 0x6, 0xd, B31 | RDPREINC, RS32, E}}}, - {O (O_MOV, SL), AV_H8H, 6, "mov.l", {{RS32, RDPREDEC, E}}, {{PREFIX_0100, 0x6, 0xd, B31 | RDPREDEC, RS32, E}}}, - {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, DISP2DST, E}}, {{PREFIX_010, B30 | B20 | DISP2DST, 0x6, 0x9, B31 | DSTDISPREG, RS32, E}}}, - {O (O_MOV, SL), AV_H8H, 6, "mov.l", {{RS32, DISP16DST, E}}, {{PREFIX_0100, 0x6, 0xf, B31 | DSTDISPREG, RS32, DSTDISP16LIST, E}}}, - {O (O_MOV, SL), AV_H8SX, 6, "mov.l", {{RS32, DISP32DST, E}}, {{0x7, 0x8, B31 | DSTDISPREG, 0x0, 0x6, 0xb, 0xa, RS32, DSTDISP32LIST, E}}}, - {O (O_MOV, SL), AV_H8H, 6, "mov.l", {{RS32, DISP32DST, E}}, {{PREFIX_0100, 0x7, 0x8, B31 | DSTDISPREG, 0x0, 0x6, 0xb, 0xa, RS32, MEMRELAX | DSTDISP32LIST, E}}}, - {O (O_MOV, SL), AV_H8H, 6, "mov.l", {{RS32, DISP32DST, E}}, {{PREFIX_0100, 0x7, 0x8, DSTDISPREG, 0x0, 0x6, 0xb, 0xa, RS32, MEMRELAX | DSTDISP32LIST, E}}}, - {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, INDEXB16D, E}}, {{PREFIX_0101, 0x6, 0xf, B31 | DSTDISPREG, RS32, DSTDISP16LIST, E}}}, - {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, INDEXW16D, E}}, {{PREFIX_0102, 0x6, 0xf, B31 | DSTDISPREG, RS32, DSTDISP16LIST, E}}}, - {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, INDEXL16D, E}}, {{PREFIX_0103, 0x6, 0xf, B31 | DSTDISPREG, RS32, DSTDISP16LIST, E}}}, - {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, INDEXB32D, E}}, {{0x7, 0x8, B31 | DSTDISPREG, 0x1, 0x6, 0xb, 0xa, RS32, DSTDISP32LIST, E}}}, - {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, INDEXW32D, E}}, {{0x7, 0x8, B31 | DSTDISPREG, 0x2, 0x6, 0xb, 0xa, RS32, DSTDISP32LIST, E}}}, - {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, INDEXL32D, E}}, {{0x7, 0x8, B31 | DSTDISPREG, 0x3, 0x6, 0xb, 0xa, RS32, DSTDISP32LIST, E}}}, - {O (O_MOV, SL), AV_H8H, 6, "mov.l", {{RS32, ABS16DST, E}}, {{PREFIX_0100, 0x6, 0xb, 0x8, RS32, DSTABS16LIST, E}}}, - {O (O_MOV, SL), AV_H8H, 6, "mov.l", {{RS32, ABS32DST, E}}, {{PREFIX_0100, 0x6, 0xb, 0xa, RS32, MEMRELAX | DSTABS32LIST, E}}}, - - {O (O_MOV, SL), AV_H8H, 4, "mov.l", {{RSIND, RD32, E}}, {{PREFIX_0100, 0x6, 0x9, B30 | RSIND, RD32, E}}}, - {O (O_MOV, SL), AV_H8H, 6, "mov.l", {{RSPOSTINC, RD32, E}}, {{PREFIX_0100, 0x6, 0xd, B30 | RSPOSTINC, RD32, E}}}, - {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RSPOSTDEC, RD32, E}}, {{PREFIX_0102, 0x6, 0xd, B30 | RSPOSTDEC, RD32, E}}}, - {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RSPREINC, RD32, E}}, {{PREFIX_0101, 0x6, 0xd, B30 | RSPREINC, RD32, E}}}, - {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RSPREDEC, RD32, E}}, {{PREFIX_0103, 0x6, 0xd, B30 | RSPREDEC, RD32, E}}}, - {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{DISP2SRC, RD32, E}}, {{PREFIX_010, B30 | B20 | DISP2SRC, 0x6, 0x9, B30 | DISPREG, RD32, E}}}, - {O (O_MOV, SL), AV_H8H, 6, "mov.l", {{DISP16SRC, RD32, E}}, {{PREFIX_0100, 0x6, 0xf, B30 | DISPREG, RD32, SRC | DISP16LIST, E}}}, - {O (O_MOV, SL), AV_H8SX, 6, "mov.l", {{DISP32SRC, RD32, E}}, {{0x7, 0x8, B31 | DISPREG, 0x0, 0x6, 0xb, 0x2, RD32, SRC | DISP32LIST, E}}}, - {O (O_MOV, SL), AV_H8H, 6, "mov.l", {{DISP32SRC, RD32, E}}, {{PREFIX_0100, 0x7, 0x8, B30 | DISPREG, 0x0, 0x6, 0xb, 0x2, RD32, MEMRELAX | SRC | DISP32LIST, E}}}, - {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{INDEXB16, RD32, E}}, {{PREFIX_0101, 0x6, 0xf, B30 | DISPREG, RD32, SRC | DISP16LIST, E}}}, - {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{INDEXW16, RD32, E}}, {{PREFIX_0102, 0x6, 0xf, B30 | DISPREG, RD32, SRC | DISP16LIST, E}}}, - {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{INDEXL16, RD32, E}}, {{PREFIX_0103, 0x6, 0xf, B30 | DISPREG, RD32, SRC | DISP16LIST, E}}}, - {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{INDEXB32, RD32, E}}, {{0x7, 0x8, B31 | DISPREG, 0x1, 0x6, 0xb, 0x2, RD32, SRC | DISP32LIST, E}}}, - {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{INDEXW32, RD32, E}}, {{0x7, 0x8, B31 | DISPREG, 0x2, 0x6, 0xb, 0x2, RD32, SRC | DISP32LIST, E}}}, - {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{INDEXL32, RD32, E}}, {{0x7, 0x8, B31 | DISPREG, 0x3, 0x6, 0xb, 0x2, RD32, SRC | DISP32LIST, E}}}, - {O (O_MOV, SL), AV_H8H, 6, "mov.l", {{ABS16SRC, RD32, E}}, {{PREFIX_0100, 0x6, 0xb, 0x0, RD32, SRC | ABS16LIST, E}}}, - {O (O_MOV, SL), AV_H8H, 6, "mov.l", {{ABS32SRC, RD32, E}}, {{PREFIX_0100, 0x6, 0xb, 0x2, RD32, SRC | MEMRELAX | ABS32LIST, E}}}, - - MOVFROM_STD (O (O_MOV, SL), PREFIX_0108, "mov.l", RSIND, FROM_IND), - MOVFROM_STD (O (O_MOV, SL), PREFIX_0108, "mov.l", RSPOSTINC, FROM_POSTINC), - MOVFROM_STD (O (O_MOV, SL), PREFIX_0108, "mov.l", RSPOSTDEC, FROM_POSTDEC), - MOVFROM_STD (O (O_MOV, SL), PREFIX_0108, "mov.l", RSPREINC, FROM_PREINC), - MOVFROM_STD (O (O_MOV, SL), PREFIX_0108, "mov.l", RSPREDEC, FROM_PREDEC), - MOVFROM_STD (O (O_MOV, SL), PREFIX_0108, "mov.l", DISP2SRC, FROM_DISP2), - MOVFROM_AD (O (O_MOV, SL), PREFIX_0108, "mov.l", DISP16SRC, FROM_DISP16, DISP16LIST), - MOVFROM_AD (O (O_MOV, SL), PREFIX_0108, "mov.l", DISP32SRC, FROM_DISP32, DISP32LIST), - MOVFROM_AD (O (O_MOV, SL), PREFIX_0108, "mov.l", INDEXB16, FROM_DISP16B, DISP16LIST), - MOVFROM_AD (O (O_MOV, SL), PREFIX_0108, "mov.l", INDEXW16, FROM_DISP16W, DISP16LIST), - MOVFROM_AD (O (O_MOV, SL), PREFIX_0108, "mov.l", INDEXL16, FROM_DISP16L, DISP16LIST), - MOVFROM_AD (O (O_MOV, SL), PREFIX_0108, "mov.l", INDEXB32, FROM_DISP32B, DISP32LIST), - MOVFROM_AD (O (O_MOV, SL), PREFIX_0108, "mov.l", INDEXW32, FROM_DISP32W, DISP32LIST), - MOVFROM_AD (O (O_MOV, SL), PREFIX_0108, "mov.l", INDEXL32, FROM_DISP32L, DISP32LIST), - MOVFROM_AD (O (O_MOV, SL), PREFIX_0108, "mov.l", ABS16SRC, FROM_ABS16, ABS16LIST), - MOVFROM_AD (O (O_MOV, SL), PREFIX_0108, "mov.l", ABS32SRC, FROM_ABS32, ABS32LIST), - -#define DO_MOVA1(TYPE, OP0, OP1) \ - {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0x8, B30 | R3_32, MEMRELAX | DISP16LIST, E}}}, \ - {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0x9, B30 | R3_32, MEMRELAX | DISP16LIST, E}}}, \ - {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xA, B30 | R3_32, MEMRELAX | DISP16LIST, E}}}, \ - {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xB, B30 | R3_32, MEMRELAX | DISP16LIST, E}}}, \ - {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xC, B30 | R3_32, MEMRELAX | DISP16LIST, E}}}, \ - {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xD, B30 | R3_32, MEMRELAX | DISP16LIST, E}}}, \ -\ - {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0x8, B31 | R3_32, MEMRELAX | DISP32LIST, E}}}, \ - {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0x9, B31 | R3_32, MEMRELAX | DISP32LIST, E}}}, \ - {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xA, B31 | R3_32, MEMRELAX | DISP32LIST, E}}}, \ - {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xB, B31 | R3_32, MEMRELAX | DISP32LIST, E}}}, \ - {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xC, B31 | R3_32, MEMRELAX | DISP32LIST, E}}}, \ - {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xD, B31 | R3_32, MEMRELAX | DISP32LIST, E}}} - -#define DO_MOVA2(TYPE, OP0, OP1, OP2) \ - {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0x8, B30 | R3_32, OP2, MEMRELAX | DISP16LIST, E}}}, \ - {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0x9, B30 | R3_32, OP2, MEMRELAX | DISP16LIST, E}}}, \ - {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xA, B30 | R3_32, OP2, MEMRELAX | DISP16LIST, E}}}, \ - {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xB, B30 | R3_32, OP2, MEMRELAX | DISP16LIST, E}}}, \ - {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xC, B30 | R3_32, OP2, MEMRELAX | DISP16LIST, E}}}, \ - {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xD, B30 | R3_32, OP2, MEMRELAX | DISP16LIST, E}}}, \ -\ - {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0x8, B31 | R3_32, OP2, MEMRELAX | DISP32LIST, E}}}, \ - {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0x9, B31 | R3_32, OP2, MEMRELAX | DISP32LIST, E}}}, \ - {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xA, B31 | R3_32, OP2, MEMRELAX | DISP32LIST, E}}}, \ - {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xB, B31 | R3_32, OP2, MEMRELAX | DISP32LIST, E}}}, \ - {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xC, B31 | R3_32, OP2, MEMRELAX | DISP32LIST, E}}}, \ - {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xD, B31 | R3_32, OP2, MEMRELAX | DISP32LIST, E}}} - - {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB16, E}}, {{0x7, 0xA, 0x8, B31 | DISPREG, MEMRELAX | DISP16LIST, E}}}, - {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW16, E}}, {{0x7, 0xA, 0x9, B31 | DISPREG, MEMRELAX | DISP16LIST, E}}}, - {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB16, E}}, {{0x7, 0xA, 0xA, B31 | DISPREG, MEMRELAX | DISP16LIST, E}}}, - {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW16, E}}, {{0x7, 0xA, 0xB, B31 | DISPREG, MEMRELAX | DISP16LIST, E}}}, - {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB16, E}}, {{0x7, 0xA, 0xC, B31 | DISPREG, MEMRELAX | DISP16LIST, E}}}, - {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW16, E}}, {{0x7, 0xA, 0xD, B31 | DISPREG, MEMRELAX | DISP16LIST, E}}}, - - {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB32, E}}, {{0x7, 0xA, 0x8, B30 | DISPREG, MEMRELAX | DISP32LIST, E}}}, - {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW32, E}}, {{0x7, 0xA, 0x9, B30 | DISPREG, MEMRELAX | DISP32LIST, E}}}, - {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB32, E}}, {{0x7, 0xA, 0xA, B30 | DISPREG, MEMRELAX | DISP32LIST, E}}}, - {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW32, E}}, {{0x7, 0xA, 0xB, B30 | DISPREG, MEMRELAX | DISP32LIST, E}}}, - {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB32, E}}, {{0x7, 0xA, 0xC, B30 | DISPREG, MEMRELAX | DISP32LIST, E}}}, - {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW32, E}}, {{0x7, 0xA, 0xD, B30 | DISPREG, MEMRELAX | DISP32LIST, E}}}, - - {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB16, RD8, R3_32}}, {{0x7, 0x8, RD8, 0x8, 0x7, 0xA, 0x8, B31 | R3_32, MEMRELAX | DISP16LIST, E}}}, - {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW16, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0x9, B31 | R3_32, MEMRELAX | DISP16LIST, E}}}, - {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB16, RD8, R3_32}}, {{0x7, 0x8, RD8, 0x8, 0x7, 0xA, 0xA, B31 | R3_32, MEMRELAX | DISP16LIST, E}}}, - {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW16, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0xB, B31 | R3_32, MEMRELAX | DISP16LIST, E}}}, - {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB16, RD8, R3_32}}, {{0x7, 0x8, RD8, 0x8, 0x7, 0xA, 0xC, B31 | R3_32, MEMRELAX | DISP16LIST, E}}}, - {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW16, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0xD, B31 | R3_32, MEMRELAX | DISP16LIST, E}}}, - - {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB32, RD8, R3_32}}, {{0x7, 0x8, RD8, 0x8, 0x7, 0xA, 0x8, B30 | R3_32, MEMRELAX | DISP32LIST, E}}}, - {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW32, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0x9, B30 | R3_32, MEMRELAX | DISP32LIST, E}}}, - {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB32, RD8, R3_32}}, {{0x7, 0x8, RD8, 0x8, 0x7, 0xA, 0xA, B30 | R3_32, MEMRELAX | DISP32LIST, E}}}, - {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW32, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0xB, B30 | R3_32, MEMRELAX | DISP32LIST, E}}}, - {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB32, RD8, R3_32}}, {{0x7, 0x8, RD8, 0x8, 0x7, 0xA, 0xC, B30 | R3_32, MEMRELAX | DISP32LIST, E}}}, - {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW32, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0xD, B30 | R3_32, MEMRELAX | DISP32LIST, E}}}, - - DO_MOVA1 (RDIND, 0x0, B30 | RDIND), - DO_MOVA1 (RDPOSTINC, 0x8, B30 | RDPOSTINC), - DO_MOVA1 (RDPOSTDEC, 0xA, B30 | RDPOSTDEC), - DO_MOVA1 (RDPREINC, 0x9, B30 | RDPREINC), - DO_MOVA1 (RDPREDEC, 0xB, B30 | RDPREDEC), - DO_MOVA1 (DISP2DST, B30 | B20 | DISP2DST, B30 | DSTDISPREG), - DO_MOVA2 (DISP16DST, 0xC, B30 | DSTDISPREG, MEMRELAX | DSTDISP16LIST), - DO_MOVA2 (DISP32DST, 0xC, B31 | DSTDISPREG, MEMRELAX | DSTDISP32LIST), - DO_MOVA2 (INDEXB16D, 0xD, B30 | DSTDISPREG, MEMRELAX | DSTDISP16LIST), - DO_MOVA2 (INDEXW16D, 0xE, B30 | DSTDISPREG, MEMRELAX | DSTDISP16LIST), - DO_MOVA2 (INDEXL16D, 0xF, B30 | DSTDISPREG, MEMRELAX | DSTDISP16LIST), - DO_MOVA2 (INDEXB32D, 0xD, B31 | DSTDISPREG, MEMRELAX | DSTDISP32LIST), - DO_MOVA2 (INDEXW32D, 0xE, B31 | DSTDISPREG, MEMRELAX | DSTDISP32LIST), - DO_MOVA2 (INDEXL32D, 0xF, B31 | DSTDISPREG, MEMRELAX | DSTDISP32LIST), - DO_MOVA2 (ABS16DST, 0x4, 0x0, MEMRELAX | DSTABS16LIST), - DO_MOVA2 (ABS32DST, 0x4, 0x8, MEMRELAX | DSTABS32LIST), - - {O (O_MOV, SB), AV_H8, 10, "movfpe", {{ABS16SRC, RD8, E}}, {{0x6, 0xA, 0x4, RD8, ABS16SRC, DATA3, E}}}, - {O (O_MOV, SB), AV_H8, 10, "movtpe", {{RS8, ABS16DST, E}}, {{0x6, 0xA, 0xC, RS8, ABS16DST, DATA3, E}}}, - - {O (O_MOVMD, SB), AV_H8SX, 0, "movmd.b", {{E}}, {{0x7, 0xb, 0x9, 0x4, E}}}, - {O (O_MOVMD, SW), AV_H8SX, 0, "movmd.w", {{E}}, {{0x7, 0xb, 0xa, 0x4, E}}}, - {O (O_MOVMD, SL), AV_H8SX, 0, "movmd.l", {{E}}, {{0x7, 0xb, 0xb, 0x4, E}}}, - {O (O_MOVSD, SB), AV_H8SX, 0, "movsd.b", {{PCREL16, E}}, {{0x7, 0xb, 0x8, 0x4, PCREL16, DATA3, E}}}, - - {O (O_MULS, SW), AV_H8SX, 0, "muls.w", {{IMM4, RD16, E}}, {{0x0, 0x1, 0xc, 0x6, 0x5, 0x0, IMM4, RD16, E}}}, - {O (O_MULS, SW), AV_H8SX, 0, "muls.w", {{RS16, RD16, E}}, {{0x0, 0x1, 0xc, 0x2, 0x5, 0x0, RS16, RD16, E}}}, - {O (O_MULS, SL), AV_H8SX, 0, "muls.l", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xc, 0x6, 0x5, 0x2, IMM4, B30 | RD32, E}}}, - {O (O_MULS, SL), AV_H8SX, 0, "muls.l", {{RS32, RD32, E}}, {{0x0, 0x1, 0xc, 0x2, 0x5, 0x2, B30 | RS32, B30 | RD32, E}}}, - - {O (O_MULU, SW), AV_H8SX, 0, "mulu.w", {{IMM4, RD16, E}}, {{0x0, 0x1, 0xc, 0xe, 0x5, 0x0, IMM4, RD16, E}}}, - {O (O_MULU, SW), AV_H8SX, 0, "mulu.w", {{RS16, RD16, E}}, {{0x0, 0x1, 0xc, 0xa, 0x5, 0x0, RS16, RD16, E}}}, - {O (O_MULU, SL), AV_H8SX, 0, "mulu.l", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xc, 0xe, 0x5, 0x2, IMM4, B30 | RD32, E}}}, - {O (O_MULU, SL), AV_H8SX, 0, "mulu.l", {{RS32, RD32, E}}, {{0x0, 0x1, 0xc, 0xa, 0x5, 0x2, B30 | RS32, B30 | RD32, E}}}, - - {O (O_MULSU, SL), AV_H8SX, 0, "muls/u.l", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xc, 0x7, 0x5, 0x2, IMM4, B30 | RD32, E}}}, - {O (O_MULSU, SL), AV_H8SX, 0, "muls/u.l", {{RS32, RD32, E}}, {{0x0, 0x1, 0xc, 0x3, 0x5, 0x2, B30 | RS32, B30 | RD32, E}}}, - {O (O_MULUU, SL), AV_H8SX, 0, "mulu/u.l", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xc, 0xf, 0x5, 0x2, IMM4, B30 | RD32, E}}}, - {O (O_MULUU, SL), AV_H8SX, 0, "mulu/u.l", {{RS32, RD32, E}}, {{0x0, 0x1, 0xc, 0xb, 0x5, 0x2, B30 | RS32, B30 | RD32, E}}}, - - {O (O_MULXS, SB), AV_H8SX, 0, "mulxs.b", {{IMM4, RD16, E}}, {{0x0, 0x1, 0xc, 0x4, 0x5, 0x0, IMM4, RD16, E}}}, - {O (O_MULXS, SB), AV_H8H, 20, "mulxs.b", {{RS8, RD16, E}}, {{0x0, 0x1, 0xc, 0x0, 0x5, 0x0, RS8, RD16, E}}}, - {O (O_MULXS, SW), AV_H8SX, 0, "mulxs.w", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xc, 0x4, 0x5, 0x2, IMM4, B30 | RD32, E}}}, - {O (O_MULXS, SW), AV_H8H, 20, "mulxs.w", {{RS16, RD32, E}}, {{0x0, 0x1, 0xc, 0x0, 0x5, 0x2, RS16, B30 | RD32, E}}}, - - {O (O_MULXU, SB), AV_H8SX, 0, "mulxu.b", {{IMM4, RD16, E}}, {{0x0, 0x1, 0xc, 0xc, 0x5, 0x0, IMM4, RD16, E}}}, - {O (O_MULXU, SB), AV_H8, 14, "mulxu.b", {{RS8, RD16, E}}, {{0x5, 0x0, RS8, RD16, E}}}, - {O (O_MULXU, SW), AV_H8SX, 0, "mulxu.w", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xc, 0xc, 0x5, 0x2, IMM4, B30 | RD32, E}}}, - {O (O_MULXU, SW), AV_H8H, 14, "mulxu.w", {{RS16, RD32, E}}, {{0x5, 0x2, RS16, B30 | RD32, E}}}, - - EXPAND_UNOP_STD_B (O (O_NEG, SB), "neg.b", PREFIX_017, 0x1, 0x7, 0x8), - EXPAND_UNOP_STD_W (O (O_NEG, SW), "neg.w", PREFIX_015, 0x1, 0x7, 0x9), - EXPAND_UNOP_STD_L (O (O_NEG, SL), "neg.l", PREFIX_010, 0x1, 0x7, 0xb), - - {O (O_NOP, SN), AV_H8, 2, "nop", {{E}}, {{0x0, 0x0, 0x0, 0x0, E}}}, - - EXPAND_UNOP_STD_B (O (O_NOT, SB), "not.b", PREFIX_017, 0x1, 0x7, 0x0), - EXPAND_UNOP_STD_W (O (O_NOT, SW), "not.w", PREFIX_015, 0x1, 0x7, 0x1), - EXPAND_UNOP_STD_L (O (O_NOT, SL), "not.l", PREFIX_010, 0x1, 0x7, 0x3), - - {O (O_OR, SB), AV_H8, 2, "or.b", {{IMM8, RD8, E}}, {{0xc, RD8, IMM8LIST, E}}}, - EXPAND_TWOOP_B (O (O_OR, SB), "or.b", 0xc, 0x1, 0x4, 0x4, 0), - - {O (O_OR, SW), AV_H8, 2, "or.w", {{RS16, RD16, E}}, {{0x6, 0x4, RS16, RD16, E}}}, - EXPAND_TWOOP_W (O (O_OR, SW), "or.w", 0x6, 0x4, 0x4), - - {O (O_OR, SL), AV_H8H, 2, "or.l", {{RS32, RD32, E}}, {{0x0, 0x1, 0xF, 0x0, 0x6, 0x4, B30 | RS32, B30 | RD32, E}}}, - EXPAND_TWOOP_L (O (O_OR, SL), "or.l", 0x4), - - {O (O_ORC, SB), AV_H8, 2, "orc", {{IMM8, CCR | DST, E}}, {{0x0, 0x4, IMM8LIST, E}}}, - {O (O_ORC, SB), AV_H8S, 2, "orc", {{IMM8, EXR | DST, E}}, {{0x0, 0x1, 0x4, EXR | DST, 0x0, 0x4, IMM8LIST, E}}}, - - {O (O_MOV, SW), AV_H8, 6, "pop.w", {{OR16, E}}, {{0x6, 0xD, 0x7, OR16, E}}}, - {O (O_MOV, SL), AV_H8H, 6, "pop.l", {{OR32, E}}, {{PREFIX_0100, 0x6, 0xD, 0x7, OR32 | B30, E}}}, - {O (O_MOV, SW), AV_H8, 6, "push.w", {{OR16, E}}, {{0x6, 0xD, 0xF, OR16, E}}}, - {O (O_MOV, SL), AV_H8H, 6, "push.l", {{OR32, E}}, {{PREFIX_0100, 0x6, 0xD, 0xF, OR32 | B30, E}}}, - - EXPAND_UNOP_STD_B (O (O_ROTL, SB), "rotl.b", PREFIX_017, 0x1, 0x2, 0x8), - EXPAND_UNOP_EXTENDED_B (O (O_ROTL, SB), "rotl.b", CONST_2, PREFIX_017, 0x1, 0x2, 0xc), - EXPAND_UNOP_STD_W (O (O_ROTL, SW), "rotl.w", PREFIX_015, 0x1, 0x2, 0x9), - EXPAND_UNOP_EXTENDED_W (O (O_ROTL, SW), "rotl.w", CONST_2, PREFIX_015, 0x1, 0x2, 0xd), - EXPAND_UNOP_STD_L (O (O_ROTL, SL), "rotl.l", PREFIX_010, 0x1, 0x2, 0xb), - EXPAND_UNOP_EXTENDED_L (O (O_ROTL, SL), "rotl.l", CONST_2, PREFIX_010, 0x1, 0x2, 0xf, B30), - EXPAND_UNOP_STD_B (O (O_ROTR, SB), "rotr.b", PREFIX_017, 0x1, 0x3, 0x8), - EXPAND_UNOP_EXTENDED_B (O (O_ROTR, SB), "rotr.b", CONST_2, PREFIX_017, 0x1, 0x3, 0xc), - EXPAND_UNOP_STD_W (O (O_ROTR, SW), "rotr.w", PREFIX_015, 0x1, 0x3, 0x9), - EXPAND_UNOP_EXTENDED_W (O (O_ROTR, SW), "rotr.w", CONST_2, PREFIX_015, 0x1, 0x3, 0xd), - EXPAND_UNOP_STD_L (O (O_ROTR, SL), "rotr.l", PREFIX_010, 0x1, 0x3, 0xb), - EXPAND_UNOP_EXTENDED_L (O (O_ROTR, SL), "rotr.l", CONST_2, PREFIX_010, 0x1, 0x3, 0xf, B30), - EXPAND_UNOP_STD_B (O (O_ROTXL, SB), "rotxl.b", PREFIX_017, 0x1, 0x2, 0x0), - EXPAND_UNOP_EXTENDED_B (O (O_ROTXL, SB), "rotxl.b", CONST_2, PREFIX_017, 0x1, 0x2, 0x4), - EXPAND_UNOP_STD_W (O (O_ROTXL, SW), "rotxl.w", PREFIX_015, 0x1, 0x2, 0x1), - EXPAND_UNOP_EXTENDED_W (O (O_ROTXL, SW), "rotxl.w", CONST_2, PREFIX_015, 0x1, 0x2, 0x5), - EXPAND_UNOP_STD_L (O (O_ROTXL, SL), "rotxl.l", PREFIX_010, 0x1, 0x2, 0x3), - EXPAND_UNOP_EXTENDED_L (O (O_ROTXL, SL), "rotxl.l", CONST_2, PREFIX_010, 0x1, 0x2, 0x7, B30), - EXPAND_UNOP_STD_B (O (O_ROTXR, SB), "rotxr.b", PREFIX_017, 0x1, 0x3, 0x0), - EXPAND_UNOP_EXTENDED_B (O (O_ROTXR, SB), "rotxr.b", CONST_2, PREFIX_017, 0x1, 0x3, 0x4), - EXPAND_UNOP_STD_W (O (O_ROTXR, SW), "rotxr.w", PREFIX_015, 0x1, 0x3, 0x1), - EXPAND_UNOP_EXTENDED_W (O (O_ROTXR, SW), "rotxr.w", CONST_2, PREFIX_015, 0x1, 0x3, 0x5), - EXPAND_UNOP_STD_L (O (O_ROTXR, SL), "rotxr.l", PREFIX_010, 0x1, 0x3, 0x3), - EXPAND_UNOP_EXTENDED_L (O (O_ROTXR, SL), "rotxr.l", CONST_2, PREFIX_010, 0x1, 0x3, 0x7, B30), - - - {O (O_BPT, SN), AV_H8, 10, "bpt", {{E}}, {{0x7, 0xA, 0xF, 0xF, E}}}, - {O (O_RTE, SN), AV_H8, 10, "rte", {{E}}, {{0x5, 0x6, 0x7, 0x0, E}}}, - {O (O_RTS, SN), AV_H8, 8, "rts", {{E}}, {{0x5, 0x4, 0x7, 0x0, E}}}, - {O (O_RTEL, SN), AV_H8SX, 0, "rte/l", {{RS32, RD32, E}}, {{0x5, 0x6, RS32 | B30, RD32 | B30, E}}}, - {O (O_RTSL, SN), AV_H8SX, 0, "rts/l", {{RS32, RD32, E}}, {{0x5, 0x4, RS32 | B30, RD32 | B30, E}}}, - - EXPAND_UNOP_STD_B (O (O_SHAL, SB), "shal.b", PREFIX_017, 0x1, 0x0, 0x8), - EXPAND_UNOP_EXTENDED_B (O (O_SHAL, SB), "shal.b", CONST_2, PREFIX_017, 0x1, 0x0, 0xc), - EXPAND_UNOP_STD_W (O (O_SHAL, SW), "shal.w", PREFIX_015, 0x1, 0x0, 0x9), - EXPAND_UNOP_EXTENDED_W (O (O_SHAL, SW), "shal.w", CONST_2, PREFIX_015, 0x1, 0x0, 0xd), - EXPAND_UNOP_STD_L (O (O_SHAL, SL), "shal.l", PREFIX_010, 0x1, 0x0, 0xb), - EXPAND_UNOP_EXTENDED_L (O (O_SHAL, SL), "shal.l", CONST_2, PREFIX_010, 0x1, 0x0, 0xf, B30), - EXPAND_UNOP_STD_B (O (O_SHAR, SB), "shar.b", PREFIX_017, 0x1, 0x1, 0x8), - EXPAND_UNOP_EXTENDED_B (O (O_SHAR, SB), "shar.b", CONST_2, PREFIX_017, 0x1, 0x1, 0xc), - EXPAND_UNOP_STD_W (O (O_SHAR, SW), "shar.w", PREFIX_015, 0x1, 0x1, 0x9), - EXPAND_UNOP_EXTENDED_W (O (O_SHAR, SW), "shar.w", CONST_2, PREFIX_015, 0x1, 0x1, 0xd), - EXPAND_UNOP_STD_L (O (O_SHAR, SL), "shar.l", PREFIX_010, 0x1, 0x1, 0xb), - EXPAND_UNOP_EXTENDED_L (O (O_SHAR, SL), "shar.l", CONST_2, PREFIX_010, 0x1, 0x1, 0xf, B30), - - EXPAND_UNOP_STD_B (O (O_SHLL, SB), "shll.b", PREFIX_017, 0x1, 0x0, 0x0), - - {O (O_SHLL, SB), AV_H8SX, 0, "shll.b", {{RS8, RD8, E}}, {{0x7, 0x8, RS8, 0x8, 0x1, 0x0, 0x0, RD8, E}}}, - - EXPAND_UNOP_EXTENDED_B (O (O_SHLL, SB), "shll.b", CONST_2, PREFIX_017, 0x1, 0x0, 0x4), - EXPAND_UNOP_EXTENDED_B (O (O_SHLL, SB), "shll.b", CONST_4, PREFIX_017, 0x1, 0x0, 0xa), - {O (O_SHLL, SB), AV_H8SX, 0, "shll.b", {{IMM5, RD8, E}}, {{0x0, 0x3, B31 | IMM5, DATA, 0x1, 0x0, 0x0, RD8, E}}}, - - EXPAND_UNOP_STD_W (O (O_SHLL, SW), "shll.w", PREFIX_015, 0x1, 0x0, 0x1), - - {O (O_SHLL, SW), AV_H8SX, 0, "shll.w", {{RS8, RD16, E}}, {{0x7, 0x8, RS8, 0x8, 0x1, 0x0, 0x1, RD16, E}}}, - - EXPAND_UNOP_EXTENDED_W (O (O_SHLL, SW), "shll.w", CONST_2, PREFIX_015, 0x1, 0x0, 0x5), - EXPAND_UNOP_EXTENDED_W (O (O_SHLL, SW), "shll.w", CONST_4, PREFIX_015, 0x1, 0x0, 0x2), - EXPAND_UNOP_EXTENDED_W (O (O_SHLL, SW), "shll.w", CONST_8, PREFIX_015, 0x1, 0x0, 0x6), - {O (O_SHLL, SW), AV_H8SX, 0, "shll.w", {{IMM5, RD16, E}}, {{0x0, 0x3, B31 | IMM5, DATA, 0x1, 0x0, 0x1, RD16, E}}}, - - EXPAND_UNOP_STD_L (O (O_SHLL, SL), "shll.l", PREFIX_010, 0x1, 0x0, 0x3), - - {O (O_SHLL, SL), AV_H8SX, 0, "shll.l", {{RS8, RD32, E}}, {{0x7, 0x8, RS8, 0x8, 0x1, 0x0, 0x3, B30 | RD32, E}}}, - - EXPAND_UNOP_EXTENDED_L (O (O_SHLL, SL), "shll.l", CONST_2, PREFIX_010, 0x1, 0x0, 0x7, B30), - EXPAND_UNOP_EXTENDED_L (O (O_SHLL, SL), "shll.l", CONST_4, PREFIX_010, 0x1, 0x0, 0x3, B31), - EXPAND_UNOP_EXTENDED_L (O (O_SHLL, SL), "shll.l", CONST_8, PREFIX_010, 0x1, 0x0, 0x7, B31), - EXPAND_UNOP_EXTENDED_L (O (O_SHLL, SL), "shll.l", CONST_16, PREFIX_010, 0x1, 0x0, 0xf, B31), - {O (O_SHLL, SL), AV_H8SX, 0, "shll.l", {{IMM5, RD32, E}}, {{0x0, 0x3, B31 | IMM5, DATA, 0x1, 0x0, 0x3, B30 | RD32, E}}}, - - EXPAND_UNOP_STD_B (O (O_SHLR, SB), "shlr.b", PREFIX_017, 0x1, 0x1, 0x0), - - {O (O_SHLR, SB), AV_H8SX, 0, "shlr.b", {{RS8, RD8, E}}, {{0x7, 0x8, RS8, 0x8, 0x1, 0x1, 0x0, RD8, E}}}, - - EXPAND_UNOP_EXTENDED_B (O (O_SHLR, SB), "shlr.b", CONST_2, PREFIX_017, 0x1, 0x1, 0x4), - EXPAND_UNOP_EXTENDED_B (O (O_SHLR, SB), "shlr.b", CONST_4, PREFIX_017, 0x1, 0x1, 0xa), - {O (O_SHLR, SB), AV_H8SX, 0, "shlr.b", {{IMM5, RD8, E}}, {{0x0, 0x3, B31 | IMM5, DATA, 0x1, 0x1, 0x0, RD8, E}}}, - - EXPAND_UNOP_STD_W (O (O_SHLR, SW), "shlr.w", PREFIX_015, 0x1, 0x1, 0x1), - - {O (O_SHLR, SW), AV_H8SX, 0, "shlr.w", {{RS8, RD16, E}}, {{0x7, 0x8, RS8, 0x8, 0x1, 0x1, 0x1, RD16, E}}}, - - EXPAND_UNOP_EXTENDED_W (O (O_SHLR, SW), "shlr.w", CONST_2, PREFIX_015, 0x1, 0x1, 0x5), - EXPAND_UNOP_EXTENDED_W (O (O_SHLR, SW), "shlr.w", CONST_4, PREFIX_015, 0x1, 0x1, 0x2), - EXPAND_UNOP_EXTENDED_W (O (O_SHLR, SW), "shlr.w", CONST_8, PREFIX_015, 0x1, 0x1, 0x6), - {O (O_SHLR, SW), AV_H8SX, 0, "shlr.w", {{IMM5, RD16, E}}, {{0x0, 0x3, B31 | IMM5, DATA, 0x1, 0x1, 0x1, RD16, E}}}, - - EXPAND_UNOP_STD_L (O (O_SHLR, SL), "shlr.l", PREFIX_010, 0x1, 0x1, 0x3), - - {O (O_SHLR, SL), AV_H8SX, 0, "shlr.l", {{RS8, RD32, E}}, {{0x7, 0x8, RS8, 0x8, 0x1, 0x1, 0x3, B30 | RD32, E}}}, - - EXPAND_UNOP_EXTENDED_L (O (O_SHLR, SL), "shlr.l", CONST_2, PREFIX_010, 0x1, 0x1, 0x7, B30), - EXPAND_UNOP_EXTENDED_L (O (O_SHLR, SL), "shlr.l", CONST_4, PREFIX_010, 0x1, 0x1, 0x3, B31), - EXPAND_UNOP_EXTENDED_L (O (O_SHLR, SL), "shlr.l", CONST_8, PREFIX_010, 0x1, 0x1, 0x7, B31), - EXPAND_UNOP_EXTENDED_L (O (O_SHLR, SL), "shlr.l", CONST_16, PREFIX_010, 0x1, 0x1, 0xf, B31), - {O (O_SHLR, SL), AV_H8SX, 0, "shlr.l", {{IMM5, RD32, E}}, {{0x0, 0x3, B31 | IMM5, DATA, 0x1, 0x1, 0x3, B30 | RD32, E}}}, - - {O (O_SLEEP, SN), AV_H8, 2, "sleep", {{E}}, {{0x0, 0x1, 0x8, 0x0, E}}}, - - {O (O_STC, SB), AV_H8, 2, "stc", {{CCR | SRC, RD8, E}}, {{0x0, 0x2, B30 | CCR | SRC, RD8, E}}}, - {O (O_STC, SB), AV_H8S, 2, "stc", {{EXR | SRC, RD8, E}}, {{0x0, 0x2, B30 | EXR | SRC, RD8, E}}}, - {O (O_STC, SW), AV_H8H, 2, "stc", {{CCR | SRC, RDIND, E}}, {{PREFIXSTC, 0x6, 0x9, B31 | RDIND, IGNORE, E}}}, - {O (O_STC, SW), AV_H8S, 2, "stc", {{EXR | SRC, RDIND, E}}, {{PREFIXSTC, 0x6, 0x9, B31 | RDIND, IGNORE, E}}}, - {O (O_STC, SW), AV_H8H, 2, "stc", {{CCR | SRC, RDPREDEC, E}}, {{PREFIXSTC, 0x6, 0xD, B31 | RDPREDEC, IGNORE, E}}}, - {O (O_STC, SW), AV_H8S, 2, "stc", {{EXR | SRC, RDPREDEC, E}}, {{PREFIXSTC, 0x6, 0xD, B31 | RDPREDEC, IGNORE, E}}}, - {O (O_STC, SW), AV_H8H, 2, "stc", {{CCR | SRC, DISP16DST, E}}, {{PREFIXSTC, 0x6, 0xF, B31 | DSTDISPREG, IGNORE, DSTDISP16LIST, E}}}, - {O (O_STC, SW), AV_H8S, 2, "stc", {{EXR | SRC, DISP16DST, E}}, {{PREFIXSTC, 0x6, 0xF, B31 | DSTDISPREG, IGNORE, DSTDISP16LIST, E}}}, - {O (O_STC, SW), AV_H8H, 2, "stc", {{CCR | SRC, DISP32DST, E}}, {{PREFIXSTC, 0x7, 0x8, B30 | DSTDISPREG, 0, 0x6, 0xB, 0xA, IGNORE, DSTDISP32LIST, E}}}, - {O (O_STC, SW), AV_H8S, 2, "stc", {{EXR | SRC, DISP32DST, E}}, {{PREFIXSTC, 0x7, 0x8, B30 | DSTDISPREG, 0, 0x6, 0xB, 0xA, IGNORE, DSTDISP32LIST, E}}}, - {O (O_STC, SW), AV_H8H, 2, "stc", {{CCR | SRC, ABS16DST, E}}, {{PREFIXSTC, 0x6, 0xB, 0x8, IGNORE, DST | ABS16LIST, E}}}, - {O (O_STC, SW), AV_H8S, 2, "stc", {{EXR | SRC, ABS16DST, E}}, {{PREFIXSTC, 0x6, 0xB, 0x8, IGNORE, DST | ABS16LIST, E}}}, - {O (O_STC, SW), AV_H8H, 2, "stc", {{CCR | SRC, ABS32DST, E}}, {{PREFIXSTC, 0x6, 0xB, 0xA, IGNORE, DST | MEMRELAX | ABS32LIST, E}}}, - {O (O_STC, SW), AV_H8S, 2, "stc", {{EXR | SRC, ABS32DST, E}}, {{PREFIXSTC, 0x6, 0xB, 0xA, IGNORE, DST | MEMRELAX | ABS32LIST, E}}}, - {O (O_STC, SL), AV_H8SX, 0, "stc", {{B30 | VBR_SBR | SRC, RD32, E}}, {{0x0, 0x2, B30 | VBR_SBR | SRC, RD32, E}}}, - - - EXPAND_TWOOP_B (O (O_SUB, SB), "sub.b", 0xa, 0x1, 0x8, 0x3, B01), - - {O (O_SUB, SW), AV_H8, 2, "sub.w", {{RS16, RD16, E}}, {{0x1, 0x9, RS16, RD16, E}}}, - {O (O_SUB, SW), AV_H8SX, 0, "sub.w", {{IMM3NZ_NS, RD16, E}}, {{0x1, 0xa, B30 | IMM3NZ, RD16, E}}}, - {O (O_SUB, SW), AV_H8SX, 0, "sub.w", {{IMM3NZ_NS, RDIND, E}}, {{0x7, 0xd, B31 | RDIND, IGNORE, 0x1, 0xa, B30 | IMM3NZ, IGNORE, E}}}, - {O (O_SUB, SW), AV_H8SX, 0, "sub.w", {{IMM3NZ_NS, ABS16DST, E}}, {{0x6, 0xb, 0x1, B31 | IGNORE, DSTABS16LIST, 0x1, 0xa, B30 | IMM3NZ, IGNORE, E}}}, - {O (O_SUB, SW), AV_H8SX, 0, "sub.w", {{IMM3NZ_NS, ABS32DST, E}}, {{0x6, 0xb, 0x3, B31 | IGNORE, DSTABS32LIST, 0x1, 0xa, B30 | IMM3NZ, IGNORE, E}}}, - EXPAND_TWOOP_W (O (O_SUB, SW), "sub.w", 0x1, 0x9, 0x3), - - {O (O_SUB, SL), AV_H8H, 6, "sub.l", {{RS32, RD32, E}}, {{0x1, 0xa, B31 | RS32, B30 | RD32, E}}}, - {O (O_SUB, SL), AV_H8SX, 0, "sub.l", {{IMM3NZ_NS, RD32, E}}, {{0x1, 0xa, B31 | IMM3NZ, B31 | RD32, E}}}, - EXPAND_TWOOP_L (O (O_SUB, SL), "sub.l", 0x3), - - {O (O_SUBS, SL), AV_H8, 2, "subs", {{KBIT, RDP, E}}, {{0x1, 0xB,KBIT, RDP, E}}}, - - {O (O_SUBX, SB), AV_H8, 2, "subx", {{IMM8, RD8, E}}, {{0xb, RD8, IMM8LIST, E}}}, - {O (O_SUBX, SB), AV_H8SX, 0, "subx.b", {{IMM8, RDIND, E}}, {{0x7, 0xd, B30 | RDIND, IGNORE, 0xb, IGNORE, IMM8LIST, E}}}, - {O (O_SUBX, SB), AV_H8SX, 0, "subx.b", {{IMM8, RDPOSTDEC, E}}, {{PREFIX_0176, 0x6, 0xc, B30 | RDPOSTDEC, B31 | IGNORE, 0xb, IGNORE, IMM8LIST, E}}}, - {O (O_SUBX, SB), AV_H8, 2, "subx", {{RS8, RD8, E}}, {{0x1, 0xe, RS8, RD8, E}}}, - {O (O_SUBX, SB), AV_H8SX, 0, "subx.b", {{RS8, RDIND, E}}, {{0x7, 0xd, B30 | RDIND, IGNORE, 0x1, 0xe, RS8, IGNORE, E}}}, - {O (O_SUBX, SB), AV_H8SX, 0, "subx.b", {{RS8, RDPOSTDEC, E}}, {{PREFIX_0176, 0x6, 0xc, B30 | RDPOSTDEC, B31 | IGNORE, 0x1, 0xe, RS8, IGNORE, E}}}, - {O (O_SUBX, SB), AV_H8SX, 0, "subx.b", {{RSIND, RD8, E}}, {{0x7, 0xc, B30 | RSIND, IGNORE, 0x1, 0xe, IGNORE, RD8, E}}}, - {O (O_SUBX, SB), AV_H8SX, 0, "subx.b", {{RSPOSTDEC, RD8, E}}, {{PREFIX_0176, 0x6, 0xc, B30 | RSPOSTDEC, B30 | B20 | IGNORE, 0x1, 0xe, IGNORE, RD8, E}}}, - {O (O_SUBX, SB), AV_H8SX, 0, "subx.b", {{RSIND, RDIND, E}}, {{PREFIX_0174, 0x6, 0x8, B30 | RSIND, 0xd, 0x0, RDIND, 0x3, IGNORE, E}}}, - {O (O_SUBX, SB), AV_H8SX, 0, "subx.b", {{RSPOSTDEC, RDPOSTDEC, E}}, {{PREFIX_0176, 0x6, 0xc, B30 | RSPOSTDEC, 0xd, 0xa, RDPOSTDEC, 0x3, IGNORE, E}}}, - - {O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{IMM16, RD16, E}}, {{PREFIX_0151, 0x7, 0x9, 0x3, RD16, IMM16LIST, E}}}, - {O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{IMM16, RDIND, E}}, {{0x7, 0xd, B31 | RDIND, B01 | IGNORE, 0x7, 0x9, 0x3, IGNORE, IMM16LIST, E}}}, - {O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{IMM16, RDPOSTDEC, E}}, {{PREFIX_0156, 0x6, 0xd, B30 | RDPOSTDEC, B31 | B20 | B01 | IGNORE, 0x7, 0x9, 0x3, IGNORE, IMM16LIST, E}}}, - {O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{RS16, RD16, E}}, {{PREFIX_0151, 0x1, 0x9, RS16, RD16, E}}}, - {O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{RS16, RDIND, E}}, {{0x7, 0xd, B31 | RDIND, B01 | IGNORE, 0x1, 0x9, RS16, IGNORE, E}}}, - {O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{RS16, RDPOSTDEC, E}}, {{PREFIX_0156, 0x6, 0xd, B30 | RDPOSTDEC, B31 | B20 | B01 | IGNORE, 0x1, 0x9, RS16, IGNORE, E}}}, - {O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{RSIND, RD16, E}}, {{0x7, 0xc, B31 | RSIND, B01 | IGNORE, 0x1, 0x9, IGNORE, RD16, E}}}, - {O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{RSPOSTDEC, RD16, E}}, {{PREFIX_0156, 0x6, 0xd, B30 | RSPOSTDEC, B30 | B20 | B01 | IGNORE, 0x1, 0x9, IGNORE, RD16, E}}}, - {O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{RSIND, RDIND, E}}, {{PREFIX_0154, 0x6, 0x9, B30 | RSIND, 0xd, 0x0, RDIND, 0x3, IGNORE, E}}}, - {O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{RSPOSTDEC, RDPOSTDEC, E}}, {{PREFIX_0156, 0x6, 0xd, B30 | RSPOSTDEC, 0xd, 0xa, RDPOSTDEC, 0x3, IGNORE, E}}}, - - {O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{IMM32, RD32, E}}, {{PREFIX_0101, 0x7, 0xa, 0x3, RD32, IMM32LIST, E}}}, - {O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{IMM32, RDIND, E}}, {{PREFIX_0104, 0x6, 0x9, B30 | RDIND, B31 | B20 | B01 | IGNORE, 0x7, 0xa, 0x3, IGNORE, IMM32LIST, E}}}, - {O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{IMM32, RDPOSTDEC, E}}, {{PREFIX_0106, 0x6, 0xd, B30 | RDPOSTDEC, B31 | B20 | B01 | IGNORE, 0x7, 0xa, 0x3, IGNORE, IMM32LIST, E}}}, - {O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{RS32, RD32, E}}, {{PREFIX_0101, 0x1, 0xa, B31 | RS32, B30 | RD32, E}}}, - {O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{RS32, RDIND, E}}, {{PREFIX_0104, 0x6, 0x9, B30 | RDIND, B31 | B20 | B01 | IGNORE, 0x1, 0xa, B31 | RS32, B30 | IGNORE, E}}}, - {O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{RS32, RDPOSTDEC, E}}, {{PREFIX_0106, 0x6, 0xd, B30 | RDPOSTDEC, B31 | B20 | B01 | IGNORE, 0x1, 0xa, B31 | RS32, B30 | IGNORE, E}}}, - {O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{RSIND, RD32, E}}, {{PREFIX_0104, 0x6, 0x9, B30 | RSIND, B30 | B20 | B01 | IGNORE, 0x1, 0xa, B31 | IGNORE, B30 | RD32, E}}}, - {O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{RSPOSTDEC, RD32, E}}, {{PREFIX_0106, 0x6, 0xd, B30 | RSPOSTDEC, B30 | B20 | B01 | IGNORE, 0x1, 0xa, B31 | IGNORE, B30 | RD32, E}}}, - {O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{RSIND, RDIND, E}}, {{PREFIX_0104, 0x6, 0x9, B30 | RSIND, 0xd, 0x0, RDIND, 0x3, IGNORE, E}}}, - {O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{RSPOSTDEC, RDPOSTDEC, E}}, {{PREFIX_0106, 0x6, 0xd, B30 | RSPOSTDEC, 0xd, 0xa, RDPOSTDEC, 0x3, IGNORE, E}}}, - - {O (O_TRAPA, SB), AV_H8H, 2, "trapa", {{IMM2, E}}, {{0x5, 0x7, IMM2, IGNORE, E}}}, - {O (O_TAS, SB), AV_H8H, 2, "tas", {{RSIND, E}}, {{0x0, 0x1, 0xe, 0x0, 0x7, 0xb, B30 | RSIND, 0xc, E}}}, - - {O (O_XOR, SB), AV_H8, 2, "xor.b", {{IMM8, RD8, E}}, {{0xd, RD8, IMM8LIST, E}}}, - EXPAND_TWOOP_B (O (O_XOR, SB), "xor.b", 0xd, 0x1, 0x5, 0x5, 0), - - {O (O_XOR, SW), AV_H8, 2, "xor.w", {{RS16, RD16, E}}, {{0x6, 0x5, RS16, RD16, E}}}, - EXPAND_TWOOP_W (O (O_XOR, SW), "xor.w", 0x6, 0x5, 0x5), - - {O (O_XOR, SL), AV_H8H, 2, "xor.l", {{RS32, RD32, E}}, {{0x0, 0x1, 0xF, 0x0, 0x6, 0x5, B30 | RS32, B30 | RD32, E}}}, - EXPAND_TWOOP_L (O (O_XOR, SL), "xor.l", 0x5), - - {O (O_XORC, SB), AV_H8, 2, "xorc", {{IMM8, CCR | DST, E}}, {{0x0, 0x5, IMM8LIST, E}}}, - {O (O_XORC, SB), AV_H8S, 2, "xorc", {{IMM8, EXR | DST, E}}, {{0x0, 0x1, 0x4, EXR | DST, 0x0, 0x5, IMM8LIST, E}}}, - - {O (O_CLRMAC, SN), AV_H8S, 2, "clrmac", {{E}}, {{0x0, 0x1, 0xa, 0x0, E}}}, - {O (O_MAC, SW), AV_H8S, 2, "mac", {{RSPOSTINC, RDPOSTINC, E}}, {{0x0, 0x1, 0x6, 0x0, 0x6, 0xd, B30 | RSPOSTINC, B30 | RDPOSTINC, E}}}, - {O (O_LDMAC, SL), AV_H8S, 2, "ldmac", {{RS32, MD32, E}}, {{0x0, 0x3, MD32, RS32, E}}}, - {O (O_STMAC, SL), AV_H8S, 2, "stmac", {{MS32, RD32, E}}, {{0x0, 0x2, MS32, RD32, E}}}, - {O (O_LDM, SL), AV_H8H, 6, "ldm.l", {{RSPOSTINC, RD32, E}}, {{0x0, 0x1, DATA, 0x0, 0x6, 0xD, 0x7, B30 | RD32, E}}}, - {O (O_STM, SL), AV_H8H, 6, "stm.l", {{RS32, RDPREDEC, E}}, {{0x0, 0x1, DATA, 0x0, 0x6, 0xD, 0xF, B30 | RS32, E}}}, - {0, 0, 0, NULL, {{0, 0, 0}}, {{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}}} -}; -#else -extern const struct h8_opcode h8_opcodes[]; -#endif - diff --git a/include/opcode/hppa.h b/include/opcode/hppa.h deleted file mode 100644 index 489ca55..0000000 --- a/include/opcode/hppa.h +++ /dev/null @@ -1,1092 +0,0 @@ -/* Table of opcodes for the PA-RISC. - Copyright 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000, - 2001, 2002, 2003, 2004, 2005, 2006, 2009, 2010 - Free Software Foundation, Inc. - - Contributed by the Center for Software Science at the - University of Utah (pa-gdb-bugs@cs.utah.edu). - - This file is part of GAS, the GNU Assembler, and GDB, the GNU disassembler. - - GAS/GDB is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3, or (at your option) - any later version. - - GAS/GDB is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with GAS or GDB; see the file COPYING3. If not, write to - the Free Software Foundation, 51 Franklin Street - Fifth Floor, - Boston, MA 02110-1301, USA. */ - -#if !defined(__STDC__) && !defined(const) -#define const -#endif - -/* - * Structure of an opcode table entry. - */ - -/* There are two kinds of delay slot nullification: normal which is - * controled by the nullification bit, and conditional, which depends - * on the direction of the branch and its success or failure. - * - * NONE is unfortunately #defined in the hiux system include files. - * #undef it away. - */ -#undef NONE -struct pa_opcode -{ - const char *name; - unsigned long int match; /* Bits that must be set... */ - unsigned long int mask; /* ... in these bits. */ - char *args; - enum pa_arch arch; - char flags; -}; - -/* Enables strict matching. Opcodes with match errors are skipped - when this bit is set. */ -#define FLAG_STRICT 0x1 - -/* - All hppa opcodes are 32 bits. - - The match component is a mask saying which bits must match a - particular opcode in order for an instruction to be an instance - of that opcode. - - The args component is a string containing one character for each operand of - the instruction. Characters used as a prefix allow any second character to - be used without conflicting with the main operand characters. - - Bit positions in this description follow HP usage of lsb = 31, - "at" is lsb of field. - - In the args field, the following characters must match exactly: - - '+,() ' - - In the args field, the following characters are unused: - - ' " - / 34 6789:; ' - '@ C M [\] ' - '` e g } ' - - Here are all the characters: - - ' !"#$%&'()*+-,./0123456789:;<=>?' - '@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_' - '`abcdefghijklmnopqrstuvwxyz{|}~ ' - -Kinds of operands: - x integer register field at 15. - b integer register field at 10. - t integer register field at 31. - a integer register field at 10 and 15 (for PERMH) - 5 5 bit immediate at 15. - s 2 bit space specifier at 17. - S 3 bit space specifier at 18. - V 5 bit immediate value at 31 - i 11 bit immediate value at 31 - j 14 bit immediate value at 31 - k 21 bit immediate value at 31 - l 16 bit immediate value at 31 (wide mode only, unusual encoding). - n nullification for branch instructions - N nullification for spop and copr instructions - w 12 bit branch displacement - W 17 bit branch displacement (PC relative) - X 22 bit branch displacement (PC relative) - z 17 bit branch displacement (just a number, not an address) - -Also these: - - . 2 bit shift amount at 25 - * 4 bit shift amount at 25 - p 5 bit shift count at 26 (to support the SHD instruction) encoded as - 31-p - ~ 6 bit shift count at 20,22:26 encoded as 63-~. - P 5 bit bit position at 26 - q 6 bit bit position at 20,22:26 - T 5 bit field length at 31 (encoded as 32-T) - % 6 bit field length at 23,27:31 (variable extract/deposit) - | 6 bit field length at 19,27:31 (fixed extract/deposit) - A 13 bit immediate at 18 (to support the BREAK instruction) - ^ like b, but describes a control register - ! sar (cr11) register - D 26 bit immediate at 31 (to support the DIAG instruction) - $ 9 bit immediate at 28 (to support POPBTS) - - v 3 bit Special Function Unit identifier at 25 - O 20 bit Special Function Unit operation split between 15 bits at 20 - and 5 bits at 31 - o 15 bit Special Function Unit operation at 20 - 2 22 bit Special Function Unit operation split between 17 bits at 20 - and 5 bits at 31 - 1 15 bit Special Function Unit operation split between 10 bits at 20 - and 5 bits at 31 - 0 10 bit Special Function Unit operation split between 5 bits at 20 - and 5 bits at 31 - u 3 bit coprocessor unit identifier at 25 - F Source Floating Point Operand Format Completer encoded 2 bits at 20 - I Source Floating Point Operand Format Completer encoded 1 bits at 20 - (for 0xe format FP instructions) - G Destination Floating Point Operand Format Completer encoded 2 bits at 18 - H Floating Point Operand Format at 26 for 'fmpyadd' and 'fmpysub' - (very similar to 'F') - - r 5 bit immediate value at 31 (for the break instruction) - (very similar to V above, except the value is unsigned instead of - low_sign_ext) - R 5 bit immediate value at 15 (for the ssm, rsm, probei instructions) - (same as r above, except the value is in a different location) - U 10 bit immediate value at 15 (for SSM, RSM on pa2.0) - Q 5 bit immediate value at 10 (a bit position specified in - the bb instruction. It's the same as r above, except the - value is in a different location) - B 5 bit immediate value at 10 (a bit position specified in - the bb instruction. Similar to Q, but 64 bit handling is - different. - Z %r1 -- implicit target of addil instruction. - L ,%r2 completer for new syntax branch - { Source format completer for fcnv - _ Destination format completer for fcnv - h cbit for fcmp - = gfx tests for ftest - d 14 bit offset for single precision FP long load/store. - # 14 bit offset for double precision FP load long/store. - J Yet another 14 bit offset for load/store with ma,mb completers. - K Yet another 14 bit offset for load/store with ma,mb completers. - y 16 bit offset for word aligned load/store (PA2.0 wide). - & 16 bit offset for dword aligned load/store (PA2.0 wide). - < 16 bit offset for load/store with ma,mb completers (PA2.0 wide). - > 16 bit offset for load/store with ma,mb completers (PA2.0 wide). - Y %sr0,%r31 -- implicit target of be,l instruction. - @ implicit immediate value of 0 - -Completer operands all have 'c' as the prefix: - - cx indexed load and store completer. - cX indexed load and store completer. Like cx, but emits a space - after in disassembler. - cm short load and store completer. - cM short load and store completer. Like cm, but emits a space - after in disassembler. - cq long load and store completer (like cm, but inserted into a - different location in the target instruction). - cs store bytes short completer. - cA store bytes short completer. Like cs, but emits a space - after in disassembler. - ce long load/store completer for LDW/STW with a different encoding - than the others - cc load cache control hint - cd load and clear cache control hint - cC store cache control hint - co ordered access - - cp branch link and push completer - cP branch pop completer - cl branch link completer - cg branch gate completer - - cw read/write completer for PROBE - cW wide completer for MFCTL - cL local processor completer for cache control - cZ System Control Completer (to support LPA, LHA, etc.) - - ci correction completer for DCOR - ca add completer - cy 32 bit add carry completer - cY 64 bit add carry completer - cv signed overflow trap completer - ct trap on condition completer for ADDI, SUB - cT trap on condition completer for UADDCM - cb 32 bit borrow completer for SUB - cB 64 bit borrow completer for SUB - - ch left/right half completer - cH signed/unsigned saturation completer - cS signed/unsigned completer at 21 - cz zero/sign extension completer. - c* permutation completer - -Condition operands all have '?' as the prefix: - - ?f Floating point compare conditions (encoded as 5 bits at 31) - - ?a add conditions - ?A 64 bit add conditions - ?@ add branch conditions followed by nullify - ?d non-negated add branch conditions - ?D negated add branch conditions - ?w wide mode non-negated add branch conditions - ?W wide mode negated add branch conditions - - ?s compare/subtract conditions - ?S 64 bit compare/subtract conditions - ?t non-negated compare and branch conditions - ?n 32 bit compare and branch conditions followed by nullify - ?N 64 bit compare and branch conditions followed by nullify - ?Q 64 bit compare and branch conditions for CMPIB instruction - - ?l logical conditions - ?L 64 bit logical conditions - - ?b branch on bit conditions - ?B 64 bit branch on bit conditions - - ?x shift/extract/deposit conditions - ?X 64 bit shift/extract/deposit conditions - ?y shift/extract/deposit conditions followed by nullify for conditional - branches - - ?u unit conditions - ?U 64 bit unit conditions - -Floating point registers all have 'f' as a prefix: - - ft target register at 31 - fT target register with L/R halves at 31 - fa operand 1 register at 10 - fA operand 1 register with L/R halves at 10 - fX Same as fA, except prints a space before register during disasm - fb operand 2 register at 15 - fB operand 2 register with L/R halves at 15 - fC operand 3 register with L/R halves at 16:18,21:23 - fe Like fT, but encoding is different. - fE Same as fe, except prints a space before register during disasm. - fx target register at 15 (only for PA 2.0 long format FLDD/FSTD). - -Float registers for fmpyadd and fmpysub: - - fi mult operand 1 register at 10 - fj mult operand 2 register at 15 - fk mult target register at 20 - fl add/sub operand register at 25 - fm add/sub target register at 31 - -*/ - - -#if 0 -/* List of characters not to put a space after. Note that - "," is included, as the "spopN" operations use literal - commas in their completer sections. */ -static const char *const completer_chars = ",CcY<>?!@+&U~FfGHINnOoZMadu|/=0123%e$m}"; -#endif - -/* The order of the opcodes in this table is significant: - - * The assembler requires that all instances of the same mnemonic be - consecutive. If they aren't, the assembler will bomb at runtime. - - * Immediate fields use pa_get_absolute_expression to parse the - string. It will generate a "bad expression" error if passed - a register name. Thus, register index variants of an opcode - need to precede immediate variants. - - * The disassembler does not care about the order of the opcodes - except in cases where implicit addressing is used. - - Here are the rules for ordering the opcodes of a mnemonic: - - 1) Opcodes with FLAG_STRICT should precede opcodes without - FLAG_STRICT. - - 2) Opcodes with FLAG_STRICT should be ordered as follows: - register index opcodes, short immediate opcodes, and finally - long immediate opcodes. When both pa10 and pa11 variants - of the same opcode are available, the pa10 opcode should - come first for correct architectural promotion. - - 3) When implicit addressing is available for an opcode, the - implicit opcode should precede the explicit opcode. - - 4) Opcodes without FLAG_STRICT should be ordered as follows: - register index opcodes, long immediate opcodes, and finally - short immediate opcodes. */ - -static const struct pa_opcode pa_opcodes[] = -{ - -/* Pseudo-instructions. */ - -{ "ldi", 0x34000000, 0xffe00000, "l,x", pa20w, 0},/* ldo val(r0),r */ -{ "ldi", 0x34000000, 0xffe0c000, "j,x", pa10, 0},/* ldo val(r0),r */ - -{ "cmpib", 0xec000000, 0xfc000000, "?Qn5,b,w", pa20, FLAG_STRICT}, -{ "cmpib", 0x84000000, 0xf4000000, "?nn5,b,w", pa10, FLAG_STRICT}, -{ "comib", 0x84000000, 0xfc000000, "?nn5,b,w", pa10, 0}, /* comib{tf}*/ -/* This entry is for the disassembler only. It will never be used by - assembler. */ -{ "comib", 0x8c000000, 0xfc000000, "?nn5,b,w", pa10, 0}, /* comib{tf}*/ -{ "cmpb", 0x9c000000, 0xdc000000, "?Nnx,b,w", pa20, FLAG_STRICT}, -{ "cmpb", 0x80000000, 0xf4000000, "?nnx,b,w", pa10, FLAG_STRICT}, -{ "comb", 0x80000000, 0xfc000000, "?nnx,b,w", pa10, 0}, /* comb{tf} */ -/* This entry is for the disassembler only. It will never be used by - assembler. */ -{ "comb", 0x88000000, 0xfc000000, "?nnx,b,w", pa10, 0}, /* comb{tf} */ -{ "addb", 0xa0000000, 0xf4000000, "?Wnx,b,w", pa20w, FLAG_STRICT}, -{ "addb", 0xa0000000, 0xfc000000, "?@nx,b,w", pa10, 0}, /* addb{tf} */ -/* This entry is for the disassembler only. It will never be used by - assembler. */ -{ "addb", 0xa8000000, 0xfc000000, "?@nx,b,w", pa10, 0}, -{ "addib", 0xa4000000, 0xf4000000, "?Wn5,b,w", pa20w, FLAG_STRICT}, -{ "addib", 0xa4000000, 0xfc000000, "?@n5,b,w", pa10, 0}, /* addib{tf}*/ -/* This entry is for the disassembler only. It will never be used by - assembler. */ -{ "addib", 0xac000000, 0xfc000000, "?@n5,b,w", pa10, 0}, /* addib{tf}*/ -{ "nop", 0x08000240, 0xffffffff, "", pa10, 0}, /* or 0,0,0 */ -{ "copy", 0x08000240, 0xffe0ffe0, "x,t", pa10, 0}, /* or r,0,t */ -{ "mtsar", 0x01601840, 0xffe0ffff, "x", pa10, 0}, /* mtctl r,cr11 */ - -/* Loads and Stores for integer registers. */ - -{ "ldd", 0x0c0000c0, 0xfc00d3c0, "cxccx(b),t", pa20, FLAG_STRICT}, -{ "ldd", 0x0c0000c0, 0xfc0013c0, "cxccx(s,b),t", pa20, FLAG_STRICT}, -{ "ldd", 0x0c0010e0, 0xfc1ff3e0, "cocc@(b),t", pa20, FLAG_STRICT}, -{ "ldd", 0x0c0010e0, 0xfc1f33e0, "cocc@(s,b),t", pa20, FLAG_STRICT}, -{ "ldd", 0x0c0010c0, 0xfc00d3c0, "cmcc5(b),t", pa20, FLAG_STRICT}, -{ "ldd", 0x0c0010c0, 0xfc0013c0, "cmcc5(s,b),t", pa20, FLAG_STRICT}, -{ "ldd", 0x50000000, 0xfc000002, "cq&(b),x", pa20w, FLAG_STRICT}, -{ "ldd", 0x50000000, 0xfc00c002, "cq#(b),x", pa20, FLAG_STRICT}, -{ "ldd", 0x50000000, 0xfc000002, "cq#(s,b),x", pa20, FLAG_STRICT}, -{ "ldw", 0x0c000080, 0xfc00dfc0, "cXx(b),t", pa10, FLAG_STRICT}, -{ "ldw", 0x0c000080, 0xfc001fc0, "cXx(s,b),t", pa10, FLAG_STRICT}, -{ "ldw", 0x0c000080, 0xfc00d3c0, "cxccx(b),t", pa11, FLAG_STRICT}, -{ "ldw", 0x0c000080, 0xfc0013c0, "cxccx(s,b),t", pa11, FLAG_STRICT}, -{ "ldw", 0x0c0010a0, 0xfc1ff3e0, "cocc@(b),t", pa20, FLAG_STRICT}, -{ "ldw", 0x0c0010a0, 0xfc1f33e0, "cocc@(s,b),t", pa20, FLAG_STRICT}, -{ "ldw", 0x0c001080, 0xfc00dfc0, "cM5(b),t", pa10, FLAG_STRICT}, -{ "ldw", 0x0c001080, 0xfc001fc0, "cM5(s,b),t", pa10, FLAG_STRICT}, -{ "ldw", 0x0c001080, 0xfc00d3c0, "cmcc5(b),t", pa11, FLAG_STRICT}, -{ "ldw", 0x0c001080, 0xfc0013c0, "cmcc5(s,b),t", pa11, FLAG_STRICT}, -{ "ldw", 0x4c000000, 0xfc000000, "ce<(b),x", pa20w, FLAG_STRICT}, -{ "ldw", 0x5c000004, 0xfc000006, "ce>(b),x", pa20w, FLAG_STRICT}, -{ "ldw", 0x48000000, 0xfc000000, "l(b),x", pa20w, FLAG_STRICT}, -{ "ldw", 0x5c000004, 0xfc00c006, "ceK(b),x", pa20, FLAG_STRICT}, -{ "ldw", 0x5c000004, 0xfc000006, "ceK(s,b),x", pa20, FLAG_STRICT}, -{ "ldw", 0x4c000000, 0xfc00c000, "ceJ(b),x", pa10, FLAG_STRICT}, -{ "ldw", 0x4c000000, 0xfc000000, "ceJ(s,b),x", pa10, FLAG_STRICT}, -{ "ldw", 0x48000000, 0xfc00c000, "j(b),x", pa10, 0}, -{ "ldw", 0x48000000, 0xfc000000, "j(s,b),x", pa10, 0}, -{ "ldh", 0x0c000040, 0xfc00dfc0, "cXx(b),t", pa10, FLAG_STRICT}, -{ "ldh", 0x0c000040, 0xfc001fc0, "cXx(s,b),t", pa10, FLAG_STRICT}, -{ "ldh", 0x0c000040, 0xfc00d3c0, "cxccx(b),t", pa11, FLAG_STRICT}, -{ "ldh", 0x0c000040, 0xfc0013c0, "cxccx(s,b),t", pa11, FLAG_STRICT}, -{ "ldh", 0x0c001060, 0xfc1ff3e0, "cocc@(b),t", pa20, FLAG_STRICT}, -{ "ldh", 0x0c001060, 0xfc1f33e0, "cocc@(s,b),t", pa20, FLAG_STRICT}, -{ "ldh", 0x0c001040, 0xfc00dfc0, "cM5(b),t", pa10, FLAG_STRICT}, -{ "ldh", 0x0c001040, 0xfc001fc0, "cM5(s,b),t", pa10, FLAG_STRICT}, -{ "ldh", 0x0c001040, 0xfc00d3c0, "cmcc5(b),t", pa11, FLAG_STRICT}, -{ "ldh", 0x0c001040, 0xfc0013c0, "cmcc5(s,b),t", pa11, FLAG_STRICT}, -{ "ldh", 0x44000000, 0xfc000000, "l(b),x", pa20w, FLAG_STRICT}, -{ "ldh", 0x44000000, 0xfc00c000, "j(b),x", pa10, 0}, -{ "ldh", 0x44000000, 0xfc000000, "j(s,b),x", pa10, 0}, -{ "ldb", 0x0c000000, 0xfc00dfc0, "cXx(b),t", pa10, FLAG_STRICT}, -{ "ldb", 0x0c000000, 0xfc001fc0, "cXx(s,b),t", pa10, FLAG_STRICT}, -{ "ldb", 0x0c000000, 0xfc00d3c0, "cxccx(b),t", pa11, FLAG_STRICT}, -{ "ldb", 0x0c000000, 0xfc0013c0, "cxccx(s,b),t", pa11, FLAG_STRICT}, -{ "ldb", 0x0c001020, 0xfc1ff3e0, "cocc@(b),t", pa20, FLAG_STRICT}, -{ "ldb", 0x0c001020, 0xfc1f33e0, "cocc@(s,b),t", pa20, FLAG_STRICT}, -{ "ldb", 0x0c001000, 0xfc00dfc0, "cM5(b),t", pa10, FLAG_STRICT}, -{ "ldb", 0x0c001000, 0xfc001fc0, "cM5(s,b),t", pa10, FLAG_STRICT}, -{ "ldb", 0x0c001000, 0xfc00d3c0, "cmcc5(b),t", pa11, FLAG_STRICT}, -{ "ldb", 0x0c001000, 0xfc0013c0, "cmcc5(s,b),t", pa11, FLAG_STRICT}, -{ "ldb", 0x40000000, 0xfc000000, "l(b),x", pa20w, FLAG_STRICT}, -{ "ldb", 0x40000000, 0xfc00c000, "j(b),x", pa10, 0}, -{ "ldb", 0x40000000, 0xfc000000, "j(s,b),x", pa10, 0}, -{ "std", 0x0c0012e0, 0xfc00f3ff, "cocCx,@(b)", pa20, FLAG_STRICT}, -{ "std", 0x0c0012e0, 0xfc0033ff, "cocCx,@(s,b)", pa20, FLAG_STRICT}, -{ "std", 0x0c0012c0, 0xfc00d3c0, "cmcCx,V(b)", pa20, FLAG_STRICT}, -{ "std", 0x0c0012c0, 0xfc0013c0, "cmcCx,V(s,b)", pa20, FLAG_STRICT}, -{ "std", 0x70000000, 0xfc000002, "cqx,&(b)", pa20w, FLAG_STRICT}, -{ "std", 0x70000000, 0xfc00c002, "cqx,#(b)", pa20, FLAG_STRICT}, -{ "std", 0x70000000, 0xfc000002, "cqx,#(s,b)", pa20, FLAG_STRICT}, -{ "stw", 0x0c0012a0, 0xfc00f3ff, "cocCx,@(b)", pa20, FLAG_STRICT}, -{ "stw", 0x0c0012a0, 0xfc0033ff, "cocCx,@(s,b)", pa20, FLAG_STRICT}, -{ "stw", 0x0c001280, 0xfc00dfc0, "cMx,V(b)", pa10, FLAG_STRICT}, -{ "stw", 0x0c001280, 0xfc001fc0, "cMx,V(s,b)", pa10, FLAG_STRICT}, -{ "stw", 0x0c001280, 0xfc00d3c0, "cmcCx,V(b)", pa11, FLAG_STRICT}, -{ "stw", 0x0c001280, 0xfc0013c0, "cmcCx,V(s,b)", pa11, FLAG_STRICT}, -{ "stw", 0x6c000000, 0xfc000000, "cex,<(b)", pa20w, FLAG_STRICT}, -{ "stw", 0x7c000004, 0xfc000006, "cex,>(b)", pa20w, FLAG_STRICT}, -{ "stw", 0x68000000, 0xfc000000, "x,l(b)", pa20w, FLAG_STRICT}, -{ "stw", 0x7c000004, 0xfc00c006, "cex,K(b)", pa20, FLAG_STRICT}, -{ "stw", 0x7c000004, 0xfc000006, "cex,K(s,b)", pa20, FLAG_STRICT}, -{ "stw", 0x6c000000, 0xfc00c000, "cex,J(b)", pa10, FLAG_STRICT}, -{ "stw", 0x6c000000, 0xfc000000, "cex,J(s,b)", pa10, FLAG_STRICT}, -{ "stw", 0x68000000, 0xfc00c000, "x,j(b)", pa10, 0}, -{ "stw", 0x68000000, 0xfc000000, "x,j(s,b)", pa10, 0}, -{ "sth", 0x0c001260, 0xfc00f3ff, "cocCx,@(b)", pa20, FLAG_STRICT}, -{ "sth", 0x0c001260, 0xfc0033ff, "cocCx,@(s,b)", pa20, FLAG_STRICT}, -{ "sth", 0x0c001240, 0xfc00dfc0, "cMx,V(b)", pa10, FLAG_STRICT}, -{ "sth", 0x0c001240, 0xfc001fc0, "cMx,V(s,b)", pa10, FLAG_STRICT}, -{ "sth", 0x0c001240, 0xfc00d3c0, "cmcCx,V(b)", pa11, FLAG_STRICT}, -{ "sth", 0x0c001240, 0xfc0013c0, "cmcCx,V(s,b)", pa11, FLAG_STRICT}, -{ "sth", 0x64000000, 0xfc000000, "x,l(b)", pa20w, FLAG_STRICT}, -{ "sth", 0x64000000, 0xfc00c000, "x,j(b)", pa10, 0}, -{ "sth", 0x64000000, 0xfc000000, "x,j(s,b)", pa10, 0}, -{ "stb", 0x0c001220, 0xfc00f3ff, "cocCx,@(b)", pa20, FLAG_STRICT}, -{ "stb", 0x0c001220, 0xfc0033ff, "cocCx,@(s,b)", pa20, FLAG_STRICT}, -{ "stb", 0x0c001200, 0xfc00dfc0, "cMx,V(b)", pa10, FLAG_STRICT}, -{ "stb", 0x0c001200, 0xfc001fc0, "cMx,V(s,b)", pa10, FLAG_STRICT}, -{ "stb", 0x0c001200, 0xfc00d3c0, "cmcCx,V(b)", pa11, FLAG_STRICT}, -{ "stb", 0x0c001200, 0xfc0013c0, "cmcCx,V(s,b)", pa11, FLAG_STRICT}, -{ "stb", 0x60000000, 0xfc000000, "x,l(b)", pa20w, FLAG_STRICT}, -{ "stb", 0x60000000, 0xfc00c000, "x,j(b)", pa10, 0}, -{ "stb", 0x60000000, 0xfc000000, "x,j(s,b)", pa10, 0}, -{ "ldwm", 0x4c000000, 0xfc00c000, "j(b),x", pa10, 0}, -{ "ldwm", 0x4c000000, 0xfc000000, "j(s,b),x", pa10, 0}, -{ "stwm", 0x6c000000, 0xfc00c000, "x,j(b)", pa10, 0}, -{ "stwm", 0x6c000000, 0xfc000000, "x,j(s,b)", pa10, 0}, -{ "ldwx", 0x0c000080, 0xfc00dfc0, "cXx(b),t", pa10, FLAG_STRICT}, -{ "ldwx", 0x0c000080, 0xfc001fc0, "cXx(s,b),t", pa10, FLAG_STRICT}, -{ "ldwx", 0x0c000080, 0xfc00d3c0, "cxccx(b),t", pa11, FLAG_STRICT}, -{ "ldwx", 0x0c000080, 0xfc0013c0, "cxccx(s,b),t", pa11, FLAG_STRICT}, -{ "ldwx", 0x0c000080, 0xfc00dfc0, "cXx(b),t", pa10, 0}, -{ "ldwx", 0x0c000080, 0xfc001fc0, "cXx(s,b),t", pa10, 0}, -{ "ldhx", 0x0c000040, 0xfc00dfc0, "cXx(b),t", pa10, FLAG_STRICT}, -{ "ldhx", 0x0c000040, 0xfc001fc0, "cXx(s,b),t", pa10, FLAG_STRICT}, -{ "ldhx", 0x0c000040, 0xfc00d3c0, "cxccx(b),t", pa11, FLAG_STRICT}, -{ "ldhx", 0x0c000040, 0xfc0013c0, "cxccx(s,b),t", pa11, FLAG_STRICT}, -{ "ldhx", 0x0c000040, 0xfc00dfc0, "cXx(b),t", pa10, 0}, -{ "ldhx", 0x0c000040, 0xfc001fc0, "cXx(s,b),t", pa10, 0}, -{ "ldbx", 0x0c000000, 0xfc00dfc0, "cXx(b),t", pa10, FLAG_STRICT}, -{ "ldbx", 0x0c000000, 0xfc001fc0, "cXx(s,b),t", pa10, FLAG_STRICT}, -{ "ldbx", 0x0c000000, 0xfc00d3c0, "cxccx(b),t", pa11, FLAG_STRICT}, -{ "ldbx", 0x0c000000, 0xfc0013c0, "cxccx(s,b),t", pa11, FLAG_STRICT}, -{ "ldbx", 0x0c000000, 0xfc00dfc0, "cXx(b),t", pa10, 0}, -{ "ldbx", 0x0c000000, 0xfc001fc0, "cXx(s,b),t", pa10, 0}, -{ "ldwa", 0x0c000180, 0xfc00dfc0, "cXx(b),t", pa10, FLAG_STRICT}, -{ "ldwa", 0x0c000180, 0xfc00d3c0, "cxccx(b),t", pa11, FLAG_STRICT}, -{ "ldwa", 0x0c0011a0, 0xfc1ff3e0, "cocc@(b),t", pa20, FLAG_STRICT}, -{ "ldwa", 0x0c001180, 0xfc00dfc0, "cM5(b),t", pa10, FLAG_STRICT}, -{ "ldwa", 0x0c001180, 0xfc00d3c0, "cmcc5(b),t", pa11, FLAG_STRICT}, -{ "ldcw", 0x0c0001c0, 0xfc00dfc0, "cXx(b),t", pa10, FLAG_STRICT}, -{ "ldcw", 0x0c0001c0, 0xfc001fc0, "cXx(s,b),t", pa10, FLAG_STRICT}, -{ "ldcw", 0x0c0001c0, 0xfc00d3c0, "cxcdx(b),t", pa11, FLAG_STRICT}, -{ "ldcw", 0x0c0001c0, 0xfc0013c0, "cxcdx(s,b),t", pa11, FLAG_STRICT}, -{ "ldcw", 0x0c0011c0, 0xfc00dfc0, "cM5(b),t", pa10, FLAG_STRICT}, -{ "ldcw", 0x0c0011c0, 0xfc001fc0, "cM5(s,b),t", pa10, FLAG_STRICT}, -{ "ldcw", 0x0c0011c0, 0xfc00d3c0, "cmcd5(b),t", pa11, FLAG_STRICT}, -{ "ldcw", 0x0c0011c0, 0xfc0013c0, "cmcd5(s,b),t", pa11, FLAG_STRICT}, -{ "stwa", 0x0c0013a0, 0xfc00d3ff, "cocCx,@(b)", pa20, FLAG_STRICT}, -{ "stwa", 0x0c001380, 0xfc00dfc0, "cMx,V(b)", pa10, FLAG_STRICT}, -{ "stwa", 0x0c001380, 0xfc00d3c0, "cmcCx,V(b)", pa11, FLAG_STRICT}, -{ "stby", 0x0c001300, 0xfc00dfc0, "cAx,V(b)", pa10, FLAG_STRICT}, -{ "stby", 0x0c001300, 0xfc001fc0, "cAx,V(s,b)", pa10, FLAG_STRICT}, -{ "stby", 0x0c001300, 0xfc00d3c0, "cscCx,V(b)", pa11, FLAG_STRICT}, -{ "stby", 0x0c001300, 0xfc0013c0, "cscCx,V(s,b)", pa11, FLAG_STRICT}, -{ "ldda", 0x0c000100, 0xfc00d3c0, "cxccx(b),t", pa20, FLAG_STRICT}, -{ "ldda", 0x0c001120, 0xfc1ff3e0, "cocc@(b),t", pa20, FLAG_STRICT}, -{ "ldda", 0x0c001100, 0xfc00d3c0, "cmcc5(b),t", pa20, FLAG_STRICT}, -{ "ldcd", 0x0c000140, 0xfc00d3c0, "cxcdx(b),t", pa20, FLAG_STRICT}, -{ "ldcd", 0x0c000140, 0xfc0013c0, "cxcdx(s,b),t", pa20, FLAG_STRICT}, -{ "ldcd", 0x0c001140, 0xfc00d3c0, "cmcd5(b),t", pa20, FLAG_STRICT}, -{ "ldcd", 0x0c001140, 0xfc0013c0, "cmcd5(s,b),t", pa20, FLAG_STRICT}, -{ "stda", 0x0c0013e0, 0xfc00f3ff, "cocCx,@(b)", pa20, FLAG_STRICT}, -{ "stda", 0x0c0013c0, 0xfc00d3c0, "cmcCx,V(b)", pa20, FLAG_STRICT}, -{ "ldwax", 0x0c000180, 0xfc00dfc0, "cXx(b),t", pa10, FLAG_STRICT}, -{ "ldwax", 0x0c000180, 0xfc00d3c0, "cxccx(b),t", pa11, FLAG_STRICT}, -{ "ldwax", 0x0c000180, 0xfc00dfc0, "cXx(b),t", pa10, 0}, -{ "ldcwx", 0x0c0001c0, 0xfc00dfc0, "cXx(b),t", pa10, FLAG_STRICT}, -{ "ldcwx", 0x0c0001c0, 0xfc001fc0, "cXx(s,b),t", pa10, FLAG_STRICT}, -{ "ldcwx", 0x0c0001c0, 0xfc00d3c0, "cxcdx(b),t", pa11, FLAG_STRICT}, -{ "ldcwx", 0x0c0001c0, 0xfc0013c0, "cxcdx(s,b),t", pa11, FLAG_STRICT}, -{ "ldcwx", 0x0c0001c0, 0xfc00dfc0, "cXx(b),t", pa10, 0}, -{ "ldcwx", 0x0c0001c0, 0xfc001fc0, "cXx(s,b),t", pa10, 0}, -{ "ldws", 0x0c001080, 0xfc00dfc0, "cM5(b),t", pa10, FLAG_STRICT}, -{ "ldws", 0x0c001080, 0xfc001fc0, "cM5(s,b),t", pa10, FLAG_STRICT}, -{ "ldws", 0x0c001080, 0xfc00d3c0, "cmcc5(b),t", pa11, FLAG_STRICT}, -{ "ldws", 0x0c001080, 0xfc0013c0, "cmcc5(s,b),t", pa11, FLAG_STRICT}, -{ "ldws", 0x0c001080, 0xfc00dfc0, "cM5(b),t", pa10, 0}, -{ "ldws", 0x0c001080, 0xfc001fc0, "cM5(s,b),t", pa10, 0}, -{ "ldhs", 0x0c001040, 0xfc00dfc0, "cM5(b),t", pa10, FLAG_STRICT}, -{ "ldhs", 0x0c001040, 0xfc001fc0, "cM5(s,b),t", pa10, FLAG_STRICT}, -{ "ldhs", 0x0c001040, 0xfc00d3c0, "cmcc5(b),t", pa11, FLAG_STRICT}, -{ "ldhs", 0x0c001040, 0xfc0013c0, "cmcc5(s,b),t", pa11, FLAG_STRICT}, -{ "ldhs", 0x0c001040, 0xfc00dfc0, "cM5(b),t", pa10, 0}, -{ "ldhs", 0x0c001040, 0xfc001fc0, "cM5(s,b),t", pa10, 0}, -{ "ldbs", 0x0c001000, 0xfc00dfc0, "cM5(b),t", pa10, FLAG_STRICT}, -{ "ldbs", 0x0c001000, 0xfc001fc0, "cM5(s,b),t", pa10, FLAG_STRICT}, -{ "ldbs", 0x0c001000, 0xfc00d3c0, "cmcc5(b),t", pa11, FLAG_STRICT}, -{ "ldbs", 0x0c001000, 0xfc0013c0, "cmcc5(s,b),t", pa11, FLAG_STRICT}, -{ "ldbs", 0x0c001000, 0xfc00dfc0, "cM5(b),t", pa10, 0}, -{ "ldbs", 0x0c001000, 0xfc001fc0, "cM5(s,b),t", pa10, 0}, -{ "ldwas", 0x0c001180, 0xfc00dfc0, "cM5(b),t", pa10, FLAG_STRICT}, -{ "ldwas", 0x0c001180, 0xfc00d3c0, "cmcc5(b),t", pa11, FLAG_STRICT}, -{ "ldwas", 0x0c001180, 0xfc00dfc0, "cM5(b),t", pa10, 0}, -{ "ldcws", 0x0c0011c0, 0xfc00dfc0, "cM5(b),t", pa10, FLAG_STRICT}, -{ "ldcws", 0x0c0011c0, 0xfc001fc0, "cM5(s,b),t", pa10, FLAG_STRICT}, -{ "ldcws", 0x0c0011c0, 0xfc00d3c0, "cmcd5(b),t", pa11, FLAG_STRICT}, -{ "ldcws", 0x0c0011c0, 0xfc0013c0, "cmcd5(s,b),t", pa11, FLAG_STRICT}, -{ "ldcws", 0x0c0011c0, 0xfc00dfc0, "cM5(b),t", pa10, 0}, -{ "ldcws", 0x0c0011c0, 0xfc001fc0, "cM5(s,b),t", pa10, 0}, -{ "stws", 0x0c001280, 0xfc00dfc0, "cMx,V(b)", pa10, FLAG_STRICT}, -{ "stws", 0x0c001280, 0xfc001fc0, "cMx,V(s,b)", pa10, FLAG_STRICT}, -{ "stws", 0x0c001280, 0xfc00d3c0, "cmcCx,V(b)", pa11, FLAG_STRICT}, -{ "stws", 0x0c001280, 0xfc0013c0, "cmcCx,V(s,b)", pa11, FLAG_STRICT}, -{ "stws", 0x0c001280, 0xfc00dfc0, "cMx,V(b)", pa10, 0}, -{ "stws", 0x0c001280, 0xfc001fc0, "cMx,V(s,b)", pa10, 0}, -{ "sths", 0x0c001240, 0xfc00dfc0, "cMx,V(b)", pa10, FLAG_STRICT}, -{ "sths", 0x0c001240, 0xfc001fc0, "cMx,V(s,b)", pa10, FLAG_STRICT}, -{ "sths", 0x0c001240, 0xfc00d3c0, "cmcCx,V(b)", pa11, FLAG_STRICT}, -{ "sths", 0x0c001240, 0xfc0013c0, "cmcCx,V(s,b)", pa11, FLAG_STRICT}, -{ "sths", 0x0c001240, 0xfc00dfc0, "cMx,V(b)", pa10, 0}, -{ "sths", 0x0c001240, 0xfc001fc0, "cMx,V(s,b)", pa10, 0}, -{ "stbs", 0x0c001200, 0xfc00dfc0, "cMx,V(b)", pa10, FLAG_STRICT}, -{ "stbs", 0x0c001200, 0xfc001fc0, "cMx,V(s,b)", pa10, FLAG_STRICT}, -{ "stbs", 0x0c001200, 0xfc00d3c0, "cmcCx,V(b)", pa11, FLAG_STRICT}, -{ "stbs", 0x0c001200, 0xfc0013c0, "cmcCx,V(s,b)", pa11, FLAG_STRICT}, -{ "stbs", 0x0c001200, 0xfc00dfc0, "cMx,V(b)", pa10, 0}, -{ "stbs", 0x0c001200, 0xfc001fc0, "cMx,V(s,b)", pa10, 0}, -{ "stwas", 0x0c001380, 0xfc00dfc0, "cMx,V(b)", pa10, FLAG_STRICT}, -{ "stwas", 0x0c001380, 0xfc00d3c0, "cmcCx,V(b)", pa11, FLAG_STRICT}, -{ "stwas", 0x0c001380, 0xfc00dfc0, "cMx,V(b)", pa10, 0}, -{ "stdby", 0x0c001340, 0xfc00d3c0, "cscCx,V(b)", pa20, FLAG_STRICT}, -{ "stdby", 0x0c001340, 0xfc0013c0, "cscCx,V(s,b)", pa20, FLAG_STRICT}, -{ "stbys", 0x0c001300, 0xfc00dfc0, "cAx,V(b)", pa10, FLAG_STRICT}, -{ "stbys", 0x0c001300, 0xfc001fc0, "cAx,V(s,b)", pa10, FLAG_STRICT}, -{ "stbys", 0x0c001300, 0xfc00d3c0, "cscCx,V(b)", pa11, FLAG_STRICT}, -{ "stbys", 0x0c001300, 0xfc0013c0, "cscCx,V(s,b)", pa11, FLAG_STRICT}, -{ "stbys", 0x0c001300, 0xfc00dfc0, "cAx,V(b)", pa10, 0}, -{ "stbys", 0x0c001300, 0xfc001fc0, "cAx,V(s,b)", pa10, 0}, - -/* Immediate instructions. */ -{ "ldo", 0x34000000, 0xfc000000, "l(b),x", pa20w, 0}, -{ "ldo", 0x34000000, 0xfc00c000, "j(b),x", pa10, 0}, -{ "ldil", 0x20000000, 0xfc000000, "k,b", pa10, 0}, -{ "addil", 0x28000000, 0xfc000000, "k,b,Z", pa10, 0}, -{ "addil", 0x28000000, 0xfc000000, "k,b", pa10, 0}, - -/* Branching instructions. */ -{ "b", 0xe8008000, 0xfc00e000, "cpnXL", pa20, FLAG_STRICT}, -{ "b", 0xe800a000, 0xfc00e000, "clnXL", pa20, FLAG_STRICT}, -{ "b", 0xe8000000, 0xfc00e000, "clnW,b", pa10, FLAG_STRICT}, -{ "b", 0xe8002000, 0xfc00e000, "cgnW,b", pa10, FLAG_STRICT}, -{ "b", 0xe8000000, 0xffe0e000, "nW", pa10, 0}, /* b,l foo,r0 */ -{ "bl", 0xe8000000, 0xfc00e000, "nW,b", pa10, 0}, -{ "gate", 0xe8002000, 0xfc00e000, "nW,b", pa10, 0}, -{ "blr", 0xe8004000, 0xfc00e001, "nx,b", pa10, 0}, -{ "bv", 0xe800c000, 0xfc00fffd, "nx(b)", pa10, 0}, -{ "bv", 0xe800c000, 0xfc00fffd, "n(b)", pa10, 0}, -{ "bve", 0xe800f001, 0xfc1ffffd, "cpn(b)L", pa20, FLAG_STRICT}, -{ "bve", 0xe800f000, 0xfc1ffffd, "cln(b)L", pa20, FLAG_STRICT}, -{ "bve", 0xe800d001, 0xfc1ffffd, "cPn(b)", pa20, FLAG_STRICT}, -{ "bve", 0xe800d000, 0xfc1ffffd, "n(b)", pa20, FLAG_STRICT}, -{ "be", 0xe4000000, 0xfc000000, "clnz(S,b),Y", pa10, FLAG_STRICT}, -{ "be", 0xe4000000, 0xfc000000, "clnz(b),Y", pa10, FLAG_STRICT}, -{ "be", 0xe0000000, 0xfc000000, "nz(S,b)", pa10, 0}, -{ "be", 0xe0000000, 0xfc000000, "nz(b)", pa10, 0}, -{ "ble", 0xe4000000, 0xfc000000, "nz(S,b)", pa10, 0}, -{ "movb", 0xc8000000, 0xfc000000, "?ynx,b,w", pa10, 0}, -{ "movib", 0xcc000000, 0xfc000000, "?yn5,b,w", pa10, 0}, -{ "combt", 0x80000000, 0xfc000000, "?tnx,b,w", pa10, 0}, -{ "combf", 0x88000000, 0xfc000000, "?tnx,b,w", pa10, 0}, -{ "comibt", 0x84000000, 0xfc000000, "?tn5,b,w", pa10, 0}, -{ "comibf", 0x8c000000, 0xfc000000, "?tn5,b,w", pa10, 0}, -{ "addbt", 0xa0000000, 0xfc000000, "?dnx,b,w", pa10, 0}, -{ "addbf", 0xa8000000, 0xfc000000, "?dnx,b,w", pa10, 0}, -{ "addibt", 0xa4000000, 0xfc000000, "?dn5,b,w", pa10, 0}, -{ "addibf", 0xac000000, 0xfc000000, "?dn5,b,w", pa10, 0}, -{ "bb", 0xc0006000, 0xffe06000, "?Bnx,!,w", pa20, FLAG_STRICT}, -{ "bb", 0xc0004000, 0xffe06000, "?bnx,!,w", pa10, FLAG_STRICT}, -{ "bb", 0xc4004000, 0xfc004000, "?Bnx,B,w", pa20, FLAG_STRICT}, -{ "bb", 0xc4004000, 0xfc006000, "?bnx,Q,w", pa10, FLAG_STRICT}, -{ "bb", 0xc4004000, 0xfc006000, "?bnx,Q,w", pa10, 0}, -{ "bvb", 0xc0004000, 0xffe04000, "?bnx,w", pa10, 0}, -{ "clrbts", 0xe8004005, 0xffffffff, "", pa20, FLAG_STRICT}, -{ "popbts", 0xe8004005, 0xfffff007, "$", pa20, FLAG_STRICT}, -{ "pushnom", 0xe8004001, 0xffffffff, "", pa20, FLAG_STRICT}, -{ "pushbts", 0xe8004001, 0xffe0ffff, "x", pa20, FLAG_STRICT}, - -/* Computation Instructions. */ - -{ "cmpclr", 0x080008a0, 0xfc000fe0, "?Sx,b,t", pa20, FLAG_STRICT}, -{ "cmpclr", 0x08000880, 0xfc000fe0, "?sx,b,t", pa10, FLAG_STRICT}, -{ "comclr", 0x08000880, 0xfc000fe0, "?sx,b,t", pa10, 0}, -{ "or", 0x08000260, 0xfc000fe0, "?Lx,b,t", pa20, FLAG_STRICT}, -{ "or", 0x08000240, 0xfc000fe0, "?lx,b,t", pa10, 0}, -{ "xor", 0x080002a0, 0xfc000fe0, "?Lx,b,t", pa20, FLAG_STRICT}, -{ "xor", 0x08000280, 0xfc000fe0, "?lx,b,t", pa10, 0}, -{ "and", 0x08000220, 0xfc000fe0, "?Lx,b,t", pa20, FLAG_STRICT}, -{ "and", 0x08000200, 0xfc000fe0, "?lx,b,t", pa10, 0}, -{ "andcm", 0x08000020, 0xfc000fe0, "?Lx,b,t", pa20, FLAG_STRICT}, -{ "andcm", 0x08000000, 0xfc000fe0, "?lx,b,t", pa10, 0}, -{ "uxor", 0x080003a0, 0xfc000fe0, "?Ux,b,t", pa20, FLAG_STRICT}, -{ "uxor", 0x08000380, 0xfc000fe0, "?ux,b,t", pa10, 0}, -{ "uaddcm", 0x080009a0, 0xfc000fa0, "cT?Ux,b,t", pa20, FLAG_STRICT}, -{ "uaddcm", 0x08000980, 0xfc000fa0, "cT?ux,b,t", pa10, FLAG_STRICT}, -{ "uaddcm", 0x08000980, 0xfc000fe0, "?ux,b,t", pa10, 0}, -{ "uaddcmt", 0x080009c0, 0xfc000fe0, "?ux,b,t", pa10, 0}, -{ "dcor", 0x08000ba0, 0xfc1f0fa0, "ci?Ub,t", pa20, FLAG_STRICT}, -{ "dcor", 0x08000b80, 0xfc1f0fa0, "ci?ub,t", pa10, FLAG_STRICT}, -{ "dcor", 0x08000b80, 0xfc1f0fe0, "?ub,t", pa10, 0}, -{ "idcor", 0x08000bc0, 0xfc1f0fe0, "?ub,t", pa10, 0}, -{ "addi", 0xb0000000, 0xfc000000, "ct?ai,b,x", pa10, FLAG_STRICT}, -{ "addi", 0xb4000000, 0xfc000000, "cv?ai,b,x", pa10, FLAG_STRICT}, -{ "addi", 0xb4000000, 0xfc000800, "?ai,b,x", pa10, 0}, -{ "addio", 0xb4000800, 0xfc000800, "?ai,b,x", pa10, 0}, -{ "addit", 0xb0000000, 0xfc000800, "?ai,b,x", pa10, 0}, -{ "addito", 0xb0000800, 0xfc000800, "?ai,b,x", pa10, 0}, -{ "add", 0x08000720, 0xfc0007e0, "cY?Ax,b,t", pa20, FLAG_STRICT}, -{ "add", 0x08000700, 0xfc0007e0, "cy?ax,b,t", pa10, FLAG_STRICT}, -{ "add", 0x08000220, 0xfc0003e0, "ca?Ax,b,t", pa20, FLAG_STRICT}, -{ "add", 0x08000200, 0xfc0003e0, "ca?ax,b,t", pa10, FLAG_STRICT}, -{ "add", 0x08000600, 0xfc000fe0, "?ax,b,t", pa10, 0}, -{ "addl", 0x08000a00, 0xfc000fe0, "?ax,b,t", pa10, 0}, -{ "addo", 0x08000e00, 0xfc000fe0, "?ax,b,t", pa10, 0}, -{ "addc", 0x08000700, 0xfc000fe0, "?ax,b,t", pa10, 0}, -{ "addco", 0x08000f00, 0xfc000fe0, "?ax,b,t", pa10, 0}, -{ "sub", 0x080004e0, 0xfc0007e0, "ct?Sx,b,t", pa20, FLAG_STRICT}, -{ "sub", 0x080004c0, 0xfc0007e0, "ct?sx,b,t", pa10, FLAG_STRICT}, -{ "sub", 0x08000520, 0xfc0007e0, "cB?Sx,b,t", pa20, FLAG_STRICT}, -{ "sub", 0x08000500, 0xfc0007e0, "cb?sx,b,t", pa10, FLAG_STRICT}, -{ "sub", 0x08000420, 0xfc0007e0, "cv?Sx,b,t", pa20, FLAG_STRICT}, -{ "sub", 0x08000400, 0xfc0007e0, "cv?sx,b,t", pa10, FLAG_STRICT}, -{ "sub", 0x08000400, 0xfc000fe0, "?sx,b,t", pa10, 0}, -{ "subo", 0x08000c00, 0xfc000fe0, "?sx,b,t", pa10, 0}, -{ "subb", 0x08000500, 0xfc000fe0, "?sx,b,t", pa10, 0}, -{ "subbo", 0x08000d00, 0xfc000fe0, "?sx,b,t", pa10, 0}, -{ "subt", 0x080004c0, 0xfc000fe0, "?sx,b,t", pa10, 0}, -{ "subto", 0x08000cc0, 0xfc000fe0, "?sx,b,t", pa10, 0}, -{ "ds", 0x08000440, 0xfc000fe0, "?sx,b,t", pa10, 0}, -{ "subi", 0x94000000, 0xfc000000, "cv?si,b,x", pa10, FLAG_STRICT}, -{ "subi", 0x94000000, 0xfc000800, "?si,b,x", pa10, 0}, -{ "subio", 0x94000800, 0xfc000800, "?si,b,x", pa10, 0}, -{ "cmpiclr", 0x90000800, 0xfc000800, "?Si,b,x", pa20, FLAG_STRICT}, -{ "cmpiclr", 0x90000000, 0xfc000800, "?si,b,x", pa10, FLAG_STRICT}, -{ "comiclr", 0x90000000, 0xfc000800, "?si,b,x", pa10, 0}, -{ "shladd", 0x08000220, 0xfc000320, "ca?Ax,.,b,t", pa20, FLAG_STRICT}, -{ "shladd", 0x08000200, 0xfc000320, "ca?ax,.,b,t", pa10, FLAG_STRICT}, -{ "sh1add", 0x08000640, 0xfc000fe0, "?ax,b,t", pa10, 0}, -{ "sh1addl", 0x08000a40, 0xfc000fe0, "?ax,b,t", pa10, 0}, -{ "sh1addo", 0x08000e40, 0xfc000fe0, "?ax,b,t", pa10, 0}, -{ "sh2add", 0x08000680, 0xfc000fe0, "?ax,b,t", pa10, 0}, -{ "sh2addl", 0x08000a80, 0xfc000fe0, "?ax,b,t", pa10, 0}, -{ "sh2addo", 0x08000e80, 0xfc000fe0, "?ax,b,t", pa10, 0}, -{ "sh3add", 0x080006c0, 0xfc000fe0, "?ax,b,t", pa10, 0}, -{ "sh3addl", 0x08000ac0, 0xfc000fe0, "?ax,b,t", pa10, 0}, -{ "sh3addo", 0x08000ec0, 0xfc000fe0, "?ax,b,t", pa10, 0}, - -/* Subword Operation Instructions. */ - -{ "hadd", 0x08000300, 0xfc00ff20, "cHx,b,t", pa20, FLAG_STRICT}, -{ "havg", 0x080002c0, 0xfc00ffe0, "x,b,t", pa20, FLAG_STRICT}, -{ "hshl", 0xf8008800, 0xffe0fc20, "x,*,t", pa20, FLAG_STRICT}, -{ "hshladd", 0x08000700, 0xfc00ff20, "x,.,b,t", pa20, FLAG_STRICT}, -{ "hshr", 0xf800c800, 0xfc1ff820, "cSb,*,t", pa20, FLAG_STRICT}, -{ "hshradd", 0x08000500, 0xfc00ff20, "x,.,b,t", pa20, FLAG_STRICT}, -{ "hsub", 0x08000100, 0xfc00ff20, "cHx,b,t", pa20, FLAG_STRICT}, -{ "mixh", 0xf8008400, 0xfc009fe0, "chx,b,t", pa20, FLAG_STRICT}, -{ "mixw", 0xf8008000, 0xfc009fe0, "chx,b,t", pa20, FLAG_STRICT}, -{ "permh", 0xf8000000, 0xfc009020, "c*a,t", pa20, FLAG_STRICT}, - - -/* Extract and Deposit Instructions. */ - -{ "shrpd", 0xd0000200, 0xfc001fe0, "?Xx,b,!,t", pa20, FLAG_STRICT}, -{ "shrpd", 0xd0000400, 0xfc001400, "?Xx,b,~,t", pa20, FLAG_STRICT}, -{ "shrpw", 0xd0000000, 0xfc001fe0, "?xx,b,!,t", pa10, FLAG_STRICT}, -{ "shrpw", 0xd0000800, 0xfc001c00, "?xx,b,p,t", pa10, FLAG_STRICT}, -{ "vshd", 0xd0000000, 0xfc001fe0, "?xx,b,t", pa10, 0}, -{ "shd", 0xd0000800, 0xfc001c00, "?xx,b,p,t", pa10, 0}, -{ "extrd", 0xd0001200, 0xfc001ae0, "cS?Xb,!,%,x", pa20, FLAG_STRICT}, -{ "extrd", 0xd8000000, 0xfc000000, "cS?Xb,q,|,x", pa20, FLAG_STRICT}, -{ "extrw", 0xd0001000, 0xfc001be0, "cS?xb,!,T,x", pa10, FLAG_STRICT}, -{ "extrw", 0xd0001800, 0xfc001800, "cS?xb,P,T,x", pa10, FLAG_STRICT}, -{ "vextru", 0xd0001000, 0xfc001fe0, "?xb,T,x", pa10, 0}, -{ "vextrs", 0xd0001400, 0xfc001fe0, "?xb,T,x", pa10, 0}, -{ "extru", 0xd0001800, 0xfc001c00, "?xb,P,T,x", pa10, 0}, -{ "extrs", 0xd0001c00, 0xfc001c00, "?xb,P,T,x", pa10, 0}, -{ "depd", 0xd4000200, 0xfc001ae0, "cz?Xx,!,%,b", pa20, FLAG_STRICT}, -{ "depd", 0xf0000000, 0xfc000000, "cz?Xx,~,|,b", pa20, FLAG_STRICT}, -{ "depdi", 0xd4001200, 0xfc001ae0, "cz?X5,!,%,b", pa20, FLAG_STRICT}, -{ "depdi", 0xf4000000, 0xfc000000, "cz?X5,~,|,b", pa20, FLAG_STRICT}, -{ "depw", 0xd4000000, 0xfc001be0, "cz?xx,!,T,b", pa10, FLAG_STRICT}, -{ "depw", 0xd4000800, 0xfc001800, "cz?xx,p,T,b", pa10, FLAG_STRICT}, -{ "depwi", 0xd4001000, 0xfc001be0, "cz?x5,!,T,b", pa10, FLAG_STRICT}, -{ "depwi", 0xd4001800, 0xfc001800, "cz?x5,p,T,b", pa10, FLAG_STRICT}, -{ "zvdep", 0xd4000000, 0xfc001fe0, "?xx,T,b", pa10, 0}, -{ "vdep", 0xd4000400, 0xfc001fe0, "?xx,T,b", pa10, 0}, -{ "zdep", 0xd4000800, 0xfc001c00, "?xx,p,T,b", pa10, 0}, -{ "dep", 0xd4000c00, 0xfc001c00, "?xx,p,T,b", pa10, 0}, -{ "zvdepi", 0xd4001000, 0xfc001fe0, "?x5,T,b", pa10, 0}, -{ "vdepi", 0xd4001400, 0xfc001fe0, "?x5,T,b", pa10, 0}, -{ "zdepi", 0xd4001800, 0xfc001c00, "?x5,p,T,b", pa10, 0}, -{ "depi", 0xd4001c00, 0xfc001c00, "?x5,p,T,b", pa10, 0}, - -/* System Control Instructions. */ - -{ "break", 0x00000000, 0xfc001fe0, "r,A", pa10, 0}, -{ "rfi", 0x00000c00, 0xffffff1f, "cr", pa10, FLAG_STRICT}, -{ "rfi", 0x00000c00, 0xffffffff, "", pa10, 0}, -{ "rfir", 0x00000ca0, 0xffffffff, "", pa11, 0}, -{ "ssm", 0x00000d60, 0xfc00ffe0, "U,t", pa20, FLAG_STRICT}, -{ "ssm", 0x00000d60, 0xffe0ffe0, "R,t", pa10, 0}, -{ "rsm", 0x00000e60, 0xfc00ffe0, "U,t", pa20, FLAG_STRICT}, -{ "rsm", 0x00000e60, 0xffe0ffe0, "R,t", pa10, 0}, -{ "mtsm", 0x00001860, 0xffe0ffff, "x", pa10, 0}, -{ "ldsid", 0x000010a0, 0xfc1fffe0, "(b),t", pa10, 0}, -{ "ldsid", 0x000010a0, 0xfc1f3fe0, "(s,b),t", pa10, 0}, -{ "mtsp", 0x00001820, 0xffe01fff, "x,S", pa10, 0}, -{ "mtctl", 0x00001840, 0xfc00ffff, "x,^", pa10, 0}, -{ "mtsarcm", 0x016018C0, 0xffe0ffff, "x", pa20, FLAG_STRICT}, -{ "mfia", 0x000014A0, 0xffffffe0, "t", pa20, FLAG_STRICT}, -{ "mfsp", 0x000004a0, 0xffff1fe0, "S,t", pa10, 0}, -{ "mfctl", 0x016048a0, 0xffffffe0, "cW!,t", pa20, FLAG_STRICT}, -{ "mfctl", 0x000008a0, 0xfc1fffe0, "^,t", pa10, 0}, -{ "sync", 0x00000400, 0xffffffff, "", pa10, 0}, -{ "syncdma", 0x00100400, 0xffffffff, "", pa10, 0}, -{ "probe", 0x04001180, 0xfc00ffa0, "cw(b),x,t", pa10, FLAG_STRICT}, -{ "probe", 0x04001180, 0xfc003fa0, "cw(s,b),x,t", pa10, FLAG_STRICT}, -{ "probei", 0x04003180, 0xfc00ffa0, "cw(b),R,t", pa10, FLAG_STRICT}, -{ "probei", 0x04003180, 0xfc003fa0, "cw(s,b),R,t", pa10, FLAG_STRICT}, -{ "prober", 0x04001180, 0xfc00ffe0, "(b),x,t", pa10, 0}, -{ "prober", 0x04001180, 0xfc003fe0, "(s,b),x,t", pa10, 0}, -{ "proberi", 0x04003180, 0xfc00ffe0, "(b),R,t", pa10, 0}, -{ "proberi", 0x04003180, 0xfc003fe0, "(s,b),R,t", pa10, 0}, -{ "probew", 0x040011c0, 0xfc00ffe0, "(b),x,t", pa10, 0}, -{ "probew", 0x040011c0, 0xfc003fe0, "(s,b),x,t", pa10, 0}, -{ "probewi", 0x040031c0, 0xfc00ffe0, "(b),R,t", pa10, 0}, -{ "probewi", 0x040031c0, 0xfc003fe0, "(s,b),R,t", pa10, 0}, -{ "lpa", 0x04001340, 0xfc00ffc0, "cZx(b),t", pa10, 0}, -{ "lpa", 0x04001340, 0xfc003fc0, "cZx(s,b),t", pa10, 0}, -{ "lci", 0x04001300, 0xfc00ffe0, "x(b),t", pa11, 0}, -{ "lci", 0x04001300, 0xfc003fe0, "x(s,b),t", pa11, 0}, -{ "pdtlb", 0x04001600, 0xfc00ffdf, "cLcZx(b)", pa20, FLAG_STRICT}, -{ "pdtlb", 0x04001600, 0xfc003fdf, "cLcZx(s,b)", pa20, FLAG_STRICT}, -{ "pdtlb", 0x04001600, 0xfc1fffdf, "cLcZ@(b)", pa20, FLAG_STRICT}, -{ "pdtlb", 0x04001600, 0xfc1f3fdf, "cLcZ@(s,b)", pa20, FLAG_STRICT}, -{ "pdtlb", 0x04001200, 0xfc00ffdf, "cZx(b)", pa10, 0}, -{ "pdtlb", 0x04001200, 0xfc003fdf, "cZx(s,b)", pa10, 0}, -{ "pitlb", 0x04000600, 0xfc001fdf, "cLcZx(S,b)", pa20, FLAG_STRICT}, -{ "pitlb", 0x04000600, 0xfc1f1fdf, "cLcZ@(S,b)", pa20, FLAG_STRICT}, -{ "pitlb", 0x04000200, 0xfc001fdf, "cZx(S,b)", pa10, 0}, -{ "pdtlbe", 0x04001240, 0xfc00ffdf, "cZx(b)", pa10, 0}, -{ "pdtlbe", 0x04001240, 0xfc003fdf, "cZx(s,b)", pa10, 0}, -{ "pitlbe", 0x04000240, 0xfc001fdf, "cZx(S,b)", pa10, 0}, -{ "idtlba", 0x04001040, 0xfc00ffff, "x,(b)", pa10, 0}, -{ "idtlba", 0x04001040, 0xfc003fff, "x,(s,b)", pa10, 0}, -{ "iitlba", 0x04000040, 0xfc001fff, "x,(S,b)", pa10, 0}, -{ "idtlbp", 0x04001000, 0xfc00ffff, "x,(b)", pa10, 0}, -{ "idtlbp", 0x04001000, 0xfc003fff, "x,(s,b)", pa10, 0}, -{ "iitlbp", 0x04000000, 0xfc001fff, "x,(S,b)", pa10, 0}, -{ "pdc", 0x04001380, 0xfc00ffdf, "cZx(b)", pa10, 0}, -{ "pdc", 0x04001380, 0xfc003fdf, "cZx(s,b)", pa10, 0}, -{ "fdc", 0x04001280, 0xfc00ffdf, "cZx(b)", pa10, FLAG_STRICT}, -{ "fdc", 0x04001280, 0xfc003fdf, "cZx(s,b)", pa10, FLAG_STRICT}, -{ "fdc", 0x04003280, 0xfc00ffff, "5(b)", pa20, FLAG_STRICT}, -{ "fdc", 0x04003280, 0xfc003fff, "5(s,b)", pa20, FLAG_STRICT}, -{ "fdc", 0x04001280, 0xfc00ffdf, "cZx(b)", pa10, 0}, -{ "fdc", 0x04001280, 0xfc003fdf, "cZx(s,b)", pa10, 0}, -{ "fic", 0x040013c0, 0xfc00dfdf, "cZx(b)", pa20, FLAG_STRICT}, -{ "fic", 0x04000280, 0xfc001fdf, "cZx(S,b)", pa10, 0}, -{ "fdce", 0x040012c0, 0xfc00ffdf, "cZx(b)", pa10, 0}, -{ "fdce", 0x040012c0, 0xfc003fdf, "cZx(s,b)", pa10, 0}, -{ "fice", 0x040002c0, 0xfc001fdf, "cZx(S,b)", pa10, 0}, -{ "diag", 0x14000000, 0xfc000000, "D", pa10, 0}, -{ "idtlbt", 0x04001800, 0xfc00ffff, "x,b", pa20, FLAG_STRICT}, -{ "iitlbt", 0x04000800, 0xfc00ffff, "x,b", pa20, FLAG_STRICT}, - -/* These may be specific to certain versions of the PA. Joel claimed - they were 72000 (7200?) specific. However, I'm almost certain the - mtcpu/mfcpu were undocumented, but available in the older 700 machines. */ -{ "mtcpu", 0x14001600, 0xfc00ffff, "x,^", pa10, 0}, -{ "mfcpu", 0x14001A00, 0xfc00ffff, "^,x", pa10, 0}, -{ "tocen", 0x14403600, 0xffffffff, "", pa10, 0}, -{ "tocdis", 0x14401620, 0xffffffff, "", pa10, 0}, -{ "shdwgr", 0x14402600, 0xffffffff, "", pa10, 0}, -{ "grshdw", 0x14400620, 0xffffffff, "", pa10, 0}, - -/* gfw and gfr are not in the HP PA 1.1 manual, but they are in either - the Timex FPU or the Mustang ERS (not sure which) manual. */ -{ "gfw", 0x04001680, 0xfc00ffdf, "cZx(b)", pa11, 0}, -{ "gfw", 0x04001680, 0xfc003fdf, "cZx(s,b)", pa11, 0}, -{ "gfr", 0x04001a80, 0xfc00ffdf, "cZx(b)", pa11, 0}, -{ "gfr", 0x04001a80, 0xfc003fdf, "cZx(s,b)", pa11, 0}, - -/* Floating Point Coprocessor Instructions. */ - -{ "fldw", 0x24000000, 0xfc00df80, "cXx(b),fT", pa10, FLAG_STRICT}, -{ "fldw", 0x24000000, 0xfc001f80, "cXx(s,b),fT", pa10, FLAG_STRICT}, -{ "fldw", 0x24000000, 0xfc00d380, "cxccx(b),fT", pa11, FLAG_STRICT}, -{ "fldw", 0x24000000, 0xfc001380, "cxccx(s,b),fT", pa11, FLAG_STRICT}, -{ "fldw", 0x24001020, 0xfc1ff3a0, "cocc@(b),fT", pa20, FLAG_STRICT}, -{ "fldw", 0x24001020, 0xfc1f33a0, "cocc@(s,b),fT", pa20, FLAG_STRICT}, -{ "fldw", 0x24001000, 0xfc00df80, "cM5(b),fT", pa10, FLAG_STRICT}, -{ "fldw", 0x24001000, 0xfc001f80, "cM5(s,b),fT", pa10, FLAG_STRICT}, -{ "fldw", 0x24001000, 0xfc00d380, "cmcc5(b),fT", pa11, FLAG_STRICT}, -{ "fldw", 0x24001000, 0xfc001380, "cmcc5(s,b),fT", pa11, FLAG_STRICT}, -{ "fldw", 0x5c000000, 0xfc000004, "y(b),fe", pa20w, FLAG_STRICT}, -{ "fldw", 0x58000000, 0xfc000000, "cJy(b),fe", pa20w, FLAG_STRICT}, -{ "fldw", 0x5c000000, 0xfc00c004, "d(b),fe", pa20, FLAG_STRICT}, -{ "fldw", 0x5c000000, 0xfc000004, "d(s,b),fe", pa20, FLAG_STRICT}, -{ "fldw", 0x58000000, 0xfc00c000, "cJd(b),fe", pa20, FLAG_STRICT}, -{ "fldw", 0x58000000, 0xfc000000, "cJd(s,b),fe", pa20, FLAG_STRICT}, -{ "fldd", 0x2c000000, 0xfc00dfc0, "cXx(b),ft", pa10, FLAG_STRICT}, -{ "fldd", 0x2c000000, 0xfc001fc0, "cXx(s,b),ft", pa10, FLAG_STRICT}, -{ "fldd", 0x2c000000, 0xfc00d3c0, "cxccx(b),ft", pa11, FLAG_STRICT}, -{ "fldd", 0x2c000000, 0xfc0013c0, "cxccx(s,b),ft", pa11, FLAG_STRICT}, -{ "fldd", 0x2c001020, 0xfc1ff3e0, "cocc@(b),ft", pa20, FLAG_STRICT}, -{ "fldd", 0x2c001020, 0xfc1f33e0, "cocc@(s,b),ft", pa20, FLAG_STRICT}, -{ "fldd", 0x2c001000, 0xfc00dfc0, "cM5(b),ft", pa10, FLAG_STRICT}, -{ "fldd", 0x2c001000, 0xfc001fc0, "cM5(s,b),ft", pa10, FLAG_STRICT}, -{ "fldd", 0x2c001000, 0xfc00d3c0, "cmcc5(b),ft", pa11, FLAG_STRICT}, -{ "fldd", 0x2c001000, 0xfc0013c0, "cmcc5(s,b),ft", pa11, FLAG_STRICT}, -{ "fldd", 0x50000002, 0xfc000002, "cq&(b),fx", pa20w, FLAG_STRICT}, -{ "fldd", 0x50000002, 0xfc00c002, "cq#(b),fx", pa20, FLAG_STRICT}, -{ "fldd", 0x50000002, 0xfc000002, "cq#(s,b),fx", pa20, FLAG_STRICT}, -{ "fstw", 0x24000200, 0xfc00df80, "cXfT,x(b)", pa10, FLAG_STRICT}, -{ "fstw", 0x24000200, 0xfc001f80, "cXfT,x(s,b)", pa10, FLAG_STRICT}, -{ "fstw", 0x24000200, 0xfc00d380, "cxcCfT,x(b)", pa11, FLAG_STRICT}, -{ "fstw", 0x24000200, 0xfc001380, "cxcCfT,x(s,b)", pa11, FLAG_STRICT}, -{ "fstw", 0x24001220, 0xfc1ff3a0, "cocCfT,@(b)", pa20, FLAG_STRICT}, -{ "fstw", 0x24001220, 0xfc1f33a0, "cocCfT,@(s,b)", pa20, FLAG_STRICT}, -{ "fstw", 0x24001200, 0xfc00df80, "cMfT,5(b)", pa10, FLAG_STRICT}, -{ "fstw", 0x24001200, 0xfc001f80, "cMfT,5(s,b)", pa10, FLAG_STRICT}, -{ "fstw", 0x24001200, 0xfc00df80, "cMfT,5(b)", pa10, FLAG_STRICT}, -{ "fstw", 0x24001200, 0xfc001f80, "cMfT,5(s,b)", pa10, FLAG_STRICT}, -{ "fstw", 0x7c000000, 0xfc000004, "fE,y(b)", pa20w, FLAG_STRICT}, -{ "fstw", 0x78000000, 0xfc000000, "cJfE,y(b)", pa20w, FLAG_STRICT}, -{ "fstw", 0x7c000000, 0xfc00c004, "fE,d(b)", pa20, FLAG_STRICT}, -{ "fstw", 0x7c000000, 0xfc000004, "fE,d(s,b)", pa20, FLAG_STRICT}, -{ "fstw", 0x78000000, 0xfc00c000, "cJfE,d(b)", pa20, FLAG_STRICT}, -{ "fstw", 0x78000000, 0xfc000000, "cJfE,d(s,b)", pa20, FLAG_STRICT}, -{ "fstd", 0x2c000200, 0xfc00dfc0, "cXft,x(b)", pa10, FLAG_STRICT}, -{ "fstd", 0x2c000200, 0xfc001fc0, "cXft,x(s,b)", pa10, FLAG_STRICT}, -{ "fstd", 0x2c000200, 0xfc00d3c0, "cxcCft,x(b)", pa11, FLAG_STRICT}, -{ "fstd", 0x2c000200, 0xfc0013c0, "cxcCft,x(s,b)", pa11, FLAG_STRICT}, -{ "fstd", 0x2c001220, 0xfc1ff3e0, "cocCft,@(b)", pa20, FLAG_STRICT}, -{ "fstd", 0x2c001220, 0xfc1f33e0, "cocCft,@(s,b)", pa20, FLAG_STRICT}, -{ "fstd", 0x2c001200, 0xfc00dfc0, "cMft,5(b)", pa10, FLAG_STRICT}, -{ "fstd", 0x2c001200, 0xfc001fc0, "cMft,5(s,b)", pa10, FLAG_STRICT}, -{ "fstd", 0x2c001200, 0xfc00d3c0, "cmcCft,5(b)", pa11, FLAG_STRICT}, -{ "fstd", 0x2c001200, 0xfc0013c0, "cmcCft,5(s,b)", pa11, FLAG_STRICT}, -{ "fstd", 0x70000002, 0xfc000002, "cqfx,&(b)", pa20w, FLAG_STRICT}, -{ "fstd", 0x70000002, 0xfc00c002, "cqfx,#(b)", pa20, FLAG_STRICT}, -{ "fstd", 0x70000002, 0xfc000002, "cqfx,#(s,b)", pa20, FLAG_STRICT}, -{ "fldwx", 0x24000000, 0xfc00df80, "cXx(b),fT", pa10, FLAG_STRICT}, -{ "fldwx", 0x24000000, 0xfc001f80, "cXx(s,b),fT", pa10, FLAG_STRICT}, -{ "fldwx", 0x24000000, 0xfc00d380, "cxccx(b),fT", pa11, FLAG_STRICT}, -{ "fldwx", 0x24000000, 0xfc001380, "cxccx(s,b),fT", pa11, FLAG_STRICT}, -{ "fldwx", 0x24000000, 0xfc00df80, "cXx(b),fT", pa10, 0}, -{ "fldwx", 0x24000000, 0xfc001f80, "cXx(s,b),fT", pa10, 0}, -{ "flddx", 0x2c000000, 0xfc00dfc0, "cXx(b),ft", pa10, FLAG_STRICT}, -{ "flddx", 0x2c000000, 0xfc001fc0, "cXx(s,b),ft", pa10, FLAG_STRICT}, -{ "flddx", 0x2c000000, 0xfc00d3c0, "cxccx(b),ft", pa11, FLAG_STRICT}, -{ "flddx", 0x2c000000, 0xfc0013c0, "cxccx(s,b),ft", pa11, FLAG_STRICT}, -{ "flddx", 0x2c000000, 0xfc00dfc0, "cXx(b),ft", pa10, 0}, -{ "flddx", 0x2c000000, 0xfc001fc0, "cXx(s,b),ft", pa10, 0}, -{ "fstwx", 0x24000200, 0xfc00df80, "cxfT,x(b)", pa10, FLAG_STRICT}, -{ "fstwx", 0x24000200, 0xfc001f80, "cxfT,x(s,b)", pa10, FLAG_STRICT}, -{ "fstwx", 0x24000200, 0xfc00d380, "cxcCfT,x(b)", pa11, FLAG_STRICT}, -{ "fstwx", 0x24000200, 0xfc001380, "cxcCfT,x(s,b)", pa11, FLAG_STRICT}, -{ "fstwx", 0x24000200, 0xfc00df80, "cxfT,x(b)", pa10, 0}, -{ "fstwx", 0x24000200, 0xfc001f80, "cxfT,x(s,b)", pa10, 0}, -{ "fstdx", 0x2c000200, 0xfc00dfc0, "cxft,x(b)", pa10, FLAG_STRICT}, -{ "fstdx", 0x2c000200, 0xfc001fc0, "cxft,x(s,b)", pa10, FLAG_STRICT}, -{ "fstdx", 0x2c000200, 0xfc00d3c0, "cxcCft,x(b)", pa11, FLAG_STRICT}, -{ "fstdx", 0x2c000200, 0xfc0013c0, "cxcCft,x(s,b)", pa11, FLAG_STRICT}, -{ "fstdx", 0x2c000200, 0xfc00dfc0, "cxft,x(b)", pa10, 0}, -{ "fstdx", 0x2c000200, 0xfc001fc0, "cxft,x(s,b)", pa10, 0}, -{ "fstqx", 0x3c000200, 0xfc00dfc0, "cXft,x(b)", pa10, 0}, -{ "fstqx", 0x3c000200, 0xfc001fc0, "cXft,x(s,b)", pa10, 0}, -{ "fldws", 0x24001000, 0xfc00df80, "cm5(b),fT", pa10, FLAG_STRICT}, -{ "fldws", 0x24001000, 0xfc001f80, "cm5(s,b),fT", pa10, FLAG_STRICT}, -{ "fldws", 0x24001000, 0xfc00d380, "cmcc5(b),fT", pa11, FLAG_STRICT}, -{ "fldws", 0x24001000, 0xfc001380, "cmcc5(s,b),fT", pa11, FLAG_STRICT}, -{ "fldws", 0x24001000, 0xfc00df80, "cm5(b),fT", pa10, 0}, -{ "fldws", 0x24001000, 0xfc001f80, "cm5(s,b),fT", pa10, 0}, -{ "fldds", 0x2c001000, 0xfc00dfc0, "cm5(b),ft", pa10, FLAG_STRICT}, -{ "fldds", 0x2c001000, 0xfc001fc0, "cm5(s,b),ft", pa10, FLAG_STRICT}, -{ "fldds", 0x2c001000, 0xfc00d3c0, "cmcc5(b),ft", pa11, FLAG_STRICT}, -{ "fldds", 0x2c001000, 0xfc0013c0, "cmcc5(s,b),ft", pa11, FLAG_STRICT}, -{ "fldds", 0x2c001000, 0xfc00dfc0, "cm5(b),ft", pa10, 0}, -{ "fldds", 0x2c001000, 0xfc001fc0, "cm5(s,b),ft", pa10, 0}, -{ "fstws", 0x24001200, 0xfc00df80, "cmfT,5(b)", pa10, FLAG_STRICT}, -{ "fstws", 0x24001200, 0xfc001f80, "cmfT,5(s,b)", pa10, FLAG_STRICT}, -{ "fstws", 0x24001200, 0xfc00d380, "cmcCfT,5(b)", pa11, FLAG_STRICT}, -{ "fstws", 0x24001200, 0xfc001380, "cmcCfT,5(s,b)", pa11, FLAG_STRICT}, -{ "fstws", 0x24001200, 0xfc00df80, "cmfT,5(b)", pa10, 0}, -{ "fstws", 0x24001200, 0xfc001f80, "cmfT,5(s,b)", pa10, 0}, -{ "fstds", 0x2c001200, 0xfc00dfc0, "cmft,5(b)", pa10, FLAG_STRICT}, -{ "fstds", 0x2c001200, 0xfc001fc0, "cmft,5(s,b)", pa10, FLAG_STRICT}, -{ "fstds", 0x2c001200, 0xfc00d3c0, "cmcCft,5(b)", pa11, FLAG_STRICT}, -{ "fstds", 0x2c001200, 0xfc0013c0, "cmcCft,5(s,b)", pa11, FLAG_STRICT}, -{ "fstds", 0x2c001200, 0xfc00dfc0, "cmft,5(b)", pa10, 0}, -{ "fstds", 0x2c001200, 0xfc001fc0, "cmft,5(s,b)", pa10, 0}, -{ "fstqs", 0x3c001200, 0xfc00dfc0, "cMft,5(b)", pa10, 0}, -{ "fstqs", 0x3c001200, 0xfc001fc0, "cMft,5(s,b)", pa10, 0}, -{ "fadd", 0x30000600, 0xfc00e7e0, "Ffa,fb,fT", pa10, 0}, -{ "fadd", 0x38000600, 0xfc00e720, "IfA,fB,fT", pa10, 0}, -{ "fsub", 0x30002600, 0xfc00e7e0, "Ffa,fb,fT", pa10, 0}, -{ "fsub", 0x38002600, 0xfc00e720, "IfA,fB,fT", pa10, 0}, -{ "fmpy", 0x30004600, 0xfc00e7e0, "Ffa,fb,fT", pa10, 0}, -{ "fmpy", 0x38004600, 0xfc00e720, "IfA,fB,fT", pa10, 0}, -{ "fdiv", 0x30006600, 0xfc00e7e0, "Ffa,fb,fT", pa10, 0}, -{ "fdiv", 0x38006600, 0xfc00e720, "IfA,fB,fT", pa10, 0}, -{ "fsqrt", 0x30008000, 0xfc1fe7e0, "Ffa,fT", pa10, 0}, -{ "fsqrt", 0x38008000, 0xfc1fe720, "FfA,fT", pa10, 0}, -{ "fabs", 0x30006000, 0xfc1fe7e0, "Ffa,fT", pa10, 0}, -{ "fabs", 0x38006000, 0xfc1fe720, "FfA,fT", pa10, 0}, -{ "frem", 0x30008600, 0xfc00e7e0, "Ffa,fb,fT", pa10, 0}, -{ "frem", 0x38008600, 0xfc00e720, "FfA,fB,fT", pa10, 0}, -{ "frnd", 0x3000a000, 0xfc1fe7e0, "Ffa,fT", pa10, 0}, -{ "frnd", 0x3800a000, 0xfc1fe720, "FfA,fT", pa10, 0}, -{ "fcpy", 0x30004000, 0xfc1fe7e0, "Ffa,fT", pa10, 0}, -{ "fcpy", 0x38004000, 0xfc1fe720, "FfA,fT", pa10, 0}, -{ "fcnvff", 0x30000200, 0xfc1f87e0, "FGfa,fT", pa10, 0}, -{ "fcnvff", 0x38000200, 0xfc1f8720, "FGfA,fT", pa10, 0}, -{ "fcnvxf", 0x30008200, 0xfc1f87e0, "FGfa,fT", pa10, 0}, -{ "fcnvxf", 0x38008200, 0xfc1f8720, "FGfA,fT", pa10, 0}, -{ "fcnvfx", 0x30010200, 0xfc1f87e0, "FGfa,fT", pa10, 0}, -{ "fcnvfx", 0x38010200, 0xfc1f8720, "FGfA,fT", pa10, 0}, -{ "fcnvfxt", 0x30018200, 0xfc1f87e0, "FGfa,fT", pa10, 0}, -{ "fcnvfxt", 0x38018200, 0xfc1f8720, "FGfA,fT", pa10, 0}, -{ "fmpyfadd", 0xb8000000, 0xfc000020, "IfA,fB,fC,fT", pa20, FLAG_STRICT}, -{ "fmpynfadd", 0xb8000020, 0xfc000020, "IfA,fB,fC,fT", pa20, FLAG_STRICT}, -{ "fneg", 0x3000c000, 0xfc1fe7e0, "Ffa,fT", pa20, FLAG_STRICT}, -{ "fneg", 0x3800c000, 0xfc1fe720, "IfA,fT", pa20, FLAG_STRICT}, -{ "fnegabs", 0x3000e000, 0xfc1fe7e0, "Ffa,fT", pa20, FLAG_STRICT}, -{ "fnegabs", 0x3800e000, 0xfc1fe720, "IfA,fT", pa20, FLAG_STRICT}, -{ "fcnv", 0x30000200, 0xfc1c0720, "{_fa,fT", pa20, FLAG_STRICT}, -{ "fcnv", 0x38000200, 0xfc1c0720, "FGfA,fT", pa20, FLAG_STRICT}, -{ "fcmp", 0x30000400, 0xfc00e7e0, "F?ffa,fb", pa10, FLAG_STRICT}, -{ "fcmp", 0x38000400, 0xfc00e720, "I?ffA,fB", pa10, FLAG_STRICT}, -{ "fcmp", 0x30000400, 0xfc0007e0, "F?ffa,fb,h", pa20, FLAG_STRICT}, -{ "fcmp", 0x38000400, 0xfc000720, "I?ffA,fB,h", pa20, FLAG_STRICT}, -{ "fcmp", 0x30000400, 0xfc00e7e0, "F?ffa,fb", pa10, 0}, -{ "fcmp", 0x38000400, 0xfc00e720, "I?ffA,fB", pa10, 0}, -{ "xmpyu", 0x38004700, 0xfc00e720, "fX,fB,fT", pa11, 0}, -{ "fmpyadd", 0x18000000, 0xfc000000, "Hfi,fj,fk,fl,fm", pa11, 0}, -{ "fmpysub", 0x98000000, 0xfc000000, "Hfi,fj,fk,fl,fm", pa11, 0}, -{ "ftest", 0x30002420, 0xffffffff, "", pa10, FLAG_STRICT}, -{ "ftest", 0x30002420, 0xffffffe0, ",=", pa20, FLAG_STRICT}, -{ "ftest", 0x30000420, 0xffff1fff, "m", pa20, FLAG_STRICT}, -{ "fid", 0x30000000, 0xffffffff, "", pa11, 0}, - -/* Performance Monitor Instructions. */ - -{ "pmdis", 0x30000280, 0xffffffdf, "N", pa20, FLAG_STRICT}, -{ "pmenb", 0x30000680, 0xffffffff, "", pa20, FLAG_STRICT}, - -/* Assist Instructions. */ - -{ "spop0", 0x10000000, 0xfc000600, "v,ON", pa10, 0}, -{ "spop1", 0x10000200, 0xfc000600, "v,oNt", pa10, 0}, -{ "spop2", 0x10000400, 0xfc000600, "v,1Nb", pa10, 0}, -{ "spop3", 0x10000600, 0xfc000600, "v,0Nx,b", pa10, 0}, -{ "copr", 0x30000000, 0xfc000000, "u,2N", pa10, 0}, -{ "cldw", 0x24000000, 0xfc00de00, "ucXx(b),t", pa10, FLAG_STRICT}, -{ "cldw", 0x24000000, 0xfc001e00, "ucXx(s,b),t", pa10, FLAG_STRICT}, -{ "cldw", 0x24000000, 0xfc00d200, "ucxccx(b),t", pa11, FLAG_STRICT}, -{ "cldw", 0x24000000, 0xfc001200, "ucxccx(s,b),t", pa11, FLAG_STRICT}, -{ "cldw", 0x24001000, 0xfc00d200, "ucocc@(b),t", pa20, FLAG_STRICT}, -{ "cldw", 0x24001000, 0xfc001200, "ucocc@(s,b),t", pa20, FLAG_STRICT}, -{ "cldw", 0x24001000, 0xfc00de00, "ucM5(b),t", pa10, FLAG_STRICT}, -{ "cldw", 0x24001000, 0xfc001e00, "ucM5(s,b),t", pa10, FLAG_STRICT}, -{ "cldw", 0x24001000, 0xfc00d200, "ucmcc5(b),t", pa11, FLAG_STRICT}, -{ "cldw", 0x24001000, 0xfc001200, "ucmcc5(s,b),t", pa11, FLAG_STRICT}, -{ "cldd", 0x2c000000, 0xfc00de00, "ucXx(b),t", pa10, FLAG_STRICT}, -{ "cldd", 0x2c000000, 0xfc001e00, "ucXx(s,b),t", pa10, FLAG_STRICT}, -{ "cldd", 0x2c000000, 0xfc00d200, "ucxccx(b),t", pa11, FLAG_STRICT}, -{ "cldd", 0x2c000000, 0xfc001200, "ucxccx(s,b),t", pa11, FLAG_STRICT}, -{ "cldd", 0x2c001000, 0xfc00d200, "ucocc@(b),t", pa20, FLAG_STRICT}, -{ "cldd", 0x2c001000, 0xfc001200, "ucocc@(s,b),t", pa20, FLAG_STRICT}, -{ "cldd", 0x2c001000, 0xfc00de00, "ucM5(b),t", pa10, FLAG_STRICT}, -{ "cldd", 0x2c001000, 0xfc001e00, "ucM5(s,b),t", pa10, FLAG_STRICT}, -{ "cldd", 0x2c001000, 0xfc00d200, "ucmcc5(b),t", pa11, FLAG_STRICT}, -{ "cldd", 0x2c001000, 0xfc001200, "ucmcc5(s,b),t", pa11, FLAG_STRICT}, -{ "cstw", 0x24000200, 0xfc00de00, "ucXt,x(b)", pa10, FLAG_STRICT}, -{ "cstw", 0x24000200, 0xfc001e00, "ucXt,x(s,b)", pa10, FLAG_STRICT}, -{ "cstw", 0x24000200, 0xfc00d200, "ucxcCt,x(b)", pa11, FLAG_STRICT}, -{ "cstw", 0x24000200, 0xfc001200, "ucxcCt,x(s,b)", pa11, FLAG_STRICT}, -{ "cstw", 0x24001200, 0xfc00d200, "ucocCt,@(b)", pa20, FLAG_STRICT}, -{ "cstw", 0x24001200, 0xfc001200, "ucocCt,@(s,b)", pa20, FLAG_STRICT}, -{ "cstw", 0x24001200, 0xfc00de00, "ucMt,5(b)", pa10, FLAG_STRICT}, -{ "cstw", 0x24001200, 0xfc001e00, "ucMt,5(s,b)", pa10, FLAG_STRICT}, -{ "cstw", 0x24001200, 0xfc00d200, "ucmcCt,5(b)", pa11, FLAG_STRICT}, -{ "cstw", 0x24001200, 0xfc001200, "ucmcCt,5(s,b)", pa11, FLAG_STRICT}, -{ "cstd", 0x2c000200, 0xfc00de00, "ucXt,x(b)", pa10, FLAG_STRICT}, -{ "cstd", 0x2c000200, 0xfc001e00, "ucXt,x(s,b)", pa10, FLAG_STRICT}, -{ "cstd", 0x2c000200, 0xfc00d200, "ucxcCt,x(b)", pa11, FLAG_STRICT}, -{ "cstd", 0x2c000200, 0xfc001200, "ucxcCt,x(s,b)", pa11, FLAG_STRICT}, -{ "cstd", 0x2c001200, 0xfc00d200, "ucocCt,@(b)", pa20, FLAG_STRICT}, -{ "cstd", 0x2c001200, 0xfc001200, "ucocCt,@(s,b)", pa20, FLAG_STRICT}, -{ "cstd", 0x2c001200, 0xfc00de00, "ucMt,5(b)", pa10, FLAG_STRICT}, -{ "cstd", 0x2c001200, 0xfc001e00, "ucMt,5(s,b)", pa10, FLAG_STRICT}, -{ "cstd", 0x2c001200, 0xfc00d200, "ucmcCt,5(b)", pa11, FLAG_STRICT}, -{ "cstd", 0x2c001200, 0xfc001200, "ucmcCt,5(s,b)", pa11, FLAG_STRICT}, -{ "cldwx", 0x24000000, 0xfc00de00, "ucXx(b),t", pa10, FLAG_STRICT}, -{ "cldwx", 0x24000000, 0xfc001e00, "ucXx(s,b),t", pa10, FLAG_STRICT}, -{ "cldwx", 0x24000000, 0xfc00d200, "ucxccx(b),t", pa11, FLAG_STRICT}, -{ "cldwx", 0x24000000, 0xfc001200, "ucxccx(s,b),t", pa11, FLAG_STRICT}, -{ "cldwx", 0x24000000, 0xfc00de00, "ucXx(b),t", pa10, 0}, -{ "cldwx", 0x24000000, 0xfc001e00, "ucXx(s,b),t", pa10, 0}, -{ "clddx", 0x2c000000, 0xfc00de00, "ucXx(b),t", pa10, FLAG_STRICT}, -{ "clddx", 0x2c000000, 0xfc001e00, "ucXx(s,b),t", pa10, FLAG_STRICT}, -{ "clddx", 0x2c000000, 0xfc00d200, "ucxccx(b),t", pa11, FLAG_STRICT}, -{ "clddx", 0x2c000000, 0xfc001200, "ucxccx(s,b),t", pa11, FLAG_STRICT}, -{ "clddx", 0x2c000000, 0xfc00de00, "ucXx(b),t", pa10, 0}, -{ "clddx", 0x2c000000, 0xfc001e00, "ucXx(s,b),t", pa10, 0}, -{ "cstwx", 0x24000200, 0xfc00de00, "ucXt,x(b)", pa10, FLAG_STRICT}, -{ "cstwx", 0x24000200, 0xfc001e00, "ucXt,x(s,b)", pa10, FLAG_STRICT}, -{ "cstwx", 0x24000200, 0xfc00d200, "ucxcCt,x(b)", pa11, FLAG_STRICT}, -{ "cstwx", 0x24000200, 0xfc001200, "ucxcCt,x(s,b)", pa11, FLAG_STRICT}, -{ "cstwx", 0x24000200, 0xfc00de00, "ucXt,x(b)", pa10, 0}, -{ "cstwx", 0x24000200, 0xfc001e00, "ucXt,x(s,b)", pa10, 0}, -{ "cstdx", 0x2c000200, 0xfc00de00, "ucXt,x(b)", pa10, FLAG_STRICT}, -{ "cstdx", 0x2c000200, 0xfc001e00, "ucXt,x(s,b)", pa10, FLAG_STRICT}, -{ "cstdx", 0x2c000200, 0xfc00d200, "ucxcCt,x(b)", pa11, FLAG_STRICT}, -{ "cstdx", 0x2c000200, 0xfc001200, "ucxcCt,x(s,b)", pa11, FLAG_STRICT}, -{ "cstdx", 0x2c000200, 0xfc00de00, "ucXt,x(b)", pa10, 0}, -{ "cstdx", 0x2c000200, 0xfc001e00, "ucXt,x(s,b)", pa10, 0}, -{ "cldws", 0x24001000, 0xfc00de00, "ucM5(b),t", pa10, FLAG_STRICT}, -{ "cldws", 0x24001000, 0xfc001e00, "ucM5(s,b),t", pa10, FLAG_STRICT}, -{ "cldws", 0x24001000, 0xfc00d200, "ucmcc5(b),t", pa11, FLAG_STRICT}, -{ "cldws", 0x24001000, 0xfc001200, "ucmcc5(s,b),t", pa11, FLAG_STRICT}, -{ "cldws", 0x24001000, 0xfc00de00, "ucM5(b),t", pa10, 0}, -{ "cldws", 0x24001000, 0xfc001e00, "ucM5(s,b),t", pa10, 0}, -{ "cldds", 0x2c001000, 0xfc00de00, "ucM5(b),t", pa10, FLAG_STRICT}, -{ "cldds", 0x2c001000, 0xfc001e00, "ucM5(s,b),t", pa10, FLAG_STRICT}, -{ "cldds", 0x2c001000, 0xfc00d200, "ucmcc5(b),t", pa11, FLAG_STRICT}, -{ "cldds", 0x2c001000, 0xfc001200, "ucmcc5(s,b),t", pa11, FLAG_STRICT}, -{ "cldds", 0x2c001000, 0xfc00de00, "ucM5(b),t", pa10, 0}, -{ "cldds", 0x2c001000, 0xfc001e00, "ucM5(s,b),t", pa10, 0}, -{ "cstws", 0x24001200, 0xfc00de00, "ucMt,5(b)", pa10, FLAG_STRICT}, -{ "cstws", 0x24001200, 0xfc001e00, "ucMt,5(s,b)", pa10, FLAG_STRICT}, -{ "cstws", 0x24001200, 0xfc00d200, "ucmcCt,5(b)", pa11, FLAG_STRICT}, -{ "cstws", 0x24001200, 0xfc001200, "ucmcCt,5(s,b)", pa11, FLAG_STRICT}, -{ "cstws", 0x24001200, 0xfc00de00, "ucMt,5(b)", pa10, 0}, -{ "cstws", 0x24001200, 0xfc001e00, "ucMt,5(s,b)", pa10, 0}, -{ "cstds", 0x2c001200, 0xfc00de00, "ucMt,5(b)", pa10, FLAG_STRICT}, -{ "cstds", 0x2c001200, 0xfc001e00, "ucMt,5(s,b)", pa10, FLAG_STRICT}, -{ "cstds", 0x2c001200, 0xfc00d200, "ucmcCt,5(b)", pa11, FLAG_STRICT}, -{ "cstds", 0x2c001200, 0xfc001200, "ucmcCt,5(s,b)", pa11, FLAG_STRICT}, -{ "cstds", 0x2c001200, 0xfc00de00, "ucMt,5(b)", pa10, 0}, -{ "cstds", 0x2c001200, 0xfc001e00, "ucMt,5(s,b)", pa10, 0}, - -/* More pseudo instructions which must follow the main table. */ -{ "call", 0xe800f000, 0xfc1ffffd, "n(b)", pa20, FLAG_STRICT}, -{ "call", 0xe800a000, 0xffe0e000, "nW", pa10, FLAG_STRICT}, -{ "ret", 0xe840d000, 0xfffffffd, "n", pa20, FLAG_STRICT}, - -}; - -#define NUMOPCODES ((sizeof pa_opcodes)/(sizeof pa_opcodes[0])) - -/* SKV 12/18/92. Added some denotations for various operands. */ - -#define PA_IMM11_AT_31 'i' -#define PA_IMM14_AT_31 'j' -#define PA_IMM21_AT_31 'k' -#define PA_DISP12 'w' -#define PA_DISP17 'W' - -#define N_HPPA_OPERAND_FORMATS 5 diff --git a/include/opcode/i370.h b/include/opcode/i370.h deleted file mode 100644 index e3b7166..0000000 --- a/include/opcode/i370.h +++ /dev/null @@ -1,267 +0,0 @@ -/* i370.h -- Header file for S/390 opcode table - Copyright 1994, 1995, 1998, 1999, 2000, 2003, 2010 - Free Software Foundation, Inc. - PowerPC version written by Ian Lance Taylor, Cygnus Support - Rewritten for i370 ESA/390 support, Linas Vepstas <linas@linas.org> - - This file is part of GDB, GAS, and the GNU binutils. - - GDB, GAS, and the GNU binutils are free software; you can redistribute - them and/or modify them under the terms of the GNU General Public - License as published by the Free Software Foundation; either version 3, - or (at your option) any later version. - - GDB, GAS, and the GNU binutils are distributed in the hope that they - will be useful, but WITHOUT ANY WARRANTY; without even the implied - warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See - the GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this file; see the file COPYING3. If not, write to the Free - Software Foundation, 51 Franklin Street - Fifth Floor, Boston, - MA 02110-1301, USA. */ - -#ifndef I370_H -#define I370_H - -/* The opcode table is an array of struct i370_opcode. */ -typedef union -{ - unsigned int i[2]; - unsigned short s[4]; - unsigned char b[8]; -} i370_insn_t; - -struct i370_opcode -{ - /* The opcode name. */ - const char *name; - - /* the length of the instruction */ - char len; - - /* The opcode itself. Those bits which will be filled in with - operands are zeroes. */ - i370_insn_t opcode; - - /* The opcode mask. This is used by the disassembler. This is a - mask containing ones indicating those bits which must match the - opcode field, and zeroes indicating those bits which need not - match (and are presumably filled in by operands). */ - i370_insn_t mask; - - /* One bit flags for the opcode. These are used to indicate which - specific processors support the instructions. The defined values - are listed below. */ - unsigned long flags; - - /* An array of operand codes. Each code is an index into the - operand table. They appear in the order which the operands must - appear in assembly code, and are terminated by a zero. */ - unsigned char operands[8]; -}; - -/* The table itself is sorted by major opcode number, and is otherwise - in the order in which the disassembler should consider - instructions. */ -extern const struct i370_opcode i370_opcodes[]; -extern const int i370_num_opcodes; - -/* Values defined for the flags field of a struct i370_opcode. */ - -/* Opcode is defined for the original 360 architecture. */ -#define I370_OPCODE_360 (0x01) - -/* Opcode is defined for the 370 architecture. */ -#define I370_OPCODE_370 (0x02) - -/* Opcode is defined for the 370-XA architecture. */ -#define I370_OPCODE_370_XA (0x04) - -/* Opcode is defined for the ESA/370 architecture. */ -#define I370_OPCODE_ESA370 (0x08) - -/* Opcode is defined for the ESA/390 architecture. */ -#define I370_OPCODE_ESA390 (0x10) - -/* Opcode is defined for the ESA/390 w/ BFP facility. */ -#define I370_OPCODE_ESA390_BF (0x20) - -/* Opcode is defined for the ESA/390 w/ branch & set authority facility. */ -#define I370_OPCODE_ESA390_BS (0x40) - -/* Opcode is defined for the ESA/390 w/ checksum facility. */ -#define I370_OPCODE_ESA390_CK (0x80) - -/* Opcode is defined for the ESA/390 w/ compare & move extended facility. */ -#define I370_OPCODE_ESA390_CM (0x100) - -/* Opcode is defined for the ESA/390 w/ flt.pt. support extensions facility. */ -#define I370_OPCODE_ESA390_FX (0x200) - -/* Opcode is defined for the ESA/390 w/ HFP facility. */ -#define I370_OPCODE_ESA390_HX (0x400) - -/* Opcode is defined for the ESA/390 w/ immediate & relative facility. */ -#define I370_OPCODE_ESA390_IR (0x800) - -/* Opcode is defined for the ESA/390 w/ move-inverse facility. */ -#define I370_OPCODE_ESA390_MI (0x1000) - -/* Opcode is defined for the ESA/390 w/ program-call-fast facility. */ -#define I370_OPCODE_ESA390_PC (0x2000) - -/* Opcode is defined for the ESA/390 w/ perform-locked-op facility. */ -#define I370_OPCODE_ESA390_PL (0x4000) - -/* Opcode is defined for the ESA/390 w/ square-root facility. */ -#define I370_OPCODE_ESA390_QR (0x8000) - -/* Opcode is defined for the ESA/390 w/ resume-program facility. */ -#define I370_OPCODE_ESA390_RP (0x10000) - -/* Opcode is defined for the ESA/390 w/ set-address-space-fast facility. */ -#define I370_OPCODE_ESA390_SA (0x20000) - -/* Opcode is defined for the ESA/390 w/ subspace group facility. */ -#define I370_OPCODE_ESA390_SG (0x40000) - -/* Opcode is defined for the ESA/390 w/ string facility. */ -#define I370_OPCODE_ESA390_SR (0x80000) - -/* Opcode is defined for the ESA/390 w/ trap facility. */ -#define I370_OPCODE_ESA390_TR (0x100000) - -#define I370_OPCODE_ESA390_SUPERSET (0x1fffff) - - -/* The operands table is an array of struct i370_operand. */ - -struct i370_operand -{ - /* The number of bits in the operand. */ - int bits; - - /* How far the operand is left shifted in the instruction. */ - int shift; - - /* Insertion function. This is used by the assembler. To insert an - operand value into an instruction, check this field. - - If it is NULL, execute - i |= (op & ((1 << o->bits) - 1)) << o->shift; - (i is the instruction which we are filling in, o is a pointer to - this structure, and op is the opcode value; this assumes twos - complement arithmetic). - - If this field is not NULL, then simply call it with the - instruction and the operand value. It will return the new value - of the instruction. If the ERRMSG argument is not NULL, then if - the operand value is illegal, *ERRMSG will be set to a warning - string (the operand will be inserted in any case). If the - operand value is legal, *ERRMSG will be unchanged (most operands - can accept any value). */ - i370_insn_t (*insert) - (i370_insn_t instruction, long op, const char **errmsg); - - /* Extraction function. This is used by the disassembler. To - extract this operand type from an instruction, check this field. - - If it is NULL, compute - op = ((i) >> o->shift) & ((1 << o->bits) - 1); - if ((o->flags & I370_OPERAND_SIGNED) != 0 - && (op & (1 << (o->bits - 1))) != 0) - op -= 1 << o->bits; - (i is the instruction, o is a pointer to this structure, and op - is the result; this assumes twos complement arithmetic). - - If this field is not NULL, then simply call it with the - instruction value. It will return the value of the operand. If - the INVALID argument is not NULL, *INVALID will be set to - non-zero if this operand type can not actually be extracted from - this operand (i.e., the instruction does not match). If the - operand is valid, *INVALID will not be changed. */ - long (*extract) (i370_insn_t instruction, int *invalid); - - /* One bit syntax flags. */ - unsigned long flags; - - /* name -- handy for debugging, otherwise pointless */ - char * name; -}; - -/* Elements in the table are retrieved by indexing with values from - the operands field of the i370_opcodes table. */ - -extern const struct i370_operand i370_operands[]; - -/* Values defined for the flags field of a struct i370_operand. */ - -/* This operand should be wrapped in parentheses rather than - separated from the previous by a comma. This is used for S, RS and - SS form instructions which want their operands to look like - reg,displacement(basereg) */ -#define I370_OPERAND_SBASE (0x01) - -/* This operand is a base register. It may or may not appear next - to an index register, i.e. either of the two forms - reg,displacement(basereg) - reg,displacement(index,basereg) */ -#define I370_OPERAND_BASE (0x02) - -/* This pair of operands should be wrapped in parentheses rather than - separated from the last by a comma. This is used for the RX form - instructions which want their operands to look like - reg,displacement(index,basereg) */ -#define I370_OPERAND_INDEX (0x04) - -/* This operand names a register. The disassembler uses this to print - register names with a leading 'r'. */ -#define I370_OPERAND_GPR (0x08) - -/* This operand names a floating point register. The disassembler - prints these with a leading 'f'. */ -#define I370_OPERAND_FPR (0x10) - -/* This operand is a displacement. */ -#define I370_OPERAND_RELATIVE (0x20) - -/* This operand is a length, such as that in SS form instructions. */ -#define I370_OPERAND_LENGTH (0x40) - -/* This operand is optional, and is zero if omitted. This is used for - the optional B2 field in the shift-left, shift-right instructions. The - assembler must count the number of operands remaining on the line, - and the number of operands remaining for the opcode, and decide - whether this operand is present or not. The disassembler should - print this operand out only if it is not zero. */ -#define I370_OPERAND_OPTIONAL (0x80) - - -/* Define some misc macros. We keep them with the operands table - for simplicity. The macro table is an array of struct i370_macro. */ - -struct i370_macro -{ - /* The macro name. */ - const char *name; - - /* The number of operands the macro takes. */ - unsigned int operands; - - /* One bit flags for the opcode. These are used to indicate which - specific processors support the instructions. The values are the - same as those for the struct i370_opcode flags field. */ - unsigned long flags; - - /* A format string to turn the macro into a normal instruction. - Each %N in the string is replaced with operand number N (zero - based). */ - const char *format; -}; - -extern const struct i370_macro i370_macros[]; -extern const int i370_num_macros; - - -#endif /* I370_H */ diff --git a/include/opcode/i386.h b/include/opcode/i386.h deleted file mode 100644 index 6021002..0000000 --- a/include/opcode/i386.h +++ /dev/null @@ -1,148 +0,0 @@ -/* opcode/i386.h -- Intel 80386 opcode macros - Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, - 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010 - Free Software Foundation, Inc. - - This file is part of GAS, the GNU Assembler, and GDB, the GNU Debugger. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, - MA 02110-1301, USA. */ - -/* The SystemV/386 SVR3.2 assembler, and probably all AT&T derived - ix86 Unix assemblers, generate floating point instructions with - reversed source and destination registers in certain cases. - Unfortunately, gcc and possibly many other programs use this - reversed syntax, so we're stuck with it. - - eg. `fsub %st(3),%st' results in st = st - st(3) as expected, but - `fsub %st,%st(3)' results in st(3) = st - st(3), rather than - the expected st(3) = st(3) - st - - This happens with all the non-commutative arithmetic floating point - operations with two register operands, where the source register is - %st, and destination register is %st(i). - - The affected opcode map is dceX, dcfX, deeX, defX. */ - -#ifndef OPCODE_I386_H -#define OPCODE_I386_H - -#ifndef SYSV386_COMPAT -/* Set non-zero for broken, compatible instructions. Set to zero for - non-broken opcodes at your peril. gcc generates SystemV/386 - compatible instructions. */ -#define SYSV386_COMPAT 1 -#endif -#ifndef OLDGCC_COMPAT -/* Set non-zero to cater for old (<= 2.8.1) versions of gcc that could - generate nonsense fsubp, fsubrp, fdivp and fdivrp with operands - reversed. */ -#define OLDGCC_COMPAT SYSV386_COMPAT -#endif - -#define MOV_AX_DISP32 0xa0 -#define POP_SEG_SHORT 0x07 -#define JUMP_PC_RELATIVE 0xeb -#define INT_OPCODE 0xcd -#define INT3_OPCODE 0xcc -/* The opcode for the fwait instruction, which disassembler treats as a - prefix when it can. */ -#define FWAIT_OPCODE 0x9b - -/* Instruction prefixes. - NOTE: For certain SSE* instructions, 0x66,0xf2,0xf3 are treated as - part of the opcode. Other prefixes may still appear between them - and the 0x0f part of the opcode. */ -#define ADDR_PREFIX_OPCODE 0x67 -#define DATA_PREFIX_OPCODE 0x66 -#define LOCK_PREFIX_OPCODE 0xf0 -#define CS_PREFIX_OPCODE 0x2e -#define DS_PREFIX_OPCODE 0x3e -#define ES_PREFIX_OPCODE 0x26 -#define FS_PREFIX_OPCODE 0x64 -#define GS_PREFIX_OPCODE 0x65 -#define SS_PREFIX_OPCODE 0x36 -#define REPNE_PREFIX_OPCODE 0xf2 -#define REPE_PREFIX_OPCODE 0xf3 -#define XACQUIRE_PREFIX_OPCODE 0xf2 -#define XRELEASE_PREFIX_OPCODE 0xf3 -#define BND_PREFIX_OPCODE 0xf2 - -#define TWO_BYTE_OPCODE_ESCAPE 0x0f -#define NOP_OPCODE (char) 0x90 - -/* register numbers */ -#define EAX_REG_NUM 0 -#define ECX_REG_NUM 1 -#define EDX_REG_NUM 2 -#define EBX_REG_NUM 3 -#define ESP_REG_NUM 4 -#define EBP_REG_NUM 5 -#define ESI_REG_NUM 6 -#define EDI_REG_NUM 7 - -/* modrm_byte.regmem for twobyte escape */ -#define ESCAPE_TO_TWO_BYTE_ADDRESSING ESP_REG_NUM -/* index_base_byte.index for no index register addressing */ -#define NO_INDEX_REGISTER ESP_REG_NUM -/* index_base_byte.base for no base register addressing */ -#define NO_BASE_REGISTER EBP_REG_NUM -#define NO_BASE_REGISTER_16 6 - -/* modrm.mode = REGMEM_FIELD_HAS_REG when a register is in there */ -#define REGMEM_FIELD_HAS_REG 0x3/* always = 0x3 */ -#define REGMEM_FIELD_HAS_MEM (~REGMEM_FIELD_HAS_REG) - -/* Extract fields from the mod/rm byte. */ -#define MODRM_MOD_FIELD(modrm) (((modrm) >> 6) & 3) -#define MODRM_REG_FIELD(modrm) (((modrm) >> 3) & 7) -#define MODRM_RM_FIELD(modrm) (((modrm) >> 0) & 7) - -/* Extract fields from the sib byte. */ -#define SIB_SCALE_FIELD(sib) (((sib) >> 6) & 3) -#define SIB_INDEX_FIELD(sib) (((sib) >> 3) & 7) -#define SIB_BASE_FIELD(sib) (((sib) >> 0) & 7) - -/* x86-64 extension prefix. */ -#define REX_OPCODE 0x40 - -/* Non-zero if OPCODE is the rex prefix. */ -#define REX_PREFIX_P(opcode) (((opcode) & 0xf0) == REX_OPCODE) - -/* Indicates 64 bit operand size. */ -#define REX_W 8 -/* High extension to reg field of modrm byte. */ -#define REX_R 4 -/* High extension to SIB index field. */ -#define REX_X 2 -/* High extension to base field of modrm or SIB, or reg field of opcode. */ -#define REX_B 1 - -/* max operands per insn */ -#define MAX_OPERANDS 5 - -/* max immediates per insn (lcall, ljmp, insertq, extrq) */ -#define MAX_IMMEDIATE_OPERANDS 2 - -/* max memory refs per insn (string ops) */ -#define MAX_MEMORY_OPERANDS 2 - -/* max size of insn mnemonics. */ -#define MAX_MNEM_SIZE 20 - -/* max size of register name in insn mnemonics. */ -#define MAX_REG_NAME_SIZE 8 - -#endif /* OPCODE_I386_H */ diff --git a/include/opcode/i860.h b/include/opcode/i860.h deleted file mode 100644 index 7f4aafd..0000000 --- a/include/opcode/i860.h +++ /dev/null @@ -1,507 +0,0 @@ -/* Table of opcodes for the i860. - Copyright 1989, 1991, 2000, 2002, 2003, 2010 - Free Software Foundation, Inc. - - This file is part of GAS, the GNU Assembler, and GDB, the GNU disassembler. - - GAS/GDB is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3, or (at your option) - any later version. - - GAS/GDB is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with GAS or GDB; see the file COPYING3. If not, write to - the Free Software Foundation, 51 Franklin Street - Fifth Floor, - Boston, MA 02110-1301, USA. */ - -/* Structure of an opcode table entry. */ -struct i860_opcode -{ - /* The opcode name. */ - const char *name; - - /* Bits that must be set. */ - unsigned long match; - - /* Bits that must not be set. */ - unsigned long lose; - - const char *args; - - /* Nonzero if this is a possible expand-instruction. */ - char expand; -}; - - -enum expand_type -{ - E_MOV = 1, E_ADDR, E_U32, E_AND, E_S32, E_DELAY, XP_ONLY -}; - - -/* All i860 opcodes are 32 bits, except for the pseudo-instructions - and the operations utilizing a 32-bit address expression, an - unsigned 32-bit constant, or a signed 32-bit constant. - These opcodes are expanded into a two-instruction sequence for - any situation where the immediate operand does not fit in 32 bits. - In the case of the add and subtract operations the expansion is - to a three-instruction sequence (ex: orh, or, adds). In cases - where the address is to be relocated, the instruction is - expanded to handle the worse case, this could be optimized at - the final link if the actual address were known. - - The pseudoinstructions are: mov, fmov, pmov, nop, and fnop. - These instructions are implemented as a one or two instruction - sequence of other operations. - - The match component is a mask saying which bits must match a - particular opcode in order for an instruction to be an instance - of that opcode. - - The args component is a string containing one character - for each operand of the instruction. - -Kinds of operands: - # Number used by optimizer. It is ignored. - 1 src1 integer register. - 2 src2 integer register. - d dest register. - c ctrlreg control register. - i 16 bit immediate. - I 16 bit immediate, aligned 2^0. (ld.b) - J 16 bit immediate, aligned 2^1. (ld.s) - K 16 bit immediate, aligned 2^2. (ld.l, {p}fld.l, fst.l) - L 16 bit immediate, aligned 2^3. ({p}fld.d, fst.d) - M 16 bit immediate, aligned 2^4. ({p}fld.q, fst.q) - 5 5 bit immediate. - l lbroff 26 bit PC relative immediate. - r sbroff 16 bit PC relative immediate. - s split 16 bit immediate. - S split 16 bit immediate, aligned 2^0. (st.b) - T split 16 bit immediate, aligned 2^1. (st.s) - U split 16 bit immediate, aligned 2^2. (st.l) - e src1 floating point register. - f src2 floating point register. - g dest floating point register. */ - - -/* The order of the opcodes in this table is significant. The assembler - requires that all instances of the same mnemonic must be consecutive. - If they aren't, the assembler will not function properly. - - The order of opcodes does not affect the disassembler. */ - -static const struct i860_opcode i860_opcodes[] = -{ -/* REG-Format Instructions. */ -{ "ld.c", 0x30000000, 0xcc000000, "c,d", 0 }, /* ld.c csrc2,idest */ -{ "ld.b", 0x00000000, 0xfc000000, "1(2),d", 0 }, /* ld.b isrc1(isrc2),idest */ -{ "ld.b", 0x04000000, 0xf8000000, "I(2),d", E_ADDR }, /* ld.b #const(isrc2),idest */ -{ "ld.s", 0x10000000, 0xec000001, "1(2),d", 0 }, /* ld.s isrc1(isrc2),idest */ -{ "ld.s", 0x14000000, 0xe8000001, "J(2),d", E_ADDR }, /* ld.s #const(isrc2),idest */ -{ "ld.l", 0x10000001, 0xec000000, "1(2),d", 0 }, /* ld.l isrc1(isrc2),idest */ -{ "ld.l", 0x14000001, 0xe8000000, "K(2),d", E_ADDR }, /* ld.l #const(isrc2),idest */ - -{ "st.c", 0x38000000, 0xc4000000, "1,c", 0 }, /* st.c isrc1ni,csrc2 */ -{ "st.b", 0x0c000000, 0xf0000000, "1,S(2)", E_ADDR }, /* st.b isrc1ni,#const(isrc2) */ -{ "st.s", 0x1c000000, 0xe0000001, "1,T(2)", E_ADDR }, /* st.s isrc1ni,#const(isrc2) */ -{ "st.l", 0x1c000001, 0xe0000000, "1,U(2)", E_ADDR }, /* st.l isrc1ni,#const(isrc2) */ - -{ "ixfr", 0x08000000, 0xf4000000, "1,g", 0 }, /* ixfr isrc1ni,fdest */ - -{ "fld.l", 0x20000002, 0xdc000001, "1(2),g", 0 }, /* fld.l isrc1(isrc2),fdest */ -{ "fld.l", 0x24000002, 0xd8000001, "K(2),g", E_ADDR }, /* fld.l #const(isrc2),fdest */ -{ "fld.l", 0x20000003, 0xdc000000, "1(2)++,g", 0 }, /* fld.l isrc1(isrc2)++,fdest */ -{ "fld.l", 0x24000003, 0xd8000000, "K(2)++,g", E_ADDR }, /* fld.l #const(isrc2)++,fdest */ -{ "fld.d", 0x20000000, 0xdc000007, "1(2),g", 0 }, /* fld.d isrc1(isrc2),fdest */ -{ "fld.d", 0x24000000, 0xd8000007, "L(2),g", E_ADDR }, /* fld.d #const(isrc2),fdest */ -{ "fld.d", 0x20000001, 0xdc000006, "1(2)++,g", 0 }, /* fld.d isrc1(isrc2)++,fdest */ -{ "fld.d", 0x24000001, 0xd8000006, "L(2)++,g", E_ADDR }, /* fld.d #const(isrc2)++,fdest */ -{ "fld.q", 0x20000004, 0xdc000003, "1(2),g", 0 }, /* fld.q isrc1(isrc2),fdest */ -{ "fld.q", 0x24000004, 0xd8000003, "M(2),g", E_ADDR }, /* fld.q #const(isrc2),fdest */ -{ "fld.q", 0x20000005, 0xdc000002, "1(2)++,g", 0 }, /* fld.q isrc1(isrc2)++,fdest */ -{ "fld.q", 0x24000005, 0xd8000002, "M(2)++,g", E_ADDR }, /* fld.q #const(isrc2)++,fdest */ - -{ "pfld.l", 0x60000002, 0x9c000001, "1(2),g", 0 }, /* pfld.l isrc1(isrc2),fdest */ -{ "pfld.l", 0x64000002, 0x98000001, "K(2),g", E_ADDR }, /* pfld.l #const(isrc2),fdest */ -{ "pfld.l", 0x60000003, 0x9c000000, "1(2)++,g", 0 }, /* pfld.l isrc1(isrc2)++,fdest */ -{ "pfld.l", 0x64000003, 0x98000000, "K(2)++,g", E_ADDR }, /* pfld.l #const(isrc2)++,fdest */ -{ "pfld.d", 0x60000000, 0x9c000007, "1(2),g", 0 }, /* pfld.d isrc1(isrc2),fdest */ -{ "pfld.d", 0x64000000, 0x98000007, "L(2),g", E_ADDR }, /* pfld.d #const(isrc2),fdest */ -{ "pfld.d", 0x60000001, 0x9c000006, "1(2)++,g", 0 }, /* pfld.d isrc1(isrc2)++,fdest */ -{ "pfld.d", 0x64000001, 0x98000006, "L(2)++,g", E_ADDR }, /* pfld.d #const(isrc2)++,fdest */ -{ "pfld.q", 0x60000004, 0x9c000003, "1(2),g", XP_ONLY }, /* pfld.q isrc1(isrc2),fdest */ -{ "pfld.q", 0x64000004, 0x98000003, "L(2),g", XP_ONLY }, /* pfld.q #const(isrc2),fdest */ -{ "pfld.q", 0x60000005, 0x9c000002, "1(2)++,g", XP_ONLY }, /* pfld.q isrc1(isrc2)++,fdest */ -{ "pfld.q", 0x64000005, 0x98000002, "L(2)++,g", XP_ONLY }, /* pfld.q #const(isrc2)++,fdest */ - -{ "fst.l", 0x28000002, 0xd4000001, "g,1(2)", 0 }, /* fst.l fdest,isrc1(isrc2) */ -{ "fst.l", 0x2c000002, 0xd0000001, "g,K(2)", E_ADDR }, /* fst.l fdest,#const(isrc2) */ -{ "fst.l", 0x28000003, 0xd4000000, "g,1(2)++", 0 }, /* fst.l fdest,isrc1(isrc2)++ */ -{ "fst.l", 0x2c000003, 0xd0000000, "g,K(2)++", E_ADDR }, /* fst.l fdest,#const(isrc2)++ */ -{ "fst.d", 0x28000000, 0xd4000007, "g,1(2)", 0 }, /* fst.d fdest,isrc1(isrc2) */ -{ "fst.d", 0x2c000000, 0xd0000007, "g,L(2)", E_ADDR }, /* fst.d fdest,#const(isrc2) */ -{ "fst.d", 0x28000001, 0xd4000006, "g,1(2)++", 0 }, /* fst.d fdest,isrc1(isrc2)++ */ -{ "fst.d", 0x2c000001, 0xd0000006, "g,L(2)++", E_ADDR }, /* fst.d fdest,#const(isrc2)++ */ -{ "fst.q", 0x28000004, 0xd4000003, "g,1(2)", 0 }, /* fst.d fdest,isrc1(isrc2) */ -{ "fst.q", 0x2c000004, 0xd0000003, "g,M(2)", E_ADDR }, /* fst.d fdest,#const(isrc2) */ -{ "fst.q", 0x28000005, 0xd4000002, "g,1(2)++", 0 }, /* fst.d fdest,isrc1(isrc2)++ */ -{ "fst.q", 0x2c000005, 0xd0000002, "g,M(2)++", E_ADDR }, /* fst.d fdest,#const(isrc2)++ */ - -{ "pst.d", 0x3c000000, 0xc0000007, "g,L(2)", E_ADDR }, /* pst.d fdest,#const(isrc2) */ -{ "pst.d", 0x3c000001, 0xc0000006, "g,L(2)++", E_ADDR }, /* pst.d fdest,#const(isrc2)++ */ - -{ "addu", 0x80000000, 0x7c000000, "1,2,d", 0 }, /* addu isrc1,isrc2,idest */ -{ "addu", 0x84000000, 0x78000000, "i,2,d", E_S32 }, /* addu #const,isrc2,idest */ -{ "adds", 0x90000000, 0x6c000000, "1,2,d", 0 }, /* adds isrc1,isrc2,idest */ -{ "adds", 0x94000000, 0x68000000, "i,2,d", E_S32 }, /* adds #const,isrc2,idest */ -{ "subu", 0x88000000, 0x74000000, "1,2,d", 0 }, /* subu isrc1,isrc2,idest */ -{ "subu", 0x8c000000, 0x70000000, "i,2,d", E_S32 }, /* subu #const,isrc2,idest */ -{ "subs", 0x98000000, 0x64000000, "1,2,d", 0 }, /* subs isrc1,isrc2,idest */ -{ "subs", 0x9c000000, 0x60000000, "i,2,d", E_S32 }, /* subs #const,isrc2,idest */ - -{ "shl", 0xa0000000, 0x5c000000, "1,2,d", 0 }, /* shl isrc1,isrc2,idest */ -{ "shl", 0xa4000000, 0x58000000, "i,2,d", 0 }, /* shl #const,isrc2,idest */ -{ "shr", 0xa8000000, 0x54000000, "1,2,d", 0 }, /* shr isrc1,isrc2,idest */ -{ "shr", 0xac000000, 0x50000000, "i,2,d", 0 }, /* shr #const,isrc2,idest */ -{ "shrd", 0xb0000000, 0x4c000000, "1,2,d", 0 }, /* shrd isrc1,isrc2,idest */ -{ "shra", 0xb8000000, 0x44000000, "1,2,d", 0 }, /* shra isrc1,isrc2,idest */ -{ "shra", 0xbc000000, 0x40000000, "i,2,d", 0 }, /* shra #const,isrc2,idest */ - -{ "mov", 0xa0000000, 0x5c00f800, "2,d", 0 }, /* shl r0,isrc2,idest */ -{ "mov", 0x94000000, 0x69e00000, "i,d", E_MOV }, /* adds #const,r0,idest */ -{ "nop", 0xa0000000, 0x5ffff800, "", 0 }, /* shl r0,r0,r0 */ -{ "fnop", 0xb0000000, 0x4ffff800, "", 0 }, /* shrd r0,r0,r0 */ - -{ "trap", 0x44000000, 0xb8000000, "1,2,d", 0 }, /* trap isrc1ni,isrc2,idest */ - -{ "flush", 0x34000004, 0xc81f0003, "L(2)", E_ADDR }, /* flush #const(isrc2) */ -{ "flush", 0x34000005, 0xc81f0002, "L(2)++", E_ADDR }, /* flush #const(isrc2)++ */ - -{ "and", 0xc0000000, 0x3c000000, "1,2,d", 0 }, /* and isrc1,isrc2,idest */ -{ "and", 0xc4000000, 0x38000000, "i,2,d", E_AND }, /* and #const,isrc2,idest */ -{ "andh", 0xcc000000, 0x30000000, "i,2,d", 0 }, /* andh #const,isrc2,idest */ -{ "andnot", 0xd0000000, 0x2c000000, "1,2,d", 0 }, /* andnot isrc1,isrc2,idest */ -{ "andnot", 0xd4000000, 0x28000000, "i,2,d", E_U32 }, /* andnot #const,isrc2,idest */ -{ "andnoth", 0xdc000000, 0x20000000, "i,2,d", 0 }, /* andnoth #const,isrc2,idest */ -{ "or", 0xe0000000, 0x1c000000, "1,2,d", 0 }, /* or isrc1,isrc2,idest */ -{ "or", 0xe4000000, 0x18000000, "i,2,d", E_U32 }, /* or #const,isrc2,idest */ -{ "orh", 0xec000000, 0x10000000, "i,2,d", 0 }, /* orh #const,isrc2,idest */ -{ "xor", 0xf0000000, 0x0c000000, "1,2,d", 0 }, /* xor isrc1,isrc2,idest */ -{ "xor", 0xf4000000, 0x08000000, "i,2,d", E_U32 }, /* xor #const,isrc2,idest */ -{ "xorh", 0xfc000000, 0x00000000, "i,2,d", 0 }, /* xorh #const,isrc2,idest */ - -{ "bte", 0x58000000, 0xa4000000, "1,2,r", 0 }, /* bte isrc1s,isrc2,sbroff */ -{ "bte", 0x5c000000, 0xa0000000, "5,2,r", 0 }, /* bte #const5,isrc2,sbroff */ -{ "btne", 0x50000000, 0xac000000, "1,2,r", 0 }, /* btne isrc1s,isrc2,sbroff */ -{ "btne", 0x54000000, 0xa8000000, "5,2,r", 0 }, /* btne #const5,isrc2,sbroff */ -{ "bla", 0xb4000000, 0x48000000, "1,2,r", E_DELAY }, /* bla isrc1s,isrc2,sbroff */ -{ "bri", 0x40000000, 0xbc000000, "1", E_DELAY }, /* bri isrc1ni */ - -/* Core Escape Instruction Format */ -{ "lock", 0x4c000001, 0xb000001e, "", 0 }, /* lock set BL in dirbase */ -{ "calli", 0x4c000002, 0xb000001d, "1", E_DELAY }, /* calli isrc1ni */ -{ "intovr", 0x4c000004, 0xb000001b, "", 0 }, /* intovr trap on integer overflow */ -{ "unlock", 0x4c000007, 0xb0000018, "", 0 }, /* unlock clear BL in dirbase */ -{ "ldio.l", 0x4c000408, 0xb00003f7, "2,d", XP_ONLY }, /* ldio.l isrc2,idest */ -{ "ldio.s", 0x4c000208, 0xb00005f7, "2,d", XP_ONLY }, /* ldio.s isrc2,idest */ -{ "ldio.b", 0x4c000008, 0xb00007f7, "2,d", XP_ONLY }, /* ldio.b isrc2,idest */ -{ "stio.l", 0x4c000409, 0xb00003f6, "1,2", XP_ONLY }, /* stio.l isrc1ni,isrc2 */ -{ "stio.s", 0x4c000209, 0xb00005f6, "1,2", XP_ONLY }, /* stio.s isrc1ni,isrc2 */ -{ "stio.b", 0x4c000009, 0xb00007f6, "1,2", XP_ONLY }, /* stio.b isrc1ni,isrc2 */ -{ "ldint.l", 0x4c00040a, 0xb00003f5, "2,d", XP_ONLY }, /* ldint.l isrc2,idest */ -{ "ldint.s", 0x4c00020a, 0xb00005f5, "2,d", XP_ONLY }, /* ldint.s isrc2,idest */ -{ "ldint.b", 0x4c00000a, 0xb00007f5, "2,d", XP_ONLY }, /* ldint.b isrc2,idest */ -{ "scyc.b", 0x4c00000b, 0xb00007f4, "2", XP_ONLY }, /* scyc.b isrc2 */ - -/* CTRL-Format Instructions */ -{ "br", 0x68000000, 0x94000000, "l", E_DELAY }, /* br lbroff */ -{ "call", 0x6c000000, 0x90000000, "l", E_DELAY }, /* call lbroff */ -{ "bc", 0x70000000, 0x8c000000, "l", 0 }, /* bc lbroff */ -{ "bc.t", 0x74000000, 0x88000000, "l", E_DELAY }, /* bc.t lbroff */ -{ "bnc", 0x78000000, 0x84000000, "l", 0 }, /* bnc lbroff */ -{ "bnc.t", 0x7c000000, 0x80000000, "l", E_DELAY }, /* bnc.t lbroff */ - -/* Floating Point Escape Instruction Format - pfam.p fsrc1,fsrc2,fdest. */ -{ "r2p1.ss", 0x48000400, 0xb40001ff, "e,f,g", 0 }, -{ "r2p1.sd", 0x48000480, 0xb400017f, "e,f,g", 0 }, -{ "r2p1.dd", 0x48000580, 0xb400007f, "e,f,g", 0 }, -{ "r2pt.ss", 0x48000401, 0xb40001fe, "e,f,g", 0 }, -{ "r2pt.sd", 0x48000481, 0xb400017e, "e,f,g", 0 }, -{ "r2pt.dd", 0x48000581, 0xb400007e, "e,f,g", 0 }, -{ "r2ap1.ss", 0x48000402, 0xb40001fd, "e,f,g", 0 }, -{ "r2ap1.sd", 0x48000482, 0xb400017d, "e,f,g", 0 }, -{ "r2ap1.dd", 0x48000582, 0xb400007d, "e,f,g", 0 }, -{ "r2apt.ss", 0x48000403, 0xb40001fc, "e,f,g", 0 }, -{ "r2apt.sd", 0x48000483, 0xb400017c, "e,f,g", 0 }, -{ "r2apt.dd", 0x48000583, 0xb400007c, "e,f,g", 0 }, -{ "i2p1.ss", 0x48000404, 0xb40001fb, "e,f,g", 0 }, -{ "i2p1.sd", 0x48000484, 0xb400017b, "e,f,g", 0 }, -{ "i2p1.dd", 0x48000584, 0xb400007b, "e,f,g", 0 }, -{ "i2pt.ss", 0x48000405, 0xb40001fa, "e,f,g", 0 }, -{ "i2pt.sd", 0x48000485, 0xb400017a, "e,f,g", 0 }, -{ "i2pt.dd", 0x48000585, 0xb400007a, "e,f,g", 0 }, -{ "i2ap1.ss", 0x48000406, 0xb40001f9, "e,f,g", 0 }, -{ "i2ap1.sd", 0x48000486, 0xb4000179, "e,f,g", 0 }, -{ "i2ap1.dd", 0x48000586, 0xb4000079, "e,f,g", 0 }, -{ "i2apt.ss", 0x48000407, 0xb40001f8, "e,f,g", 0 }, -{ "i2apt.sd", 0x48000487, 0xb4000178, "e,f,g", 0 }, -{ "i2apt.dd", 0x48000587, 0xb4000078, "e,f,g", 0 }, -{ "rat1p2.ss", 0x48000408, 0xb40001f7, "e,f,g", 0 }, -{ "rat1p2.sd", 0x48000488, 0xb4000177, "e,f,g", 0 }, -{ "rat1p2.dd", 0x48000588, 0xb4000077, "e,f,g", 0 }, -{ "m12apm.ss", 0x48000409, 0xb40001f6, "e,f,g", 0 }, -{ "m12apm.sd", 0x48000489, 0xb4000176, "e,f,g", 0 }, -{ "m12apm.dd", 0x48000589, 0xb4000076, "e,f,g", 0 }, -{ "ra1p2.ss", 0x4800040a, 0xb40001f5, "e,f,g", 0 }, -{ "ra1p2.sd", 0x4800048a, 0xb4000175, "e,f,g", 0 }, -{ "ra1p2.dd", 0x4800058a, 0xb4000075, "e,f,g", 0 }, -{ "m12ttpa.ss", 0x4800040b, 0xb40001f4, "e,f,g", 0 }, -{ "m12ttpa.sd", 0x4800048b, 0xb4000174, "e,f,g", 0 }, -{ "m12ttpa.dd", 0x4800058b, 0xb4000074, "e,f,g", 0 }, -{ "iat1p2.ss", 0x4800040c, 0xb40001f3, "e,f,g", 0 }, -{ "iat1p2.sd", 0x4800048c, 0xb4000173, "e,f,g", 0 }, -{ "iat1p2.dd", 0x4800058c, 0xb4000073, "e,f,g", 0 }, -{ "m12tpm.ss", 0x4800040d, 0xb40001f2, "e,f,g", 0 }, -{ "m12tpm.sd", 0x4800048d, 0xb4000172, "e,f,g", 0 }, -{ "m12tpm.dd", 0x4800058d, 0xb4000072, "e,f,g", 0 }, -{ "ia1p2.ss", 0x4800040e, 0xb40001f1, "e,f,g", 0 }, -{ "ia1p2.sd", 0x4800048e, 0xb4000171, "e,f,g", 0 }, -{ "ia1p2.dd", 0x4800058e, 0xb4000071, "e,f,g", 0 }, -{ "m12tpa.ss", 0x4800040f, 0xb40001f0, "e,f,g", 0 }, -{ "m12tpa.sd", 0x4800048f, 0xb4000170, "e,f,g", 0 }, -{ "m12tpa.dd", 0x4800058f, 0xb4000070, "e,f,g", 0 }, - -/* Floating Point Escape Instruction Format - pfsm.p fsrc1,fsrc2,fdest. */ -{ "r2s1.ss", 0x48000410, 0xb40001ef, "e,f,g", 0 }, -{ "r2s1.sd", 0x48000490, 0xb400016f, "e,f,g", 0 }, -{ "r2s1.dd", 0x48000590, 0xb400006f, "e,f,g", 0 }, -{ "r2st.ss", 0x48000411, 0xb40001ee, "e,f,g", 0 }, -{ "r2st.sd", 0x48000491, 0xb400016e, "e,f,g", 0 }, -{ "r2st.dd", 0x48000591, 0xb400006e, "e,f,g", 0 }, -{ "r2as1.ss", 0x48000412, 0xb40001ed, "e,f,g", 0 }, -{ "r2as1.sd", 0x48000492, 0xb400016d, "e,f,g", 0 }, -{ "r2as1.dd", 0x48000592, 0xb400006d, "e,f,g", 0 }, -{ "r2ast.ss", 0x48000413, 0xb40001ec, "e,f,g", 0 }, -{ "r2ast.sd", 0x48000493, 0xb400016c, "e,f,g", 0 }, -{ "r2ast.dd", 0x48000593, 0xb400006c, "e,f,g", 0 }, -{ "i2s1.ss", 0x48000414, 0xb40001eb, "e,f,g", 0 }, -{ "i2s1.sd", 0x48000494, 0xb400016b, "e,f,g", 0 }, -{ "i2s1.dd", 0x48000594, 0xb400006b, "e,f,g", 0 }, -{ "i2st.ss", 0x48000415, 0xb40001ea, "e,f,g", 0 }, -{ "i2st.sd", 0x48000495, 0xb400016a, "e,f,g", 0 }, -{ "i2st.dd", 0x48000595, 0xb400006a, "e,f,g", 0 }, -{ "i2as1.ss", 0x48000416, 0xb40001e9, "e,f,g", 0 }, -{ "i2as1.sd", 0x48000496, 0xb4000169, "e,f,g", 0 }, -{ "i2as1.dd", 0x48000596, 0xb4000069, "e,f,g", 0 }, -{ "i2ast.ss", 0x48000417, 0xb40001e8, "e,f,g", 0 }, -{ "i2ast.sd", 0x48000497, 0xb4000168, "e,f,g", 0 }, -{ "i2ast.dd", 0x48000597, 0xb4000068, "e,f,g", 0 }, -{ "rat1s2.ss", 0x48000418, 0xb40001e7, "e,f,g", 0 }, -{ "rat1s2.sd", 0x48000498, 0xb4000167, "e,f,g", 0 }, -{ "rat1s2.dd", 0x48000598, 0xb4000067, "e,f,g", 0 }, -{ "m12asm.ss", 0x48000419, 0xb40001e6, "e,f,g", 0 }, -{ "m12asm.sd", 0x48000499, 0xb4000166, "e,f,g", 0 }, -{ "m12asm.dd", 0x48000599, 0xb4000066, "e,f,g", 0 }, -{ "ra1s2.ss", 0x4800041a, 0xb40001e5, "e,f,g", 0 }, -{ "ra1s2.sd", 0x4800049a, 0xb4000165, "e,f,g", 0 }, -{ "ra1s2.dd", 0x4800059a, 0xb4000065, "e,f,g", 0 }, -{ "m12ttsa.ss", 0x4800041b, 0xb40001e4, "e,f,g", 0 }, -{ "m12ttsa.sd", 0x4800049b, 0xb4000164, "e,f,g", 0 }, -{ "m12ttsa.dd", 0x4800059b, 0xb4000064, "e,f,g", 0 }, -{ "iat1s2.ss", 0x4800041c, 0xb40001e3, "e,f,g", 0 }, -{ "iat1s2.sd", 0x4800049c, 0xb4000163, "e,f,g", 0 }, -{ "iat1s2.dd", 0x4800059c, 0xb4000063, "e,f,g", 0 }, -{ "m12tsm.ss", 0x4800041d, 0xb40001e2, "e,f,g", 0 }, -{ "m12tsm.sd", 0x4800049d, 0xb4000162, "e,f,g", 0 }, -{ "m12tsm.dd", 0x4800059d, 0xb4000062, "e,f,g", 0 }, -{ "ia1s2.ss", 0x4800041e, 0xb40001e1, "e,f,g", 0 }, -{ "ia1s2.sd", 0x4800049e, 0xb4000161, "e,f,g", 0 }, -{ "ia1s2.dd", 0x4800059e, 0xb4000061, "e,f,g", 0 }, -{ "m12tsa.ss", 0x4800041f, 0xb40001e0, "e,f,g", 0 }, -{ "m12tsa.sd", 0x4800049f, 0xb4000160, "e,f,g", 0 }, -{ "m12tsa.dd", 0x4800059f, 0xb4000060, "e,f,g", 0 }, - -/* Floating Point Escape Instruction Format - pfmam.p fsrc1,fsrc2,fdest. */ -{ "mr2p1.ss", 0x48000000, 0xb40005ff, "e,f,g", 0 }, -{ "mr2p1.sd", 0x48000080, 0xb400057f, "e,f,g", 0 }, -{ "mr2p1.dd", 0x48000180, 0xb400047f, "e,f,g", 0 }, -{ "mr2pt.ss", 0x48000001, 0xb40005fe, "e,f,g", 0 }, -{ "mr2pt.sd", 0x48000081, 0xb400057e, "e,f,g", 0 }, -{ "mr2pt.dd", 0x48000181, 0xb400047e, "e,f,g", 0 }, -{ "mr2mp1.ss", 0x48000002, 0xb40005fd, "e,f,g", 0 }, -{ "mr2mp1.sd", 0x48000082, 0xb400057d, "e,f,g", 0 }, -{ "mr2mp1.dd", 0x48000182, 0xb400047d, "e,f,g", 0 }, -{ "mr2mpt.ss", 0x48000003, 0xb40005fc, "e,f,g", 0 }, -{ "mr2mpt.sd", 0x48000083, 0xb400057c, "e,f,g", 0 }, -{ "mr2mpt.dd", 0x48000183, 0xb400047c, "e,f,g", 0 }, -{ "mi2p1.ss", 0x48000004, 0xb40005fb, "e,f,g", 0 }, -{ "mi2p1.sd", 0x48000084, 0xb400057b, "e,f,g", 0 }, -{ "mi2p1.dd", 0x48000184, 0xb400047b, "e,f,g", 0 }, -{ "mi2pt.ss", 0x48000005, 0xb40005fa, "e,f,g", 0 }, -{ "mi2pt.sd", 0x48000085, 0xb400057a, "e,f,g", 0 }, -{ "mi2pt.dd", 0x48000185, 0xb400047a, "e,f,g", 0 }, -{ "mi2mp1.ss", 0x48000006, 0xb40005f9, "e,f,g", 0 }, -{ "mi2mp1.sd", 0x48000086, 0xb4000579, "e,f,g", 0 }, -{ "mi2mp1.dd", 0x48000186, 0xb4000479, "e,f,g", 0 }, -{ "mi2mpt.ss", 0x48000007, 0xb40005f8, "e,f,g", 0 }, -{ "mi2mpt.sd", 0x48000087, 0xb4000578, "e,f,g", 0 }, -{ "mi2mpt.dd", 0x48000187, 0xb4000478, "e,f,g", 0 }, -{ "mrmt1p2.ss", 0x48000008, 0xb40005f7, "e,f,g", 0 }, -{ "mrmt1p2.sd", 0x48000088, 0xb4000577, "e,f,g", 0 }, -{ "mrmt1p2.dd", 0x48000188, 0xb4000477, "e,f,g", 0 }, -{ "mm12mpm.ss", 0x48000009, 0xb40005f6, "e,f,g", 0 }, -{ "mm12mpm.sd", 0x48000089, 0xb4000576, "e,f,g", 0 }, -{ "mm12mpm.dd", 0x48000189, 0xb4000476, "e,f,g", 0 }, -{ "mrm1p2.ss", 0x4800000a, 0xb40005f5, "e,f,g", 0 }, -{ "mrm1p2.sd", 0x4800008a, 0xb4000575, "e,f,g", 0 }, -{ "mrm1p2.dd", 0x4800018a, 0xb4000475, "e,f,g", 0 }, -{ "mm12ttpm.ss",0x4800000b, 0xb40005f4, "e,f,g", 0 }, -{ "mm12ttpm.sd",0x4800008b, 0xb4000574, "e,f,g", 0 }, -{ "mm12ttpm.dd",0x4800018b, 0xb4000474, "e,f,g", 0 }, -{ "mimt1p2.ss", 0x4800000c, 0xb40005f3, "e,f,g", 0 }, -{ "mimt1p2.sd", 0x4800008c, 0xb4000573, "e,f,g", 0 }, -{ "mimt1p2.dd", 0x4800018c, 0xb4000473, "e,f,g", 0 }, -{ "mm12tpm.ss", 0x4800000d, 0xb40005f2, "e,f,g", 0 }, -{ "mm12tpm.sd", 0x4800008d, 0xb4000572, "e,f,g", 0 }, -{ "mm12tpm.dd", 0x4800018d, 0xb4000472, "e,f,g", 0 }, -{ "mim1p2.ss", 0x4800000e, 0xb40005f1, "e,f,g", 0 }, -{ "mim1p2.sd", 0x4800008e, 0xb4000571, "e,f,g", 0 }, -{ "mim1p2.dd", 0x4800018e, 0xb4000471, "e,f,g", 0 }, - -/* Floating Point Escape Instruction Format - pfmsm.p fsrc1,fsrc2,fdest. */ -{ "mr2s1.ss", 0x48000010, 0xb40005ef, "e,f,g", 0 }, -{ "mr2s1.sd", 0x48000090, 0xb400056f, "e,f,g", 0 }, -{ "mr2s1.dd", 0x48000190, 0xb400046f, "e,f,g", 0 }, -{ "mr2st.ss", 0x48000011, 0xb40005ee, "e,f,g", 0 }, -{ "mr2st.sd", 0x48000091, 0xb400056e, "e,f,g", 0 }, -{ "mr2st.dd", 0x48000191, 0xb400046e, "e,f,g", 0 }, -{ "mr2ms1.ss", 0x48000012, 0xb40005ed, "e,f,g", 0 }, -{ "mr2ms1.sd", 0x48000092, 0xb400056d, "e,f,g", 0 }, -{ "mr2ms1.dd", 0x48000192, 0xb400046d, "e,f,g", 0 }, -{ "mr2mst.ss", 0x48000013, 0xb40005ec, "e,f,g", 0 }, -{ "mr2mst.sd", 0x48000093, 0xb400056c, "e,f,g", 0 }, -{ "mr2mst.dd", 0x48000193, 0xb400046c, "e,f,g", 0 }, -{ "mi2s1.ss", 0x48000014, 0xb40005eb, "e,f,g", 0 }, -{ "mi2s1.sd", 0x48000094, 0xb400056b, "e,f,g", 0 }, -{ "mi2s1.dd", 0x48000194, 0xb400046b, "e,f,g", 0 }, -{ "mi2st.ss", 0x48000015, 0xb40005ea, "e,f,g", 0 }, -{ "mi2st.sd", 0x48000095, 0xb400056a, "e,f,g", 0 }, -{ "mi2st.dd", 0x48000195, 0xb400046a, "e,f,g", 0 }, -{ "mi2ms1.ss", 0x48000016, 0xb40005e9, "e,f,g", 0 }, -{ "mi2ms1.sd", 0x48000096, 0xb4000569, "e,f,g", 0 }, -{ "mi2ms1.dd", 0x48000196, 0xb4000469, "e,f,g", 0 }, -{ "mi2mst.ss", 0x48000017, 0xb40005e8, "e,f,g", 0 }, -{ "mi2mst.sd", 0x48000097, 0xb4000568, "e,f,g", 0 }, -{ "mi2mst.dd", 0x48000197, 0xb4000468, "e,f,g", 0 }, -{ "mrmt1s2.ss", 0x48000018, 0xb40005e7, "e,f,g", 0 }, -{ "mrmt1s2.sd", 0x48000098, 0xb4000567, "e,f,g", 0 }, -{ "mrmt1s2.dd", 0x48000198, 0xb4000467, "e,f,g", 0 }, -{ "mm12msm.ss", 0x48000019, 0xb40005e6, "e,f,g", 0 }, -{ "mm12msm.sd", 0x48000099, 0xb4000566, "e,f,g", 0 }, -{ "mm12msm.dd", 0x48000199, 0xb4000466, "e,f,g", 0 }, -{ "mrm1s2.ss", 0x4800001a, 0xb40005e5, "e,f,g", 0 }, -{ "mrm1s2.sd", 0x4800009a, 0xb4000565, "e,f,g", 0 }, -{ "mrm1s2.dd", 0x4800019a, 0xb4000465, "e,f,g", 0 }, -{ "mm12ttsm.ss",0x4800001b, 0xb40005e4, "e,f,g", 0 }, -{ "mm12ttsm.sd",0x4800009b, 0xb4000564, "e,f,g", 0 }, -{ "mm12ttsm.dd",0x4800019b, 0xb4000464, "e,f,g", 0 }, -{ "mimt1s2.ss", 0x4800001c, 0xb40005e3, "e,f,g", 0 }, -{ "mimt1s2.sd", 0x4800009c, 0xb4000563, "e,f,g", 0 }, -{ "mimt1s2.dd", 0x4800019c, 0xb4000463, "e,f,g", 0 }, -{ "mm12tsm.ss", 0x4800001d, 0xb40005e2, "e,f,g", 0 }, -{ "mm12tsm.sd", 0x4800009d, 0xb4000562, "e,f,g", 0 }, -{ "mm12tsm.dd", 0x4800019d, 0xb4000462, "e,f,g", 0 }, -{ "mim1s2.ss", 0x4800001e, 0xb40005e1, "e,f,g", 0 }, -{ "mim1s2.sd", 0x4800009e, 0xb4000561, "e,f,g", 0 }, -{ "mim1s2.dd", 0x4800019e, 0xb4000461, "e,f,g", 0 }, - -{ "fmul.ss", 0x48000020, 0xb40005df, "e,f,g", 0 }, /* fmul.p fsrc1,fsrc2,fdest */ -{ "fmul.sd", 0x480000a0, 0xb400055f, "e,f,g", 0 }, /* fmul.p fsrc1,fsrc2,fdest */ -{ "fmul.dd", 0x480001a0, 0xb400045f, "e,f,g", 0 }, /* fmul.p fsrc1,fsrc2,fdest */ -{ "pfmul.ss", 0x48000420, 0xb40001df, "e,f,g", 0 }, /* pfmul.p fsrc1,fsrc2,fdest */ -{ "pfmul.sd", 0x480004a0, 0xb400015f, "e,f,g", 0 }, /* pfmul.p fsrc1,fsrc2,fdest */ -{ "pfmul.dd", 0x480005a0, 0xb400005f, "e,f,g", 0 }, /* pfmul.p fsrc1,fsrc2,fdest */ -{ "pfmul3.dd", 0x480005a4, 0xb400005b, "e,f,g", 0 }, /* pfmul3.p fsrc1,fsrc2,fdest */ -{ "fmlow.dd", 0x480001a1, 0xb400045e, "e,f,g", 0 }, /* fmlow.dd fsrc1,fsrc2,fdest */ -{ "frcp.ss", 0x48000022, 0xb40005dd, "f,g", 0 }, /* frcp.p fsrc2,fdest */ -{ "frcp.sd", 0x480000a2, 0xb400055d, "f,g", 0 }, /* frcp.p fsrc2,fdest */ -{ "frcp.dd", 0x480001a2, 0xb400045d, "f,g", 0 }, /* frcp.p fsrc2,fdest */ -{ "frsqr.ss", 0x48000023, 0xb40005dc, "f,g", 0 }, /* frsqr.p fsrc2,fdest */ -{ "frsqr.sd", 0x480000a3, 0xb400055c, "f,g", 0 }, /* frsqr.p fsrc2,fdest */ -{ "frsqr.dd", 0x480001a3, 0xb400045c, "f,g", 0 }, /* frsqr.p fsrc2,fdest */ -{ "fadd.ss", 0x48000030, 0xb40005cf, "e,f,g", 0 }, /* fadd.p fsrc1,fsrc2,fdest */ -{ "fadd.sd", 0x480000b0, 0xb400054f, "e,f,g", 0 }, /* fadd.p fsrc1,fsrc2,fdest */ -{ "fadd.dd", 0x480001b0, 0xb400044f, "e,f,g", 0 }, /* fadd.p fsrc1,fsrc2,fdest */ -{ "pfadd.ss", 0x48000430, 0xb40001cf, "e,f,g", 0 }, /* pfadd.p fsrc1,fsrc2,fdest */ -{ "pfadd.sd", 0x480004b0, 0xb400014f, "e,f,g", 0 }, /* pfadd.p fsrc1,fsrc2,fdest */ -{ "pfadd.dd", 0x480005b0, 0xb400004f, "e,f,g", 0 }, /* pfadd.p fsrc1,fsrc2,fdest */ -{ "fsub.ss", 0x48000031, 0xb40005ce, "e,f,g", 0 }, /* fsub.p fsrc1,fsrc2,fdest */ -{ "fsub.sd", 0x480000b1, 0xb400054e, "e,f,g", 0 }, /* fsub.p fsrc1,fsrc2,fdest */ -{ "fsub.dd", 0x480001b1, 0xb400044e, "e,f,g", 0 }, /* fsub.p fsrc1,fsrc2,fdest */ -{ "pfsub.ss", 0x48000431, 0xb40001ce, "e,f,g", 0 }, /* pfsub.p fsrc1,fsrc2,fdest */ -{ "pfsub.sd", 0x480004b1, 0xb400014e, "e,f,g", 0 }, /* pfsub.p fsrc1,fsrc2,fdest */ -{ "pfsub.dd", 0x480005b1, 0xb400004e, "e,f,g", 0 }, /* pfsub.p fsrc1,fsrc2,fdest */ -{ "fix.sd", 0x480000b2, 0xb400054d, "e,g", 0 }, /* fix.p fsrc1,fdest */ -{ "fix.dd", 0x480001b2, 0xb400044d, "e,g", 0 }, /* fix.p fsrc1,fdest */ -{ "pfix.sd", 0x480004b2, 0xb400014d, "e,g", 0 }, /* pfix.p fsrc1,fdest */ -{ "pfix.dd", 0x480005b2, 0xb400004d, "e,g", 0 }, /* pfix.p fsrc1,fdest */ -{ "famov.ss", 0x48000033, 0xb40005cc, "e,g", 0 }, /* famov.p fsrc1,fdest */ -{ "famov.ds", 0x48000133, 0xb40004cc, "e,g", 0 }, /* famov.p fsrc1,fdest */ -{ "famov.sd", 0x480000b3, 0xb400054c, "e,g", 0 }, /* famov.p fsrc1,fdest */ -{ "famov.dd", 0x480001b3, 0xb400044c, "e,g", 0 }, /* famov.p fsrc1,fdest */ -{ "pfamov.ss", 0x48000433, 0xb40001cc, "e,g", 0 }, /* pfamov.p fsrc1,fdest */ -{ "pfamov.ds", 0x48000533, 0xb40000cc, "e,g", 0 }, /* pfamov.p fsrc1,fdest */ -{ "pfamov.sd", 0x480004b3, 0xb400014c, "e,g", 0 }, /* pfamov.p fsrc1,fdest */ -{ "pfamov.dd", 0x480005b3, 0xb400004c, "e,g", 0 }, /* pfamov.p fsrc1,fdest */ -/* Opcode pfgt has R bit cleared; pfle has R bit set. */ -{ "pfgt.ss", 0x48000434, 0xb40001cb, "e,f,g", 0 }, /* pfgt.p fsrc1,fsrc2,fdest */ -{ "pfgt.dd", 0x48000534, 0xb40000cb, "e,f,g", 0 }, /* pfgt.p fsrc1,fsrc2,fdest */ -/* Opcode pfgt has R bit cleared; pfle has R bit set. */ -{ "pfle.ss", 0x480004b4, 0xb400014b, "e,f,g", 0 }, /* pfle.p fsrc1,fsrc2,fdest */ -{ "pfle.dd", 0x480005b4, 0xb400004b, "e,f,g", 0 }, /* pfle.p fsrc1,fsrc2,fdest */ -{ "pfeq.ss", 0x48000435, 0xb40001ca, "e,f,g", 0 }, /* pfeq.p fsrc1,fsrc2,fdest */ -{ "pfeq.dd", 0x48000535, 0xb40000ca, "e,f,g", 0 }, /* pfeq.p fsrc1,fsrc2,fdest */ -{ "ftrunc.sd", 0x480000ba, 0xb4000545, "e,g", 0 }, /* ftrunc.p fsrc1,fdest */ -{ "ftrunc.dd", 0x480001ba, 0xb4000445, "e,g", 0 }, /* ftrunc.p fsrc1,fdest */ -{ "pftrunc.sd", 0x480004ba, 0xb4000145, "e,g", 0 }, /* pftrunc.p fsrc1,fdest */ -{ "pftrunc.dd", 0x480005ba, 0xb4000045, "e,g", 0 }, /* pftrunc.p fsrc1,fdest */ -{ "fxfr", 0x48000040, 0xb40005bf, "e,d", 0 }, /* fxfr fsrc1,idest */ -{ "fiadd.ss", 0x48000049, 0xb40005b6, "e,f,g", 0 }, /* fiadd.w fsrc1,fsrc2,fdest */ -{ "fiadd.dd", 0x480001c9, 0xb4000436, "e,f,g", 0 }, /* fiadd.w fsrc1,fsrc2,fdest */ -{ "pfiadd.ss", 0x48000449, 0xb40001b6, "e,f,g", 0 }, /* pfiadd.w fsrc1,fsrc2,fdest */ -{ "pfiadd.dd", 0x480005c9, 0xb4000036, "e,f,g", 0 }, /* pfiadd.w fsrc1,fsrc2,fdest */ -{ "fisub.ss", 0x4800004d, 0xb40005b2, "e,f,g", 0 }, /* fisub.w fsrc1,fsrc2,fdest */ -{ "fisub.dd", 0x480001cd, 0xb4000432, "e,f,g", 0 }, /* fisub.w fsrc1,fsrc2,fdest */ -{ "pfisub.ss", 0x4800044d, 0xb40001b2, "e,f,g", 0 }, /* pfisub.w fsrc1,fsrc2,fdest */ -{ "pfisub.dd", 0x480005cd, 0xb4000032, "e,f,g", 0 }, /* pfisub.w fsrc1,fsrc2,fdest */ -{ "fzchkl", 0x480001d7, 0xb4000428, "e,f,g", 0 }, /* fzchkl fsrc1,fsrc2,fdest */ -{ "pfzchkl", 0x480005d7, 0xb4000028, "e,f,g", 0 }, /* pfzchkl fsrc1,fsrc2,fdest */ -{ "fzchks", 0x480001df, 0xb4000420, "e,f,g", 0 }, /* fzchks fsrc1,fsrc2,fdest */ -{ "pfzchks", 0x480005df, 0xb4000020, "e,f,g", 0 }, /* pfzchks fsrc1,fsrc2,fdest */ -{ "faddp", 0x480001d0, 0xb400042f, "e,f,g", 0 }, /* faddp fsrc1,fsrc2,fdest */ -{ "pfaddp", 0x480005d0, 0xb400002f, "e,f,g", 0 }, /* pfaddp fsrc1,fsrc2,fdest */ -{ "faddz", 0x480001d1, 0xb400042e, "e,f,g", 0 }, /* faddz fsrc1,fsrc2,fdest */ -{ "pfaddz", 0x480005d1, 0xb400002e, "e,f,g", 0 }, /* pfaddz fsrc1,fsrc2,fdest */ -{ "form", 0x480001da, 0xb4000425, "e,g", 0 }, /* form fsrc1,fdest */ -{ "pform", 0x480005da, 0xb4000025, "e,g", 0 }, /* pform fsrc1,fdest */ - -/* Floating point pseudo-instructions. */ -{ "fmov.ss", 0x48000049, 0xb7e005b6, "e,g", 0 }, /* fiadd.ss fsrc1,f0,fdest */ -{ "fmov.dd", 0x480001c9, 0xb7e00436, "e,g", 0 }, /* fiadd.dd fsrc1,f0,fdest */ -{ "fmov.sd", 0x480000b3, 0xb400054c, "e,g", 0 }, /* famov.sd fsrc1,fdest */ -{ "fmov.ds", 0x48000133, 0xb40004cc, "e,g", 0 }, /* famov.ds fsrc1,fdest */ -{ "pfmov.ds", 0x48000533, 0xb40000cc, "e,g", 0 }, /* pfamov.ds fsrc1,fdest */ -{ "pfmov.dd", 0x480005c9, 0xb7e00036, "e,g", 0 }, /* pfiadd.dd fsrc1,f0,fdest */ -{ 0, 0, 0, 0, 0 }, - -}; - -#define NUMOPCODES ((sizeof i860_opcodes)/(sizeof i860_opcodes[0])) - - diff --git a/include/opcode/i960.h b/include/opcode/i960.h deleted file mode 100644 index 7b8e1f5..0000000 --- a/include/opcode/i960.h +++ /dev/null @@ -1,525 +0,0 @@ -/* Basic 80960 instruction formats. - - Copyright 2001-2013 Free Software Foundation, Inc. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3, or (at your option) - any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, - Boston, MA 02110-1301, USA. */ - -/* The 'COJ' instructions are actually COBR instructions with the 'b' in - the mnemonic replaced by a 'j'; they are ALWAYS "de-optimized" if - necessary: if the displacement will not fit in 13 bits, the assembler will - replace them with the corresponding compare and branch instructions. - - All of the 'MEMn' instructions are the same format; the 'n' in the name - indicates the default index scale factor (the size of the datum operated on). - - The FBRA formats are not actually an instruction format. They are the - "convenience directives" for branching on floating-point comparisons, - each of which generates 2 instructions (a 'bno' and one other branch). - - The CALLJ format is not actually an instruction format. It indicates that - the instruction generated (a CTRL-format 'call') should have its relocation - specially flagged for link-time replacement with a 'bal' or 'calls' if - appropriate. */ - -#define CTRL 0 -#define COBR 1 -#define COJ 2 -#define REG 3 -#define MEM1 4 -#define MEM2 5 -#define MEM4 6 -#define MEM8 7 -#define MEM12 8 -#define MEM16 9 -#define FBRA 10 -#define CALLJ 11 - -/* Masks for the mode bits in REG format instructions */ -#define M1 0x0800 -#define M2 0x1000 -#define M3 0x2000 - -/* Generate the 12-bit opcode for a REG format instruction by placing the - * high 8 bits in instruction bits 24-31, the low 4 bits in instruction bits - * 7-10. - */ - -#define REG_OPC(opc) ((opc & 0xff0) << 20) | ((opc & 0xf) << 7) - -/* Generate a template for a REG format instruction: place the opcode bits - * in the appropriate fields and OR in mode bits for the operands that will not - * be used. I.e., - * set m1=1, if src1 will not be used - * set m2=1, if src2 will not be used - * set m3=1, if dst will not be used - * - * Setting the "unused" mode bits to 1 speeds up instruction execution(!). - * The information is also useful to us because some 1-operand REG instructions - * use the src1 field, others the dst field; and some 2-operand REG instructions - * use src1/src2, others src1/dst. The set mode bits enable us to distinguish. - */ -#define R_0(opc) ( REG_OPC(opc) | M1 | M2 | M3 ) /* No operands */ -#define R_1(opc) ( REG_OPC(opc) | M2 | M3 ) /* 1 operand: src1 */ -#define R_1D(opc) ( REG_OPC(opc) | M1 | M2 ) /* 1 operand: dst */ -#define R_2(opc) ( REG_OPC(opc) | M3 ) /* 2 ops: src1/src2 */ -#define R_2D(opc) ( REG_OPC(opc) | M2 ) /* 2 ops: src1/dst */ -#define R_3(opc) ( REG_OPC(opc) ) /* 3 operands */ - -/* DESCRIPTOR BYTES FOR REGISTER OPERANDS - * - * Interpret names as follows: - * R: global or local register only - * RS: global, local, or (if target allows) special-function register only - * RL: global or local register, or integer literal - * RSL: global, local, or (if target allows) special-function register; - * or integer literal - * F: global, local, or floating-point register - * FL: global, local, or floating-point register; or literal (including - * floating point) - * - * A number appended to a name indicates that registers must be aligned, - * as follows: - * 2: register number must be multiple of 2 - * 4: register number must be multiple of 4 - */ - -#define SFR 0x10 /* Mask for the "sfr-OK" bit */ -#define LIT 0x08 /* Mask for the "literal-OK" bit */ -#define FP 0x04 /* Mask for "floating-point-OK" bit */ - -/* This macro ors the bits together. Note that 'align' is a mask - * for the low 0, 1, or 2 bits of the register number, as appropriate. - */ -#define OP(align,lit,fp,sfr) ( align | lit | fp | sfr ) - -#define R OP( 0, 0, 0, 0 ) -#define RS OP( 0, 0, 0, SFR ) -#define RL OP( 0, LIT, 0, 0 ) -#define RSL OP( 0, LIT, 0, SFR ) -#define F OP( 0, 0, FP, 0 ) -#define FL OP( 0, LIT, FP, 0 ) -#define R2 OP( 1, 0, 0, 0 ) -#define RL2 OP( 1, LIT, 0, 0 ) -#define F2 OP( 1, 0, FP, 0 ) -#define FL2 OP( 1, LIT, FP, 0 ) -#define R4 OP( 3, 0, 0, 0 ) -#define RL4 OP( 3, LIT, 0, 0 ) -#define F4 OP( 3, 0, FP, 0 ) -#define FL4 OP( 3, LIT, FP, 0 ) - -#define M 0x7f /* Memory operand (MEMA & MEMB format instructions) */ - -/* Macros to extract info from the register operand descriptor byte 'od'. - */ -#define SFR_OK(od) (od & SFR) /* TRUE if sfr operand allowed */ -#define LIT_OK(od) (od & LIT) /* TRUE if literal operand allowed */ -#define FP_OK(od) (od & FP) /* TRUE if floating-point op allowed */ -#define REG_ALIGN(od,n) ((od & 0x3 & n) == 0) - /* TRUE if reg #n is properly aligned */ -#define MEMOP(od) (od == M) /* TRUE if operand is a memory operand*/ - -/* Description of a single i80960 instruction */ -struct i960_opcode { - long opcode; /* 32 bits, constant fields filled in, rest zeroed */ - char *name; /* Assembler mnemonic */ - short iclass; /* Class: see #defines below */ - char format; /* REG, COBR, CTRL, MEMn, COJ, FBRA, or CALLJ */ - char num_ops; /* Number of operands */ - char operand[3];/* Operand descriptors; same order as assembler instr */ -}; - -/* Classes of 960 instructions: - * - each instruction falls into one class. - * - each target architecture supports one or more classes. - * - * EACH CONSTANT MUST CONTAIN 1 AND ONLY 1 SET BIT!: see targ_has_iclass(). - */ -#define I_BASE 0x01 /* 80960 base instruction set */ -#define I_CX 0x02 /* 80960Cx instruction */ -#define I_DEC 0x04 /* Decimal instruction */ -#define I_FP 0x08 /* Floating point instruction */ -#define I_KX 0x10 /* 80960Kx instruction */ -#define I_MIL 0x20 /* Military instruction */ -#define I_CASIM 0x40 /* CA simulator instruction */ -#define I_CX2 0x80 /* Cx/Jx/Hx instructions */ -#define I_JX 0x100 /* Jx/Hx instruction */ -#define I_HX 0x200 /* Hx instructions */ - -/****************************************************************************** - * - * TABLE OF i960 INSTRUCTION DESCRIPTIONS - * - ******************************************************************************/ - -const struct i960_opcode i960_opcodes[] = { - - /* if a CTRL instruction has an operand, it's always a displacement */ - - /* callj default=='call' */ - { 0x09000000, "callj", I_BASE, CALLJ, 1, { 0, 0, 0 } }, - { 0x08000000, "b", I_BASE, CTRL, 1, { 0, 0, 0 } }, - { 0x09000000, "call", I_BASE, CTRL, 1, { 0, 0, 0 } }, - { 0x0a000000, "ret", I_BASE, CTRL, 0, { 0, 0, 0 } }, - { 0x0b000000, "bal", I_BASE, CTRL, 1, { 0, 0, 0 } }, - { 0x10000000, "bno", I_BASE, CTRL, 1, { 0, 0, 0 } }, - /* bf same as bno */ - { 0x10000000, "bf", I_BASE, CTRL, 1, { 0, 0, 0 } }, - /* bru same as bno */ - { 0x10000000, "bru", I_BASE, CTRL, 1, { 0, 0, 0 } }, - { 0x11000000, "bg", I_BASE, CTRL, 1, { 0, 0, 0 } }, - /* brg same as bg */ - { 0x11000000, "brg", I_BASE, CTRL, 1, { 0, 0, 0 } }, - { 0x12000000, "be", I_BASE, CTRL, 1, { 0, 0, 0 } }, - /* bre same as be */ - { 0x12000000, "bre", I_BASE, CTRL, 1, { 0, 0, 0 } }, - { 0x13000000, "bge", I_BASE, CTRL, 1, { 0, 0, 0 } }, - /* brge same as bge */ - { 0x13000000, "brge", I_BASE, CTRL, 1, { 0, 0, 0 } }, - { 0x14000000, "bl", I_BASE, CTRL, 1, { 0, 0, 0 } }, - /* brl same as bl */ - { 0x14000000, "brl", I_BASE, CTRL, 1, { 0, 0, 0 } }, - { 0x15000000, "bne", I_BASE, CTRL, 1, { 0, 0, 0 } }, - /* brlg same as bne */ - { 0x15000000, "brlg", I_BASE, CTRL, 1, { 0, 0, 0 } }, - { 0x16000000, "ble", I_BASE, CTRL, 1, { 0, 0, 0 } }, - /* brle same as ble */ - { 0x16000000, "brle", I_BASE, CTRL, 1, { 0, 0, 0 } }, - { 0x17000000, "bo", I_BASE, CTRL, 1, { 0, 0, 0 } }, - /* bt same as bo */ - { 0x17000000, "bt", I_BASE, CTRL, 1, { 0, 0, 0 } }, - /* bro same as bo */ - { 0x17000000, "bro", I_BASE, CTRL, 1, { 0, 0, 0 } }, - { 0x18000000, "faultno", I_BASE, CTRL, 0, { 0, 0, 0 } }, - /* faultf same as faultno */ - { 0x18000000, "faultf", I_BASE, CTRL, 0, { 0, 0, 0 } }, - { 0x19000000, "faultg", I_BASE, CTRL, 0, { 0, 0, 0 } }, - { 0x1a000000, "faulte", I_BASE, CTRL, 0, { 0, 0, 0 } }, - { 0x1b000000, "faultge", I_BASE, CTRL, 0, { 0, 0, 0 } }, - { 0x1c000000, "faultl", I_BASE, CTRL, 0, { 0, 0, 0 } }, - { 0x1d000000, "faultne", I_BASE, CTRL, 0, { 0, 0, 0 } }, - { 0x1e000000, "faultle", I_BASE, CTRL, 0, { 0, 0, 0 } }, - { 0x1f000000, "faulto", I_BASE, CTRL, 0, { 0, 0, 0 } }, - /* faultt syn for faulto */ - { 0x1f000000, "faultt", I_BASE, CTRL, 0, { 0, 0, 0 } }, - - { 0x01000000, "syscall", I_CASIM,CTRL, 0, { 0, 0, 0 } }, - - /* If a COBR (or COJ) has 3 operands, the last one is always a - * displacement and does not appear explicitly in the table. - */ - - { 0x20000000, "testno", I_BASE, COBR, 1, { R, 0, 0 } }, - { 0x21000000, "testg", I_BASE, COBR, 1, { R, 0, 0 } }, - { 0x22000000, "teste", I_BASE, COBR, 1, { R, 0, 0 } }, - { 0x23000000, "testge", I_BASE, COBR, 1, { R, 0, 0 } }, - { 0x24000000, "testl", I_BASE, COBR, 1, { R, 0, 0 } }, - { 0x25000000, "testne", I_BASE, COBR, 1, { R, 0, 0 } }, - { 0x26000000, "testle", I_BASE, COBR, 1, { R, 0, 0 } }, - { 0x27000000, "testo", I_BASE, COBR, 1, { R, 0, 0 } }, - { 0x30000000, "bbc", I_BASE, COBR, 3, { RL, RS, 0 } }, - { 0x31000000, "cmpobg", I_BASE, COBR, 3, { RL, RS, 0 } }, - { 0x32000000, "cmpobe", I_BASE, COBR, 3, { RL, RS, 0 } }, - { 0x33000000, "cmpobge", I_BASE, COBR, 3, { RL, RS, 0 } }, - { 0x34000000, "cmpobl", I_BASE, COBR, 3, { RL, RS, 0 } }, - { 0x35000000, "cmpobne", I_BASE, COBR, 3, { RL, RS, 0 } }, - { 0x36000000, "cmpoble", I_BASE, COBR, 3, { RL, RS, 0 } }, - { 0x37000000, "bbs", I_BASE, COBR, 3, { RL, RS, 0 } }, - { 0x38000000, "cmpibno", I_BASE, COBR, 3, { RL, RS, 0 } }, - { 0x39000000, "cmpibg", I_BASE, COBR, 3, { RL, RS, 0 } }, - { 0x3a000000, "cmpibe", I_BASE, COBR, 3, { RL, RS, 0 } }, - { 0x3b000000, "cmpibge", I_BASE, COBR, 3, { RL, RS, 0 } }, - { 0x3c000000, "cmpibl", I_BASE, COBR, 3, { RL, RS, 0 } }, - { 0x3d000000, "cmpibne", I_BASE, COBR, 3, { RL, RS, 0 } }, - { 0x3e000000, "cmpible", I_BASE, COBR, 3, { RL, RS, 0 } }, - { 0x3f000000, "cmpibo", I_BASE, COBR, 3, { RL, RS, 0 } }, - { 0x31000000, "cmpojg", I_BASE, COJ, 3, { RL, RS, 0 } }, - { 0x32000000, "cmpoje", I_BASE, COJ, 3, { RL, RS, 0 } }, - { 0x33000000, "cmpojge", I_BASE, COJ, 3, { RL, RS, 0 } }, - { 0x34000000, "cmpojl", I_BASE, COJ, 3, { RL, RS, 0 } }, - { 0x35000000, "cmpojne", I_BASE, COJ, 3, { RL, RS, 0 } }, - { 0x36000000, "cmpojle", I_BASE, COJ, 3, { RL, RS, 0 } }, - { 0x38000000, "cmpijno", I_BASE, COJ, 3, { RL, RS, 0 } }, - { 0x39000000, "cmpijg", I_BASE, COJ, 3, { RL, RS, 0 } }, - { 0x3a000000, "cmpije", I_BASE, COJ, 3, { RL, RS, 0 } }, - { 0x3b000000, "cmpijge", I_BASE, COJ, 3, { RL, RS, 0 } }, - { 0x3c000000, "cmpijl", I_BASE, COJ, 3, { RL, RS, 0 } }, - { 0x3d000000, "cmpijne", I_BASE, COJ, 3, { RL, RS, 0 } }, - { 0x3e000000, "cmpijle", I_BASE, COJ, 3, { RL, RS, 0 } }, - { 0x3f000000, "cmpijo", I_BASE, COJ, 3, { RL, RS, 0 } }, - - { 0x80000000, "ldob", I_BASE, MEM1, 2, { M, R, 0 } }, - { 0x82000000, "stob", I_BASE, MEM1, 2, { R, M, 0 } }, - { 0x84000000, "bx", I_BASE, MEM1, 1, { M, 0, 0 } }, - { 0x85000000, "balx", I_BASE, MEM1, 2, { M, R, 0 } }, - { 0x86000000, "callx", I_BASE, MEM1, 1, { M, 0, 0 } }, - { 0x88000000, "ldos", I_BASE, MEM2, 2, { M, R, 0 } }, - { 0x8a000000, "stos", I_BASE, MEM2, 2, { R, M, 0 } }, - { 0x8c000000, "lda", I_BASE, MEM1, 2, { M, R, 0 } }, - { 0x90000000, "ld", I_BASE, MEM4, 2, { M, R, 0 } }, - { 0x92000000, "st", I_BASE, MEM4, 2, { R, M, 0 } }, - { 0x98000000, "ldl", I_BASE, MEM8, 2, { M, R2, 0 } }, - { 0x9a000000, "stl", I_BASE, MEM8, 2, { R2, M, 0 } }, - { 0xa0000000, "ldt", I_BASE, MEM12, 2, { M, R4, 0 } }, - { 0xa2000000, "stt", I_BASE, MEM12, 2, { R4, M, 0 } }, - { 0xb0000000, "ldq", I_BASE, MEM16, 2, { M, R4, 0 } }, - { 0xb2000000, "stq", I_BASE, MEM16, 2, { R4, M, 0 } }, - { 0xc0000000, "ldib", I_BASE, MEM1, 2, { M, R, 0 } }, - { 0xc2000000, "stib", I_BASE, MEM1, 2, { R, M, 0 } }, - { 0xc8000000, "ldis", I_BASE, MEM2, 2, { M, R, 0 } }, - { 0xca000000, "stis", I_BASE, MEM2, 2, { R, M, 0 } }, - - { R_3(0x580), "notbit", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x581), "and", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x582), "andnot", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x583), "setbit", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x584), "notand", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x586), "xor", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x587), "or", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x588), "nor", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x589), "xnor", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_2D(0x58a), "not", I_BASE, REG, 2, { RSL,RS, 0 } }, - { R_3(0x58b), "ornot", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x58c), "clrbit", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x58d), "notor", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x58e), "nand", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x58f), "alterbit", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x590), "addo", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x591), "addi", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x592), "subo", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x593), "subi", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x598), "shro", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x59a), "shrdi", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x59b), "shri", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x59c), "shlo", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x59d), "rotate", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x59e), "shli", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_2(0x5a0), "cmpo", I_BASE, REG, 2, { RSL,RSL, 0 } }, - { R_2(0x5a1), "cmpi", I_BASE, REG, 2, { RSL,RSL, 0 } }, - { R_2(0x5a2), "concmpo", I_BASE, REG, 2, { RSL,RSL, 0 } }, - { R_2(0x5a3), "concmpi", I_BASE, REG, 2, { RSL,RSL, 0 } }, - { R_3(0x5a4), "cmpinco", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x5a5), "cmpinci", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x5a6), "cmpdeco", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x5a7), "cmpdeci", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_2(0x5ac), "scanbyte", I_BASE, REG, 2, { RSL,RSL, 0 } }, - { R_2(0x5ae), "chkbit", I_BASE, REG, 2, { RSL,RSL, 0 } }, - { R_3(0x5b0), "addc", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x5b2), "subc", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_2D(0x5cc), "mov", I_BASE, REG, 2, { RSL,RS, 0 } }, - { R_2D(0x5dc), "movl", I_BASE, REG, 2, { RL2,R2, 0 } }, - { R_2D(0x5ec), "movt", I_BASE, REG, 2, { RL4,R4, 0 } }, - { R_2D(0x5fc), "movq", I_BASE, REG, 2, { RL4,R4, 0 } }, - { R_3(0x610), "atmod", I_BASE, REG, 3, { RS, RSL,R } }, - { R_3(0x612), "atadd", I_BASE, REG, 3, { RS, RSL,RS } }, - { R_2D(0x640), "spanbit", I_BASE, REG, 2, { RSL,RS, 0 } }, - { R_2D(0x641), "scanbit", I_BASE, REG, 2, { RSL,RS, 0 } }, - { R_3(0x645), "modac", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x650), "modify", I_BASE, REG, 3, { RSL,RSL,R } }, - { R_3(0x651), "extract", I_BASE, REG, 3, { RSL,RSL,R } }, - { R_3(0x654), "modtc", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x655), "modpc", I_BASE, REG, 3, { RSL,RSL,R } }, - { R_1(0x660), "calls", I_BASE, REG, 1, { RSL, 0, 0 } }, - { R_0(0x66b), "mark", I_BASE, REG, 0, { 0, 0, 0 } }, - { R_0(0x66c), "fmark", I_BASE, REG, 0, { 0, 0, 0 } }, - { R_0(0x66d), "flushreg", I_BASE, REG, 0, { 0, 0, 0 } }, - { R_0(0x66f), "syncf", I_BASE, REG, 0, { 0, 0, 0 } }, - { R_3(0x670), "emul", I_BASE, REG, 3, { RSL,RSL,R2 } }, - { R_3(0x671), "ediv", I_BASE, REG, 3, { RSL,RL2,RS } }, - { R_2D(0x672), "cvtadr", I_CASIM,REG, 2, { RL, R2, 0 } }, - { R_3(0x701), "mulo", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x708), "remo", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x70b), "divo", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x741), "muli", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x748), "remi", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x749), "modi", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x74b), "divi", I_BASE, REG, 3, { RSL,RSL,RS } }, - - /* Floating-point instructions */ - - { R_2D(0x674), "cvtir", I_FP, REG, 2, { RL, F, 0 } }, - { R_2D(0x675), "cvtilr", I_FP, REG, 2, { RL, F, 0 } }, - { R_3(0x676), "scalerl", I_FP, REG, 3, { RL, FL2,F2 } }, - { R_3(0x677), "scaler", I_FP, REG, 3, { RL, FL, F } }, - { R_3(0x680), "atanr", I_FP, REG, 3, { FL, FL, F } }, - { R_3(0x681), "logepr", I_FP, REG, 3, { FL, FL, F } }, - { R_3(0x682), "logr", I_FP, REG, 3, { FL, FL, F } }, - { R_3(0x683), "remr", I_FP, REG, 3, { FL, FL, F } }, - { R_2(0x684), "cmpor", I_FP, REG, 2, { FL, FL, 0 } }, - { R_2(0x685), "cmpr", I_FP, REG, 2, { FL, FL, 0 } }, - { R_2D(0x688), "sqrtr", I_FP, REG, 2, { FL, F, 0 } }, - { R_2D(0x689), "expr", I_FP, REG, 2, { FL, F, 0 } }, - { R_2D(0x68a), "logbnr", I_FP, REG, 2, { FL, F, 0 } }, - { R_2D(0x68b), "roundr", I_FP, REG, 2, { FL, F, 0 } }, - { R_2D(0x68c), "sinr", I_FP, REG, 2, { FL, F, 0 } }, - { R_2D(0x68d), "cosr", I_FP, REG, 2, { FL, F, 0 } }, - { R_2D(0x68e), "tanr", I_FP, REG, 2, { FL, F, 0 } }, - { R_1(0x68f), "classr", I_FP, REG, 1, { FL, 0, 0 } }, - { R_3(0x690), "atanrl", I_FP, REG, 3, { FL2,FL2,F2 } }, - { R_3(0x691), "logeprl", I_FP, REG, 3, { FL2,FL2,F2 } }, - { R_3(0x692), "logrl", I_FP, REG, 3, { FL2,FL2,F2 } }, - { R_3(0x693), "remrl", I_FP, REG, 3, { FL2,FL2,F2 } }, - { R_2(0x694), "cmporl", I_FP, REG, 2, { FL2,FL2, 0 } }, - { R_2(0x695), "cmprl", I_FP, REG, 2, { FL2,FL2, 0 } }, - { R_2D(0x698), "sqrtrl", I_FP, REG, 2, { FL2,F2, 0 } }, - { R_2D(0x699), "exprl", I_FP, REG, 2, { FL2,F2, 0 } }, - { R_2D(0x69a), "logbnrl", I_FP, REG, 2, { FL2,F2, 0 } }, - { R_2D(0x69b), "roundrl", I_FP, REG, 2, { FL2,F2, 0 } }, - { R_2D(0x69c), "sinrl", I_FP, REG, 2, { FL2,F2, 0 } }, - { R_2D(0x69d), "cosrl", I_FP, REG, 2, { FL2,F2, 0 } }, - { R_2D(0x69e), "tanrl", I_FP, REG, 2, { FL2,F2, 0 } }, - { R_1(0x69f), "classrl", I_FP, REG, 1, { FL2, 0, 0 } }, - { R_2D(0x6c0), "cvtri", I_FP, REG, 2, { FL, R, 0 } }, - { R_2D(0x6c1), "cvtril", I_FP, REG, 2, { FL, R2, 0 } }, - { R_2D(0x6c2), "cvtzri", I_FP, REG, 2, { FL, R, 0 } }, - { R_2D(0x6c3), "cvtzril", I_FP, REG, 2, { FL, R2, 0 } }, - { R_2D(0x6c9), "movr", I_FP, REG, 2, { FL, F, 0 } }, - { R_2D(0x6d9), "movrl", I_FP, REG, 2, { FL2,F2, 0 } }, - { R_2D(0x6e1), "movre", I_FP, REG, 2, { FL4,F4, 0 } }, - { R_3(0x6e2), "cpysre", I_FP, REG, 3, { FL4,FL4,F4 } }, - { R_3(0x6e3), "cpyrsre", I_FP, REG, 3, { FL4,FL4,F4 } }, - { R_3(0x78b), "divr", I_FP, REG, 3, { FL, FL, F } }, - { R_3(0x78c), "mulr", I_FP, REG, 3, { FL, FL, F } }, - { R_3(0x78d), "subr", I_FP, REG, 3, { FL, FL, F } }, - { R_3(0x78f), "addr", I_FP, REG, 3, { FL, FL, F } }, - { R_3(0x79b), "divrl", I_FP, REG, 3, { FL2,FL2,F2 } }, - { R_3(0x79c), "mulrl", I_FP, REG, 3, { FL2,FL2,F2 } }, - { R_3(0x79d), "subrl", I_FP, REG, 3, { FL2,FL2,F2 } }, - { R_3(0x79f), "addrl", I_FP, REG, 3, { FL2,FL2,F2 } }, - - /* These are the floating point branch instructions. Each actually - * generates 2 branch instructions: the first a CTRL instruction with - * the indicated opcode, and the second a 'bno'. - */ - - { 0x12000000, "brue", I_FP, FBRA, 1, { 0, 0, 0 } }, - { 0x11000000, "brug", I_FP, FBRA, 1, { 0, 0, 0 } }, - { 0x13000000, "bruge", I_FP, FBRA, 1, { 0, 0, 0 } }, - { 0x14000000, "brul", I_FP, FBRA, 1, { 0, 0, 0 } }, - { 0x16000000, "brule", I_FP, FBRA, 1, { 0, 0, 0 } }, - { 0x15000000, "brulg", I_FP, FBRA, 1, { 0, 0, 0 } }, - - - /* Decimal instructions */ - - { R_3(0x642), "daddc", I_DEC, REG, 3, { RSL,RSL,RS } }, - { R_3(0x643), "dsubc", I_DEC, REG, 3, { RSL,RSL,RS } }, - { R_2D(0x644), "dmovt", I_DEC, REG, 2, { RSL,RS, 0 } }, - - - /* KX extensions */ - - { R_2(0x600), "synmov", I_KX, REG, 2, { R, R, 0 } }, - { R_2(0x601), "synmovl", I_KX, REG, 2, { R, R, 0 } }, - { R_2(0x602), "synmovq", I_KX, REG, 2, { R, R, 0 } }, - { R_2D(0x615), "synld", I_KX, REG, 2, { R, R, 0 } }, - - - /* MC extensions */ - - { R_3(0x603), "cmpstr", I_MIL, REG, 3, { R, R, RL } }, - { R_3(0x604), "movqstr", I_MIL, REG, 3, { R, R, RL } }, - { R_3(0x605), "movstr", I_MIL, REG, 3, { R, R, RL } }, - { R_2D(0x613), "inspacc", I_MIL, REG, 2, { R, R, 0 } }, - { R_2D(0x614), "ldphy", I_MIL, REG, 2, { R, R, 0 } }, - { R_3(0x617), "fill", I_MIL, REG, 3, { R, RL, RL } }, - { R_2D(0x646), "condrec", I_MIL, REG, 2, { R, R, 0 } }, - { R_2D(0x656), "receive", I_MIL, REG, 2, { R, R, 0 } }, - { R_3(0x662), "send", I_MIL, REG, 3, { R, RL, R } }, - { R_1(0x663), "sendserv", I_MIL, REG, 1, { R, 0, 0 } }, - { R_1(0x664), "resumprcs", I_MIL, REG, 1, { R, 0, 0 } }, - { R_1(0x665), "schedprcs", I_MIL, REG, 1, { R, 0, 0 } }, - { R_0(0x666), "saveprcs", I_MIL, REG, 0, { 0, 0, 0 } }, - { R_1(0x668), "condwait", I_MIL, REG, 1, { R, 0, 0 } }, - { R_1(0x669), "wait", I_MIL, REG, 1, { R, 0, 0 } }, - { R_1(0x66a), "signal", I_MIL, REG, 1, { R, 0, 0 } }, - { R_1D(0x673), "ldtime", I_MIL, REG, 1, { R2, 0, 0 } }, - - - /* CX extensions */ - - { R_3(0x5d8), "eshro", I_CX2, REG, 3, { RSL,RSL,RS } }, - { R_3(0x630), "sdma", I_CX, REG, 3, { RSL,RSL,RL } }, - { R_3(0x631), "udma", I_CX, REG, 0, { 0, 0, 0 } }, - { R_3(0x659), "sysctl", I_CX2, REG, 3, { RSL,RSL,RL } }, - - - /* Jx extensions. */ - { R_3(0x780), "addono", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x790), "addog", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x7a0), "addoe", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x7b0), "addoge", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x7c0), "addol", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x7d0), "addone", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x7e0), "addole", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x7f0), "addoo", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x781), "addino", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x791), "addig", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x7a1), "addie", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x7b1), "addige", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x7c1), "addil", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x7d1), "addine", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x7e1), "addile", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x7f1), "addio", I_JX, REG, 3, { RSL,RSL,RS } }, - - { R_2D(0x5ad), "bswap", I_JX, REG, 2, { RSL, RS, 0 } }, - - { R_2(0x594), "cmpob", I_JX, REG, 2, { RSL,RSL, 0 } }, - { R_2(0x595), "cmpib", I_JX, REG, 2, { RSL,RSL, 0 } }, - { R_2(0x596), "cmpos", I_JX, REG, 2, { RSL,RSL, 0 } }, - { R_2(0x597), "cmpis", I_JX, REG, 2, { RSL,RSL, 0 } }, - - { R_3(0x784), "selno", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x794), "selg", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x7a4), "sele", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x7b4), "selge", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x7c4), "sell", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x7d4), "selne", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x7e4), "selle", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x7f4), "selo", I_JX, REG, 3, { RSL,RSL,RS } }, - - { R_3(0x782), "subono", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x792), "subog", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x7a2), "suboe", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x7b2), "suboge", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x7c2), "subol", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x7d2), "subone", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x7e2), "subole", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x7f2), "suboo", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x783), "subino", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x793), "subig", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x7a3), "subie", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x7b3), "subige", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x7c3), "subil", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x7d3), "subine", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x7e3), "subile", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x7f3), "subio", I_JX, REG, 3, { RSL,RSL,RS } }, - - { R_3(0x65c), "dcctl", I_JX, REG, 3, { RSL,RSL,RL } }, - { R_3(0x65b), "icctl", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_2D(0x658), "intctl", I_JX, REG, 2, { RSL, RS, 0 } }, - { R_0(0x5b4), "intdis", I_JX, REG, 0, { 0, 0, 0 } }, - { R_0(0x5b5), "inten", I_JX, REG, 0, { 0, 0, 0 } }, - { R_0(0x65d), "halt", I_JX, REG, 1, { RSL, 0, 0 } }, - - /* Hx extensions. */ - { 0xac000000, "dcinva", I_HX, MEM1, 1, { M, 0, 0 } }, - - /* END OF TABLE */ - - { 0, NULL, 0, 0, 0, { 0, 0, 0 } } -}; - - /* end of i960-opcode.h */ diff --git a/include/opcode/ia64.h b/include/opcode/ia64.h deleted file mode 100644 index 433c505..0000000 --- a/include/opcode/ia64.h +++ /dev/null @@ -1,422 +0,0 @@ -/* ia64.h -- Header file for ia64 opcode table - Copyright (C) 1998, 1999, 2000, 2002, 2005, 2006, 2010 - Free Software Foundation, Inc. - Contributed by David Mosberger-Tang <davidm@hpl.hp.com> - - This file is part of BFD, the Binary File Descriptor library. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software Foundation, - Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ - -#ifndef opcode_ia64_h -#define opcode_ia64_h - -#include <sys/types.h> - -#include "bfd.h" - - -typedef BFD_HOST_U_64_BIT ia64_insn; - -enum ia64_insn_type - { - IA64_TYPE_NIL = 0, /* illegal type */ - IA64_TYPE_A, /* integer alu (I- or M-unit) */ - IA64_TYPE_I, /* non-alu integer (I-unit) */ - IA64_TYPE_M, /* memory (M-unit) */ - IA64_TYPE_B, /* branch (B-unit) */ - IA64_TYPE_F, /* floating-point (F-unit) */ - IA64_TYPE_X, /* long encoding (X-unit) */ - IA64_TYPE_DYN, /* Dynamic opcode */ - IA64_NUM_TYPES - }; - -enum ia64_unit - { - IA64_UNIT_NIL = 0, /* illegal unit */ - IA64_UNIT_I, /* integer unit */ - IA64_UNIT_M, /* memory unit */ - IA64_UNIT_B, /* branching unit */ - IA64_UNIT_F, /* floating-point unit */ - IA64_UNIT_L, /* long "unit" */ - IA64_UNIT_X, /* may be integer or branch unit */ - IA64_NUM_UNITS - }; - -/* Changes to this enumeration must be propagated to the operand table in - bfd/cpu-ia64-opc.c - */ -enum ia64_opnd - { - IA64_OPND_NIL, /* no operand---MUST BE FIRST!*/ - - /* constants */ - IA64_OPND_AR_CSD, /* application register csd (ar.csd) */ - IA64_OPND_AR_CCV, /* application register ccv (ar.ccv) */ - IA64_OPND_AR_PFS, /* application register pfs (ar.pfs) */ - IA64_OPND_C1, /* the constant 1 */ - IA64_OPND_C8, /* the constant 8 */ - IA64_OPND_C16, /* the constant 16 */ - IA64_OPND_GR0, /* gr0 */ - IA64_OPND_IP, /* instruction pointer (ip) */ - IA64_OPND_PR, /* predicate register (pr) */ - IA64_OPND_PR_ROT, /* rotating predicate register (pr.rot) */ - IA64_OPND_PSR, /* processor status register (psr) */ - IA64_OPND_PSR_L, /* processor status register L (psr.l) */ - IA64_OPND_PSR_UM, /* processor status register UM (psr.um) */ - - /* register operands: */ - IA64_OPND_AR3, /* third application register # (bits 20-26) */ - IA64_OPND_B1, /* branch register # (bits 6-8) */ - IA64_OPND_B2, /* branch register # (bits 13-15) */ - IA64_OPND_CR3, /* third control register # (bits 20-26) */ - IA64_OPND_F1, /* first floating-point register # */ - IA64_OPND_F2, /* second floating-point register # */ - IA64_OPND_F3, /* third floating-point register # */ - IA64_OPND_F4, /* fourth floating-point register # */ - IA64_OPND_P1, /* first predicate # */ - IA64_OPND_P2, /* second predicate # */ - IA64_OPND_R1, /* first register # */ - IA64_OPND_R2, /* second register # */ - IA64_OPND_R3, /* third register # */ - IA64_OPND_R3_2, /* third register # (limited to gr0-gr3) */ - IA64_OPND_DAHR3, /* dahr reg # ( bits 23-25) */ - - /* memory operands: */ - IA64_OPND_MR3, /* memory at addr of third register # */ - - /* indirect operands: */ - IA64_OPND_CPUID_R3, /* cpuid[reg] */ - IA64_OPND_DBR_R3, /* dbr[reg] */ - IA64_OPND_DTR_R3, /* dtr[reg] */ - IA64_OPND_ITR_R3, /* itr[reg] */ - IA64_OPND_IBR_R3, /* ibr[reg] */ - IA64_OPND_MSR_R3, /* msr[reg] */ - IA64_OPND_PKR_R3, /* pkr[reg] */ - IA64_OPND_PMC_R3, /* pmc[reg] */ - IA64_OPND_PMD_R3, /* pmd[reg] */ - IA64_OPND_DAHR_R3, /* dahr[reg] */ - IA64_OPND_RR_R3, /* rr[reg] */ - - /* immediate operands: */ - IA64_OPND_CCNT5, /* 5-bit count (31 - bits 20-24) */ - IA64_OPND_CNT2a, /* 2-bit count (1 + bits 27-28) */ - IA64_OPND_CNT2b, /* 2-bit count (bits 27-28): 1, 2, 3 */ - IA64_OPND_CNT2c, /* 2-bit count (bits 30-31): 0, 7, 15, or 16 */ - IA64_OPND_CNT5, /* 5-bit count (bits 14-18) */ - IA64_OPND_CNT6, /* 6-bit count (bits 27-32) */ - IA64_OPND_CPOS6a, /* 6-bit count (63 - bits 20-25) */ - IA64_OPND_CPOS6b, /* 6-bit count (63 - bits 14-19) */ - IA64_OPND_CPOS6c, /* 6-bit count (63 - bits 31-36) */ - IA64_OPND_IMM1, /* signed 1-bit immediate (bit 36) */ - IA64_OPND_IMMU2, /* unsigned 2-bit immediate (bits 13-14) */ - IA64_OPND_IMMU5b, /* unsigned 5-bit immediate (32 + bits 14-18) */ - IA64_OPND_IMMU7a, /* unsigned 7-bit immediate (bits 13-19) */ - IA64_OPND_IMMU7b, /* unsigned 7-bit immediate (bits 20-26) */ - IA64_OPND_SOF, /* 8-bit stack frame size */ - IA64_OPND_SOL, /* 8-bit size of locals */ - IA64_OPND_SOR, /* 6-bit number of rotating registers (scaled by 8) */ - IA64_OPND_IMM8, /* signed 8-bit immediate (bits 13-19 & 36) */ - IA64_OPND_IMM8U4, /* cmp4*u signed 8-bit immediate (bits 13-19 & 36) */ - IA64_OPND_IMM8M1, /* signed 8-bit immediate -1 (bits 13-19 & 36) */ - IA64_OPND_IMM8M1U4, /* cmp4*u signed 8-bit immediate -1 (bits 13-19 & 36)*/ - IA64_OPND_IMM8M1U8, /* cmp*u signed 8-bit immediate -1 (bits 13-19 & 36) */ - IA64_OPND_IMMU9, /* unsigned 9-bit immediate (bits 33-34, 20-26) */ - IA64_OPND_IMM9a, /* signed 9-bit immediate (bits 6-12, 27, 36) */ - IA64_OPND_IMM9b, /* signed 9-bit immediate (bits 13-19, 27, 36) */ - IA64_OPND_IMM14, /* signed 14-bit immediate (bits 13-19, 27-32, 36) */ - IA64_OPND_IMMU16, /* unsigned 16-bit immediate (bits 6-9, 12-22, 36) */ - IA64_OPND_IMM17, /* signed 17-bit immediate (2*bits 6-12, 24-31, 36) */ - IA64_OPND_IMMU19, /* unsigned 19-bit immediate (bits 6-9, 12-25, 36) */ - IA64_OPND_IMMU21, /* unsigned 21-bit immediate (bits 6-25, 36) */ - IA64_OPND_IMM22, /* signed 22-bit immediate (bits 13-19, 22-36) */ - IA64_OPND_IMMU24, /* unsigned 24-bit immediate (bits 6-26, 31-32, 36) */ - IA64_OPND_IMM44, /* signed 44-bit immediate (2^16*bits 6-32, 36) */ - IA64_OPND_IMMU62, /* unsigned 62-bit immediate */ - IA64_OPND_IMMU64, /* unsigned 64-bit immediate (lotsa bits...) */ - IA64_OPND_INC3, /* signed 3-bit (bits 13-15): +/-1, 4, 8, 16 */ - IA64_OPND_LEN4, /* 4-bit count (bits 27-30 + 1) */ - IA64_OPND_LEN6, /* 6-bit count (bits 27-32 + 1) */ - IA64_OPND_MBTYPE4, /* 4-bit mux type (bits 20-23) */ - IA64_OPND_MHTYPE8, /* 8-bit mux type (bits 20-27) */ - IA64_OPND_POS6, /* 6-bit count (bits 14-19) */ - IA64_OPND_TAG13, /* signed 13-bit tag (ip + 16*bits 6-12, 33-34) */ - IA64_OPND_TAG13b, /* signed 13-bit tag (ip + 16*bits 24-32) */ - IA64_OPND_TGT25, /* signed 25-bit (ip + 16*bits 6-25, 36) */ - IA64_OPND_TGT25b, /* signed 25-bit (ip + 16*bits 6-12, 20-32, 36) */ - IA64_OPND_TGT25c, /* signed 25-bit (ip + 16*bits 13-32, 36) */ - IA64_OPND_TGT64, /* 64-bit (ip + 16*bits 13-32, 36, 2-40(L)) */ - IA64_OPND_LDXMOV, /* any symbol, generates R_IA64_LDXMOV. */ - - IA64_OPND_CNT6a, /* 6-bit count (bits 6-11) */ - IA64_OPND_STRD5b, /* 5-bit stride (bits 13-17) */ - - IA64_OPND_COUNT /* # of operand types (MUST BE LAST!) */ - }; - -enum ia64_dependency_mode -{ - IA64_DV_RAW, - IA64_DV_WAW, - IA64_DV_WAR, -}; - -enum ia64_dependency_semantics -{ - IA64_DVS_NONE, - IA64_DVS_IMPLIED, - IA64_DVS_IMPLIEDF, - IA64_DVS_DATA, - IA64_DVS_INSTR, - IA64_DVS_SPECIFIC, - IA64_DVS_STOP, - IA64_DVS_OTHER, -}; - -enum ia64_resource_specifier -{ - IA64_RS_ANY, - IA64_RS_AR_K, - IA64_RS_AR_UNAT, - IA64_RS_AR, /* 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 45-47, 67-111 */ - IA64_RS_ARb, /* 48-63, 112-127 */ - IA64_RS_BR, - IA64_RS_CFM, - IA64_RS_CPUID, - IA64_RS_CR_IIB, - IA64_RS_CR_IRR, - IA64_RS_CR_LRR, - IA64_RS_CR, /* 3-7,10-15,18,28-63,75-79,82-127 */ - IA64_RS_DAHR, - IA64_RS_DBR, - IA64_RS_FR, - IA64_RS_FRb, - IA64_RS_GR0, - IA64_RS_GR, - IA64_RS_IBR, - IA64_RS_INSERVICE, /* CR[EOI] or CR[IVR] */ - IA64_RS_MSR, - IA64_RS_PKR, - IA64_RS_PMC, - IA64_RS_PMD, - IA64_RS_PR, /* non-rotating, 1-15 */ - IA64_RS_PRr, /* rotating, 16-62 */ - IA64_RS_PR63, - IA64_RS_RR, - - IA64_RS_ARX, /* ARs not in RS_AR or RS_ARb */ - IA64_RS_CRX, /* CRs not in RS_CR */ - IA64_RS_PSR, /* PSR bits */ - IA64_RS_RSE, /* implementation-specific RSE resources */ - IA64_RS_AR_FPSR, - -}; - -enum ia64_rse_resource -{ - IA64_RSE_N_STACKED_PHYS, - IA64_RSE_BOF, - IA64_RSE_STORE_REG, - IA64_RSE_LOAD_REG, - IA64_RSE_BSPLOAD, - IA64_RSE_RNATBITINDEX, - IA64_RSE_CFLE, - IA64_RSE_NDIRTY, -}; - -/* Information about a given resource dependency */ -struct ia64_dependency -{ - /* Name of the resource */ - const char *name; - /* Does this dependency need further specification? */ - enum ia64_resource_specifier specifier; - /* Mode of dependency */ - enum ia64_dependency_mode mode; - /* Dependency semantics */ - enum ia64_dependency_semantics semantics; - /* Register index, if applicable (distinguishes AR, CR, and PSR deps) */ -#define REG_NONE (-1) - int regindex; - /* Special info on semantics */ - const char *info; -}; - -/* Two arrays of indexes into the ia64_dependency table. - chks are dependencies to check for conflicts when an opcode is - encountered; regs are dependencies to register (mark as used) when an - opcode is used. chks correspond to readers (RAW) or writers (WAW or - WAR) of a resource, while regs correspond to writers (RAW or WAW) and - readers (WAR) of a resource. */ -struct ia64_opcode_dependency -{ - int nchks; - const unsigned short *chks; - int nregs; - const unsigned short *regs; -}; - -/* encode/extract the note/index for a dependency */ -#define RDEP(N,X) (((N)<<11)|(X)) -#define NOTE(X) (((X)>>11)&0x1F) -#define DEP(X) ((X)&0x7FF) - -/* A template descriptor describes the execution units that are active - for each of the three slots. It also specifies the location of - instruction group boundaries that may be present between two slots. */ -struct ia64_templ_desc - { - int group_boundary; /* 0=no boundary, 1=between slot 0 & 1, etc. */ - enum ia64_unit exec_unit[3]; - const char *name; - }; - -/* The opcode table is an array of struct ia64_opcode. */ - -struct ia64_opcode - { - /* The opcode name. */ - const char *name; - - /* The type of the instruction: */ - enum ia64_insn_type type; - - /* Number of output operands: */ - int num_outputs; - - /* The opcode itself. Those bits which will be filled in with - operands are zeroes. */ - ia64_insn opcode; - - /* The opcode mask. This is used by the disassembler. This is a - mask containing ones indicating those bits which must match the - opcode field, and zeroes indicating those bits which need not - match (and are presumably filled in by operands). */ - ia64_insn mask; - - /* An array of operand codes. Each code is an index into the - operand table. They appear in the order which the operands must - appear in assembly code, and are terminated by a zero. */ - enum ia64_opnd operands[5]; - - /* One bit flags for the opcode. These are primarily used to - indicate specific processors and environments support the - instructions. The defined values are listed below. */ - unsigned int flags; - - /* Used by ia64_find_next_opcode (). */ - short ent_index; - - /* Opcode dependencies. */ - const struct ia64_opcode_dependency *dependencies; - }; - -/* Values defined for the flags field of a struct ia64_opcode. */ - -#define IA64_OPCODE_FIRST (1<<0) /* must be first in an insn group */ -#define IA64_OPCODE_X_IN_MLX (1<<1) /* insn is allowed in X slot of MLX */ -#define IA64_OPCODE_LAST (1<<2) /* must be last in an insn group */ -#define IA64_OPCODE_PRIV (1<<3) /* privileged instruct */ -#define IA64_OPCODE_SLOT2 (1<<4) /* insn allowed in slot 2 only */ -#define IA64_OPCODE_NO_PRED (1<<5) /* insn cannot be predicated */ -#define IA64_OPCODE_PSEUDO (1<<6) /* insn is a pseudo-op */ -#define IA64_OPCODE_F2_EQ_F3 (1<<7) /* constraint: F2 == F3 */ -#define IA64_OPCODE_LEN_EQ_64MCNT (1<<8) /* constraint: LEN == 64-CNT */ -#define IA64_OPCODE_MOD_RRBS (1<<9) /* modifies all rrbs in CFM */ -#define IA64_OPCODE_POSTINC (1<<10) /* postincrement MR3 operand */ - -/* A macro to extract the major opcode from an instruction. */ -#define IA64_OP(i) (((i) >> 37) & 0xf) - -enum ia64_operand_class - { - IA64_OPND_CLASS_CST, /* constant */ - IA64_OPND_CLASS_REG, /* register */ - IA64_OPND_CLASS_IND, /* indirect register */ - IA64_OPND_CLASS_ABS, /* absolute value */ - IA64_OPND_CLASS_REL, /* IP-relative value */ - }; - -/* The operands table is an array of struct ia64_operand. */ - -struct ia64_operand -{ - enum ia64_operand_class op_class; - - /* Set VALUE as the operand bits for the operand of type SELF in the - instruction pointed to by CODE. If an error occurs, *CODE is not - modified and the returned string describes the cause of the - error. If no error occurs, NULL is returned. */ - const char *(*insert) (const struct ia64_operand *self, ia64_insn value, - ia64_insn *code); - - /* Extract the operand bits for an operand of type SELF from - instruction CODE store them in *VALUE. If an error occurs, the - cause of the error is described by the string returned. If no - error occurs, NULL is returned. */ - const char *(*extract) (const struct ia64_operand *self, ia64_insn code, - ia64_insn *value); - - /* A string whose meaning depends on the operand class. */ - - const char *str; - - struct bit_field - { - /* The number of bits in the operand. */ - int bits; - - /* How far the operand is left shifted in the instruction. */ - int shift; - } - field[4]; /* no operand has more than this many bit-fields */ - - unsigned int flags; - - const char *desc; /* brief description */ -}; - -/* Values defined for the flags field of a struct ia64_operand. */ - -/* Disassemble as signed decimal (instead of hex): */ -#define IA64_OPND_FLAG_DECIMAL_SIGNED (1<<0) -/* Disassemble as unsigned decimal (instead of hex): */ -#define IA64_OPND_FLAG_DECIMAL_UNSIGNED (1<<1) - -extern const struct ia64_templ_desc ia64_templ_desc[16]; - -/* The tables are sorted by major opcode number and are otherwise in - the order in which the disassembler should consider instructions. */ -extern struct ia64_opcode ia64_opcodes_a[]; -extern struct ia64_opcode ia64_opcodes_i[]; -extern struct ia64_opcode ia64_opcodes_m[]; -extern struct ia64_opcode ia64_opcodes_b[]; -extern struct ia64_opcode ia64_opcodes_f[]; -extern struct ia64_opcode ia64_opcodes_d[]; - - -extern struct ia64_opcode *ia64_find_opcode (const char *); -extern struct ia64_opcode *ia64_find_next_opcode (struct ia64_opcode *); - -extern struct ia64_opcode *ia64_dis_opcode (ia64_insn, - enum ia64_insn_type); - -extern void ia64_free_opcode (struct ia64_opcode *); -extern const struct ia64_dependency *ia64_find_dependency (int); - -/* To avoid circular library dependencies, this array is implemented - in bfd/cpu-ia64-opc.c: */ -extern const struct ia64_operand elf64_ia64_operands[IA64_OPND_COUNT]; - -#endif /* opcode_ia64_h */ diff --git a/include/opcode/m68hc11.h b/include/opcode/m68hc11.h deleted file mode 100644 index 1a00200..0000000 --- a/include/opcode/m68hc11.h +++ /dev/null @@ -1,456 +0,0 @@ -/* m68hc11.h -- Header file for Motorola 68HC11 & 68HC12 opcode table - Copyright 1999, 2000, 2002, 2003, 2010, 2012 - Free Software Foundation, Inc. - Written by Stephane Carrez (stcarrez@nerim.fr) - - This file is part of GDB, GAS, and the GNU binutils. - - GDB, GAS, and the GNU binutils are free software; you can redistribute - them and/or modify them under the terms of the GNU General Public - License as published by the Free Software Foundation; either version 3, - or (at your option) any later version. - - GDB, GAS, and the GNU binutils are distributed in the hope that they - will be useful, but WITHOUT ANY WARRANTY; without even the implied - warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See - the GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this file; see the file COPYING3. If not, write to the Free - Software Foundation, 51 Franklin Street - Fifth Floor, Boston, - MA 02110-1301, USA. */ - -#ifndef _OPCODE_M68HC11_H -#define _OPCODE_M68HC11_H - -/* Flags for the definition of the 68HC11 & 68HC12 CCR. */ -#define M6811_S_BIT 0x80 /* Stop disable */ -#define M6811_X_BIT 0x40 /* X-interrupt mask */ -#define M6811_H_BIT 0x20 /* Half carry flag */ -#define M6811_I_BIT 0x10 /* I-interrupt mask */ -#define M6811_N_BIT 0x08 /* Negative */ -#define M6811_Z_BIT 0x04 /* Zero */ -#define M6811_V_BIT 0x02 /* Overflow */ -#define M6811_C_BIT 0x01 /* Carry */ - -/* 68HC11 register address offsets (range 0..0x3F or 0..64). - The absolute address of the I/O register depends on the setting - of the M6811_INIT register. At init time, the I/O registers are - mapped at 0x1000. Address of registers is then: - - 0x1000 + M6811_xxx. */ -#define M6811_PORTA 0x00 /* Port A register */ -#define M6811__RES1 0x01 /* Unused/Reserved */ -#define M6811_PIOC 0x02 /* Parallel I/O Control register */ -#define M6811_PORTC 0x03 /* Port C register */ -#define M6811_PORTB 0x04 /* Port B register */ -#define M6811_PORTCL 0x05 /* Alternate latched port C */ -#define M6811__RES6 0x06 /* Unused/Reserved */ -#define M6811_DDRC 0x07 /* Data direction register for port C */ -#define M6811_PORTD 0x08 /* Port D register */ -#define M6811_DDRD 0x09 /* Data direction register for port D */ -#define M6811_PORTE 0x0A /* Port E input register */ -#define M6811_CFORC 0x0B /* Compare Force Register */ -#define M6811_OC1M 0x0C /* OC1 Action Mask register */ -#define M6811_OC1D 0x0D /* OC1 Action Data register */ -#define M6811_TCTN 0x0E /* Timer Counter Register */ -#define M6811_TCTN_H 0x0E /* " " " High part */ -#define M6811_TCTN_L 0x0F /* " " " Low part */ -#define M6811_TIC1 0x10 /* Input capture 1 register */ -#define M6811_TIC1_H 0x10 /* " " " High part */ -#define M6811_TIC1_L 0x11 /* " " " Low part */ -#define M6811_TIC2 0x12 /* Input capture 2 register */ -#define M6811_TIC2_H 0x12 /* " " " High part */ -#define M6811_TIC2_L 0x13 /* " " " Low part */ -#define M6811_TIC3 0x14 /* Input capture 3 register */ -#define M6811_TIC3_H 0x14 /* " " " High part */ -#define M6811_TIC3_L 0x15 /* " " " Low part */ -#define M6811_TOC1 0x16 /* Output Compare 1 register */ -#define M6811_TOC1_H 0x16 /* " " " High part */ -#define M6811_TOC1_L 0x17 /* " " " Low part */ -#define M6811_TOC2 0x18 /* Output Compare 2 register */ -#define M6811_TOC2_H 0x18 /* " " " High part */ -#define M6811_TOC2_L 0x19 /* " " " Low part */ -#define M6811_TOC3 0x1A /* Output Compare 3 register */ -#define M6811_TOC3_H 0x1A /* " " " High part */ -#define M6811_TOC3_L 0x1B /* " " " Low part */ -#define M6811_TOC4 0x1C /* Output Compare 4 register */ -#define M6811_TOC4_H 0x1C /* " " " High part */ -#define M6811_TOC4_L 0x1D /* " " " Low part */ -#define M6811_TOC5 0x1E /* Output Compare 5 register */ -#define M6811_TOC5_H 0x1E /* " " " High part */ -#define M6811_TOC5_L 0x1F /* " " " Low part */ -#define M6811_TCTL1 0x20 /* Timer Control register 1 */ -#define M6811_TCTL2 0x21 /* Timer Control register 2 */ -#define M6811_TMSK1 0x22 /* Timer Interrupt Mask Register 1 */ -#define M6811_TFLG1 0x23 /* Timer Interrupt Flag Register 1 */ -#define M6811_TMSK2 0x24 /* Timer Interrupt Mask Register 2 */ -#define M6811_TFLG2 0x25 /* Timer Interrupt Flag Register 2 */ -#define M6811_PACTL 0x26 /* Pulse Accumulator Control Register */ -#define M6811_PACNT 0x27 /* Pulse Accumulator Count Register */ -#define M6811_SPCR 0x28 /* SPI Control register */ -#define M6811_SPSR 0x29 /* SPI Status register */ -#define M6811_SPDR 0x2A /* SPI Data register */ -#define M6811_BAUD 0x2B /* SCI Baud register */ -#define M6811_SCCR1 0x2C /* SCI Control register 1 */ -#define M6811_SCCR2 0x2D /* SCI Control register 2 */ -#define M6811_SCSR 0x2E /* SCI Status register */ -#define M6811_SCDR 0x2F /* SCI Data (Read => RDR, Write => TDR) */ -#define M6811_ADCTL 0x30 /* A/D Control register */ -#define M6811_ADR1 0x31 /* A/D, Analog Result register 1 */ -#define M6811_ADR2 0x32 /* A/D, Analog Result register 2 */ -#define M6811_ADR3 0x33 /* A/D, Analog Result register 3 */ -#define M6811_ADR4 0x34 /* A/D, Analog Result register 4 */ -#define M6811__RES35 0x35 -#define M6811__RES36 0x36 -#define M6811__RES37 0x37 -#define M6811__RES38 0x38 -#define M6811_OPTION 0x39 /* System Configuration Options */ -#define M6811_COPRST 0x3A /* Arm/Reset COP Timer Circuitry */ -#define M6811_PPROG 0x3B /* EEPROM Programming Control Register */ -#define M6811_HPRIO 0x3C /* Highest priority I-Bit int and misc */ -#define M6811_INIT 0x3D /* Ram and I/O mapping register */ -#define M6811_TEST1 0x3E /* Factory test control register */ -#define M6811_CONFIG 0x3F /* COP, ROM and EEPROM enables */ - - -/* Flags of the CONFIG register (in EEPROM). */ -#define M6811_NOSEC 0x08 /* Security mode disable */ -#define M6811_NOCOP 0x04 /* COP system disable */ -#define M6811_ROMON 0x02 /* Enable on-chip rom */ -#define M6811_EEON 0x01 /* Enable on-chip eeprom */ - -/* Flags of the PPROG register. */ -#define M6811_BYTE 0x10 /* Byte mode */ -#define M6811_ROW 0x08 /* Row mode */ -#define M6811_ERASE 0x04 /* Erase mode select (1 = erase, 0 = read) */ -#define M6811_EELAT 0x02 /* EEPROM Latch Control */ -#define M6811_EEPGM 0x01 /* EEPROM Programming Voltage Enable */ - -/* Flags of the PIOC register. */ -#define M6811_STAF 0x80 /* Strobe A Interrupt Status Flag */ -#define M6811_STAI 0x40 /* Strobe A Interrupt Enable Mask */ -#define M6811_CWOM 0x20 /* Port C Wire OR mode */ -#define M6811_HNDS 0x10 /* Handshake mode */ -#define M6811_OIN 0x08 /* Output or Input handshaking */ -#define M6811_PLS 0x04 /* Pulse/Interlocked Handshake Operation */ -#define M6811_EGA 0x02 /* Active Edge for Strobe A */ -#define M6811_INVB 0x01 /* Invert Strobe B */ - -/* Flags of the SCCR1 register. */ -#define M6811_R8 0x80 /* Receive Data bit 8 */ -#define M6811_T8 0x40 /* Transmit data bit 8 */ -#define M6811__SCCR1_5 0x20 /* Unused */ -#define M6811_M 0x10 /* SCI Character length */ -#define M6811_WAKE 0x08 /* Wake up method select (0=idle, 1=addr mark) */ - -/* Flags of the SCCR2 register. */ -#define M6811_TIE 0x80 /* Transmit Interrupt enable */ -#define M6811_TCIE 0x40 /* Transmit Complete Interrupt Enable */ -#define M6811_RIE 0x20 /* Receive Interrupt Enable */ -#define M6811_ILIE 0x10 /* Idle Line Interrupt Enable */ -#define M6811_TE 0x08 /* Transmit Enable */ -#define M6811_RE 0x04 /* Receive Enable */ -#define M6811_RWU 0x02 /* Receiver Wake Up */ -#define M6811_SBK 0x01 /* Send Break */ - -/* Flags of the SCSR register. */ -#define M6811_TDRE 0x80 /* Transmit Data Register Empty */ -#define M6811_TC 0x40 /* Transmit Complete */ -#define M6811_RDRF 0x20 /* Receive Data Register Full */ -#define M6811_IDLE 0x10 /* Idle Line Detect */ -#define M6811_OR 0x08 /* Overrun Error */ -#define M6811_NF 0x04 /* Noise Flag */ -#define M6811_FE 0x02 /* Framing Error */ -#define M6811__SCSR_0 0x01 /* Unused */ - -/* Flags of the BAUD register. */ -#define M6811_TCLR 0x80 /* Clear Baud Rate (TEST mode) */ -#define M6811__BAUD_6 0x40 /* Not used */ -#define M6811_SCP1 0x20 /* SCI Baud rate prescaler select */ -#define M6811_SCP0 0x10 -#define M6811_RCKB 0x08 /* Baud Rate Clock Check (TEST mode) */ -#define M6811_SCR2 0x04 /* SCI Baud rate select */ -#define M6811_SCR1 0x02 -#define M6811_SCR0 0x01 - -#define M6811_BAUD_DIV_1 (0) -#define M6811_BAUD_DIV_3 (M6811_SCP0) -#define M6811_BAUD_DIV_4 (M6811_SCP1) -#define M6811_BAUD_DIV_13 (M6811_SCP1|M6811_SCP0) - -/* Flags of the SPCR register. */ -#define M6811_SPIE 0x80 /* Serial Peripheral Interrupt Enable */ -#define M6811_SPE 0x40 /* Serial Peripheral System Enable */ -#define M6811_DWOM 0x20 /* Port D Wire-OR mode option */ -#define M6811_MSTR 0x10 /* Master Mode Select */ -#define M6811_CPOL 0x08 /* Clock Polarity */ -#define M6811_CPHA 0x04 /* Clock Phase */ -#define M6811_SPR1 0x02 /* SPI Clock Rate Select */ -#define M6811_SPR0 0x01 - -/* Flags of the SPSR register. */ -#define M6811_SPIF 0x80 /* SPI Transfer Complete flag */ -#define M6811_WCOL 0x40 /* Write Collision */ -#define M6811_MODF 0x10 /* Mode Fault */ - -/* Flags of the ADCTL register. */ -#define M6811_CCF 0x80 /* Conversions Complete Flag */ -#define M6811_SCAN 0x20 /* Continuous Scan Control */ -#define M6811_MULT 0x10 /* Multiple Channel/Single Channel Control */ -#define M6811_CD 0x08 /* Channel Select D */ -#define M6811_CC 0x04 /* C */ -#define M6811_CB 0x02 /* B */ -#define M6811_CA 0x01 /* A */ - -/* Flags of the CFORC register. */ -#define M6811_FOC1 0x80 /* Force Output Compare 1 */ -#define M6811_FOC2 0x40 /* 2 */ -#define M6811_FOC3 0x20 /* 3 */ -#define M6811_FOC4 0x10 /* 4 */ -#define M6811_FOC5 0x08 /* 5 */ - -/* Flags of the OC1M register. */ -#define M6811_OC1M7 0x80 /* Output Compare 7 */ -#define M6811_OC1M6 0x40 /* 6 */ -#define M6811_OC1M5 0x20 /* 5 */ -#define M6811_OC1M4 0x10 /* 4 */ -#define M6811_OC1M3 0x08 /* 3 */ - -/* Flags of the OC1D register. */ -#define M6811_OC1D7 0x80 -#define M6811_OC1D6 0x40 -#define M6811_OC1D5 0x20 -#define M6811_OC1D4 0x10 -#define M6811_OC1D3 0x08 - -/* Flags of the TCTL1 register. */ -#define M6811_OM2 0x80 /* Output Mode 2 */ -#define M6811_OL2 0x40 /* Output Level 2 */ -#define M6811_OM3 0x20 -#define M6811_OL3 0x10 -#define M6811_OM4 0x08 -#define M6811_OL4 0x04 -#define M6811_OM5 0x02 -#define M6811_OL5 0x01 - -/* Flags of the TCTL2 register. */ -#define M6811_EDG1B 0x20 /* Input Edge Capture Control 1 */ -#define M6811_EDG1A 0x10 -#define M6811_EDG2B 0x08 /* Input 2 */ -#define M6811_EDG2A 0x04 -#define M6811_EDG3B 0x02 /* Input 3 */ -#define M6811_EDG3A 0x01 - -/* Flags of the TMSK1 register. */ -#define M6811_OC1I 0x80 /* Output Compare 1 Interrupt */ -#define M6811_OC2I 0x40 /* 2 */ -#define M6811_OC3I 0x20 /* 3 */ -#define M6811_OC4I 0x10 /* 4 */ -#define M6811_OC5I 0x08 /* 5 */ -#define M6811_IC1I 0x04 /* Input Capture 1 Interrupt */ -#define M6811_IC2I 0x02 /* 2 */ -#define M6811_IC3I 0x01 /* 3 */ - -/* Flags of the TFLG1 register. */ -#define M6811_OC1F 0x80 /* Output Compare 1 Flag */ -#define M6811_OC2F 0x40 /* 2 */ -#define M6811_OC3F 0x20 /* 3 */ -#define M6811_OC4F 0x10 /* 4 */ -#define M6811_OC5F 0x08 /* 5 */ -#define M6811_IC1F 0x04 /* Input Capture 1 Flag */ -#define M6811_IC2F 0x02 /* 2 */ -#define M6811_IC3F 0x01 /* 3 */ - -/* Flags of Timer Interrupt Mask Register 2 (TMSK2). */ -#define M6811_TOI 0x80 /* Timer Overflow Interrupt Enable */ -#define M6811_RTII 0x40 /* RTI Interrupt Enable */ -#define M6811_PAOVI 0x20 /* Pulse Accumulator Overflow Interrupt En. */ -#define M6811_PAII 0x10 /* Pulse Accumulator Interrupt Enable */ -#define M6811_PR1 0x02 /* Timer prescaler */ -#define M6811_PR0 0x01 /* Timer prescaler */ -#define M6811_TPR_1 0x00 /* " " prescale div 1 */ -#define M6811_TPR_4 0x01 /* " " prescale div 4 */ -#define M6811_TPR_8 0x02 /* " " prescale div 8 */ -#define M6811_TPR_16 0x03 /* " " prescale div 16 */ - -/* Flags of Timer Interrupt Flag Register 2 (M6811_TFLG2). */ -#define M6811_TOF 0x80 /* Timer overflow bit */ -#define M6811_RTIF 0x40 /* Read time interrupt flag */ -#define M6811_PAOVF 0x20 /* Pulse accumulator overflow Interrupt flag */ -#define M6811_PAIF 0x10 /* Pulse accumulator Input Edge " " " */ - -/* Flags of Pulse Accumulator Control Register (PACTL). */ -#define M6811_DDRA7 0x80 /* Data direction for port A bit 7 */ -#define M6811_PAEN 0x40 /* Pulse accumulator system enable */ -#define M6811_PAMOD 0x20 /* Pulse accumulator mode */ -#define M6811_PEDGE 0x10 /* Pulse accumulator edge control */ -#define M6811_RTR1 0x02 /* RTI Interrupt rates select */ -#define M6811_RTR0 0x01 /* " " " " */ - -/* Flags of the Options register. */ -#define M6811_ADPU 0x80 /* A/D Powerup */ -#define M6811_CSEL 0x40 /* A/D/EE Charge pump clock source select */ -#define M6811_IRQE 0x20 /* IRQ Edge/Level sensitive */ -#define M6811_DLY 0x10 /* Stop exit turn on delay */ -#define M6811_CME 0x08 /* Clock Monitor enable */ -#define M6811_CR1 0x02 /* COP timer rate select */ -#define M6811_CR0 0x01 /* COP timer rate select */ - -/* Flags of the HPRIO register. */ -#define M6811_RBOOT 0x80 /* Read Bootstrap ROM */ -#define M6811_SMOD 0x40 /* Special Mode */ -#define M6811_MDA 0x20 /* Mode Select A */ -#define M6811_IRV 0x10 /* Internal Read Visibility */ -#define M6811_PSEL3 0x08 /* Priority Select */ -#define M6811_PSEL2 0x04 -#define M6811_PSEL1 0x02 -#define M6811_PSEL0 0x01 - -/* Some insns used by gas to turn relative branches into absolute ones. */ -#define M6811_BRA 0x20 -#define M6811_JMP 0x7e -#define M6811_BSR 0x8d -#define M6811_JSR 0xbd -#define M6812_JMP 0x06 -#define M6812_BSR 0x07 -#define M6812_JSR 0x16 - -/* Instruction code pages. Code page 1 is the default. */ -/*#define M6811_OPCODE_PAGE1 0x00*/ -#define M6811_OPCODE_PAGE2 0x18 -#define M6811_OPCODE_PAGE3 0x1A -#define M6811_OPCODE_PAGE4 0xCD - - -/* 68HC11 operands formats as stored in the m6811_opcode table. These - flags do not correspond to anything in the 68HC11 or 68HC12. - They are only used by GAS to recognize operands. */ -#define M6811_OP_NONE 0 /* No operand */ -#define M6811_OP_DIRECT 0x0001 /* Page 0 addressing: *<val-8bits> */ -#define M6811_OP_IMM8 0x0002 /* 8 bits immediat: #<val-8bits> */ -#define M6811_OP_IMM16 0x0004 /* 16 bits immediat: #<val-16bits> */ -#define M6811_OP_IND16 0x0008 /* Indirect abs: <val-16> */ -#define M6812_OP_IND16_P2 0x0010 /* Second parameter indirect abs. */ -#define M6812_OP_REG 0x0020 /* Register operand 1 */ -#define M6812_OP_REG_2 0x0040 /* Register operand 2 */ - -#define M6811_OP_IX 0x0080 /* Indirect IX: <val-8>,x */ -#define M6811_OP_IY 0x0100 /* Indirect IY: <val-8>,y */ -#define M6812_OP_IDX 0x0200 /* Indirect: N,r N,[+-]r[+-] N:5-bits */ -#define M6812_OP_IDX_1 0x0400 /* N,r N:9-bits */ -#define M6812_OP_IDX_2 0x0800 /* N,r N:16-bits */ -#define M6812_OP_D_IDX 0x1000 /* Indirect indexed: [D,r] */ -#define M6812_OP_D_IDX_2 0x2000 /* [N,r] N:16-bits */ -#define M6812_OP_PAGE 0x4000 /* Page number */ -#define M6811_OP_MASK 0x07FFF -#define M6811_OP_BRANCH 0x00008000 /* Branch, jsr, call */ -#define M6811_OP_BITMASK 0x00010000 /* Bitmask: #<val-8> */ -#define M6811_OP_JUMP_REL 0x00020000 /* Pc-Relative: <val-8> */ -#define M6812_OP_JUMP_REL16 0x00040000 /* Pc-relative: <val-16> */ -#define M6811_OP_PAGE1 0x0000 -#define M6811_OP_PAGE2 0x00080000 /* Need a page2 opcode before */ -#define M6811_OP_PAGE3 0x00100000 /* Need a page3 opcode before */ -#define M6811_OP_PAGE4 0x00200000 /* Need a page4 opcode before */ -#define M6811_MAX_OPERANDS 3 /* Max operands: brset <dst> <mask> <b> */ - -#define M6812_ACC_OFFSET 0x00400000 /* A,r B,r D,r */ -#define M6812_ACC_IND 0x00800000 /* [D,r] */ -#define M6812_PRE_INC 0x01000000 /* n,+r n = -8..8 */ -#define M6812_PRE_DEC 0x02000000 /* n,-r */ -#define M6812_POST_INC 0x04000000 /* n,r+ */ -#define M6812_POST_DEC 0x08000000 /* n,r- */ -#define M6812_INDEXED_IND 0x10000000 /* [n,r] n = 16-bits */ -#define M6812_INDEXED 0x20000000 /* n,r n = 5, 9 or 16-bits */ -#define M6812_OP_IDX_P2 0x40000000 - -/* XGATE defines. - These overlap with HC11/12 as above but not used at the same time. */ -#define M68XG_OP_NONE 0x0001 -#define M68XG_OP_IMM3 0x0002 -#define M68XG_OP_R 0x0004 -#define M68XG_OP_R_R 0x0008 -#define M68XG_OP_R_IMM4 0x0010 -#define M68XG_OP_R_R_R 0x0020 -#define M68XG_OP_REL9 0x0040 -#define M68XG_OP_REL10 0x0080 -#define M68XG_OP_R_R_OFFS5 0x0100 -#define M68XG_OP_RD_RB_RI 0x0200 -#define M68XG_OP_RD_RB_RIp 0x0400 -#define M68XG_OP_RD_RB_mRI 0x0800 -#define M68XG_OP_R_IMM8 0x1000 -#define M68XG_OP_R_IMM16 0x2000 -#define M68XG_OP_REG 0x4000 /* Register operand 1. */ -#define M68XG_OP_REG_2 0x8000 /* Register operand 2. */ -#define M68XG_MAX_OPERANDS 3 /* Max operands of triadic r1, r2, r3. */ - -/* Markers to identify some instructions. */ -#define M6812_OP_EXG_MARKER 0x01000000 /* exg r1,r2 */ -#define M6812_OP_TFR_MARKER 0x02000000 /* tfr r1,r2 */ -#define M6812_OP_SEX_MARKER 0x04000000 /* sex r1,r2 */ - -#define M6812_OP_EQ_MARKER 0x80000000 /* dbeq/ibeq/tbeq */ -#define M6812_OP_DBCC_MARKER 0x04000000 /* dbeq/dbne */ -#define M6812_OP_IBCC_MARKER 0x02000000 /* ibeq/ibne */ -#define M6812_OP_TBCC_MARKER 0x01000000 - -/* XGATE markers. */ -#define M68XG_OP_B_MARKER 0x04000000 /* bXX rel9 */ -#define M68XG_OP_BRA_MARKER 0x02000000 /* bra rel10 */ - -#define M6812_OP_TRAP_ID 0x80000000 /* trap #N */ - -#define M6811_OP_HIGH_ADDR 0x01000000 /* Used internally by gas. */ -#define M6811_OP_LOW_ADDR 0x02000000 - -#define M68HC12_BANK_VIRT 0x010000 -#define M68HC12_BANK_MASK 0x00003fff -#define M68HC12_BANK_BASE 0x00008000 -#define M68HC12_BANK_SHIFT 14 -#define M68HC12_BANK_PAGE_MASK 0x0ff - - -/* CPU identification. */ -#define cpu6811 0x01 -#define cpu6812 0x02 -#define cpu6812s 0x04 -#define cpu9s12x 0x08 /* 9S12X main cpu. */ -#define cpuxgate 0x10 /* The XGATE module itself. */ - -/* The opcode table is an array of struct m68hc11_opcode. */ -struct m68hc11_opcode -{ - const char * name; /* Op-code name. */ - long format; - unsigned char size; - unsigned int opcode; - unsigned char cycles_low; - unsigned char cycles_high; - unsigned char set_flags_mask; - unsigned char clr_flags_mask; - unsigned char chg_flags_mask; - unsigned char arch; - unsigned int xg_mask; /* Mask with zero in register place for xgate. */ -}; - -/* Alias definition for 68HC12. */ -struct m68hc12_opcode_alias -{ - const char* name; - const char* translation; - unsigned char size; - unsigned char code1; - unsigned char code2; -}; - -/* The opcode table. The table contains all the opcodes (all pages). - You can't rely on the order. */ -extern const struct m68hc11_opcode m68hc11_opcodes[]; -extern const int m68hc11_num_opcodes; - -/* Alias table for 68HC12. It translates some 68HC11 insn which are not - implemented in 68HC12 but have equivalent translations. */ -extern const struct m68hc12_opcode_alias m68hc12_alias[]; -extern const int m68hc12_num_alias; - -#endif /* _OPCODE_M68HC11_H */ diff --git a/include/opcode/m68k.h b/include/opcode/m68k.h deleted file mode 100644 index f7bd8b4..0000000 --- a/include/opcode/m68k.h +++ /dev/null @@ -1,378 +0,0 @@ -/* Opcode table header for m680[01234]0/m6888[12]/m68851. - Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1999, 2001, - 2003, 2004, 2006, 2010 Free Software Foundation, Inc. - - This file is part of GDB, GAS, and the GNU binutils. - - GDB, GAS, and the GNU binutils are free software; you can redistribute - them and/or modify them under the terms of the GNU General Public - License as published by the Free Software Foundation; either version 3, - or (at your option) any later version. - - GDB, GAS, and the GNU binutils are distributed in the hope that they - will be useful, but WITHOUT ANY WARRANTY; without even the implied - warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See - the GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this file; see the file COPYING3. If not, write to the Free - Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA - 02110-1301, USA. */ - -/* These are used as bit flags for the arch field in the m68k_opcode - structure. */ -#define _m68k_undef 0 -#define m68000 0x001 -#define m68010 0x002 -#define m68020 0x004 -#define m68030 0x008 -#define m68040 0x010 -#define m68060 0x020 -#define m68881 0x040 -#define m68851 0x080 -#define cpu32 0x100 /* e.g., 68332 */ -#define fido_a 0x200 -#define m68k_mask 0x3ff - -#define mcfmac 0x400 /* ColdFire MAC. */ -#define mcfemac 0x800 /* ColdFire EMAC. */ -#define cfloat 0x1000 /* ColdFire FPU. */ -#define mcfhwdiv 0x2000 /* ColdFire hardware divide. */ - -#define mcfisa_a 0x4000 /* ColdFire ISA_A. */ -#define mcfisa_aa 0x8000 /* ColdFire ISA_A+. */ -#define mcfisa_b 0x10000 /* ColdFire ISA_B. */ -#define mcfisa_c 0x20000 /* ColdFire ISA_C. */ -#define mcfusp 0x40000 /* ColdFire USP instructions. */ -#define mcf_mask 0x7e400 - -/* Handy aliases. */ -#define m68040up (m68040 | m68060) -#define m68030up (m68030 | m68040up) -#define m68020up (m68020 | m68030up) -#define m68010up (m68010 | cpu32 | fido_a | m68020up) -#define m68000up (m68000 | m68010up) - -#define mfloat (m68881 | m68040 | m68060) -#define mmmu (m68851 | m68030 | m68040 | m68060) - -/* The structure used to hold information for an opcode. */ - -struct m68k_opcode -{ - /* The opcode name. */ - const char *name; - /* The pseudo-size of the instruction(in bytes). Used to determine - number of bytes necessary to disassemble the instruction. */ - unsigned int size; - /* The opcode itself. */ - unsigned long opcode; - /* The mask used by the disassembler. */ - unsigned long match; - /* The arguments. */ - const char *args; - /* The architectures which support this opcode. */ - unsigned int arch; -}; - -/* The structure used to hold information for an opcode alias. */ - -struct m68k_opcode_alias -{ - /* The alias name. */ - const char *alias; - /* The instruction for which this is an alias. */ - const char *primary; -}; - -/* We store four bytes of opcode for all opcodes because that is the - most any of them need. The actual length of an instruction is - always at least 2 bytes, and is as much longer as necessary to hold - the operands it has. - - The match field is a mask saying which bits must match particular - opcode in order for an instruction to be an instance of that - opcode. - - The args field is a string containing two characters for each - operand of the instruction. The first specifies the kind of - operand; the second, the place it is stored. - - If the first char of args is '.', it indicates that the opcode is - two words. This is only necessary when the match field does not - have any bits set in the second opcode word. Such a '.' is skipped - for operand processing. */ - -/* Kinds of operands: - Characters used: AaBbCcDdEeFfGgHIiJjKkLlMmnOopQqRrSsTtUuVvWwXxYyZz01234|*~%;@!&$?/<>#^+- - - D data register only. Stored as 3 bits. - A address register only. Stored as 3 bits. - a address register indirect only. Stored as 3 bits. - R either kind of register. Stored as 4 bits. - r either kind of register indirect only. Stored as 4 bits. - At the moment, used only for cas2 instruction. - F floating point coprocessor register only. Stored as 3 bits. - O an offset (or width): immediate data 0-31 or data register. - Stored as 6 bits in special format for BF... insns. - + autoincrement only. Stored as 3 bits (number of the address register). - - autodecrement only. Stored as 3 bits (number of the address register). - Q quick immediate data. Stored as 3 bits. - This matches an immediate operand only when value is in range 1 .. 8. - M moveq immediate data. Stored as 8 bits. - This matches an immediate operand only when value is in range -128..127 - T trap vector immediate data. Stored as 4 bits. - - k K-factor for fmove.p instruction. Stored as a 7-bit constant or - a three bit register offset, depending on the field type. - - # immediate data. Stored in special places (b, w or l) - which say how many bits to store. - ^ immediate data for floating point instructions. Special places - are offset by 2 bytes from '#'... - B pc-relative address, converted to an offset - that is treated as immediate data. - d displacement and register. Stores the register as 3 bits - and stores the displacement in the entire second word. - - C the CCR. No need to store it; this is just for filtering validity. - S the SR. No need to store, just as with CCR. - U the USP. No need to store, just as with CCR. - E the MAC ACC. No need to store, just as with CCR. - e the EMAC ACC[0123]. - G the MAC/EMAC MACSR. No need to store, just as with CCR. - g the EMAC ACCEXT{01,23}. - H the MASK. No need to store, just as with CCR. - i the MAC/EMAC scale factor. - - I Coprocessor ID. Not printed if 1. The Coprocessor ID is always - extracted from the 'd' field of word one, which means that an extended - coprocessor opcode can be skipped using the 'i' place, if needed. - - s System Control register for the floating point coprocessor. - - J Misc register for movec instruction, stored in 'j' format. - Possible values: - 0x000 SFC Source Function Code reg [60, 40, 30, 20, 10] - 0x001 DFC Data Function Code reg [60, 40, 30, 20, 10] - 0x002 CACR Cache Control Register [60, 40, 30, 20, mcf] - 0x003 TC MMU Translation Control [60, 40] - 0x004 ITT0 Instruction Transparent - Translation reg 0 [60, 40] - 0x005 ITT1 Instruction Transparent - Translation reg 1 [60, 40] - 0x006 DTT0 Data Transparent - Translation reg 0 [60, 40] - 0x007 DTT1 Data Transparent - Translation reg 1 [60, 40] - 0x008 BUSCR Bus Control Register [60] - 0x800 USP User Stack Pointer [60, 40, 30, 20, 10] - 0x801 VBR Vector Base reg [60, 40, 30, 20, 10, mcf] - 0x802 CAAR Cache Address Register [ 30, 20] - 0x803 MSP Master Stack Pointer [ 40, 30, 20] - 0x804 ISP Interrupt Stack Pointer [ 40, 30, 20] - 0x805 MMUSR MMU Status reg [ 40] - 0x806 URP User Root Pointer [60, 40] - 0x807 SRP Supervisor Root Pointer [60, 40] - 0x808 PCR Processor Configuration reg [60] - 0xC00 ROMBAR ROM Base Address Register [520X] - 0xC04 RAMBAR0 RAM Base Address Register 0 [520X] - 0xC05 RAMBAR1 RAM Base Address Register 0 [520X] - 0xC0F MBAR0 RAM Base Address Register 0 [520X] - 0xC04 FLASHBAR FLASH Base Address Register [mcf528x] - 0xC05 RAMBAR Static RAM Base Address Register [mcf528x] - - L Register list of the type d0-d7/a0-a7 etc. - (New! Improved! Can also hold fp0-fp7, as well!) - The assembler tries to see if the registers match the insn by - looking at where the insn wants them stored. - - l Register list like L, but with all the bits reversed. - Used for going the other way. . . - - c cache identifier which may be "nc" for no cache, "ic" - for instruction cache, "dc" for data cache, or "bc" - for both caches. Used in cinv and cpush. Always - stored in position "d". - - u Any register, with ``upper'' or ``lower'' specification. Used - in the mac instructions with size word. - - The remainder are all stored as 6 bits using an address mode and a - register number; they differ in which addressing modes they match. - - * all (modes 0-6,7.0-4) - ~ alterable memory (modes 2-6,7.0,7.1) - (not 0,1,7.2-4) - % alterable (modes 0-6,7.0,7.1) - (not 7.2-4) - ; data (modes 0,2-6,7.0-4) - (not 1) - @ data, but not immediate (modes 0,2-6,7.0-3) - (not 1,7.4) - ! control (modes 2,5,6,7.0-3) - (not 0,1,3,4,7.4) - & alterable control (modes 2,5,6,7.0,7.1) - (not 0,1,3,4,7.2-4) - $ alterable data (modes 0,2-6,7.0,7.1) - (not 1,7.2-4) - ? alterable control, or data register (modes 0,2,5,6,7.0,7.1) - (not 1,3,4,7.2-4) - / control, or data register (modes 0,2,5,6,7.0-3) - (not 1,3,4,7.4) - > *save operands (modes 2,4,5,6,7.0,7.1) - (not 0,1,3,7.2-4) - < *restore operands (modes 2,3,5,6,7.0-3) - (not 0,1,4,7.4) - - coldfire move operands: - m (modes 0-4) - n (modes 5,7.2) - o (modes 6,7.0,7.1,7.3,7.4) - p (modes 0-5) - - coldfire bset/bclr/btst/mulsl/mulul operands: - q (modes 0,2-5) - v (modes 0,2-5,7.0,7.1) - b (modes 0,2-5,7.2) - w (modes 2-5,7.2) - y (modes 2,5) - z (modes 2,5,7.2) - x mov3q immediate operand. - j coprocessor ET operand. - K coprocessor command number. - 4 (modes 2,3,4,5) - */ - -/* For the 68851: */ -/* I didn't use much imagination in choosing the - following codes, so many of them aren't very - mnemonic. -rab - - 0 32 bit pmmu register - Possible values: - 000 TC Translation Control Register (68030, 68851) - - 1 16 bit pmmu register - 111 AC Access Control (68851) - - 2 8 bit pmmu register - 100 CAL Current Access Level (68851) - 101 VAL Validate Access Level (68851) - 110 SCC Stack Change Control (68851) - - 3 68030-only pmmu registers (32 bit) - 010 TT0 Transparent Translation reg 0 - (aka Access Control reg 0 -- AC0 -- on 68ec030) - 011 TT1 Transparent Translation reg 1 - (aka Access Control reg 1 -- AC1 -- on 68ec030) - - W wide pmmu registers - Possible values: - 001 DRP Dma Root Pointer (68851) - 010 SRP Supervisor Root Pointer (68030, 68851) - 011 CRP Cpu Root Pointer (68030, 68851) - - f function code register (68030, 68851) - 0 SFC - 1 DFC - - V VAL register only (68851) - - X BADx, BACx (16 bit) - 100 BAD Breakpoint Acknowledge Data (68851) - 101 BAC Breakpoint Acknowledge Control (68851) - - Y PSR (68851) (MMUSR on 68030) (ACUSR on 68ec030) - Z PCSR (68851) - - | memory (modes 2-6, 7.*) - - t address test level (68030 only) - Stored as 3 bits, range 0-7. - Also used for breakpoint instruction now. - -*/ - -/* Places to put an operand, for non-general operands: - Characters used: BbCcDdFfGgHhIijkLlMmNnostWw123456789/ - - s source, low bits of first word. - d dest, shifted 9 in first word - 1 second word, shifted 12 - 2 second word, shifted 6 - 3 second word, shifted 0 - 4 third word, shifted 12 - 5 third word, shifted 6 - 6 third word, shifted 0 - 7 second word, shifted 7 - 8 second word, shifted 10 - 9 second word, shifted 5 - E second word, shifted 9 - D store in both place 1 and place 3; for divul and divsl. - B first word, low byte, for branch displacements - W second word (entire), for branch displacements - L second and third words (entire), for branch displacements - (also overloaded for move16) - b second word, low byte - w second word (entire) [variable word/long branch offset for dbra] - W second word (entire) (must be signed 16 bit value) - l second and third word (entire) - g variable branch offset for bra and similar instructions. - The place to store depends on the magnitude of offset. - t store in both place 7 and place 8; for floating point operations - c branch offset for cpBcc operations. - The place to store is word two if bit six of word one is zero, - and words two and three if bit six of word one is one. - i Increment by two, to skip over coprocessor extended operands. Only - works with the 'I' format. - k Dynamic K-factor field. Bits 6-4 of word 2, used as a register number. - Also used for dynamic fmovem instruction. - C floating point coprocessor constant - 7 bits. Also used for static - K-factors... - j Movec register #, stored in 12 low bits of second word. - m For M[S]ACx; 4 bits split with MSB shifted 6 bits in first word - and remaining 3 bits of register shifted 9 bits in first word. - Indicate upper/lower in 1 bit shifted 7 bits in second word. - Use with `R' or `u' format. - n `m' withouth upper/lower indication. (For M[S]ACx; 4 bits split - with MSB shifted 6 bits in first word and remaining 3 bits of - register shifted 9 bits in first word. No upper/lower - indication is done.) Use with `R' or `u' format. - o For M[S]ACw; 4 bits shifted 12 in second word (like `1'). - Indicate upper/lower in 1 bit shifted 7 bits in second word. - Use with `R' or `u' format. - M For M[S]ACw; 4 bits in low bits of first word. Indicate - upper/lower in 1 bit shifted 6 bits in second word. Use with - `R' or `u' format. - N For M[S]ACw; 4 bits in low bits of second word. Indicate - upper/lower in 1 bit shifted 6 bits in second word. Use with - `R' or `u' format. - h shift indicator (scale factor), 1 bit shifted 10 in second word - - Places to put operand, for general operands: - d destination, shifted 6 bits in first word - b source, at low bit of first word, and immediate uses one byte - w source, at low bit of first word, and immediate uses two bytes - l source, at low bit of first word, and immediate uses four bytes - s source, at low bit of first word. - Used sometimes in contexts where immediate is not allowed anyway. - f single precision float, low bit of 1st word, immediate uses 4 bytes - F double precision float, low bit of 1st word, immediate uses 8 bytes - x extended precision float, low bit of 1st word, immediate uses 12 bytes - p packed float, low bit of 1st word, immediate uses 12 bytes - G EMAC accumulator, load (bit 4 2nd word, !bit8 first word) - H EMAC accumulator, non load (bit 4 2nd word, bit 8 first word) - F EMAC ACCx - f EMAC ACCy - I MAC/EMAC scale factor - / Like 's', but set 2nd word, bit 5 if trailing_ampersand set - ] first word, bit 10 -*/ - -extern const struct m68k_opcode m68k_opcodes[]; -extern const struct m68k_opcode_alias m68k_opcode_aliases[]; - -extern const int m68k_numopcodes, m68k_numaliases; - -/* end of m68k-opcode.h */ diff --git a/include/opcode/m88k.h b/include/opcode/m88k.h deleted file mode 100644 index 739c0e9..0000000 --- a/include/opcode/m88k.h +++ /dev/null @@ -1,455 +0,0 @@ -/* Table of opcodes for the Motorola M88k family. - Copyright 1989, 1990, 1991, 1993, 2001, 2002, 2010 - Free Software Foundation, Inc. - - This file is part of GDB and GAS. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, - MA 02110-1301, USA. */ - -/* - * Disassembler Instruction Table - * - * The first field of the table is the opcode field. If an opcode - * is specified which has any non-opcode bits on, a system error - * will occur when the system attempts the install it into the - * instruction table. The second parameter is a pointer to the - * instruction mnemonic. Each operand is specified by offset, width, - * and type. The offset is the bit number of the least significant - * bit of the operand with bit 0 being the least significant bit of - * the instruction. The width is the number of bits used to specify - * the operand. The type specifies the output format to be used for - * the operand. The valid formats are: register, register indirect, - * hex constant, and bit field specification. The last field is a - * pointer to the next instruction in the linked list. These pointers - * are initialized by init_disasm(). - * - * Revision History - * - * Revision 1.0 11/08/85 Creation date - * 1.1 02/05/86 Updated instruction mnemonic table MD - * 1.2 06/16/86 Updated SIM_FLAGS for floating point - * 1.3 09/20/86 Updated for new encoding - * 05/11/89 R. Trawick adapted from Motorola disassembler - */ - -#include <stdio.h> - -/* Define the number of bits in the primary opcode field of the instruction, - the destination field, the source 1 and source 2 fields. */ - -/* Size of opcode field. */ -#define OP 8 - -/* Size of destination. */ -#define DEST 6 - -/* Size of source1. */ -#define SOURCE1 6 - -/* Size of source2. */ -#define SOURCE2 6 - -/* Number of registers. */ -#define REGs 32 - -/* Type definitions. */ - -typedef unsigned int UINT; -#define WORD long -#define FLAG unsigned -#define STATE short - -/* The next four equates define the priorities that the various classes - * of instructions have regarding writing results back into registers and - * signalling exceptions. */ - -/* PMEM is also defined in <sys/param.h> on Delta 88's. Sigh! */ -#undef PMEM - -/* Integer priority. */ -#define PINT 0 - -/* Floating point priority. */ -#define PFLT 1 - -/* Memory priority. */ -#define PMEM 2 - -/* Not applicable, instruction doesn't write to regs. */ -#define NA 3 - -/* Highest of these priorities. */ -#define HIPRI 3 - -/* The instruction registers are an artificial mechanism to speed up - * simulator execution. In the real processor, an instruction register - * is 32 bits wide. In the simulator, the 32 bit instruction is kept in - * a structure field called rawop, and the instruction is partially decoded, - * and split into various fields and flags which make up the other fields - * of the structure. - * The partial decode is done when the instructions are initially loaded - * into simulator memory. The simulator code memory is not an array of - * 32 bit words, but is an array of instruction register structures. - * Yes this wastes memory, but it executes much quicker. - */ - -struct IR_FIELDS -{ - unsigned op:OP, - dest: DEST, - src1: SOURCE1, - src2: SOURCE2; - int ltncy, - extime, - /* Writeback priority. */ - wb_pri; - /* Immediate size. */ - unsigned imm_flags:2, - /* Register source 1 used. */ - rs1_used:1, - /* Register source 2 used. */ - rs2_used:1, - /* Register source/dest. used. */ - rsd_used:1, - /* Complement. */ - c_flag:1, - /* Upper half word. */ - u_flag:1, - /* Execute next. */ - n_flag:1, - /* Uses writeback slot. */ - wb_flag:1, - /* Dest size. */ - dest_64:1, - /* Source 1 size. */ - s1_64:1, - /* Source 2 size. */ - s2_64:1, - scale_flag:1, - /* Scaled register. */ - brk_flg:1; -}; - -struct mem_segs -{ - /* Pointer (returned by calloc) to segment. */ - struct mem_wrd *seg; - - /* Base load address from file headers. */ - unsigned long baseaddr; - - /* Ending address of segment. */ - unsigned long endaddr; - - /* Segment control flags (none defined). */ - int flags; -}; - -#define MAXSEGS (10) /* max number of segment allowed */ -#define MEMSEGSIZE (sizeof(struct mem_segs))/* size of mem_segs structure */ - -#if 0 -#define BRK_RD (0x01) /* break on memory read */ -#define BRK_WR (0x02) /* break on memory write */ -#define BRK_EXEC (0x04) /* break on execution */ -#define BRK_CNT (0x08) /* break on terminal count */ -#endif - -struct mem_wrd -{ - /* Simulator instruction break down. */ - struct IR_FIELDS opcode; - union { - /* Memory element break down. */ - unsigned long l; - unsigned short s[2]; - unsigned char c[4]; - } mem; -}; - -/* Size of each 32 bit memory model. */ -#define MEMWRDSIZE (sizeof (struct mem_wrd)) - -extern struct mem_segs memory[]; -extern struct PROCESSOR m78000; - -struct PROCESSOR -{ - unsigned WORD - /* Execute instruction pointer. */ - ip, - /* Vector base register. */ - vbr, - /* Processor status register. */ - psr; - - /* Source 1. */ - WORD S1bus, - /* Source 2. */ - S2bus, - /* Destination. */ - Dbus, - /* Data address bus. */ - DAbus, - ALU, - /* Data registers. */ - Regs[REGs], - /* Max clocks before reg is available. */ - time_left[REGs], - /* Writeback priority of reg. */ - wb_pri[REGs], - /* Integer unit control regs. */ - SFU0_regs[REGs], - /* Floating point control regs. */ - SFU1_regs[REGs], - Scoreboard[REGs], - Vbr; - unsigned WORD scoreboard, - Psw, - Tpsw; - /* Waiting for a jump instruction. */ - FLAG jump_pending:1; -}; - -/* Size of immediate field. */ - -#define i26bit 1 -#define i16bit 2 -#define i10bit 3 - -/* Definitions for fields in psr. */ - -#define psr_mode 31 -#define psr_rbo 30 -#define psr_ser 29 -#define psr_carry 28 -#define psr_sf7m 11 -#define psr_sf6m 10 -#define psr_sf5m 9 -#define psr_sf4m 8 -#define psr_sf3m 7 -#define psr_sf2m 6 -#define psr_sf1m 5 -#define psr_mam 4 -#define psr_inm 3 -#define psr_exm 2 -#define psr_trm 1 -#define psr_ovfm 0 - -/* The 1 clock operations. */ - -#define ADDU 1 -#define ADDC 2 -#define ADDUC 3 -#define ADD 4 - -#define SUBU ADD+1 -#define SUBB ADD+2 -#define SUBUB ADD+3 -#define SUB ADD+4 - -#define AND_ ADD+5 -#define OR ADD+6 -#define XOR ADD+7 -#define CMP ADD+8 - -/* Loads. */ - -#define LDAB CMP+1 -#define LDAH CMP+2 -#define LDA CMP+3 -#define LDAD CMP+4 - -#define LDB LDAD+1 -#define LDH LDAD+2 -#define LD LDAD+3 -#define LDD LDAD+4 -#define LDBU LDAD+5 -#define LDHU LDAD+6 - -/* Stores. */ - -#define STB LDHU+1 -#define STH LDHU+2 -#define ST LDHU+3 -#define STD LDHU+4 - -/* Exchange. */ - -#define XMEMBU LDHU+5 -#define XMEM LDHU+6 - -/* Branches. */ - -#define JSR STD+1 -#define BSR STD+2 -#define BR STD+3 -#define JMP STD+4 -#define BB1 STD+5 -#define BB0 STD+6 -#define RTN STD+7 -#define BCND STD+8 - -/* Traps. */ - -#define TB1 BCND+1 -#define TB0 BCND+2 -#define TCND BCND+3 -#define RTE BCND+4 -#define TBND BCND+5 - -/* Misc. */ - -#define MUL TBND + 1 -#define DIV MUL +2 -#define DIVU MUL +3 -#define MASK MUL +4 -#define FF0 MUL +5 -#define FF1 MUL +6 -#define CLR MUL +7 -#define SET MUL +8 -#define EXT MUL +9 -#define EXTU MUL +10 -#define MAK MUL +11 -#define ROT MUL +12 - -/* Control register manipulations. */ - -#define LDCR ROT +1 -#define STCR ROT +2 -#define XCR ROT +3 - -#define FLDCR ROT +4 -#define FSTCR ROT +5 -#define FXCR ROT +6 - -#define NOP XCR +1 - -/* Floating point instructions. */ - -#define FADD NOP +1 -#define FSUB NOP +2 -#define FMUL NOP +3 -#define FDIV NOP +4 -#define FSQRT NOP +5 -#define FCMP NOP +6 -#define FIP NOP +7 -#define FLT NOP +8 -#define INT NOP +9 -#define NINT NOP +10 -#define TRNC NOP +11 -#define FLDC NOP +12 -#define FSTC NOP +13 -#define FXC NOP +14 - -#define UEXT(src,off,wid) \ - ((((unsigned int)(src)) >> (off)) & ((1 << (wid)) - 1)) - -#define SEXT(src,off,wid) \ - (((((int)(src))<<(32 - ((off) + (wid)))) >>(32 - (wid))) ) - -#define MAKE(src,off,wid) \ - ((((unsigned int)(src)) & ((1 << (wid)) - 1)) << (off)) - -#define opword(n) (unsigned long) (memaddr->mem.l) - -/* Constants and masks. */ - -#define SFU0 0x80000000 -#define SFU1 0x84000000 -#define SFU7 0x9c000000 -#define RRI10 0xf0000000 -#define RRR 0xf4000000 -#define SFUMASK 0xfc00ffe0 -#define RRRMASK 0xfc00ffe0 -#define RRI10MASK 0xfc00fc00 -#define DEFMASK 0xfc000000 -#define CTRL 0x0000f000 -#define CTRLMASK 0xfc00f800 - -/* Operands types. */ - -enum operand_type -{ - HEX = 1, - REG = 2, - CONT = 3, - IND = 3, - BF = 4, - /* Scaled register. */ - REGSC = 5, - /* Control register. */ - CRREG = 6, - /* Floating point control register. */ - FCRREG = 7, - PCREL = 8, - CONDMASK = 9, - /* Extended register. */ - XREG = 10, - /* Decimal. */ - DEC = 11 -}; - -/* Hashing specification. */ - -#define HASHVAL 79 - -/* Structure templates. */ - -typedef struct -{ - unsigned int offset; - unsigned int width; - enum operand_type type; -} OPSPEC; - -struct SIM_FLAGS -{ - int ltncy, /* latency (max number of clocks needed to execute). */ - extime, /* execution time (min number of clocks needed to execute). */ - wb_pri; /* writeback slot priority. */ - unsigned op:OP, /* simulator version of opcode. */ - imm_flags:2, /* 10,16 or 26 bit immediate flags. */ - rs1_used:1, /* register source 1 used. */ - rs2_used:1, /* register source 2 used. */ - rsd_used:1, /* register source/dest used. */ - c_flag:1, /* complement. */ - u_flag:1, /* upper half word. */ - n_flag:1, /* execute next. */ - wb_flag:1, /* uses writeback slot. */ - dest_64:1, /* double precision dest. */ - s1_64:1, /* double precision source 1. */ - s2_64:1, /* double precision source 2. */ - scale_flag:1; /* register is scaled. */ -}; - -typedef struct INSTRUCTAB { - unsigned int opcode; - char *mnemonic; - OPSPEC op1,op2,op3; - struct SIM_FLAGS flgs; -} INSTAB; - - -#define NO_OPERAND {0,0,0} - -extern const INSTAB instructions[]; - -/* - * Local Variables: - * fill-column: 131 - * End: - */ diff --git a/include/opcode/metag.h b/include/opcode/metag.h deleted file mode 100644 index c9bb668..0000000 --- a/include/opcode/metag.h +++ /dev/null @@ -1,2079 +0,0 @@ -/* Imagination Technologies Meta opcode table. - Copyright (C) 2013 Free Software Foundation, Inc. - Contributed by Imagination Technologies Ltd. - - This file is part of GDB and GAS. - - GDB and GAS are free software; you can redistribute it and/or - modify it under the terms of the GNU General Public License as - published by the Free Software Foundation; either version 3, or (at - your option) any later version. - - GDB and GAS are distributed in the hope that it will be useful, but - WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - General Public License for more details. - - You should have received a copy of the GNU General Public License - along with GDB or GAS; see the file COPYING3. If not, write to the - Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, - MA 02110-1301, USA. */ - -enum metag_unit -{ - UNIT_CT, - UNIT_D0, - UNIT_D1, - UNIT_A0, - UNIT_A1, - UNIT_PC, - UNIT_RD, - UNIT_TR, - UNIT_TT, - UNIT_FX, - UNIT_DT, /* DSP Template Table */ - UNIT_ACC_D0, - UNIT_ACC_D1, - UNIT_RAM_D0, - UNIT_RAM_D1, -}; - -typedef struct -{ - const char * name; - enum metag_unit unit; - unsigned int no; -} metag_reg; - -static const metag_reg metag_regtab[] = - { - { "TXENABLE", UNIT_CT, 0 }, - { "CT.0", UNIT_CT, 0 }, - { "TXMODE", UNIT_CT, 1 }, - { "CT.1", UNIT_CT, 1 }, - { "TXSTATUS", UNIT_CT, 2 }, - { "CT.2", UNIT_CT, 2 }, - { "TXRPT", UNIT_CT, 3 }, - { "CT.3", UNIT_CT, 3 }, - { "TXTIMER", UNIT_CT, 4 }, - { "CT.4", UNIT_CT, 4 }, - { "TXL1START", UNIT_CT, 5 }, - { "CT.5", UNIT_CT, 5 }, - { "TXL1END", UNIT_CT, 6 }, - { "CT.6", UNIT_CT, 6 }, - { "TXL1COUNT", UNIT_CT, 7 }, - { "CT.7", UNIT_CT, 7 }, - { "TXL2START", UNIT_CT, 8 }, - { "CT.8", UNIT_CT, 8 }, - { "TXL2END", UNIT_CT, 9 }, - { "CT.9", UNIT_CT, 9 }, - { "TXL2COUNT", UNIT_CT, 10 }, - { "CT.10", UNIT_CT, 10 }, - { "TXBPOBITS", UNIT_CT, 11 }, - { "CT.11", UNIT_CT, 11 }, - { "TXMRSIZE", UNIT_CT, 12 }, - { "CT.12", UNIT_CT, 12 }, - { "TXTIMERI", UNIT_CT, 13 }, - { "CT.13", UNIT_CT, 13 }, - { "TXDRCTRL", UNIT_CT, 14 }, - { "CT.14", UNIT_CT, 14 }, - { "TXDRSIZE", UNIT_CT, 15 }, - { "CT.15", UNIT_CT, 15 }, - { "TXCATCH0", UNIT_CT, 16 }, - { "CT.16", UNIT_CT, 16 }, - { "TXCATCH1", UNIT_CT, 17 }, - { "CT.17", UNIT_CT, 17 }, - { "TXCATCH2", UNIT_CT, 18 }, - { "CT.18", UNIT_CT, 18 }, - { "TXCATCH3", UNIT_CT, 19 }, - { "CT.19", UNIT_CT, 19 }, - { "TXDEFR", UNIT_CT, 20 }, - { "CT.20", UNIT_CT, 20 }, - { "TXCPRS", UNIT_CT, 21 }, - { "CT.21", UNIT_CT, 21 }, - { "TXCLKCTRL", UNIT_CT, 22 }, - { "CT.22", UNIT_CT, 22 }, - { "TXINTERN0", UNIT_CT, 23 }, - { "TXSTATE", UNIT_CT, 23 }, - { "CT.23", UNIT_CT, 23 }, - { "TXAMAREG0", UNIT_CT, 24 }, - { "CT.24", UNIT_CT, 24 }, - { "TXAMAREG1", UNIT_CT, 25 }, - { "CT.25", UNIT_CT, 25 }, - { "TXAMAREG2", UNIT_CT, 26 }, - { "CT.26", UNIT_CT, 26 }, - { "TXAMAREG3", UNIT_CT, 27 }, - { "CT.27", UNIT_CT, 27 }, - { "TXDIVTIME", UNIT_CT, 28 }, - { "CT.28", UNIT_CT, 28 }, - { "TXPRIVEXT", UNIT_CT, 29 }, - { "CT.29", UNIT_CT, 29 }, - { "TXTACTCYC", UNIT_CT, 30 }, - { "TXACTCYC", UNIT_CT, 30 }, - { "CT.30", UNIT_CT, 30 }, - { "TXIDLECYC", UNIT_CT, 31 }, - { "CT.31", UNIT_CT, 31 }, - - { "D0Re0", UNIT_D0, 0 }, - { "D0.0", UNIT_D0, 0 }, - { "D0Ar6", UNIT_D0, 1 }, - { "D0.1", UNIT_D0, 1 }, - { "D0Ar4", UNIT_D0, 2 }, - { "D0.2", UNIT_D0, 2 }, - { "D0Ar2", UNIT_D0, 3 }, - { "D0.3", UNIT_D0, 3 }, - { "D0FrT", UNIT_D0, 4 }, - { "D0.4", UNIT_D0, 4 }, - { "D0.5", UNIT_D0, 5 }, - { "D0.6", UNIT_D0, 6 }, - { "D0.7", UNIT_D0, 7 }, - { "D0.8", UNIT_D0, 8 }, - { "D0.9", UNIT_D0, 9 }, - { "D0.10", UNIT_D0, 10 }, - { "D0.11", UNIT_D0, 11 }, - { "D0.12", UNIT_D0, 12 }, - { "D0.13", UNIT_D0, 13 }, - { "D0.14", UNIT_D0, 14 }, - { "D0.15", UNIT_D0, 15 }, - { "D0.16", UNIT_D0, 16 }, - { "D0.17", UNIT_D0, 17 }, - { "D0.18", UNIT_D0, 18 }, - { "D0.19", UNIT_D0, 19 }, - { "D0.20", UNIT_D0, 20 }, - { "D0.21", UNIT_D0, 21 }, - { "D0.22", UNIT_D0, 22 }, - { "D0.23", UNIT_D0, 23 }, - { "D0.24", UNIT_D0, 24 }, - { "D0.25", UNIT_D0, 25 }, - { "D0.26", UNIT_D0, 26 }, - { "D0.27", UNIT_D0, 27 }, - { "D0.28", UNIT_D0, 28 }, - { "D0.29", UNIT_D0, 29 }, - { "D0.30", UNIT_D0, 30 }, - { "D0.31", UNIT_D0, 31 }, - - { "D1Re0", UNIT_D1, 0 }, - { "D1.0", UNIT_D1, 0 }, - { "D1Ar5", UNIT_D1, 1 }, - { "D1.1", UNIT_D1, 1 }, - { "D1Ar3", UNIT_D1, 2 }, - { "D1.2", UNIT_D1, 2 }, - { "D1Ar1", UNIT_D1, 3 }, - { "D1.3", UNIT_D1, 3 }, - { "D1RtP", UNIT_D1, 4 }, - { "D1.4", UNIT_D1, 4 }, - { "D1.5", UNIT_D1, 5 }, - { "D1.6", UNIT_D1, 6 }, - { "D1.7", UNIT_D1, 7 }, - { "D1.8", UNIT_D1, 8 }, - { "D1.9", UNIT_D1, 9 }, - { "D1.10", UNIT_D1, 10 }, - { "D1.11", UNIT_D1, 11 }, - { "D1.12", UNIT_D1, 12 }, - { "D1.13", UNIT_D1, 13 }, - { "D1.14", UNIT_D1, 14 }, - { "D1.15", UNIT_D1, 15 }, - { "D1.16", UNIT_D1, 16 }, - { "D1.17", UNIT_D1, 17 }, - { "D1.18", UNIT_D1, 18 }, - { "D1.19", UNIT_D1, 19 }, - { "D1.20", UNIT_D1, 20 }, - { "D1.21", UNIT_D1, 21 }, - { "D1.22", UNIT_D1, 22 }, - { "D1.23", UNIT_D1, 23 }, - { "D1.24", UNIT_D1, 24 }, - { "D1.25", UNIT_D1, 25 }, - { "D1.26", UNIT_D1, 26 }, - { "D1.27", UNIT_D1, 27 }, - { "D1.28", UNIT_D1, 28 }, - { "D1.29", UNIT_D1, 29 }, - { "D1.30", UNIT_D1, 30 }, - { "D1.31", UNIT_D1, 31 }, - - { "A0StP", UNIT_A0, 0 }, - { "A0.0", UNIT_A0, 0 }, - { "A0FrP", UNIT_A0, 1 }, - { "A0.1", UNIT_A0, 1 }, - { "A0.2", UNIT_A0, 2 }, - { "A0.3", UNIT_A0, 3 }, - { "A0.4", UNIT_A0, 4 }, - { "A0.5", UNIT_A0, 5 }, - { "A0.6", UNIT_A0, 6 }, - { "A0.7", UNIT_A0, 7 }, - { "A0.8", UNIT_A0, 8 }, - { "A0.9", UNIT_A0, 9 }, - { "A0.10", UNIT_A0, 10 }, - { "A0.11", UNIT_A0, 11 }, - { "A0.12", UNIT_A0, 12 }, - { "A0.13", UNIT_A0, 13 }, - { "A0.14", UNIT_A0, 14 }, - { "A0.15", UNIT_A0, 15 }, - { "CPC0", UNIT_A0, 16 }, - - { "A1GbP", UNIT_A1, 0 }, - { "A1.0", UNIT_A1, 0 }, - { "A1LbP", UNIT_A1, 1 }, - { "A1.1", UNIT_A1, 1 }, - { "A1.2", UNIT_A1, 2 }, - { "A1.3", UNIT_A1, 3 }, - { "A1.4", UNIT_A1, 4 }, - { "A1.5", UNIT_A1, 5 }, - { "A1.6", UNIT_A1, 6 }, - { "A1.7", UNIT_A1, 7 }, - { "A1.8", UNIT_A1, 8 }, - { "A1.9", UNIT_A1, 9 }, - { "A1.10", UNIT_A1, 10 }, - { "A1.11", UNIT_A1, 11 }, - { "A1.12", UNIT_A1, 12 }, - { "A1.13", UNIT_A1, 13 }, - { "A1.14", UNIT_A1, 14 }, - { "A1.15", UNIT_A1, 15 }, - { "CPC1", UNIT_A1, 16 }, - - { "PC", UNIT_PC, 0 }, - { "PCX", UNIT_PC, 1 }, - - { "RD", UNIT_RD, 0 }, - { "RA", UNIT_RD, 16 }, - { "RD", UNIT_RD, 16 }, - { "RAPF", UNIT_RD, 17 }, - { "RAM8X32", UNIT_RD, 22 }, - { "RAM8X", UNIT_RD, 23 }, - { "RABZ", UNIT_RD, 24 }, - { "RAWZ", UNIT_RD, 25 }, - { "RADZ", UNIT_RD, 26 }, - { "RABX", UNIT_RD, 28 }, - { "RAWX", UNIT_RD, 29 }, - { "RADX", UNIT_RD, 30 }, - { "RAMX", UNIT_RD, 31 }, - { "RAM16X", UNIT_RD, 31 }, - - { "TXSTAT", UNIT_TR, 0 }, - { "TR.0", UNIT_TR, 0 }, - { "TXMASK", UNIT_TR, 1 }, - { "TR.1", UNIT_TR, 1 }, - { "TXSTATI", UNIT_TR, 2 }, - { "TR.2", UNIT_TR, 2 }, - { "TXMASKI", UNIT_TR, 3 }, - { "TR.3", UNIT_TR, 3 }, - { "TXPOLL", UNIT_TR, 4 }, - { "TR.4", UNIT_TR, 4 }, - { "TXGPIOI", UNIT_TR, 5 }, - { "TR.5", UNIT_TR, 5 }, - { "TXPOLLI", UNIT_TR, 6 }, - { "TR.6", UNIT_TR, 6 }, - { "TXGPIOO", UNIT_TR, 7 }, - { "TR.7", UNIT_TR, 7 }, - - { "TTEXEC", UNIT_TT, 0 }, - { "TT.0", UNIT_TT, 0 }, - { "TTCTRL", UNIT_TT, 1 }, - { "TT.1", UNIT_TT, 1 }, - { "TTMARK", UNIT_TT, 2 }, - { "TT.2", UNIT_TT, 2 }, - { "TTREC", UNIT_TT, 3 }, - { "TT.3", UNIT_TT, 3 }, - { "GTEXEC", UNIT_TT, 4 }, - { "TT.4", UNIT_TT, 4 }, - - { "FX.0", UNIT_FX, 0 }, - { "FX.1", UNIT_FX, 1 }, - { "FX.2", UNIT_FX, 2 }, - { "FX.3", UNIT_FX, 3 }, - { "FX.4", UNIT_FX, 4 }, - { "FX.5", UNIT_FX, 5 }, - { "FX.6", UNIT_FX, 6 }, - { "FX.7", UNIT_FX, 7 }, - { "FX.8", UNIT_FX, 8 }, - { "FX.9", UNIT_FX, 9 }, - { "FX.10", UNIT_FX, 10 }, - { "FX.11", UNIT_FX, 11 }, - { "FX.12", UNIT_FX, 12 }, - { "FX.13", UNIT_FX, 13 }, - { "FX.14", UNIT_FX, 14 }, - { "FX.15", UNIT_FX, 15 }, - }; - -static const metag_reg metag_dsp_regtab[] = - { - { "D0AR.0", UNIT_RAM_D0, 0 }, - { "D0AR.1", UNIT_RAM_D0, 1 }, - { "D0AW.0", UNIT_RAM_D0, 2 }, - { "D0AW.1", UNIT_RAM_D0, 3 }, - { "D0BR.0", UNIT_RAM_D0, 4 }, - { "D0BR.1", UNIT_RAM_D0, 5 }, - { "D0BW.0", UNIT_RAM_D0, 6 }, - { "D0BW.1", UNIT_RAM_D0, 7 }, - { "D0ARI.0", UNIT_RAM_D0, 8 }, - { "D0ARI.1", UNIT_RAM_D0, 9 }, - { "D0AWI.0", UNIT_RAM_D0, 10 }, - { "D0AWI.1", UNIT_RAM_D0, 11 }, - { "D0BRI.0", UNIT_RAM_D0, 12 }, - { "D0BRI.1", UNIT_RAM_D0, 13 }, - { "D0BWI.0", UNIT_RAM_D0, 14 }, - { "D0BWI.1", UNIT_RAM_D0, 15 }, - - { "AC0.0", UNIT_ACC_D0, 16 }, - { "AC0.1", UNIT_ACC_D0, 17 }, - { "AC0.2", UNIT_ACC_D0, 18 }, - { "AC0.3", UNIT_ACC_D0, 19 }, - - { "D1AR.0", UNIT_RAM_D1, 0 }, - { "D1AR.1", UNIT_RAM_D1, 1 }, - { "D1AW.0", UNIT_RAM_D1, 2 }, - { "D1AW.1", UNIT_RAM_D1, 3 }, - { "D1BR.0", UNIT_RAM_D1, 4 }, - { "D1BR.1", UNIT_RAM_D1, 5 }, - { "D1BW.0", UNIT_RAM_D1, 6 }, - { "D1BW.1", UNIT_RAM_D1, 7 }, - { "D1ARI.0", UNIT_RAM_D1, 8 }, - { "D1ARI.1", UNIT_RAM_D1, 9 }, - { "D1AWI.0", UNIT_RAM_D1, 10 }, - { "D1AWI.1", UNIT_RAM_D1, 11 }, - { "D1BRI.0", UNIT_RAM_D1, 12 }, - { "D1BRI.1", UNIT_RAM_D1, 13 }, - { "D1BWI.0", UNIT_RAM_D1, 14 }, - { "D1BWI.1", UNIT_RAM_D1, 15 }, - - { "AC1.0", UNIT_ACC_D1, 16 }, - { "AC1.1", UNIT_ACC_D1, 17 }, - { "AC1.2", UNIT_ACC_D1, 18 }, - { "AC1.3", UNIT_ACC_D1, 19 }, - - { "T0", UNIT_DT, 0 }, - { "T1", UNIT_DT, 1 }, - { "T2", UNIT_DT, 2 }, - { "T3", UNIT_DT, 3 }, - { "T4", UNIT_DT, 4 }, - { "T5", UNIT_DT, 5 }, - { "T6", UNIT_DT, 6 }, - { "T7", UNIT_DT, 7 }, - { "T8", UNIT_DT, 8 }, - { "T9", UNIT_DT, 9 }, - { "TA", UNIT_DT, 10 }, - { "TB", UNIT_DT, 11 }, - { "TC", UNIT_DT, 12 }, - { "TD", UNIT_DT, 13 }, - { "TE", UNIT_DT, 14 }, - { "TF", UNIT_DT, 15 }, - }; - -/* This table differs from 'metag_dsp_regtab' in that the number - fields in this table are suitable for insertion into DSPRAM - template definition instruction encodings. - - The table is indexed by "load". The main benefit of this is that we - can implicitly check that the correct DSPRAM register has been used - when parsing, e.g. the read pointer only appears in the load table - and the write pointer only exists in the store table. - - The ordering of the table entries might look a bit weird but it is - based on matching the longest register string. */ -static const metag_reg metag_dsp_tmpl_regtab[2][56] = - { - { - { "D0AW.0+D0AWI.0++", UNIT_RAM_D0, 18 }, - { "D0AW.0+D0AWI.0", UNIT_RAM_D0, 18 }, - { "D0AW.0+D0AWI.1++", UNIT_RAM_D0, 19 }, - { "D0AW.0+D0AWI.1", UNIT_RAM_D0, 19 }, - { "D0AW.0++", UNIT_RAM_D0, 17 }, - { "D0AW.0", UNIT_RAM_D0, 16 }, - { "D0AWI.0", UNIT_RAM_D0, 18 }, - { "D0AWI.1", UNIT_RAM_D0, 19 }, - { "D0AW.1+D0AWI.0++", UNIT_RAM_D0, 22 }, - { "D0AW.1+D0AWI.0", UNIT_RAM_D0, 22 }, - { "D0AW.1+D0AWI.1++", UNIT_RAM_D0, 23 }, - { "D0AW.1+D0AWI.1", UNIT_RAM_D0, 23 }, - { "D0AW.1++", UNIT_RAM_D0, 21 }, - { "D0AW.1", UNIT_RAM_D0, 20 }, - { "D0BW.0+D0BWI.0++", UNIT_RAM_D0, 26 }, - { "D0BW.0+D0BWI.0", UNIT_RAM_D0, 26 }, - { "D0BW.0+D0BWI.1++", UNIT_RAM_D0, 27 }, - { "D0BW.0+D0BWI.1", UNIT_RAM_D0, 27 }, - { "D0BW.0++", UNIT_RAM_D0, 25 }, - { "D0BW.0", UNIT_RAM_D0, 24 }, - { "D0BWI.0", UNIT_RAM_D0, 18 }, - { "D0BWI.1", UNIT_RAM_D0, 19 }, - { "D0BW.1+D0BWI.0++", UNIT_RAM_D0, 30 }, - { "D0BW.1+D0BWI.0", UNIT_RAM_D0, 30 }, - { "D0BW.1+D0BWI.1++", UNIT_RAM_D0, 31 }, - { "D0BW.1+D0BWI.1", UNIT_RAM_D0, 31 }, - { "D0BW.1++", UNIT_RAM_D0, 29 }, - { "D0BW.1", UNIT_RAM_D0, 28 }, - - { "D1AW.0+D1AWI.0++", UNIT_RAM_D1, 18 }, - { "D1AW.0+D1AWI.0", UNIT_RAM_D1, 18 }, - { "D1AW.0+D1AWI.1++", UNIT_RAM_D1, 19 }, - { "D1AW.0+D1AWI.1", UNIT_RAM_D1, 19 }, - { "D1AW.0++", UNIT_RAM_D1, 17 }, - { "D1AW.0", UNIT_RAM_D1, 16 }, - { "D1AWI.0", UNIT_RAM_D1, 18 }, - { "D1AWI.1", UNIT_RAM_D1, 19 }, - { "D1AW.1+D1AWI.0++", UNIT_RAM_D1, 22 }, - { "D1AW.1+D1AWI.0", UNIT_RAM_D1, 22 }, - { "D1AW.1+D1AWI.1++", UNIT_RAM_D1, 23 }, - { "D1AW.1+D1AWI.1", UNIT_RAM_D1, 23 }, - { "D1AW.1++", UNIT_RAM_D1, 21 }, - { "D1AW.1", UNIT_RAM_D1, 20 }, - { "D1BW.0+D1BWI.0++", UNIT_RAM_D1, 26 }, - { "D1BW.0+D1BWI.0", UNIT_RAM_D1, 26 }, - { "D1BW.0+D1BWI.1++", UNIT_RAM_D1, 27 }, - { "D1BW.0+D1BWI.1", UNIT_RAM_D1, 27 }, - { "D1BW.0++", UNIT_RAM_D1, 25 }, - { "D1BW.0", UNIT_RAM_D1, 24 }, - { "D1BWI.0", UNIT_RAM_D1, 18 }, - { "D1BWI.1", UNIT_RAM_D1, 19 }, - { "D1BW.1+D1BWI.0++", UNIT_RAM_D1, 30 }, - { "D1BW.1+D1BWI.0", UNIT_RAM_D1, 30 }, - { "D1BW.1+D1BWI.1++", UNIT_RAM_D1, 31 }, - { "D1BW.1+D1BWI.1", UNIT_RAM_D1, 31 }, - { "D1BW.1++", UNIT_RAM_D1, 29 }, - { "D1BW.1", UNIT_RAM_D1, 28 }, - }, - - { - { "D0AR.0+D0ARI.0++", UNIT_RAM_D0, 18 }, - { "D0AR.0+D0ARI.0", UNIT_RAM_D0, 18 }, - { "D0AR.0+D0ARI.1++", UNIT_RAM_D0, 19 }, - { "D0AR.0+D0ARI.1", UNIT_RAM_D0, 19 }, - { "D0AR.0++", UNIT_RAM_D0, 17 }, - { "D0AR.0", UNIT_RAM_D0, 16 }, - { "D0ARI.0", UNIT_RAM_D0, 18 }, - { "D0ARI.1", UNIT_RAM_D0, 19 }, - { "D0AR.1+D0ARI.0++", UNIT_RAM_D0, 22 }, - { "D0AR.1+D0ARI.0", UNIT_RAM_D0, 22 }, - { "D0AR.1+D0ARI.1++", UNIT_RAM_D0, 23 }, - { "D0AR.1+D0ARI.1", UNIT_RAM_D0, 23 }, - { "D0AR.1++", UNIT_RAM_D0, 21 }, - { "D0AR.1", UNIT_RAM_D0, 20 }, - { "D0BR.0+D0BRI.0++", UNIT_RAM_D0, 26 }, - { "D0BR.0+D0BRI.0", UNIT_RAM_D0, 26 }, - { "D0BR.0+D0BRI.1++", UNIT_RAM_D0, 27 }, - { "D0BR.0+D0BRI.1", UNIT_RAM_D0, 27 }, - { "D0BR.0++", UNIT_RAM_D0, 25 }, - { "D0BR.0", UNIT_RAM_D0, 24 }, - { "D0BRI.0", UNIT_RAM_D0, 18 }, - { "D0BRI.1", UNIT_RAM_D0, 19 }, - { "D0BR.1+D0BRI.0++", UNIT_RAM_D0, 30 }, - { "D0BR.1+D0BRI.0", UNIT_RAM_D0, 30 }, - { "D0BR.1+D0BRI.1++", UNIT_RAM_D0, 31 }, - { "D0BR.1+D0BRI.1", UNIT_RAM_D0, 31 }, - { "D0BR.1++", UNIT_RAM_D0, 29 }, - { "D0BR.1", UNIT_RAM_D0, 28 }, - - { "D1AR.0+D1ARI.0++", UNIT_RAM_D1, 18 }, - { "D1AR.0+D1ARI.0", UNIT_RAM_D1, 18 }, - { "D1AR.0+D1ARI.1++", UNIT_RAM_D1, 19 }, - { "D1AR.0+D1ARI.1", UNIT_RAM_D1, 19 }, - { "D1AR.0++", UNIT_RAM_D1, 17 }, - { "D1AR.0", UNIT_RAM_D1, 16 }, - { "D1ARI.0", UNIT_RAM_D1, 18 }, - { "D1ARI.1", UNIT_RAM_D1, 19 }, - { "D1AR.1+D1ARI.0++", UNIT_RAM_D1, 22 }, - { "D1AR.1+D1ARI.0", UNIT_RAM_D1, 22 }, - { "D1AR.1+D1ARI.1++", UNIT_RAM_D1, 23 }, - { "D1AR.1+D1ARI.1", UNIT_RAM_D1, 23 }, - { "D1AR.1++", UNIT_RAM_D1, 21 }, - { "D1AR.1", UNIT_RAM_D1, 20 }, - { "D1BR.0+D1BRI.0++", UNIT_RAM_D1, 26 }, - { "D1BR.0+D1BRI.0", UNIT_RAM_D1, 26 }, - { "D1BR.0+D1BRI.1++", UNIT_RAM_D1, 27 }, - { "D1BR.0+D1BRI.1", UNIT_RAM_D1, 27 }, - { "D1BR.0++", UNIT_RAM_D1, 25 }, - { "D1BR.0", UNIT_RAM_D1, 24 }, - { "D1BR.1+D1BRI.0++", UNIT_RAM_D1, 30 }, - { "D1BR.1+D1BRI.0", UNIT_RAM_D1, 30 }, - { "D1BR.1+D1BRI.1++", UNIT_RAM_D1, 31 }, - { "D1BR.1+D1BRI.1", UNIT_RAM_D1, 31 }, - { "D1BR.1++", UNIT_RAM_D1, 29 }, - { "D1BR.1", UNIT_RAM_D1, 28 }, - { "D1BRI.0", UNIT_RAM_D1, 18 }, - { "D1BRI.1", UNIT_RAM_D1, 19 }, - }, - }; - -typedef struct -{ - const char * name; - unsigned int part; -} metag_acf; - -static const metag_acf metag_acftab[] = - { - { "ACF.0", 0}, - { "ACF.1", 1}, - { "ACF.2", 2}, - { "ACF.3", 3}, - }; - -enum insn_encoding -{ - ENC_NONE, - ENC_MOV_U2U, - ENC_MOV_PORT, - ENC_MMOV, - ENC_MDRD, - ENC_MOVL_TTREC, - ENC_GET_SET, - ENC_GET_SET_EXT, - ENC_MGET_MSET, - ENC_COND_SET, - ENC_XFR, - ENC_MOV_CT, - ENC_SWAP, - ENC_JUMP, - ENC_CALLR, - ENC_ALU, - ENC_SHIFT, - ENC_MIN_MAX, - ENC_BITOP, - ENC_CMP, - ENC_BRANCH, - ENC_KICK, - ENC_SWITCH, - ENC_CACHER, - ENC_CACHEW, - ENC_ICACHE, - ENC_LNKGET, - ENC_FMOV, - ENC_FMMOV, - ENC_FMOV_DATA, - ENC_FMOV_I, - ENC_FPACK, - ENC_FSWAP, - ENC_FCMP, - ENC_FMINMAX, - ENC_FCONV, - ENC_FCONVX, - ENC_FBARITH, - ENC_FEARITH, - ENC_FREC, - ENC_FSIMD, - ENC_FGET_SET_ACF, - ENC_DGET_SET, - ENC_DTEMPLATE, - ENC_DALU, - ENC_MAX, -}; - -enum insn_type -{ - INSN_GP, - INSN_FPU, - INSN_DSP, - INSN_DSP_FPU, -}; - -typedef struct -{ - const char *name; - - unsigned int core_flags; -#define CoreMeta11 0x1 /* The earliest Meta core we support */ -#define CoreMeta12 0x2 -#define CoreMeta21 0x4 - -#define FpuMeta21 0x21 - -#define DspMeta21 0x100 - - unsigned int meta_opcode; - unsigned int meta_mask; - - enum insn_type insn_type; - - enum insn_encoding encoding; - -#define DSP_ARGS_1 0x0000001 /* De.r,Dx.r,De.r (3 register operands) */ -#define DSP_ARGS_ACC2 0x0000002 /* Accumulator source operand 2 */ -#define DSP_ARGS_QR 0x0000004 /* QUICKRoT */ -#define DSP_ARGS_XACC 0x0000008 /* Cross-unit accumulator op */ -#define DSP_ARGS_DACC 0x0000010 /* Target accumulator as destination */ -#define DSP_ARGS_SRD 0x0000020 /* Source the RD port */ -#define DSP_ARGS_2 0x0000040 /* De.r,Dx.r (2 register operands) */ -#define DSP_ARGS_DSP_SRC1 0x0000080 /* Source a DSP register */ -#define DSP_ARGS_DSP_SRC2 0x0000100 /* Source a DSP register */ -#define DSP_ARGS_IMM 0x0000200 /* Immediate value for src 2 */ -#define DSP_ARGS_SPLIT8 0x0000400 /* Data unit split 8 operations */ -#define DSP_ARGS_12 0x0000800 /* De.r,Dx.r */ -#define DSP_ARGS_13 0x0001000 /* Dx.r,Rx.r */ -#define DSP_ARGS_14 0x0002000 /* DSPe.r,Dx.r */ -#define DSP_ARGS_15 0x0004000 /* DSPx.r,#I16 */ -#define DSP_ARGS_16 0x0008000 /* De.r,DSPx.r */ -#define DSP_ARGS_17 0x0010000 /* De.r|ACe.r,Dx.r,Rx.r|RD */ -#define DSP_ARGS_18 0x0020000 /* De.r,Dx.r|ACx.r */ -#define DSP_ARGS_20 0x0080000 /* De.r,Dx.r|ACx.r,De.r */ -#define DSP_ARGS_21 0x0100000 /* De.r,Dx.r|ACx.r,#I5 */ -#define DSP_ARGS_22 0x0200000 /* De.r,Dx.r|ACx.r,De.r|#I5 */ -#define DSP_ARGS_23 0x0400000 /* Ux.r,Dx.r|ACx.r,De.r|#I5 */ -#define GP_ARGS_QR 0x0000001 /* QUICKRoT */ - unsigned int arg_type; -} insn_template; - -enum major_opcode -{ - OPC_ADD, - OPC_SUB, - OPC_AND, - OPC_OR, - OPC_XOR, - OPC_SHIFT, - OPC_MUL, - OPC_CMP, - OPC_ADDR, - OPC_9, - OPC_MISC, - OPC_SET, - OPC_GET, - OPC_XFR, - OPC_CPR, - OPC_FPU, -}; - -#define GET_EXT_MINOR 0x7 -#define MOV_EXT_MINOR 0x6 -#define MOVL_MINOR 0x2 - -#define MAJOR_OPCODE(opcode) (((opcode) >> 28) & 0xf) -#define MINOR_OPCODE(opcode) (((opcode) >> 24) & 0xf) - -enum cond_code -{ - COND_A, - COND_EQ, - COND_NE, - COND_CS, - COND_CC, - COND_MI, - COND_PL, - COND_VS, - COND_VC, - COND_HI, - COND_LS, - COND_GE, - COND_LT, - COND_GT, - COND_LE, - COND_NV, -}; - -enum scond_code -{ - SCOND_A, - SCOND_LEQ, - SCOND_LNE, - SCOND_LLO, - SCOND_LHS, - SCOND_HEQ, - SCOND_HNE, - SCOND_HLO, - SCOND_HHS, - SCOND_LGR, - SCOND_LLE, - SCOND_HGR, - SCOND_HLE, - SCOND_EEQ, - SCOND_ELO, - SCOND_NV, -}; - -typedef struct -{ - const char *name; - enum scond_code code; -} split_condition; - -static const split_condition metag_scondtab[] = - { - { "LEQ", SCOND_LEQ }, - { "LEZ", SCOND_LEQ }, - { "LNE", SCOND_LNE }, - { "LNZ", SCOND_LNE }, - { "LLO", SCOND_LLO }, - { "LCS", SCOND_LLO }, - { "LHS", SCOND_LHS }, - { "LCC", SCOND_LHS }, - { "HEQ", SCOND_HEQ }, - { "HEZ", SCOND_HEQ }, - { "HNE", SCOND_HNE }, - { "HNZ", SCOND_HNE }, - { "HLO", SCOND_HLO }, - { "HCS", SCOND_HLO }, - { "HHS", SCOND_HHS }, - { "HCC", SCOND_HHS }, - { "LGR", SCOND_LGR }, - { "LHI", SCOND_LGR }, - { "LLE", SCOND_LLE }, - { "LLS", SCOND_LLE }, - { "HGR", SCOND_HGR }, - { "HHI", SCOND_HGR }, - { "HLE", SCOND_HLE }, - { "HLS", SCOND_HLE }, - { "EEQ", SCOND_EEQ }, - { "EEZ", SCOND_EEQ }, - { "ELO", SCOND_ELO }, - { "ECS", SCOND_ELO }, - }; - -static const split_condition metag_dsp_scondtab[] = - { - { "LEQ", SCOND_LEQ }, - { "LEZ", SCOND_LEQ }, - { "LNE", SCOND_LNE }, - { "LNZ", SCOND_LNE }, - { "LCS", SCOND_LLO }, - { "LLO", SCOND_LLO }, - { "LCC", SCOND_LHS }, - { "LHS", SCOND_LHS }, - { "HEQ", SCOND_HEQ }, - { "HEZ", SCOND_HEQ }, - { "HNE", SCOND_HNE }, - { "HNZ", SCOND_HNE }, - { "HCS", SCOND_HLO }, - { "HLO", SCOND_HLO }, - { "HCC", SCOND_HHS }, - { "HHS", SCOND_HHS }, - { "LHI", SCOND_LGR }, - { "LGR", SCOND_LGR }, - { "LLS", SCOND_LLE }, - { "LLE", SCOND_LLE }, - { "HHI", SCOND_HGR }, - { "HGR", SCOND_HGR }, - { "HLS", SCOND_HLE }, - { "HLE", SCOND_HLE }, - { "EEQ", SCOND_EEQ }, - { "EEZ", SCOND_EEQ }, - { "ECS", SCOND_ELO }, - { "ELO", SCOND_ELO }, - }; - -static const split_condition metag_fpu_scondtab[] = - { - { "LEQ", SCOND_LEQ }, - { "LEZ", SCOND_LEQ }, - { "LNE", SCOND_LNE }, - { "LNZ", SCOND_LNE }, - { "LLO", SCOND_LLO }, - { "LCS", SCOND_LLO }, - { "LHS", SCOND_LHS }, - { "LCC", SCOND_LHS }, - { "HEQ", SCOND_HEQ }, - { "HEZ", SCOND_HEQ }, - { "HNE", SCOND_HNE }, - { "HNZ", SCOND_HNE }, - { "HLO", SCOND_HLO }, - { "HCS", SCOND_HLO }, - { "HHS", SCOND_HHS }, - { "HCC", SCOND_HHS }, - { "LGR", SCOND_LGR }, - { "LHI", SCOND_LGR }, - { "LLE", SCOND_LLE }, - { "LLS", SCOND_LLE }, - { "HGR", SCOND_HGR }, - { "HHI", SCOND_HGR }, - { "HLE", SCOND_HLE }, - { "HLS", SCOND_HLE }, - { "EEQ", SCOND_EEQ }, - { "EEZ", SCOND_EEQ }, - { "ELO", SCOND_ELO }, - { "ECS", SCOND_ELO }, - }; - -enum fcond_code -{ - FCOND_A, - FCOND_FEQ, - FCOND_UNE, - FCOND_FLT, - FCOND_UGE, - - FCOND_UVS = 7, - FCOND_FVC, - FCOND_UGT, - FCOND_FLE, - FCOND_FGE, - FCOND_ULT, - FCOND_FGT, - FCOND_ULE, - FCOND_NV, -}; - -#define COND_INSN(mnemonic, suffix, field_shift, flags, meta_opcode, \ - meta_mask, insn_type, encoding, args) \ - { mnemonic suffix, flags, meta_opcode, meta_mask, \ - insn_type, encoding, args }, \ - { mnemonic "A" suffix, flags, meta_opcode, meta_mask, \ - insn_type, encoding, args }, \ - { mnemonic "EQ" suffix, flags, meta_opcode | (COND_EQ << field_shift), \ - meta_mask, insn_type, encoding, args }, \ - { mnemonic "Z" suffix, flags, meta_opcode | (COND_EQ << field_shift), \ - meta_mask, insn_type, encoding, args }, \ - { mnemonic "NE" suffix, flags, meta_opcode | (COND_NE << field_shift), \ - meta_mask, insn_type, encoding, args }, \ - { mnemonic "NZ" suffix, flags, meta_opcode | (COND_NE << field_shift), \ - meta_mask, insn_type, encoding, args }, \ - { mnemonic "CS" suffix, flags, meta_opcode | (COND_CS << field_shift), \ - meta_mask, insn_type, encoding, args }, \ - { mnemonic "LO" suffix, flags, meta_opcode | (COND_CS << field_shift), \ - meta_mask, insn_type, encoding, args }, \ - { mnemonic "CC" suffix, flags, meta_opcode | (COND_CC << field_shift), \ - meta_mask, insn_type, encoding, args }, \ - { mnemonic "HS" suffix, flags, meta_opcode | (COND_CC << field_shift), \ - meta_mask, insn_type, encoding, args }, \ - { mnemonic "MI" suffix, flags, meta_opcode | (COND_MI << field_shift), \ - meta_mask, insn_type, encoding, args }, \ - { mnemonic "N" suffix, flags, meta_opcode | (COND_MI << field_shift), \ - meta_mask, insn_type, encoding, args }, \ - { mnemonic "PL" suffix, flags, meta_opcode | (COND_PL << field_shift), \ - meta_mask, insn_type, encoding, args }, \ - { mnemonic "NC" suffix, flags, meta_opcode | (COND_PL << field_shift), \ - meta_mask, insn_type, encoding, args }, \ - { mnemonic "VS" suffix, flags, meta_opcode | (COND_VS << field_shift), \ - meta_mask, insn_type, encoding, args }, \ - { mnemonic "VC" suffix, flags, meta_opcode | (COND_VC << field_shift), \ - meta_mask, insn_type, encoding, args }, \ - { mnemonic "HI" suffix, flags, meta_opcode | (COND_HI << field_shift), \ - meta_mask, insn_type, encoding, args }, \ - { mnemonic "LS" suffix, flags, meta_opcode | (COND_LS << field_shift), \ - meta_mask, insn_type, encoding, args }, \ - { mnemonic "GE" suffix, flags, meta_opcode | (COND_GE << field_shift), \ - meta_mask, insn_type, encoding, args }, \ - { mnemonic "LT" suffix, flags, meta_opcode | (COND_LT << field_shift), \ - meta_mask, insn_type, encoding, args }, \ - { mnemonic "GT" suffix, flags, meta_opcode | (COND_GT << field_shift), \ - meta_mask, insn_type, encoding, args }, \ - { mnemonic "LE" suffix, flags, meta_opcode | (COND_LE << field_shift), \ - meta_mask, insn_type, encoding, args }, \ - { mnemonic "NV" suffix, flags, meta_opcode | (COND_NV << field_shift), \ - meta_mask, insn_type, encoding, args }, \ - { mnemonic "FEQ" suffix, flags, meta_opcode | \ - (FCOND_FEQ << field_shift), meta_mask, INSN_FPU, encoding, args }, \ - { mnemonic "FZ" suffix, flags, meta_opcode | \ - (FCOND_FEQ << field_shift), meta_mask, INSN_FPU, encoding, args }, \ - { mnemonic "UNE" suffix, flags, meta_opcode | \ - (FCOND_UNE << field_shift), meta_mask, INSN_FPU, encoding, args }, \ - { mnemonic "UNZ" suffix, flags, meta_opcode | \ - (FCOND_UNE << field_shift), meta_mask, INSN_FPU, encoding, args }, \ - { mnemonic "FLT" suffix, flags, meta_opcode | \ - (FCOND_FLT << field_shift), meta_mask, INSN_FPU, encoding, args }, \ - { mnemonic "FLO" suffix, flags, meta_opcode | \ - (FCOND_FLT << field_shift), meta_mask, INSN_FPU, encoding, args }, \ - { mnemonic "UGE" suffix, flags, meta_opcode | \ - (FCOND_UGE << field_shift), meta_mask, INSN_FPU, encoding, args }, \ - { mnemonic "UHS" suffix, flags, meta_opcode | \ - (FCOND_UGE << field_shift), meta_mask, INSN_FPU, encoding, args }, \ - { mnemonic "UVS" suffix, flags, meta_opcode | \ - (FCOND_UVS << field_shift), meta_mask, INSN_FPU, encoding, args }, \ - { mnemonic "FVC" suffix, flags, meta_opcode | \ - (FCOND_FVC << field_shift), meta_mask, INSN_FPU, encoding, args }, \ - { mnemonic "UGT" suffix, flags, meta_opcode | \ - (FCOND_UGT << field_shift), meta_mask, INSN_FPU, encoding, args }, \ - { mnemonic "UHI" suffix, flags, meta_opcode | \ - (FCOND_UGT << field_shift), meta_mask, INSN_FPU, encoding, args }, \ - { mnemonic "FLE" suffix, flags, meta_opcode | \ - (FCOND_FLE << field_shift), meta_mask, INSN_FPU, encoding, args }, \ - { mnemonic "FGE" suffix, flags, meta_opcode | \ - (FCOND_FGE << field_shift), meta_mask, INSN_FPU, encoding, args }, \ - { mnemonic "FHS" suffix, flags, meta_opcode | \ - (FCOND_FGE << field_shift), meta_mask, INSN_FPU, encoding, args }, \ - { mnemonic "ULT" suffix, flags, meta_opcode | \ - (FCOND_ULT << field_shift), meta_mask, INSN_FPU, encoding, args }, \ - { mnemonic "ULO" suffix, flags, meta_opcode | \ - (FCOND_ULT << field_shift), meta_mask, INSN_FPU, encoding, args }, \ - { mnemonic "FGT" suffix, flags, meta_opcode | \ - (FCOND_FGT << field_shift), meta_mask, INSN_FPU, encoding, args }, \ - { mnemonic "FHI" suffix, flags, meta_opcode | \ - (FCOND_FGT << field_shift), meta_mask, INSN_FPU, encoding, args }, \ - { mnemonic "ULE" suffix, flags, meta_opcode | \ - (FCOND_ULE << field_shift), meta_mask, INSN_FPU, encoding, args }, \ - { mnemonic "NV" suffix, flags, meta_opcode | \ - (FCOND_NV << field_shift), meta_mask, INSN_FPU, encoding, args } - -#define FCOND_INSN(mnemonic, suffix, field_shift, flags, meta_opcode, \ - meta_mask, insn_type, encoding, args) \ - { mnemonic suffix, flags, meta_opcode, meta_mask, \ - insn_type, encoding, args }, \ - { mnemonic "A" suffix, flags, meta_opcode, meta_mask, \ - insn_type, encoding, args }, \ - { mnemonic "FEQ" suffix, flags, meta_opcode | \ - (FCOND_FEQ << field_shift), meta_mask, INSN_FPU, encoding, args }, \ - { mnemonic "FZ" suffix, flags, meta_opcode | \ - (FCOND_FEQ << field_shift), meta_mask, INSN_FPU, encoding, args }, \ - { mnemonic "UNE" suffix, flags, meta_opcode | \ - (FCOND_UNE << field_shift), meta_mask, INSN_FPU, encoding, args }, \ - { mnemonic "UNZ" suffix, flags, meta_opcode | \ - (FCOND_UNE << field_shift), meta_mask, INSN_FPU, encoding, args }, \ - { mnemonic "FLO" suffix, flags, meta_opcode | \ - (FCOND_FLT << field_shift), meta_mask, INSN_FPU, encoding, args }, \ - { mnemonic "FLT" suffix, flags, meta_opcode | \ - (FCOND_FLT << field_shift), meta_mask, INSN_FPU, encoding, args }, \ - { mnemonic "UHS" suffix, flags, meta_opcode | \ - (FCOND_UGE << field_shift), meta_mask, INSN_FPU, encoding, args }, \ - { mnemonic "UGE" suffix, flags, meta_opcode | \ - (FCOND_UGE << field_shift), meta_mask, INSN_FPU, encoding, args }, \ - { mnemonic "UVS" suffix, flags, meta_opcode | \ - (FCOND_UVS << field_shift), meta_mask, INSN_FPU, encoding, args }, \ - { mnemonic "FVC" suffix, flags, meta_opcode | \ - (FCOND_FVC << field_shift), meta_mask, INSN_FPU, encoding, args }, \ - { mnemonic "UHI" suffix, flags, meta_opcode | \ - (FCOND_UGT << field_shift), meta_mask, INSN_FPU, encoding, args }, \ - { mnemonic "UGT" suffix, flags, meta_opcode | \ - (FCOND_UGT << field_shift), meta_mask, INSN_FPU, encoding, args }, \ - { mnemonic "FLE" suffix, flags, meta_opcode | \ - (FCOND_FLE << field_shift), meta_mask, INSN_FPU, encoding, args }, \ - { mnemonic "FGE" suffix, flags, meta_opcode | \ - (FCOND_FGE << field_shift), meta_mask, INSN_FPU, encoding, args }, \ - { mnemonic "FHS" suffix, flags, meta_opcode | \ - (FCOND_FGE << field_shift), meta_mask, INSN_FPU, encoding, args }, \ - { mnemonic "ULT" suffix, flags, meta_opcode | \ - (FCOND_ULT << field_shift), meta_mask, INSN_FPU, encoding, args }, \ - { mnemonic "ULO" suffix, flags, meta_opcode | \ - (FCOND_ULT << field_shift), meta_mask, INSN_FPU, encoding, args }, \ - { mnemonic "FGT" suffix, flags, meta_opcode | \ - (FCOND_FGT << field_shift), meta_mask, INSN_FPU, encoding, args }, \ - { mnemonic "FHI" suffix, flags, meta_opcode | \ - (FCOND_FGT << field_shift), meta_mask, INSN_FPU, encoding, args }, \ - { mnemonic "ULE" suffix, flags, meta_opcode | \ - (FCOND_ULE << field_shift), meta_mask, INSN_FPU, encoding, args }, \ - { mnemonic "NV" suffix, flags, meta_opcode | \ - (FCOND_NV << field_shift), meta_mask, INSN_FPU, encoding, args }, \ - { mnemonic "EQ" suffix, flags, meta_opcode | (COND_EQ << field_shift), \ - meta_mask, insn_type, encoding, args }, \ - { mnemonic "Z" suffix, flags, meta_opcode | (COND_EQ << field_shift), \ - meta_mask, insn_type, encoding, args }, \ - { mnemonic "NE" suffix, flags, meta_opcode | (COND_NE << field_shift), \ - meta_mask, insn_type, encoding, args }, \ - { mnemonic "NZ" suffix, flags, meta_opcode | (COND_NE << field_shift), \ - meta_mask, insn_type, encoding, args }, \ - { mnemonic "CS" suffix, flags, meta_opcode | (COND_CS << field_shift), \ - meta_mask, insn_type, encoding, args }, \ - { mnemonic "LO" suffix, flags, meta_opcode | (COND_CS << field_shift), \ - meta_mask, insn_type, encoding, args }, \ - { mnemonic "CC" suffix, flags, meta_opcode | (COND_CC << field_shift), \ - meta_mask, insn_type, encoding, args }, \ - { mnemonic "HS" suffix, flags, meta_opcode | (COND_CC << field_shift), \ - meta_mask, insn_type, encoding, args }, \ - { mnemonic "MI" suffix, flags, meta_opcode | (COND_MI << field_shift), \ - meta_mask, insn_type, encoding, args }, \ - { mnemonic "N" suffix, flags, meta_opcode | (COND_MI << field_shift), \ - meta_mask, insn_type, encoding, args }, \ - { mnemonic "PL" suffix, flags, meta_opcode | (COND_PL << field_shift), \ - meta_mask, insn_type, encoding, args }, \ - { mnemonic "NC" suffix, flags, meta_opcode | (COND_PL << field_shift), \ - meta_mask, insn_type, encoding, args }, \ - { mnemonic "VS" suffix, flags, meta_opcode | (COND_VS << field_shift), \ - meta_mask, insn_type, encoding, args }, \ - { mnemonic "VC" suffix, flags, meta_opcode | (COND_VC << field_shift), \ - meta_mask, insn_type, encoding, args }, \ - { mnemonic "HI" suffix, flags, meta_opcode | (COND_HI << field_shift), \ - meta_mask, insn_type, encoding, args }, \ - { mnemonic "LS" suffix, flags, meta_opcode | (COND_LS << field_shift), \ - meta_mask, insn_type, encoding, args }, \ - { mnemonic "GE" suffix, flags, meta_opcode | (COND_GE << field_shift), \ - meta_mask, insn_type, encoding, args }, \ - { mnemonic "LT" suffix, flags, meta_opcode | (COND_LT << field_shift), \ - meta_mask, insn_type, encoding, args }, \ - { mnemonic "GT" suffix, flags, meta_opcode | (COND_GT << field_shift), \ - meta_mask, insn_type, encoding, args }, \ - { mnemonic "LE" suffix, flags, meta_opcode | (COND_LE << field_shift), \ - meta_mask, insn_type, encoding, args }, \ - { mnemonic "NV" suffix, flags, meta_opcode | (COND_NV << field_shift), \ - meta_mask, insn_type, encoding, args } - -#define TEMPLATE_INSN(flags, meta_opcode, meta_mask, insn_type) \ - { "T0", flags, meta_opcode | 0x0, meta_mask, insn_type, ENC_DTEMPLATE, 0 }, \ - { "T1", flags, meta_opcode | 0x1, meta_mask, insn_type, ENC_DTEMPLATE, 0 }, \ - { "T2", flags, meta_opcode | 0x2, meta_mask, insn_type, ENC_DTEMPLATE, 0 }, \ - { "T3", flags, meta_opcode | 0x3, meta_mask, insn_type, ENC_DTEMPLATE, 0 }, \ - { "T4", flags, meta_opcode | 0x4, meta_mask, insn_type, ENC_DTEMPLATE, 0 }, \ - { "T5", flags, meta_opcode | 0x5, meta_mask, insn_type, ENC_DTEMPLATE, 0 }, \ - { "T6", flags, meta_opcode | 0x6, meta_mask, insn_type, ENC_DTEMPLATE, 0 }, \ - { "T7", flags, meta_opcode | 0x7, meta_mask, insn_type, ENC_DTEMPLATE, 0 }, \ - { "T8", flags, meta_opcode | 0x8, meta_mask, insn_type, ENC_DTEMPLATE, 0 }, \ - { "T9", flags, meta_opcode | 0x9, meta_mask, insn_type, ENC_DTEMPLATE, 0 }, \ - { "TA", flags, meta_opcode | 0xa, meta_mask, insn_type, ENC_DTEMPLATE, 0 }, \ - { "TB", flags, meta_opcode | 0xb, meta_mask, insn_type, ENC_DTEMPLATE, 0 }, \ - { "TC", flags, meta_opcode | 0xc, meta_mask, insn_type, ENC_DTEMPLATE, 0 }, \ - { "TD", flags, meta_opcode | 0xd, meta_mask, insn_type, ENC_DTEMPLATE, 0 }, \ - { "TE", flags, meta_opcode | 0xe, meta_mask, insn_type, ENC_DTEMPLATE, 0 }, \ - { "TF", flags, meta_opcode | 0xf, meta_mask, insn_type, ENC_DTEMPLATE, 0 } - - -/* Unimplemented GP instructions: - CPR - coprocessor read - CPW - coprocessor write - MORT - morton order operation - VPACK, VADD, VSUB - vector instructions - - The order of the entries in this table is extremely important. DO - NOT modify it unless you know what you're doing. If you do modify - it, be sure to run the entire testsuite to make sure you haven't - caused a regression. */ - -static const insn_template metag_optab[] = - { - /* Port-to-unit MOV */ - COND_INSN ("MOVB", "", 1, CoreMeta11|CoreMeta12|CoreMeta21, - 0xa1800000, 0xfff83e1f, INSN_GP, ENC_MOV_PORT, 0), - COND_INSN ("MOVW", "", 1, CoreMeta11|CoreMeta12|CoreMeta21, - 0xa1800001, 0xfff83e1f, INSN_GP, ENC_MOV_PORT, 0), - COND_INSN ("MOVD", "", 1, CoreMeta11|CoreMeta12|CoreMeta21, - 0xa1800200, 0xfff83e1f, INSN_GP, ENC_MOV_PORT, 0), - COND_INSN ("MOVL", "", 1, CoreMeta11|CoreMeta12|CoreMeta21, - 0xa2800000, 0xfff8019f, INSN_GP, ENC_MOV_PORT, 0), - - /* Read pipeline prime/drain */ - { "MMOVD", CoreMeta11|CoreMeta12|CoreMeta21, - 0xca000000, 0xff00001f, INSN_GP, ENC_MMOV, 0 }, - { "MMOVL", CoreMeta11|CoreMeta12|CoreMeta21, - 0xcb000000, 0xff00001f, INSN_GP, ENC_MMOV, 0 }, - { "MMOVD", CoreMeta11|CoreMeta12|CoreMeta21, - 0xcc000000, 0xff07c067, INSN_GP, ENC_MMOV, 0 }, - { "MMOVL", CoreMeta11|CoreMeta12|CoreMeta21, - 0xcd000000, 0xff07c067, INSN_GP, ENC_MMOV, 0 }, - - /* Read pipeline flush */ - { "MDRD", CoreMeta11|CoreMeta12|CoreMeta21, - 0xcc000002, 0xffffc07f, INSN_GP, ENC_MDRD, 0 }, - - /* Unit-to-TTREC MOVL */ - COND_INSN ("MOVL", "", 1, CoreMeta12|CoreMeta21, - 0xa2002001, 0xff003e7f, INSN_GP, ENC_MOVL_TTREC, 0), - - /* MOV to RA (extended) */ - { "MOVB", CoreMeta11|CoreMeta12|CoreMeta21, - 0xa6000000, 0xff00001e, INSN_GP, ENC_GET_SET_EXT, 0 }, - { "MOVW", CoreMeta11|CoreMeta12|CoreMeta21, - 0xa6000002, 0xff00001e, INSN_GP, ENC_GET_SET_EXT, 0 }, - { "MOVD", CoreMeta11|CoreMeta12|CoreMeta21, - 0xa6000004, 0xff00001e, INSN_GP, ENC_GET_SET_EXT, 0 }, - { "MOVL", CoreMeta11|CoreMeta12|CoreMeta21, - 0xa6000006, 0xff00001e, INSN_GP, ENC_GET_SET_EXT, 0 }, - - /* Extended GET */ - { "GETB", CoreMeta11|CoreMeta12|CoreMeta21, - 0xa7000000, 0xff000006, INSN_GP, ENC_GET_SET_EXT, 0 }, - { "GETW", CoreMeta11|CoreMeta12|CoreMeta21, - 0xa7000002, 0xff000006, INSN_GP, ENC_GET_SET_EXT, 0 }, - { "GETD", CoreMeta11|CoreMeta12|CoreMeta21, - 0xa7000004, 0xff000006, INSN_GP, ENC_GET_SET_EXT, 0 }, - { "GETL", CoreMeta11|CoreMeta12|CoreMeta21, - 0xa7000006, 0xff000006, INSN_GP, ENC_GET_SET_EXT, 0 }, - - /* Extended SET */ - { "SETB", CoreMeta11|CoreMeta12|CoreMeta21, - 0xa5000000, 0xff000006, INSN_GP, ENC_GET_SET_EXT, 0 }, - { "SETW", CoreMeta11|CoreMeta12|CoreMeta21, - 0xa5000002, 0xff000006, INSN_GP, ENC_GET_SET_EXT, 0 }, - { "SETD", CoreMeta11|CoreMeta12|CoreMeta21, - 0xa5000004, 0xff000006, INSN_GP, ENC_GET_SET_EXT, 0 }, - { "SETL", CoreMeta11|CoreMeta12|CoreMeta21, - 0xa5000006, 0xff000006, INSN_GP, ENC_GET_SET_EXT, 0 }, - - /* MOV to RA */ - { "MOVB", CoreMeta11|CoreMeta12|CoreMeta21, - 0xc000000c, 0xfd00001e, INSN_GP, ENC_GET_SET, 0 }, - { "MOVW", CoreMeta11|CoreMeta12|CoreMeta21, - 0xc100000c, 0xfd00001e, INSN_GP, ENC_GET_SET, 0 }, - { "MOVD", CoreMeta11|CoreMeta12|CoreMeta21, - 0xc400000c, 0xfd00001e, INSN_GP, ENC_GET_SET, 0 }, - { "MOVL", CoreMeta11|CoreMeta12|CoreMeta21, - 0xc500000c, 0xfd00001e, INSN_GP, ENC_GET_SET, 0 }, - - /* Standard GET */ - { "GETB", CoreMeta11|CoreMeta12|CoreMeta21, - 0xc0000000, 0xfd000000, INSN_GP, ENC_GET_SET, 0 }, - { "GETW", CoreMeta11|CoreMeta12|CoreMeta21, - 0xc1000000, 0xfd000000, INSN_GP, ENC_GET_SET, 0 }, - { "GETD", CoreMeta11|CoreMeta12|CoreMeta21, - 0xc4000000, 0xfd000000, INSN_GP, ENC_GET_SET, 0 }, - /* GET is a synonym for GETD. */ - { "GET", CoreMeta11|CoreMeta12|CoreMeta21, - 0xc4000000, 0xfd000000, INSN_GP, ENC_GET_SET, 0 }, - { "GETL", CoreMeta11|CoreMeta12|CoreMeta21, - 0xc5000000, 0xfd000000, INSN_GP, ENC_GET_SET, 0 }, - - /* Standard SET */ - { "SETB", CoreMeta11|CoreMeta12|CoreMeta21, - 0xb0000000, 0xfd000000, INSN_GP, ENC_GET_SET, 0 }, - { "SETW", CoreMeta11|CoreMeta12|CoreMeta21, - 0xb1000000, 0xfd000000, INSN_GP, ENC_GET_SET, 0 }, - { "SETD", CoreMeta11|CoreMeta12|CoreMeta21, - 0xb4000000, 0xfd000000, INSN_GP, ENC_GET_SET, 0 }, - /* SET is a synonym for SETD. */ - { "SET", CoreMeta11|CoreMeta12|CoreMeta21, - 0xb4000000, 0xfd000000, INSN_GP, ENC_GET_SET, 0 }, - { "SETL", CoreMeta11|CoreMeta12|CoreMeta21, - 0xb5000000, 0xfd000000, INSN_GP, ENC_GET_SET, 0 }, - - /* Multiple GET */ - { "MGETD", CoreMeta11|CoreMeta12|CoreMeta21, - 0xc8000000, 0xff000007, INSN_GP, ENC_MGET_MSET, 0 }, - { "MGETL", CoreMeta11|CoreMeta12|CoreMeta21, - 0xc9000000, 0xff000007, INSN_GP, ENC_MGET_MSET, 0 }, - - /* Multiple SET */ - { "MSETD", CoreMeta11|CoreMeta12|CoreMeta21, - 0xb8000000, 0xff000007, INSN_GP, ENC_MGET_MSET, 0 }, - { "MSETL", CoreMeta11|CoreMeta12|CoreMeta21, - 0xb9000000, 0xff000007, INSN_GP, ENC_MGET_MSET, 0 }, - - /* Conditional SET */ - COND_INSN ("SETB", "", 1, CoreMeta11|CoreMeta12|CoreMeta21, - 0xa4000000, 0xff00039f, INSN_GP, ENC_COND_SET, 0), - COND_INSN ("SETW", "", 1, CoreMeta11|CoreMeta12|CoreMeta21, - 0xa4000001, 0xff00039f, INSN_GP, ENC_COND_SET, 0), - COND_INSN ("SETD", "", 1, CoreMeta11|CoreMeta12|CoreMeta21, - 0xa4000200, 0xff00039f, INSN_GP, ENC_COND_SET, 0), - COND_INSN ("SETL", "", 1, CoreMeta11|CoreMeta12|CoreMeta21, - 0xa4000201, 0xff00039f, INSN_GP, ENC_COND_SET, 0), - { "XFRD", CoreMeta11|CoreMeta12|CoreMeta21, - 0xd0000000, 0xf2000000, INSN_GP, ENC_XFR, 0 }, - { "XFRL", CoreMeta11|CoreMeta12|CoreMeta21, - 0xd2000000, 0xf2000000, INSN_GP, ENC_XFR, 0 }, - - /* Fast control register setup */ - { "MOV", CoreMeta11|CoreMeta12|CoreMeta21, - 0xa9000000, 0xff000005, INSN_GP, ENC_MOV_CT, 0 }, - { "MOVT", CoreMeta11|CoreMeta12|CoreMeta21, - 0xa9000001, 0xff000005, INSN_GP, ENC_MOV_CT, 0 }, - { "MOV", CoreMeta11|CoreMeta12|CoreMeta21, - 0xa9000004, 0xff000005, INSN_GP, ENC_MOV_CT, 0 }, - { "MOVT", CoreMeta11|CoreMeta12|CoreMeta21, - 0xa9000005, 0xff000005, INSN_GP, ENC_MOV_CT, 0 }, - - /* Internal transfer operations */ - { "JUMP", CoreMeta11|CoreMeta12|CoreMeta21, - 0xac000000, 0xff000004, INSN_GP, ENC_JUMP, 0 }, - { "CALL", CoreMeta11|CoreMeta12|CoreMeta21, - 0xac000004, 0xff000004, INSN_GP, ENC_JUMP, 0 }, - { "CALLR", CoreMeta11|CoreMeta12|CoreMeta21, - 0xab000000, 0xff000000, INSN_GP, ENC_CALLR, 0 }, - - /* Address unit ALU operations */ - { "MOV", CoreMeta11|CoreMeta12|CoreMeta21, - 0x80000004, 0xfe0001fc, INSN_GP, ENC_ALU, 0 }, - { "MOV", CoreMeta11|CoreMeta12|CoreMeta21, - 0x82000004, 0xfe000005, INSN_GP, ENC_ALU, 0 }, - { "MOVT", CoreMeta11|CoreMeta12|CoreMeta21, - 0x82000005, 0xfe000005, INSN_GP, ENC_ALU, 0 }, - { "ADD", CoreMeta11|CoreMeta12|CoreMeta21, - 0x80000000, 0xfe0001fc, INSN_GP, ENC_ALU, 0 }, - { "ADD", CoreMeta11|CoreMeta12|CoreMeta21, - 0x82000000, 0xfe000005, INSN_GP, ENC_ALU, 0 }, - { "ADDT", CoreMeta11|CoreMeta12|CoreMeta21, - 0x82000001, 0xfe000005, INSN_GP, ENC_ALU, 0 }, - { "ADD", CoreMeta11|CoreMeta12|CoreMeta21, - 0x86000020, 0xfe000021, INSN_GP, ENC_ALU, 0 }, - COND_INSN ("ADD", "", 1, CoreMeta11|CoreMeta12|CoreMeta21, - 0x84000000, 0xfe00001e, INSN_GP, ENC_ALU, 0), - COND_INSN ("ADD", "", 1, CoreMeta11|CoreMeta12|CoreMeta21, - 0x86000000, 0xfe00003f, INSN_GP, ENC_ALU, 0), - { "NEG", CoreMeta11|CoreMeta12|CoreMeta21, - 0x88000004, 0xfe0001fc, INSN_GP, ENC_ALU, 0 }, - { "NEG", CoreMeta11|CoreMeta12|CoreMeta21, - 0x8a000004, 0xfe000005, INSN_GP, ENC_ALU, 0 }, - { "NEGT", CoreMeta11|CoreMeta12|CoreMeta21, - 0x8a000005, 0xfe000005, INSN_GP, ENC_ALU, 0 }, - { "SUB", CoreMeta11|CoreMeta12|CoreMeta21, - 0x88000000, 0xfe0001fc, INSN_GP, ENC_ALU, 0 }, - { "SUB", CoreMeta11|CoreMeta12|CoreMeta21, - 0x8a000000, 0xfe000005, INSN_GP, ENC_ALU, 0 }, - { "SUBT", CoreMeta11|CoreMeta12|CoreMeta21, - 0x8a000001, 0xfe000005, INSN_GP, ENC_ALU, 0 }, - { "SUB", CoreMeta11|CoreMeta12|CoreMeta21, - 0x8e000020, 0xfe000021, INSN_GP, ENC_ALU, 0 }, - COND_INSN ("SUB", "", 1, CoreMeta11|CoreMeta12|CoreMeta21, - 0x8c000000, 0xfe00001e, INSN_GP, ENC_ALU, 0), - COND_INSN ("SUB", "", 1, CoreMeta11|CoreMeta12|CoreMeta21, - 0x8e000000, 0xfe00003f, INSN_GP, ENC_ALU, 0), - - /* Data unit ALU operations */ - { "MOV", CoreMeta11|CoreMeta12|CoreMeta21, - 0x00000004, 0xfe0001fc, INSN_GP, ENC_ALU, 0 }, - { "MOVS", CoreMeta11|CoreMeta12|CoreMeta21, - 0x08000004, 0xfe0001fc, INSN_GP, ENC_ALU, 0 }, - { "MOV", CoreMeta11|CoreMeta12|CoreMeta21, - 0x02000004, 0xfe000005, INSN_GP, ENC_ALU, 0 }, - { "MOVS", CoreMeta11|CoreMeta12|CoreMeta21, - 0x0a000004, 0xfe000005, INSN_GP, ENC_ALU, 0 }, - { "MOVT", CoreMeta11|CoreMeta12|CoreMeta21, - 0x02000005, 0xfe000007, INSN_GP, ENC_ALU, 0 }, - { "MOVST", CoreMeta11|CoreMeta12|CoreMeta21, - 0x0a000005, 0xfe000007, INSN_GP, ENC_ALU, 0 }, - { "ADD", DspMeta21, - 0x00000100, 0xfe000104, INSN_DSP, ENC_DALU, - DSP_ARGS_1|DSP_ARGS_ACC2|DSP_ARGS_XACC|DSP_ARGS_IMM }, - { "ADD", DspMeta21, - 0x02000003, 0xfe000003, INSN_DSP, ENC_DALU, - DSP_ARGS_1|DSP_ARGS_IMM }, - COND_INSN ("ADD", "", 1, DspMeta21, - 0x040001e0, 0xfe0001fe, INSN_DSP, ENC_DALU, DSP_ARGS_1), - { "ADD", CoreMeta11|CoreMeta12|CoreMeta21, - 0x00000000, 0xfe0001fc, INSN_GP, ENC_ALU, 0 }, - { "ADDS", DspMeta21, - 0x08000100, 0xfe000104, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_ACC2 }, - { "ADDS", DspMeta21, - 0x0a000003, 0xfe000003, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_IMM }, - { "ADDS", CoreMeta11|CoreMeta12|CoreMeta21, - 0x08000000, 0xfe0001fc, INSN_GP, ENC_ALU, 0 }, - { "ADD", CoreMeta11|CoreMeta12|CoreMeta21, - 0x02000000, 0xfe000005, INSN_GP, ENC_ALU, 0 }, - { "ADDS", CoreMeta11|CoreMeta12|CoreMeta21, - 0x0a000000, 0xfe000005, INSN_GP, ENC_ALU, 0 }, - { "ADDT", CoreMeta11|CoreMeta12|CoreMeta21, - 0x02000001, 0xfe000005, INSN_GP, ENC_ALU, 0 }, - { "ADDST", CoreMeta11|CoreMeta12|CoreMeta21, - 0x0a000001, 0xfe000005, INSN_GP, ENC_ALU, 0 }, - { "ADD", CoreMeta11|CoreMeta12|CoreMeta21, - 0x06000020, 0xfe000021, INSN_GP, ENC_ALU, 0 }, - COND_INSN ("ADDS", "", 1, DspMeta21, - 0x0c0001e0, 0xfe0001fe, INSN_DSP, ENC_DALU, DSP_ARGS_1), - { "ADDS", CoreMeta11|CoreMeta12|CoreMeta21, - 0x0e000020, 0xfe000021, INSN_GP, ENC_ALU, 0 }, - COND_INSN ("ADD", "", 1, CoreMeta11|CoreMeta12|CoreMeta21, - 0x04000000, 0xfe00001e, INSN_GP, ENC_ALU, 0), - COND_INSN ("ADDS", "", 1, CoreMeta11|CoreMeta12|CoreMeta21, - 0x0c000000, 0xfe00001e, INSN_GP, ENC_ALU, 0), - COND_INSN ("ADD", "", 1, CoreMeta11|CoreMeta12|CoreMeta21, - 0x06000000, 0xfe00003f, INSN_GP, ENC_ALU, 0), - COND_INSN ("ADDS", "", 1, CoreMeta11|CoreMeta12|CoreMeta21, - 0x0e000000, 0xfe00003f, INSN_GP, ENC_ALU, 0), - { "NEG", CoreMeta11|CoreMeta12|CoreMeta21, - 0x10000004, 0xfe0001fc, INSN_GP, ENC_ALU, 0 }, - { "NEGS", CoreMeta11|CoreMeta12|CoreMeta21, - 0x18000004, 0xfe0001fc, INSN_GP, ENC_ALU, 0 }, - { "NEG", CoreMeta11|CoreMeta12|CoreMeta21, - 0x12000004, 0xfe000005, INSN_GP, ENC_ALU, 0 }, - { "NEGS", CoreMeta11|CoreMeta12|CoreMeta21, - 0x1a000004, 0xfe000005, INSN_GP, ENC_ALU, 0 }, - { "NEGT", CoreMeta11|CoreMeta12|CoreMeta21, - 0x12000005, 0xfe000007, INSN_GP, ENC_ALU, 0 }, - { "NEGST", CoreMeta11|CoreMeta12|CoreMeta21, - 0x1a000005, 0xfe000007, INSN_GP, ENC_ALU, 0 }, - { "SUB", DspMeta21, - 0x10000100, 0xfe000104, INSN_DSP, ENC_DALU, - DSP_ARGS_1|DSP_ARGS_ACC2|DSP_ARGS_XACC }, - { "SUB", DspMeta21, - 0x12000003, 0xfe000003, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_IMM }, - { "SUB", CoreMeta11|CoreMeta12|CoreMeta21, - 0x10000000, 0xfe0001fc, INSN_GP, ENC_ALU, 0 }, - { "SUBS", CoreMeta11|CoreMeta12|CoreMeta21, - 0x18000000, 0xfe0001fc, INSN_GP, ENC_ALU, 0 }, - { "SUB", CoreMeta11|CoreMeta12|CoreMeta21, - 0x12000000, 0xfe000005, INSN_GP, ENC_ALU, 0 }, - { "SUBS", CoreMeta11|CoreMeta12|CoreMeta21, - 0x1a000000, 0xfe000005, INSN_GP, ENC_ALU, 0 }, - { "SUBT", CoreMeta11|CoreMeta12|CoreMeta21, - 0x12000001, 0xfe000005, INSN_GP, ENC_ALU, 0 }, - { "SUBS", DspMeta21, - 0x18000100, 0xfe000104, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_ACC2 }, - { "SUBS", DspMeta21, - 0x1a000003, 0xfe000003, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_IMM }, - { "SUBST", CoreMeta11|CoreMeta12|CoreMeta21, - 0x1a000001, 0xfe000005, INSN_GP, ENC_ALU, 0 }, - { "SUB", CoreMeta11|CoreMeta12|CoreMeta21, - 0x16000020, 0xfe000021, INSN_GP, ENC_ALU, 0 }, - { "SUBS", CoreMeta11|CoreMeta12|CoreMeta21, - 0x1e000020, 0xfe000021, INSN_GP, ENC_ALU, 0 }, - COND_INSN ("SUBS", "", 1, DspMeta21, - 0x1c0001e0, 0xfe0001fe, INSN_DSP, ENC_DALU, DSP_ARGS_1), - COND_INSN ("SUB", "", 1, DspMeta21, - 0x140001e0, 0xfe0001fe, INSN_DSP, ENC_DALU, DSP_ARGS_1), - COND_INSN ("SUB", "", 1, CoreMeta11|CoreMeta12|CoreMeta21, - 0x14000000, 0xfe00001e, INSN_GP, ENC_ALU, 0), - COND_INSN ("SUBS", "", 1, CoreMeta11|CoreMeta12|CoreMeta21, - 0x1c000000, 0xfe00001e, INSN_GP, ENC_ALU, 0), - COND_INSN ("SUB", "", 1, CoreMeta11|CoreMeta12|CoreMeta21, - 0x16000000, 0xfe00003f, INSN_GP, ENC_ALU, 0), - COND_INSN ("SUBS", "", 1, CoreMeta11|CoreMeta12|CoreMeta21, - 0x1e000000, 0xfe00003f, INSN_GP, ENC_ALU, 0), - { "AND", CoreMeta11|CoreMeta12|CoreMeta21, - 0x20000000, 0xfe0001fe, INSN_GP, ENC_ALU, 0 }, - { "ANDS", CoreMeta11|CoreMeta12|CoreMeta21, - 0x28000000, 0xfe0001fe, INSN_GP, ENC_ALU, 0 }, - { "ANDQ", CoreMeta11|CoreMeta12|CoreMeta21, - 0x20000040, 0xfe00017e, INSN_GP, ENC_ALU, GP_ARGS_QR }, - { "ANDSQ", CoreMeta11|CoreMeta12|CoreMeta21, - 0x28000040, 0xfe00017e, INSN_GP, ENC_ALU, GP_ARGS_QR }, - { "AND", CoreMeta11|CoreMeta12|CoreMeta21, - 0x22000000, 0xfe000005, INSN_GP, ENC_ALU, 0 }, - { "ANDMB", CoreMeta11|CoreMeta12|CoreMeta21, - 0x22000004, 0xfe000005, INSN_GP, ENC_ALU, 0 }, - { "ANDS", CoreMeta11|CoreMeta12|CoreMeta21, - 0x2a000000, 0xfe000005, INSN_GP, ENC_ALU, 0 }, - { "ANDSMB", CoreMeta11|CoreMeta12|CoreMeta21, - 0x2a000004, 0xfe000005, INSN_GP, ENC_ALU, 0 }, - { "ANDT", CoreMeta11|CoreMeta12|CoreMeta21, - 0x22000001, 0xfe000007, INSN_GP, ENC_ALU, 0 }, - { "ANDMT", CoreMeta11|CoreMeta12|CoreMeta21, - 0x22000005, 0xfe000007, INSN_GP, ENC_ALU, 0 }, - { "ANDST", CoreMeta11|CoreMeta12|CoreMeta21, - 0x2a000001, 0xfe000007, INSN_GP, ENC_ALU, 0 }, - { "ANDSMT", CoreMeta11|CoreMeta12|CoreMeta21, - 0x2a000005, 0xfe000007, INSN_GP, ENC_ALU, 0 }, - { "AND", DspMeta21, - 0x20000100, 0xfe00014c, INSN_DSP, ENC_DALU, DSP_ARGS_1 }, - { "AND", CoreMeta11|CoreMeta12|CoreMeta21, - 0x26000020, 0xfe000021, INSN_GP, ENC_ALU, 0 }, - { "ANDS", CoreMeta11|CoreMeta12|CoreMeta21, - 0x2e000020, 0xfe000021, INSN_GP, ENC_ALU, 0 }, - { "ANDQ", CoreMeta11|CoreMeta12|CoreMeta21, - 0x26000021, 0xfe000021, INSN_GP, ENC_ALU, GP_ARGS_QR }, - { "ANDSQ", CoreMeta11|CoreMeta12|CoreMeta21, - 0x2e000021, 0xfe000021, INSN_GP, ENC_ALU, GP_ARGS_QR }, - { "ANDQ", DspMeta21, - 0x20000140, 0xfe00014c, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_QR }, - COND_INSN ("ANDQ", "", 1, DspMeta21, - 0x240001c0, 0xfe0001de, INSN_DSP, ENC_DALU, - DSP_ARGS_1|DSP_ARGS_QR), - COND_INSN ("AND", "", 1, CoreMeta11|CoreMeta12|CoreMeta21, - 0x24000000, 0xfe00001e, INSN_GP, ENC_ALU, 0), - { "ANDSQ", DspMeta21, - 0x28000140, 0xfe00014c, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_QR }, - COND_INSN ("ANDSQ", "", 1, DspMeta21, - 0x2c0001c0, 0xfe0001de, INSN_DSP, ENC_DALU, - DSP_ARGS_1|DSP_ARGS_QR), - COND_INSN ("ANDS", "", 1, CoreMeta11|CoreMeta12|CoreMeta21, - 0x2c000000, 0xfe00001e, INSN_GP, ENC_ALU, 0), - COND_INSN ("AND", "", 1, CoreMeta11|CoreMeta12|CoreMeta21, - 0x26000000, 0xfe00003f, INSN_GP, ENC_ALU, 0), - COND_INSN ("ANDS", "", 1, CoreMeta11|CoreMeta12|CoreMeta21, - 0x2e000000, 0xfe00003f, INSN_GP, ENC_ALU, 0), - COND_INSN ("ANDQ", "", 1, CoreMeta11|CoreMeta12|CoreMeta21, - 0x26000001, 0xfe00003f, INSN_GP, ENC_ALU, GP_ARGS_QR), - COND_INSN ("ANDSQ", "", 1, CoreMeta11|CoreMeta12|CoreMeta21, - 0x2e000001, 0xfe00003f, INSN_GP, ENC_ALU, GP_ARGS_QR), - { "OR", CoreMeta11|CoreMeta12|CoreMeta21, - 0x30000000, 0xfe0001fe, INSN_GP, ENC_ALU, 0 }, - { "ORS", CoreMeta11|CoreMeta12|CoreMeta21, - 0x38000000, 0xfe0001fe, INSN_GP, ENC_ALU, 0 }, - { "ORQ", CoreMeta11|CoreMeta12|CoreMeta21, - 0x30000040, 0xfe00017e, INSN_GP, ENC_ALU, GP_ARGS_QR }, - { "ORSQ", CoreMeta11|CoreMeta12|CoreMeta21, - 0x38000040, 0xfe00017e, INSN_GP, ENC_ALU, GP_ARGS_QR }, - { "OR", CoreMeta11|CoreMeta12|CoreMeta21, - 0x32000000, 0xfe000005, INSN_GP, ENC_ALU, 0 }, - { "ORMB", CoreMeta11|CoreMeta12|CoreMeta21, - 0x32000004, 0xfe000005, INSN_GP, ENC_ALU, 0 }, - { "ORS", CoreMeta11|CoreMeta12|CoreMeta21, - 0x3a000000, 0xfe000005, INSN_GP, ENC_ALU, 0 }, - { "ORSMB", CoreMeta11|CoreMeta12|CoreMeta21, - 0x3a000004, 0xfe000005, INSN_GP, ENC_ALU, 0 }, - { "ORT", CoreMeta11|CoreMeta12|CoreMeta21, - 0x32000001, 0xfe000007, INSN_GP, ENC_ALU, 0 }, - { "ORMT", CoreMeta11|CoreMeta12|CoreMeta21, - 0x32000005, 0xfe000007, INSN_GP, ENC_ALU, 0 }, - { "ORST", CoreMeta11|CoreMeta12|CoreMeta21, - 0x3a000001, 0xfe000007, INSN_GP, ENC_ALU, 0 }, - { "ORSMT", CoreMeta11|CoreMeta12|CoreMeta21, - 0x3a000005, 0xfe000007, INSN_GP, ENC_ALU, 0 }, - { "OR", CoreMeta11|CoreMeta12|CoreMeta21, - 0x36000020, 0xfe000021, INSN_GP, ENC_ALU, 0 }, - { "ORS", CoreMeta11|CoreMeta12|CoreMeta21, - 0x3e000020, 0xfe000021, INSN_GP, ENC_ALU, 0 }, - { "ORQ", CoreMeta11|CoreMeta12|CoreMeta21, - 0x36000021, 0xfe000021, INSN_GP, ENC_ALU, GP_ARGS_QR }, - { "ORSQ", CoreMeta11|CoreMeta12|CoreMeta21, - 0x3e000021, 0xfe000021, INSN_GP, ENC_ALU, GP_ARGS_QR }, - { "ORQ", DspMeta21, - 0x30000140, 0xfe00014c, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_QR }, - COND_INSN ("ORQ", "", 1, DspMeta21, - 0x340001c0, 0xfe0001de, INSN_DSP, ENC_DALU, - DSP_ARGS_1|DSP_ARGS_QR), - COND_INSN ("OR", "", 1, CoreMeta11|CoreMeta12|CoreMeta21, - 0x34000000, 0xfe00001e, INSN_GP, ENC_ALU, 0), - { "ORSQ", DspMeta21, - 0x38000140, 0xfe00014c, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_QR }, - COND_INSN ("ORSQ", "", 1, DspMeta21, - 0x3c0001c0, 0xfe0001de, INSN_DSP, ENC_DALU, - DSP_ARGS_1|DSP_ARGS_QR), - COND_INSN ("ORS", "", 1, CoreMeta11|CoreMeta12|CoreMeta21, - 0x3c000000, 0xfe00001e, INSN_GP, ENC_ALU, 0), - COND_INSN ("OR", "", 1, CoreMeta11|CoreMeta12|CoreMeta21, - 0x36000000, 0xfe00003f, INSN_GP, ENC_ALU, 0), - COND_INSN ("ORS", "", 1, CoreMeta11|CoreMeta12|CoreMeta21, - 0x3e000000, 0xfe00003f, INSN_GP, ENC_ALU, 0), - COND_INSN ("ORQ", "", 1, CoreMeta11|CoreMeta12|CoreMeta21, - 0x36000001, 0xfe00003f, INSN_GP, ENC_ALU, GP_ARGS_QR), - COND_INSN ("ORSQ", "", 1, CoreMeta11|CoreMeta12|CoreMeta21, - 0x3e000001, 0xfe00003f, INSN_GP, ENC_ALU, GP_ARGS_QR), - { "XOR", CoreMeta11|CoreMeta12|CoreMeta21, - 0x40000000, 0xfe0001fe, INSN_GP, ENC_ALU, 0 }, - { "XORS", CoreMeta11|CoreMeta12|CoreMeta21, - 0x48000000, 0xfe0001fe, INSN_GP, ENC_ALU, 0 }, - { "XORQ", CoreMeta11|CoreMeta12|CoreMeta21, - 0x40000040, 0xfe00017e, INSN_GP, ENC_ALU, GP_ARGS_QR }, - { "XORSQ", CoreMeta11|CoreMeta12|CoreMeta21, - 0x48000040, 0xfe00017e, INSN_GP, ENC_ALU, GP_ARGS_QR }, - { "XOR", CoreMeta11|CoreMeta12|CoreMeta21, - 0x42000000, 0xfe000005, INSN_GP, ENC_ALU, 0 }, - { "XORMB", CoreMeta11|CoreMeta12|CoreMeta21, - 0x42000004, 0xfe000005, INSN_GP, ENC_ALU, 0 }, - { "XORS", CoreMeta11|CoreMeta12|CoreMeta21, - 0x4a000000, 0xfe000005, INSN_GP, ENC_ALU, 0 }, - { "XORSMB", CoreMeta11|CoreMeta12|CoreMeta21, - 0x4a000004, 0xfe000005, INSN_GP, ENC_ALU, 0 }, - { "XORT", CoreMeta11|CoreMeta12|CoreMeta21, - 0x42000001, 0xfe000007, INSN_GP, ENC_ALU, 0 }, - { "XORMT", CoreMeta11|CoreMeta12|CoreMeta21, - 0x42000005, 0xfe000007, INSN_GP, ENC_ALU, 0 }, - { "XORST", CoreMeta11|CoreMeta12|CoreMeta21, - 0x4a000001, 0xfe000007, INSN_GP, ENC_ALU, 0 }, - { "XORSMT", CoreMeta11|CoreMeta12|CoreMeta21, - 0x4a000005, 0xfe000007, INSN_GP, ENC_ALU, 0 }, - { "XOR", CoreMeta11|CoreMeta12|CoreMeta21, - 0x46000020, 0xfe000021, INSN_GP, ENC_ALU, 0 }, - { "XORS", CoreMeta11|CoreMeta12|CoreMeta21, - 0x4e000020, 0xfe000021, INSN_GP, ENC_ALU, 0 }, - { "XORQ", CoreMeta11|CoreMeta12|CoreMeta21, - 0x46000021, 0xfe000021, INSN_GP, ENC_ALU, GP_ARGS_QR }, - { "XORSQ", CoreMeta11|CoreMeta12|CoreMeta21, - 0x4e000021, 0xfe000021, INSN_GP, ENC_ALU, GP_ARGS_QR }, - { "XORQ", DspMeta21, - 0x40000140, 0xfe00014c, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_QR }, - COND_INSN ("XORQ", "", 1, DspMeta21, - 0x440001c0, 0xfe0001de, INSN_DSP, ENC_DALU, - DSP_ARGS_1|DSP_ARGS_QR), - COND_INSN ("XOR", "", 1, CoreMeta11|CoreMeta12|CoreMeta21, - 0x44000000, 0xfe00001e, INSN_GP, ENC_ALU, 0), - { "XORSQ", DspMeta21, - 0x48000140, 0xfe000140, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_QR }, - COND_INSN ("XORSQ", "", 1, DspMeta21, - 0x4c0001c0, 0xfe0001de, INSN_DSP, ENC_DALU, - DSP_ARGS_1|DSP_ARGS_QR), - COND_INSN ("XORS", "", 1, CoreMeta11|CoreMeta12|CoreMeta21, - 0x4c000000, 0xfe00001e, INSN_GP, ENC_ALU, 0), - COND_INSN ("XOR", "", 1, CoreMeta11|CoreMeta12|CoreMeta21, - 0x46000000, 0xfe00003f, INSN_GP, ENC_ALU, 0), - COND_INSN ("XORS", "", 1, CoreMeta11|CoreMeta12|CoreMeta21, - 0x4e000000, 0xfe00003f, INSN_GP, ENC_ALU, 0), - COND_INSN ("XORQ", "", 1, CoreMeta11|CoreMeta12|CoreMeta21, - 0x46000001, 0xfe00003f, INSN_GP, ENC_ALU, GP_ARGS_QR), - COND_INSN ("XORSQ", "", 1, CoreMeta11|CoreMeta12|CoreMeta21, - 0x4e000001, 0xfe00003f, INSN_GP, ENC_ALU, GP_ARGS_QR), - { "LSL", CoreMeta11|CoreMeta12|CoreMeta21, - 0x50000000, 0xfc0001ff, INSN_GP, ENC_SHIFT, 0 }, - { "LSL", CoreMeta11|CoreMeta12|CoreMeta21, - 0x54000020, 0xfc0001e0, INSN_GP, ENC_SHIFT, 0 }, - COND_INSN ("LSL", "", 1, CoreMeta11|CoreMeta12|CoreMeta21, - 0x54000000, 0xfc0001ff, INSN_GP, ENC_SHIFT, 0), - { "LSLS", CoreMeta11|CoreMeta12|CoreMeta21, - 0x58000000, 0xfc0001ff, INSN_GP, ENC_SHIFT, 0 }, - { "LSLS", CoreMeta11|CoreMeta12|CoreMeta21, - 0x5c000020, 0xfc0001e0, INSN_GP, ENC_SHIFT, 0 }, - COND_INSN ("LSLS", "", 1, CoreMeta11|CoreMeta12|CoreMeta21, - 0x5c000000, 0xfc0001ff, INSN_GP, ENC_SHIFT, 0), - { "LSR", CoreMeta11|CoreMeta12|CoreMeta21, - 0x50000040, 0xfc0001ff, INSN_GP, ENC_SHIFT, 0 }, - { "LSR", CoreMeta11|CoreMeta12|CoreMeta21, - 0x54000060, 0xfc0001e0, INSN_GP, ENC_SHIFT, 0 }, - COND_INSN ("LSR", "", 1, CoreMeta11|CoreMeta12|CoreMeta21, - 0x54000040, 0xfc0001ff, INSN_GP, ENC_SHIFT, 0), - { "LSRS", CoreMeta11|CoreMeta12|CoreMeta21, - 0x58000040, 0xfc0001ff, INSN_GP, ENC_SHIFT, 0 }, - { "LSRS", CoreMeta11|CoreMeta12|CoreMeta21, - 0x5c000060, 0xfc0001e0, INSN_GP, ENC_SHIFT, 0 }, - COND_INSN ("LSRS", "", 1, CoreMeta11|CoreMeta12|CoreMeta21, - 0x5c000040, 0xfc0001ff, INSN_GP, ENC_SHIFT, 0), - { "ASL", CoreMeta11|CoreMeta12|CoreMeta21, - 0x50000080, 0xfc0001ff, INSN_GP, ENC_SHIFT, 0 }, - { "ASL", CoreMeta11|CoreMeta12|CoreMeta21, - 0x540000a0, 0xfc0001e0, INSN_GP, ENC_SHIFT, 0 }, - COND_INSN ("ASL", "", 1, CoreMeta11|CoreMeta12|CoreMeta21, - 0x54000080, 0xfc0001ff, INSN_GP, ENC_SHIFT, 0), - { "ASLS", CoreMeta11|CoreMeta12|CoreMeta21, - 0x58000080, 0xfc0001ff, INSN_GP, ENC_SHIFT, 0 }, - { "ASLS", CoreMeta11|CoreMeta12|CoreMeta21, - 0x5c0000a0, 0xfc0001e0, INSN_GP, ENC_SHIFT, 0 }, - COND_INSN ("ASLS", "", 1, CoreMeta11|CoreMeta12|CoreMeta21, - 0x5c000080, 0xfc0001ff, INSN_GP, ENC_SHIFT, 0), - { "ASR", CoreMeta11|CoreMeta12|CoreMeta21, - 0x500000c0, 0xfc0001ff, INSN_GP, ENC_SHIFT, 0 }, - { "ASR", CoreMeta11|CoreMeta12|CoreMeta21, - 0x540000e0, 0xfc0001e0, INSN_GP, ENC_SHIFT, 0 }, - COND_INSN ("ASR", "", 1, CoreMeta11|CoreMeta12|CoreMeta21, - 0x540000c0, 0xfc0001ff, INSN_GP, ENC_SHIFT, 0), - { "ASRS", CoreMeta11|CoreMeta12|CoreMeta21, - 0x580000c0, 0xfc0001ff, INSN_GP, ENC_SHIFT, 0 }, - { "ASRS", CoreMeta11|CoreMeta12|CoreMeta21, - 0x5c0000e0, 0xfc0001e0, INSN_GP, ENC_SHIFT, 0 }, - COND_INSN ("ASRS", "", 1, CoreMeta11|CoreMeta12|CoreMeta21, - 0x5c0000c0, 0xfc0001ff, INSN_GP, ENC_SHIFT, 0), - { "MULW", CoreMeta11|CoreMeta12|CoreMeta21, - 0x60000000, 0xfe0001fe, INSN_GP, ENC_ALU, 0 }, - { "MULD", CoreMeta11|CoreMeta12|CoreMeta21, - 0x60000040, 0xfe0001fe, INSN_GP, ENC_ALU, 0 }, - /* MUL is a synonym from MULD. */ - { "MUL", CoreMeta11|CoreMeta12|CoreMeta21, - 0x60000040, 0xfe0001fe, INSN_GP, ENC_ALU, 0 }, - { "MULW", CoreMeta11|CoreMeta12|CoreMeta21, - 0x62000000, 0xfe000005, INSN_GP, ENC_ALU, 0 }, - { "MULD", CoreMeta11|CoreMeta12|CoreMeta21, - 0x62000004, 0xfe000005, INSN_GP, ENC_ALU, 0 }, - { "MUL", CoreMeta11|CoreMeta12|CoreMeta21, - 0x62000004, 0xfe000005, INSN_GP, ENC_ALU, 0 }, - { "MULWT", CoreMeta11|CoreMeta12|CoreMeta21, - 0x62000001, 0xfe000007, INSN_GP, ENC_ALU, 0 }, - { "MULDT", CoreMeta11|CoreMeta12|CoreMeta21, - 0x62000005, 0xfe000007, INSN_GP, ENC_ALU, 0 }, - { "MULT", CoreMeta11|CoreMeta12|CoreMeta21, - 0x62000005, 0xfe000007, INSN_GP, ENC_ALU, 0 }, - { "MULW", CoreMeta11|CoreMeta12|CoreMeta21, - 0x64000020, 0xfe0001e0, INSN_GP, ENC_ALU, 0 }, - { "MULD", CoreMeta11|CoreMeta12|CoreMeta21, - 0x64000060, 0xfe0001e0, INSN_GP, ENC_ALU, 0 }, - { "MUL", CoreMeta11|CoreMeta12|CoreMeta21, - 0x64000060, 0xfe0001e0, INSN_GP, ENC_ALU, 0 }, - { "MULW", CoreMeta11|CoreMeta12|CoreMeta21, - 0x66000020, 0xfe000021, INSN_GP, ENC_ALU, 0 }, - { "MULD", CoreMeta11|CoreMeta12|CoreMeta21, - 0x66000021, 0xfe000021, INSN_GP, ENC_ALU, 0 }, - { "MUL", CoreMeta11|CoreMeta12|CoreMeta21, - 0x66000021, 0xfe000021, INSN_GP, ENC_ALU, 0 }, - COND_INSN ("MULW", "", 1, CoreMeta11|CoreMeta12|CoreMeta21, - 0x64000000, 0xfe0001fe, INSN_GP, ENC_ALU, 0), - COND_INSN ("MULD", "", 1, CoreMeta11|CoreMeta12|CoreMeta21, - 0x64000040, 0xfe0001fe, INSN_GP, ENC_ALU, 0), - COND_INSN ("MUL", "", 1, CoreMeta11|CoreMeta12|CoreMeta21, - 0x64000040, 0xfe0001fe, INSN_GP, ENC_ALU, 0), - COND_INSN ("MULW", "", 1, CoreMeta11|CoreMeta12|CoreMeta21, - 0x66000000, 0xfe00003f, INSN_GP, ENC_ALU, 0), - COND_INSN ("MULD", "", 1, CoreMeta11|CoreMeta12|CoreMeta21, - 0x66000001, 0xfe00003f, INSN_GP, ENC_ALU, 0), - COND_INSN ("MUL", "", 1, CoreMeta11|CoreMeta12|CoreMeta21, - 0x66000001, 0xfe00003f, INSN_GP, ENC_ALU, 0), - { "MIN", CoreMeta11|CoreMeta12|CoreMeta21, - 0x70000020, 0xfe0001ff, INSN_GP, ENC_MIN_MAX, 0 }, - { "MAX", CoreMeta11|CoreMeta12|CoreMeta21, - 0x70000024, 0xfe0001ff, INSN_GP, ENC_MIN_MAX, 0 }, - { "FFB", CoreMeta11|CoreMeta12|CoreMeta21, - 0x70000004, 0xfe003fff, INSN_GP, ENC_BITOP, 0 }, - { "NORM", CoreMeta11|CoreMeta12|CoreMeta21, - 0x70000008, 0xfe003fff, INSN_GP, ENC_BITOP, 0 }, - { "ABS", CoreMeta11|CoreMeta12|CoreMeta21, - 0x70000028, 0xfe003fff, INSN_GP, ENC_BITOP, 0 }, - { "XSDB", CoreMeta11|CoreMeta12|CoreMeta21, - 0xaa000000, 0xff003ffe, INSN_GP, ENC_BITOP, 0 }, - { "XSDSB", CoreMeta11|CoreMeta12|CoreMeta21, - 0xaa000008, 0xff003ffe, INSN_GP, ENC_BITOP, 0 }, - { "XSDW", CoreMeta11|CoreMeta12|CoreMeta21, - 0xaa000002, 0xff003ffe, INSN_GP, ENC_BITOP, 0 }, - { "XSDSW", CoreMeta11|CoreMeta12|CoreMeta21, - 0xaa00000a, 0xff003ffe, INSN_GP, ENC_BITOP, 0 }, - { "RTDW", CoreMeta11|CoreMeta12|CoreMeta21, - 0xaa000006, 0xff003ffe, INSN_GP, ENC_BITOP, 0 }, - { "RTDSW", CoreMeta11|CoreMeta12|CoreMeta21, - 0xaa00000e, 0xff003ffe, INSN_GP, ENC_BITOP, 0 }, - { "NMIN", CoreMeta11|CoreMeta12|CoreMeta21, - 0x7000002c, 0xfe0001ff, INSN_GP, ENC_MIN_MAX, 0 }, - - /* Condition setting operations */ - { "CMP", CoreMeta11|CoreMeta12|CoreMeta21, - 0x70000000, 0xfef801fe, INSN_GP, ENC_CMP, 0 }, - { "TST", CoreMeta11|CoreMeta12|CoreMeta21, - 0x78000000, 0xfef801fe, INSN_GP, ENC_CMP, 0 }, - { "CMP", CoreMeta11|CoreMeta12|CoreMeta21, - 0x72000000, 0xfe000005, INSN_GP, ENC_CMP, 0 }, - { "CMPMB", CoreMeta11|CoreMeta12|CoreMeta21, - 0x72000004, 0xfe000005, INSN_GP, ENC_CMP, 0 }, - { "TST", CoreMeta11|CoreMeta12|CoreMeta21, - 0x7a000000, 0xfe000005, INSN_GP, ENC_CMP, 0 }, - { "TSTMB", CoreMeta11|CoreMeta12|CoreMeta21, - 0x7a000004, 0xfe000005, INSN_GP, ENC_CMP, 0 }, - { "CMPT", CoreMeta11|CoreMeta12|CoreMeta21, - 0x72000001, 0xfe000007, INSN_GP, ENC_CMP, 0 }, - { "CMPMT", CoreMeta11|CoreMeta12|CoreMeta21, - 0x72000005, 0xfe000007, INSN_GP, ENC_CMP, 0 }, - { "TSTT", CoreMeta11|CoreMeta12|CoreMeta21, - 0x7a000001, 0xfe000007, INSN_GP, ENC_CMP, 0 }, - { "TSTMT", CoreMeta11|CoreMeta12|CoreMeta21, - 0x7a000005, 0xfe000007, INSN_GP, ENC_CMP, 0 }, - COND_INSN ("CMP", "", 1, CoreMeta11|CoreMeta12|CoreMeta21, - 0x74000000, 0xfef801fe, INSN_GP, ENC_CMP, 0), - COND_INSN ("TST", "", 1, CoreMeta11|CoreMeta12|CoreMeta21, - 0x7c000000, 0xfef801fe, INSN_GP, ENC_CMP, 0), - COND_INSN ("CMP", "", 1, CoreMeta11|CoreMeta12|CoreMeta21, - 0x76000000, 0xfef8003e, INSN_GP, ENC_CMP, 0), - COND_INSN ("TST", "", 1, CoreMeta11|CoreMeta12|CoreMeta21, - 0x7e000000, 0xfef8003e, INSN_GP, ENC_CMP, 0), - - /* No-op (BNV) */ - { "NOP", CoreMeta11|CoreMeta12|CoreMeta21, - 0xa0fffffe, 0xffffffff, INSN_GP, ENC_NONE, 0 }, - - /* Branch */ - COND_INSN ("B", "", 1, CoreMeta11|CoreMeta12|CoreMeta21, - 0xa0000000, 0xff00001f, INSN_GP, ENC_BRANCH, 0), - COND_INSN ("B", "R", 1, CoreMeta11|CoreMeta12|CoreMeta21, - 0xa0000001, 0xff00001f, INSN_GP, ENC_BRANCH, 0), - - /* System operations */ - { "LOCK0", CoreMeta11|CoreMeta12|CoreMeta21, - 0xa8000000, 0xffffffff, INSN_GP, ENC_NONE, 0 }, - { "LOCK1", CoreMeta11|CoreMeta12|CoreMeta21, - 0xa8000001, 0xffffffff, INSN_GP, ENC_NONE, 0 }, - { "LOCK2", CoreMeta11|CoreMeta12|CoreMeta21, - 0xa8000003, 0xffffffff, INSN_GP, ENC_NONE, 0 }, - { "RTI", CoreMeta11|CoreMeta12|CoreMeta21, - 0xa3ffffff, 0xffffffff, INSN_GP, ENC_NONE, 0 }, - { "RTH", CoreMeta11|CoreMeta12|CoreMeta21, - 0xa37fffff, 0xffffffff, INSN_GP, ENC_NONE, 0 }, - COND_INSN ("KICK", "", 1, CoreMeta11|CoreMeta12|CoreMeta21, - 0xa3000001, 0xff003e1f, INSN_GP, ENC_KICK, 0), - { "SWITCH", CoreMeta11|CoreMeta12|CoreMeta21, - 0xaf000000, 0xff000000, INSN_GP, ENC_SWITCH, 0 }, - { "DCACHE", CoreMeta11|CoreMeta12|CoreMeta21, - 0xad000000, 0xff000087, INSN_GP, ENC_CACHEW, 0 }, - { "ICACHEEXIT", CoreMeta12|CoreMeta21, - 0xae000000, 0xffffffff, INSN_GP, ENC_NONE, 0 }, - { "ICACHEEXITR", CoreMeta12|CoreMeta21, - 0xae000001, 0xffffffff, INSN_GP, ENC_NONE, 0 }, - { "ICACHE", CoreMeta12|CoreMeta21, - 0xae000000, 0xff0001e1, INSN_GP, ENC_ICACHE, 0 }, - { "ICACHER", CoreMeta12|CoreMeta21, - 0xae000001, 0xff0001e1, INSN_GP, ENC_ICACHE, 0 }, - - /* Meta 2 instructions */ - { "CACHERD", CoreMeta21, - 0xad000081, 0xff000087, INSN_GP, ENC_CACHER, 0 }, - { "CACHERL", CoreMeta21, - 0xad000083, 0xff000087, INSN_GP, ENC_CACHER, 0 }, - { "CACHEWD", CoreMeta21, - 0xad000001, 0xff000087, INSN_GP, ENC_CACHEW, 0 }, - { "CACHEWL", CoreMeta21, - 0xad000003, 0xff000087, INSN_GP, ENC_CACHEW, 0 }, - COND_INSN ("DEFR", "", 1, CoreMeta21, - 0xa3002001, 0xff003e1f, INSN_GP, ENC_KICK, 0), - { "BEXD", CoreMeta21, - 0xaa000004, 0xff003ffe, INSN_GP, ENC_BITOP, 0 }, - { "BEXSD", CoreMeta21, - 0xaa00000c, 0xff003ffe, INSN_GP, ENC_BITOP, 0 }, - { "BEXL", CoreMeta21, - 0xaa000014, 0xff003ffe, INSN_GP, ENC_BITOP, 0 }, - { "BEXSL", CoreMeta21, - 0xaa00001c, 0xff003ffe, INSN_GP, ENC_BITOP, 0 }, - { "LNKGETB", CoreMeta21, - 0xad000080, 0xff000087, INSN_GP, ENC_LNKGET, 0 }, - { "LNKGETW", CoreMeta21, - 0xad000082, 0xff000087, INSN_GP, ENC_LNKGET, 0 }, - { "LNKGETD", CoreMeta21, - 0xad000084, 0xff000087, INSN_GP, ENC_LNKGET, 0 }, - { "LNKGETL", CoreMeta21, - 0xad000086, 0xff000087, INSN_GP, ENC_LNKGET, 0 }, - COND_INSN ("LNKSETB", "", 1, CoreMeta21, - 0xa4000080, 0xff00039f, INSN_GP, ENC_COND_SET, 0), - COND_INSN ("LNKSETW", "", 1, CoreMeta21, - 0xa4000081, 0xff00039f, INSN_GP, ENC_COND_SET, 0), - COND_INSN ("LNKSETD", "", 1, CoreMeta21, - 0xa4000280, 0xff00039f, INSN_GP, ENC_COND_SET, 0), - COND_INSN ("LNKSETL", "", 1, CoreMeta21, - 0xa4000281, 0xff00039f, INSN_GP, ENC_COND_SET, 0), - - /* Meta 2 FPU instructions */ - - /* Port-to-unit MOV */ - COND_INSN ("MOVL", "", 1, FpuMeta21, - 0xa1800201, 0xfff83e1f, INSN_FPU, ENC_MOV_PORT, 0), - - /* Read pipeline drain */ - { "MMOVD", FpuMeta21, - 0xce000006, 0xfffc007f, INSN_FPU, ENC_MMOV, 0 }, - { "MMOVL", FpuMeta21, - 0xcf000006, 0xfffc007f, INSN_FPU, ENC_MMOV, 0 }, - - /* FP data movement instructions */ - FCOND_INSN ("ABS", "", 1, FpuMeta21, - 0xf0000080, 0xff843f9f, INSN_FPU, ENC_FMOV, 0), - { "MMOVD", FpuMeta21, - 0xbe000002, 0xff84007e, INSN_FPU, ENC_FMMOV, 0 }, - { "MMOVL", FpuMeta21, - 0xbf000002, 0xff84007e, INSN_FPU, ENC_FMMOV, 0 }, - { "MMOVD", FpuMeta21, - 0xce000002, 0xff84007e, INSN_FPU, ENC_FMMOV, 0 }, - { "MMOVL", FpuMeta21, - 0xcf000002, 0xff84007e, INSN_FPU, ENC_FMMOV, 0 }, - { "MOVD", FpuMeta21, - 0x08000144, 0xfe03e1ff, INSN_FPU, ENC_FMOV_DATA, 0 }, - { "MOVD", FpuMeta21, - 0x080001c4, 0xfe83c1ff, INSN_FPU, ENC_FMOV_DATA, 0 }, - { "MOVL", FpuMeta21, - 0x08000154, 0xfe03e1ff, INSN_FPU, ENC_FMOV_DATA, 0 }, - { "MOVL", FpuMeta21, - 0x080001d4, 0xfe83c1ff, INSN_FPU, ENC_FMOV_DATA, 0 }, - FCOND_INSN ("MOV", "", 1, FpuMeta21, - 0xf0000000, 0xff843f9f, INSN_FPU, ENC_FMOV, 0), - { "MOV", FpuMeta21, - 0xf0000001, 0xff800001, INSN_FPU, ENC_FMOV_I, 0 }, - FCOND_INSN ("NEG", "", 1, FpuMeta21, - 0xf0000100, 0xff843f9f, INSN_FPU, ENC_FMOV, 0), - { "PACK", FpuMeta21, - 0xf0000180, 0xff8c21ff, INSN_FPU, ENC_FPACK, 0 }, - { "SWAP", FpuMeta21, - 0xf00001c0, 0xff8c7fff, INSN_FPU, ENC_FSWAP, 0 }, - - /* FP comparison instructions */ - FCOND_INSN ("CMP", "", 1, FpuMeta21, - 0xf3000000, 0xfff4201f, INSN_FPU, ENC_FCMP, 0), - FCOND_INSN ("MAX", "", 1, FpuMeta21, - 0xf3000081, 0xff84219f, INSN_FPU, ENC_FMINMAX, 0), - FCOND_INSN ("MIN", "", 1, FpuMeta21, - 0xf3000001, 0xff84219f, INSN_FPU, ENC_FMINMAX, 0), - - /* FP data conversion instructions */ - FCOND_INSN ("DTOF", "", 1, FpuMeta21, - 0xf2000121, 0xff843fff, INSN_FPU, ENC_FCONV, 0), - FCOND_INSN ("FTOD", "", 1, FpuMeta21, - 0xf2000101, 0xff843fff, INSN_FPU, ENC_FCONV, 0), - FCOND_INSN ("DTOH", "", 1, FpuMeta21, - 0xf2000320, 0xff843fff, INSN_FPU, ENC_FCONV, 0), - FCOND_INSN ("FTOH", "", 1, FpuMeta21, - 0xf2000300, 0xff843fbf, INSN_FPU, ENC_FCONV, 0), - FCOND_INSN ("DTOI", "", 1, FpuMeta21, - 0xf2002120, 0xff842fff, INSN_FPU, ENC_FCONV, 0), - FCOND_INSN ("FTOI", "", 1, FpuMeta21, - 0xf2002100, 0xff842fbf, INSN_FPU, ENC_FCONV, 0), - FCOND_INSN ("DTOL", "", 1, FpuMeta21, - 0xf2002320, 0xff8c6fff, INSN_FPU, ENC_FCONV, 0), - - FCOND_INSN ("DTOX", "", 1, FpuMeta21, - 0xf2000020, 0xff8401bf, INSN_FPU, ENC_FCONVX, 0), - FCOND_INSN ("FTOX", "", 1, FpuMeta21, - 0xf2000000, 0xff8401bf, INSN_FPU, ENC_FCONVX, 0), - FCOND_INSN ("DTOXL", "", 1, FpuMeta21, - 0xf20000a0, 0xff8c40ff, INSN_FPU, ENC_FCONVX, 0), - - FCOND_INSN ("HTOD", "", 1, FpuMeta21, - 0xf2000321, 0xff843fff, INSN_FPU, ENC_FCONV, 0), - FCOND_INSN ("HTOF", "", 1, FpuMeta21, - 0xf2000301, 0xff843fbf, INSN_FPU, ENC_FCONV, 0), - FCOND_INSN ("ITOD", "", 1, FpuMeta21, - 0xf2002121, 0xff843fff, INSN_FPU, ENC_FCONV, 0), - FCOND_INSN ("ITOF", "", 1, FpuMeta21, - 0xf2002101, 0xff843fbf, INSN_FPU, ENC_FCONV, 0), - FCOND_INSN ("LTOD", "", 1, FpuMeta21, - 0xf2002321, 0xff8c7fff, INSN_FPU, ENC_FCONV, 0), - - FCOND_INSN ("XTOD", "", 1, FpuMeta21, - 0xf2000021, 0xff8401bf, INSN_FPU, ENC_FCONVX, 0), - FCOND_INSN ("XTOF", "", 1, FpuMeta21, - 0xf2000001, 0xff8401bf, INSN_FPU, ENC_FCONVX, 0), - FCOND_INSN ("XLTOD", "", 1, FpuMeta21, - 0xf20000a1, 0xff8c40ff, INSN_FPU, ENC_FCONVX, 0), - - /* FP basic arithmetic instructions */ - FCOND_INSN ("ADD", "", 1, FpuMeta21, - 0xf1000001, 0xff84211f, INSN_FPU, ENC_FBARITH, 0), - FCOND_INSN ("MUL", "", 1, FpuMeta21, - 0xf1000100, 0xff84211f, INSN_FPU, ENC_FBARITH, 0), - FCOND_INSN ("SUB", "", 1, FpuMeta21, - 0xf1000101, 0xff84211f, INSN_FPU, ENC_FBARITH, 0), - - /* FP extended arithmetic instructions */ - { "MAC", FpuMeta21, - 0xf6000000, 0xfffc219f, INSN_FPU, ENC_FEARITH, 0 }, - { "MACS", FpuMeta21, - 0xf6000100, 0xfffc219f, INSN_FPU, ENC_FEARITH, 0 }, - - { "MAR", FpuMeta21, - 0xf6000004, 0xff84211f, INSN_FPU, ENC_FEARITH, 0 }, - { "MARS", FpuMeta21, - 0xf6000104, 0xff84211f, INSN_FPU, ENC_FEARITH, 0 }, - - { "MAW", FpuMeta21, - 0xf6000008, 0xff84219f, INSN_FPU, ENC_FEARITH, 0 }, - { "MAWS", FpuMeta21, - 0xf6000108, 0xff84219f, INSN_FPU, ENC_FEARITH, 0 }, - { "MAW1", FpuMeta21, - 0xf6000009, 0xff84219f, INSN_FPU, ENC_FEARITH, 0 }, - { "MAWS1", FpuMeta21, - 0xf6000109, 0xff84219f, INSN_FPU, ENC_FEARITH, 0 }, - - FCOND_INSN ("MXA", "", 1, FpuMeta21, - 0xf5000000, 0xff84211f, INSN_FPU, ENC_FEARITH, 0), - FCOND_INSN ("MXAS", "", 1, FpuMeta21, - 0xf5000100, 0xff84211f, INSN_FPU, ENC_FEARITH, 0), - FCOND_INSN ("MXA1", "", 1, FpuMeta21, - 0xf5000001, 0xff84211f, INSN_FPU, ENC_FEARITH, 0), - FCOND_INSN ("MXAS1", "", 1, FpuMeta21, - 0xf5000101, 0xff84211f, INSN_FPU, ENC_FEARITH, 0), - - { "MUZ", FpuMeta21, - 0xf6000010, 0xff84211d, INSN_FPU, ENC_FEARITH, 0 }, - { "MUZS", FpuMeta21, - 0xf6000110, 0xff84211d, INSN_FPU, ENC_FEARITH, 0 }, - { "MUZ1", FpuMeta21, - 0xf6000011, 0xff84211d, INSN_FPU, ENC_FEARITH, 0 }, - { "MUZS1", FpuMeta21, - 0xf6000111, 0xff84211d, INSN_FPU, ENC_FEARITH, 0 }, - - { "RCP", FpuMeta21, - 0xf7000000, 0xff84391f, INSN_FPU, ENC_FREC, 0 }, - { "RSQ", FpuMeta21, - 0xf7000100, 0xff84391f, INSN_FPU, ENC_FREC, 0 }, - - /* FP SIMD arithmetic instructions */ - { "ADDRE", FpuMeta21, - 0xf4000000, 0xff8c637f, INSN_FPU, ENC_FSIMD, 0 }, - { "MULRE", FpuMeta21, - 0xf4000001, 0xff8c637f, INSN_FPU, ENC_FSIMD, 0 }, - { "SUBRE", FpuMeta21, - 0xf4000100, 0xff8c637f, INSN_FPU, ENC_FSIMD, 0 }, - - /* FP memory instructions */ - { "MGETD", FpuMeta21, - 0xce000000, 0xff00001f, INSN_FPU, ENC_MGET_MSET, 0 }, - { "MGET", FpuMeta21, - 0xce000000, 0xff00001f, INSN_FPU, ENC_MGET_MSET, 0 }, - { "MGETL", FpuMeta21, - 0xcf000000, 0xff00001f, INSN_FPU, ENC_MGET_MSET, 0 }, - - { "MSETD", FpuMeta21, - 0xbe000000, 0xff00001f, INSN_FPU, ENC_MGET_MSET, 0 }, - { "MSET", FpuMeta21, - 0xbe000000, 0xff00001f, INSN_FPU, ENC_MGET_MSET, 0 }, - { "MSETL", FpuMeta21, - 0xbf000000, 0xff00001f, INSN_FPU, ENC_MGET_MSET, 0 }, - - /* FP accumulator memory instructions */ - { "GETL", FpuMeta21, - 0xcf000004, 0xffe03f9f, INSN_FPU, ENC_FGET_SET_ACF, 0 }, - { "SETL", FpuMeta21, - 0xbf000004, 0xffe03f9f, INSN_FPU, ENC_FGET_SET_ACF, 0 }, - - /* DSP FPU data movement */ - { "MOV", DspMeta21|FpuMeta21, - 0x08000146, 0xfe0001ee, INSN_DSP_FPU, ENC_DALU, - DSP_ARGS_2|DSP_ARGS_DSP_SRC1 }, - { "MOV", DspMeta21|FpuMeta21, - 0x080001c6, 0xfe0001ee, INSN_DSP_FPU, ENC_DALU, - DSP_ARGS_2|DSP_ARGS_DSP_SRC2 }, - - /* Unit-to-unit MOV */ - COND_INSN ("MOV", "", 1, CoreMeta11|CoreMeta12|CoreMeta21, - 0xa3000000, 0xff00021f, INSN_GP, ENC_MOV_U2U, 0), - COND_INSN ("TTMOV", "", 1, CoreMeta12|CoreMeta21, - 0xa3000201, 0xff00021f, INSN_GP, ENC_MOV_U2U, 0), - COND_INSN ("SWAP", "", 1, CoreMeta11|CoreMeta12|CoreMeta21, - 0xa3000200, 0xff00021f, INSN_GP, ENC_SWAP, 0), - - /* DSP memory instructions */ - { "GETD", DspMeta21, - 0x94000100, 0xff0001fc, INSN_DSP, ENC_DGET_SET, 0 }, - { "SETD", DspMeta21, - 0x94000000, 0xff0001fc, INSN_DSP, ENC_DGET_SET, 0 }, - { "GETL", DspMeta21, - 0x94000104, 0xff0001fc, INSN_DSP, ENC_DGET_SET, 0 }, - { "SETL", DspMeta21, - 0x94000004, 0xff0001fc, INSN_DSP, ENC_DGET_SET, 0 }, - - /* DSP read pipeline prime/drain */ - { "MMOVD", DspMeta21, - 0xca000001, 0xff00001f, INSN_DSP, ENC_MMOV, 0 }, - { "MMOVL", DspMeta21, - 0xcb000001, 0xff00001f, INSN_DSP, ENC_MMOV, 0 }, - { "MMOVD", DspMeta21, - 0xcc000001, 0xff07c067, INSN_DSP, ENC_MMOV, 0 }, - { "MMOVL", DspMeta21, - 0xcd000001, 0xff07c067, INSN_DSP, ENC_MMOV, 0 }, - - /* DSP Template instantiation */ - TEMPLATE_INSN (DspMeta21, 0x90000000, 0xff00000f, INSN_DSP), - TEMPLATE_INSN (DspMeta21, 0x93000000, 0xff0001ff, INSN_DSP), - TEMPLATE_INSN (DspMeta21, 0x95000000, 0xff00000f, INSN_DSP), - - { "AND", DspMeta21, - 0x22000003, 0xfe000003, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_IMM }, - { "ANDS", DspMeta21, - 0x28000100, 0xfe00014c, INSN_DSP, ENC_DALU, DSP_ARGS_1 }, - { "ANDS", DspMeta21, - 0x2a000003, 0xfe000003, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_IMM }, - { "MAX", DspMeta21, - 0x70000124, 0xfe0001ec, INSN_DSP, ENC_DALU, DSP_ARGS_1 }, - { "MIN", DspMeta21, - 0x70000120, 0xfe0001ec, INSN_DSP, ENC_DALU, DSP_ARGS_1 }, - { "NMIN", DspMeta21, - 0x7000012c, 0xfe0001ec, INSN_DSP, ENC_DALU, DSP_ARGS_1 }, - { "OR", DspMeta21, - 0x30000100, 0xfe00014c, INSN_DSP, ENC_DALU, DSP_ARGS_1 }, - { "OR", DspMeta21, - 0x32000003, 0xfe000003, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_IMM }, - { "ORS", DspMeta21, - 0x38000100, 0xfe00014c, INSN_DSP, ENC_DALU, DSP_ARGS_1 }, - { "ORS", DspMeta21, - 0x3a000003, 0xfe000003, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_IMM }, - { "XOR", DspMeta21, - 0x40000100, 0xfe00014c, INSN_DSP, ENC_DALU, DSP_ARGS_1 }, - { "XOR", DspMeta21, - 0x42000003, 0xfe000003, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_IMM }, - { "XORS", DspMeta21, - 0x48000100, 0xfe00014c, INSN_DSP, ENC_DALU, DSP_ARGS_1 }, - { "XORS", DspMeta21, - 0x4a000003, 0xfe000003, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_IMM }, - { "ADDB8", DspMeta21, - 0x20000108, 0xfe00010c, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_SPLIT8 }, - { "ADDT8", DspMeta21, - 0x2000010c, 0xfe00010c, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_SPLIT8 }, - { "ADDSB8", DspMeta21, - 0x28000108, 0xfe00014c, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_SPLIT8 }, - { "ADDST8", DspMeta21, - 0x2800010c, 0xfe00014c, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_SPLIT8 }, - { "MULB8", DspMeta21, - 0x40000108, 0xfe00012c, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_SPLIT8 }, - { "MULT8", DspMeta21, - 0x4000010c, 0xfe00012c, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_SPLIT8 }, - { "MULSB8", DspMeta21, - 0x48000108, 0xfe00012c, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_SPLIT8 }, - { "MULST8", DspMeta21, - 0x4800010c, 0xfe00012c, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_SPLIT8 }, - { "SUBB8", DspMeta21, - 0x30000108, 0xfe00010c, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_SPLIT8 }, - { "SUBT8", DspMeta21, - 0x3000010c, 0xfe00014c, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_SPLIT8 }, - { "SUBSB8", DspMeta21, - 0x38000108, 0xfe00014c, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_SPLIT8 }, - { "SUBST8", DspMeta21, - 0x3800010c, 0xfe00014c, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_SPLIT8 }, - { "MUL", DspMeta21, - 0x60000100, 0xfe000100, INSN_DSP, ENC_DALU, - DSP_ARGS_1|DSP_ARGS_DACC }, - { "MUL", DspMeta21, - 0x62000003, 0xfe000003, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_IMM }, - { "ABS", DspMeta21, - 0x70000128, 0xfe0001ec, INSN_DSP, ENC_DALU, DSP_ARGS_2 }, - { "FFB", DspMeta21, - 0x70000104, 0xfe0001ec, INSN_DSP, ENC_DALU, DSP_ARGS_2 }, - { "NORM", DspMeta21, - 0x70000108, 0xfe0001ec, INSN_DSP, ENC_DALU, DSP_ARGS_2 }, - { "CMP", DspMeta21, - 0x70000000, 0xfe0000ec, INSN_DSP, ENC_DALU, DSP_ARGS_2|DSP_ARGS_IMM }, - { "CMP", DspMeta21, - 0x72000003, 0xfe000003, INSN_DSP, ENC_DALU, DSP_ARGS_2|DSP_ARGS_IMM }, - { "TST", DspMeta21, - 0x78000100, 0xfe0001ec, INSN_DSP, ENC_DALU, DSP_ARGS_2|DSP_ARGS_IMM }, - { "TST", DspMeta21, - 0x7a000003, 0xfe000003, INSN_DSP, ENC_DALU, DSP_ARGS_2|DSP_ARGS_IMM }, - { "MOV", DspMeta21, - 0x00000104, 0xfe078146, INSN_DSP, ENC_DALU, - DSP_ARGS_2|DSP_ARGS_DSP_SRC1|DSP_ARGS_DSP_SRC2|DSP_ARGS_IMM }, - { "MOVS", DspMeta21, - 0x08000104, 0xfe000146, INSN_DSP, ENC_DALU, DSP_ARGS_2|DSP_ARGS_DSP_SRC2 }, - { "MOV", DspMeta21, - 0x91000000, 0xff000000, INSN_DSP, ENC_DALU, - DSP_ARGS_2|DSP_ARGS_DSP_SRC1|DSP_ARGS_IMM }, - { "MOV", DspMeta21, - 0x92000000, 0xff000000, INSN_DSP, ENC_DALU, DSP_ARGS_2|DSP_ARGS_DSP_SRC2 }, - { "NEG", DspMeta21, - 0x10000104, 0xfe000146, INSN_DSP, ENC_DALU, DSP_ARGS_2|DSP_ARGS_DSP_SRC2 }, - { "NEGS", DspMeta21, - 0x18000104, 0xfe000146, INSN_DSP, ENC_DALU, DSP_ARGS_2|DSP_ARGS_DSP_SRC2 }, - { "XSDB", DspMeta21, - 0xaa000100, 0xff0001ee, INSN_DSP, ENC_DALU, DSP_ARGS_2 }, - { "XSD", DspMeta21, - 0xaa000100, 0xff0001ee, INSN_DSP, ENC_DALU, DSP_ARGS_2 }, - { "XSDW", DspMeta21, - 0xaa000102, 0xff0001ee, INSN_DSP, ENC_DALU, DSP_ARGS_2 }, - { "XSDSB", DspMeta21, - 0xaa000108, 0xff0001ee, INSN_DSP, ENC_DALU, DSP_ARGS_2 }, - { "XSDS", DspMeta21, - 0xaa000108, 0xff0001ee, INSN_DSP, ENC_DALU, DSP_ARGS_2 }, - { "XSDSW", DspMeta21, - 0xaa00010a, 0xff0001ee, INSN_DSP, ENC_DALU, DSP_ARGS_2 }, - { "LSL", DspMeta21, - 0x50000100, 0xfc0001c0, INSN_DSP, ENC_DALU, 0 }, - { "LSR", DspMeta21, - 0x50000140, 0xfc0001c0, INSN_DSP, ENC_DALU, 0 }, - { "ASL", DspMeta21, - 0x50000180, 0xfc0001c0, INSN_DSP, ENC_DALU, 0 }, - { "ASR", DspMeta21, - 0x500001c0, 0xfc0001c0, INSN_DSP, ENC_DALU, 0 }, - { "LSL", DspMeta21, - 0x54000120, 0xfc0001e0, INSN_DSP, ENC_DALU, DSP_ARGS_IMM }, - { "LSR", DspMeta21, - 0x54000160, 0xfc0001e0, INSN_DSP, ENC_DALU, DSP_ARGS_IMM }, - { "ASL", DspMeta21, - 0x540001a0, 0xfc0001e0, INSN_DSP, ENC_DALU, DSP_ARGS_IMM }, - { "ASR", DspMeta21, - 0x540001e0, 0xfc0001e0, INSN_DSP, ENC_DALU, DSP_ARGS_IMM }, - COND_INSN ("LSL", "", 1, DspMeta21, - 0x54000100, 0xfc0001fe, INSN_DSP, ENC_DALU, 0), - COND_INSN ("LSR", "", 1, DspMeta21, - 0x54000140, 0xfc0001fe, INSN_DSP, ENC_DALU, 0), - COND_INSN ("ASL", "", 1, DspMeta21, - 0x54000180, 0xfc0001fe, INSN_DSP, ENC_DALU, 0), - COND_INSN ("ASR", "", 1, DspMeta21, - 0x540001c0, 0xfc0001fe, INSN_DSP, ENC_DALU, 0), - { "LSLS", DspMeta21, - 0x58000100, 0xfc0001c0, INSN_DSP, ENC_DALU, 0 }, - { "LSRS", DspMeta21, - 0x58000140, 0xfc0001c0, INSN_DSP, ENC_DALU, 0 }, - { "ASLS", DspMeta21, - 0x58000180, 0xfc0001c0, INSN_DSP, ENC_DALU, 0 }, - { "ASRS", DspMeta21, - 0x580001c0, 0xfc0001c0, INSN_DSP, ENC_DALU, 0 }, - COND_INSN ("LSLS", "", 1, DspMeta21, - 0x5c000100, 0xfc0001fe, INSN_DSP, ENC_DALU, 0), - COND_INSN ("LSRS", "", 1, DspMeta21, - 0x5c000140, 0xfc0001fe, INSN_DSP, ENC_DALU, 0), - COND_INSN ("ASLS", "", 1, DspMeta21, - 0x5c000180, 0xfc0001fe, INSN_DSP, ENC_DALU, 0), - COND_INSN ("ASRS", "", 1, DspMeta21, - 0x5c0001c0, 0xfc0001fe, INSN_DSP, ENC_DALU, 0), - { "LSLS", DspMeta21, - 0x5c000120, 0xfc0001e0, INSN_DSP, ENC_DALU, 0 }, - { "LSRS", DspMeta21, - 0x5c000160, 0xfc0001e0, INSN_DSP, ENC_DALU, 0 }, - { "ASLS", DspMeta21, - 0x5c0001a0, 0xfc0001e0, INSN_DSP, ENC_DALU, 0 }, - { "ASRS", DspMeta21, - 0x5c0001e0, 0xfc0001e0, INSN_DSP, ENC_DALU, 0 }, - { "RTDW", DspMeta21, - 0xaa000106, 0xff00010e, INSN_DSP, ENC_DALU, DSP_ARGS_2 }, - { "RTDSW", DspMeta21, - 0xaa00010e, 0xff00010e, INSN_DSP, ENC_DALU, DSP_ARGS_2 }, - }; - -#define UNIT_MASK 0xf -#define SHORT_UNIT_MASK 0x3 -#define EXT_BASE_REG_MASK 0x1 -#define REG_MASK 0x1f -#define CC_MASK 0xf -#define RMASK_MASK 0x7f -#define GET_SET_IMM_MASK 0x3f -#define GET_SET_IMM_BITS 6 -#define GET_SET_EXT_IMM_MASK 0xfff -#define GET_SET_EXT_IMM_BITS 12 -#define DGET_SET_IMM_MASK 0x3 -#define DGET_SET_IMM_BITS 2 -#define MGET_MSET_MAX_REGS 8 -#define MMOV_MAX_REGS 8 -#define IMM16_MASK 0xffff -#define IMM16_BITS 16 -#define IMM19_MASK 0x7ffff -#define IMM19_BITS 19 -#define IMM8_MASK 0xff -#define IMM8_BITS 8 -#define IMM24_MASK 0xffffff -#define IMM24_BITS 24 -#define IMM5_MASK 0x1f -#define IMM5_BITS 5 -#define IMM6_MASK 0x3f -#define IMM6_BITS 6 -#define IMM15_MASK 0x7fff -#define IMM15_BITS 15 -#define IMM4_MASK 0x1f -#define IMM4_BITS 4 -#define CALLR_REG_MASK 0x7 -#define CPC_REG_MASK 0xf -#define O2R_REG_MASK 0x7 -#define ACF_PART_MASK 0x3 -#define DSP_REG_MASK 0xf -#define DSP_PART_MASK 0x17 -#define TEMPLATE_NUM_REGS 4 -#define TEMPLATE_REGS_MASK 0xf - -#define IS_TEMPLATE_DEF(insn) (insn->dsp_daoppame_flags & DSP_DAOPPAME_TEMP) - -unsigned int metag_get_set_size_bytes (unsigned int opcode); -unsigned int metag_get_set_ext_size_bytes (unsigned int opcode); -unsigned int metag_cond_set_size_bytes (unsigned int opcode); diff --git a/include/opcode/mips.h b/include/opcode/mips.h deleted file mode 100644 index f21697e..0000000 --- a/include/opcode/mips.h +++ /dev/null @@ -1,2082 +0,0 @@ -/* mips.h. Mips opcode list for GDB, the GNU debugger. - Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, - 2003, 2004, 2005, 2008, 2009, 2010, 2013 - Free Software Foundation, Inc. - Contributed by Ralph Campbell and OSF - Commented and modified by Ian Lance Taylor, Cygnus Support - - This file is part of GDB, GAS, and the GNU binutils. - - GDB, GAS, and the GNU binutils are free software; you can redistribute - them and/or modify them under the terms of the GNU General Public - License as published by the Free Software Foundation; either version 3, - or (at your option) any later version. - - GDB, GAS, and the GNU binutils are distributed in the hope that they - will be useful, but WITHOUT ANY WARRANTY; without even the implied - warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See - the GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this file; see the file COPYING3. If not, write to the Free - Software Foundation, 51 Franklin Street - Fifth Floor, Boston, - MA 02110-1301, USA. */ - -#ifndef _MIPS_H_ -#define _MIPS_H_ - -#include "bfd.h" - -/* These are bit masks and shift counts to use to access the various - fields of an instruction. To retrieve the X field of an - instruction, use the expression - (i >> OP_SH_X) & OP_MASK_X - To set the same field (to j), use - i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X) - - Make sure you use fields that are appropriate for the instruction, - of course. - - The 'i' format uses OP, RS, RT and IMMEDIATE. - - The 'j' format uses OP and TARGET. - - The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT. - - The 'b' format uses OP, RS, RT and DELTA. - - The floating point 'i' format uses OP, RS, RT and IMMEDIATE. - - The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT. - - A breakpoint instruction uses OP, CODE and SPEC (10 bits of the - breakpoint instruction are not defined; Kane says the breakpoint - code field in BREAK is 20 bits; yet MIPS assemblers and debuggers - only use ten bits). An optional two-operand form of break/sdbbp - allows the lower ten bits to be set too, and MIPS32 and later - architectures allow 20 bits to be set with a signal operand - (using CODE20). - - The syscall instruction uses CODE20. - - The general coprocessor instructions use COPZ. */ - -#define OP_MASK_OP 0x3f -#define OP_SH_OP 26 -#define OP_MASK_RS 0x1f -#define OP_SH_RS 21 -#define OP_MASK_FR 0x1f -#define OP_SH_FR 21 -#define OP_MASK_FMT 0x1f -#define OP_SH_FMT 21 -#define OP_MASK_BCC 0x7 -#define OP_SH_BCC 18 -#define OP_MASK_CODE 0x3ff -#define OP_SH_CODE 16 -#define OP_MASK_CODE2 0x3ff -#define OP_SH_CODE2 6 -#define OP_MASK_RT 0x1f -#define OP_SH_RT 16 -#define OP_MASK_FT 0x1f -#define OP_SH_FT 16 -#define OP_MASK_CACHE 0x1f -#define OP_SH_CACHE 16 -#define OP_MASK_RD 0x1f -#define OP_SH_RD 11 -#define OP_MASK_FS 0x1f -#define OP_SH_FS 11 -#define OP_MASK_PREFX 0x1f -#define OP_SH_PREFX 11 -#define OP_MASK_CCC 0x7 -#define OP_SH_CCC 8 -#define OP_MASK_CODE20 0xfffff /* 20 bit syscall/breakpoint code. */ -#define OP_SH_CODE20 6 -#define OP_MASK_SHAMT 0x1f -#define OP_SH_SHAMT 6 -#define OP_MASK_EXTLSB OP_MASK_SHAMT -#define OP_SH_EXTLSB OP_SH_SHAMT -#define OP_MASK_STYPE OP_MASK_SHAMT -#define OP_SH_STYPE OP_SH_SHAMT -#define OP_MASK_FD 0x1f -#define OP_SH_FD 6 -#define OP_MASK_TARGET 0x3ffffff -#define OP_SH_TARGET 0 -#define OP_MASK_COPZ 0x1ffffff -#define OP_SH_COPZ 0 -#define OP_MASK_IMMEDIATE 0xffff -#define OP_SH_IMMEDIATE 0 -#define OP_MASK_DELTA 0xffff -#define OP_SH_DELTA 0 -#define OP_MASK_FUNCT 0x3f -#define OP_SH_FUNCT 0 -#define OP_MASK_SPEC 0x3f -#define OP_SH_SPEC 0 -#define OP_SH_LOCC 8 /* FP condition code. */ -#define OP_SH_HICC 18 /* FP condition code. */ -#define OP_MASK_CC 0x7 -#define OP_SH_COP1NORM 25 /* Normal COP1 encoding. */ -#define OP_MASK_COP1NORM 0x1 /* a single bit. */ -#define OP_SH_COP1SPEC 21 /* COP1 encodings. */ -#define OP_MASK_COP1SPEC 0xf -#define OP_MASK_COP1SCLR 0x4 -#define OP_MASK_COP1CMP 0x3 -#define OP_SH_COP1CMP 4 -#define OP_SH_FORMAT 21 /* FP short format field. */ -#define OP_MASK_FORMAT 0x7 -#define OP_SH_TRUE 16 -#define OP_MASK_TRUE 0x1 -#define OP_SH_GE 17 -#define OP_MASK_GE 0x01 -#define OP_SH_UNSIGNED 16 -#define OP_MASK_UNSIGNED 0x1 -#define OP_SH_HINT 16 -#define OP_MASK_HINT 0x1f -#define OP_SH_MMI 0 /* Multimedia (parallel) op. */ -#define OP_MASK_MMI 0x3f -#define OP_SH_MMISUB 6 -#define OP_MASK_MMISUB 0x1f -#define OP_MASK_PERFREG 0x1f /* Performance monitoring. */ -#define OP_SH_PERFREG 1 -#define OP_SH_SEL 0 /* Coprocessor select field. */ -#define OP_MASK_SEL 0x7 /* The sel field of mfcZ and mtcZ. */ -#define OP_SH_CODE19 6 /* 19 bit wait code. */ -#define OP_MASK_CODE19 0x7ffff -#define OP_SH_ALN 21 -#define OP_MASK_ALN 0x7 -#define OP_SH_VSEL 21 -#define OP_MASK_VSEL 0x1f -#define OP_MASK_VECBYTE 0x7 /* Selector field is really 4 bits, - but 0x8-0xf don't select bytes. */ -#define OP_SH_VECBYTE 22 -#define OP_MASK_VECALIGN 0x7 /* Vector byte-align (alni.ob) op. */ -#define OP_SH_VECALIGN 21 -#define OP_MASK_INSMSB 0x1f /* "ins" MSB. */ -#define OP_SH_INSMSB 11 -#define OP_MASK_EXTMSBD 0x1f /* "ext" MSBD. */ -#define OP_SH_EXTMSBD 11 - -/* MIPS DSP ASE */ -#define OP_SH_DSPACC 11 -#define OP_MASK_DSPACC 0x3 -#define OP_SH_DSPACC_S 21 -#define OP_MASK_DSPACC_S 0x3 -#define OP_SH_DSPSFT 20 -#define OP_MASK_DSPSFT 0x3f -#define OP_SH_DSPSFT_7 19 -#define OP_MASK_DSPSFT_7 0x7f -#define OP_SH_SA3 21 -#define OP_MASK_SA3 0x7 -#define OP_SH_SA4 21 -#define OP_MASK_SA4 0xf -#define OP_SH_IMM8 16 -#define OP_MASK_IMM8 0xff -#define OP_SH_IMM10 16 -#define OP_MASK_IMM10 0x3ff -#define OP_SH_WRDSP 11 -#define OP_MASK_WRDSP 0x3f -#define OP_SH_RDDSP 16 -#define OP_MASK_RDDSP 0x3f -#define OP_SH_BP 11 -#define OP_MASK_BP 0x3 - -/* MIPS MT ASE */ -#define OP_SH_MT_U 5 -#define OP_MASK_MT_U 0x1 -#define OP_SH_MT_H 4 -#define OP_MASK_MT_H 0x1 -#define OP_SH_MTACC_T 18 -#define OP_MASK_MTACC_T 0x3 -#define OP_SH_MTACC_D 13 -#define OP_MASK_MTACC_D 0x3 - -/* MIPS MCU ASE */ -#define OP_MASK_3BITPOS 0x7 -#define OP_SH_3BITPOS 12 -#define OP_MASK_OFFSET12 0xfff -#define OP_SH_OFFSET12 0 - -#define OP_OP_COP0 0x10 -#define OP_OP_COP1 0x11 -#define OP_OP_COP2 0x12 -#define OP_OP_COP3 0x13 -#define OP_OP_LWC1 0x31 -#define OP_OP_LWC2 0x32 -#define OP_OP_LWC3 0x33 /* a.k.a. pref */ -#define OP_OP_LDC1 0x35 -#define OP_OP_LDC2 0x36 -#define OP_OP_LDC3 0x37 /* a.k.a. ld */ -#define OP_OP_SWC1 0x39 -#define OP_OP_SWC2 0x3a -#define OP_OP_SWC3 0x3b -#define OP_OP_SDC1 0x3d -#define OP_OP_SDC2 0x3e -#define OP_OP_SDC3 0x3f /* a.k.a. sd */ - -/* MIPS VIRT ASE */ -#define OP_MASK_CODE10 0x3ff -#define OP_SH_CODE10 11 - -/* Values in the 'VSEL' field. */ -#define MDMX_FMTSEL_IMM_QH 0x1d -#define MDMX_FMTSEL_IMM_OB 0x1e -#define MDMX_FMTSEL_VEC_QH 0x15 -#define MDMX_FMTSEL_VEC_OB 0x16 - -/* UDI */ -#define OP_SH_UDI1 6 -#define OP_MASK_UDI1 0x1f -#define OP_SH_UDI2 6 -#define OP_MASK_UDI2 0x3ff -#define OP_SH_UDI3 6 -#define OP_MASK_UDI3 0x7fff -#define OP_SH_UDI4 6 -#define OP_MASK_UDI4 0xfffff - -/* Octeon */ -#define OP_SH_BBITIND 16 -#define OP_MASK_BBITIND 0x1f -#define OP_SH_CINSPOS 6 -#define OP_MASK_CINSPOS 0x1f -#define OP_SH_CINSLM1 11 -#define OP_MASK_CINSLM1 0x1f -#define OP_SH_SEQI 6 -#define OP_MASK_SEQI 0x3ff - -/* Loongson */ -#define OP_SH_OFFSET_A 6 -#define OP_MASK_OFFSET_A 0xff -#define OP_SH_OFFSET_B 3 -#define OP_MASK_OFFSET_B 0xff -#define OP_SH_OFFSET_C 6 -#define OP_MASK_OFFSET_C 0x1ff -#define OP_SH_RZ 0 -#define OP_MASK_RZ 0x1f -#define OP_SH_FZ 0 -#define OP_MASK_FZ 0x1f - -/* Every MICROMIPSOP_X definition requires a corresponding OP_X - definition, and vice versa. This simplifies various parts - of the operand handling in GAS. The fields below only exist - in the microMIPS encoding, so define each one to have an empty - range. */ -#define OP_MASK_TRAP 0 -#define OP_SH_TRAP 0 -#define OP_MASK_OFFSET10 0 -#define OP_SH_OFFSET10 0 -#define OP_MASK_RS3 0 -#define OP_SH_RS3 0 -#define OP_MASK_MB 0 -#define OP_SH_MB 0 -#define OP_MASK_MC 0 -#define OP_SH_MC 0 -#define OP_MASK_MD 0 -#define OP_SH_MD 0 -#define OP_MASK_ME 0 -#define OP_SH_ME 0 -#define OP_MASK_MF 0 -#define OP_SH_MF 0 -#define OP_MASK_MG 0 -#define OP_SH_MG 0 -#define OP_MASK_MH 0 -#define OP_SH_MH 0 -#define OP_MASK_MJ 0 -#define OP_SH_MJ 0 -#define OP_MASK_ML 0 -#define OP_SH_ML 0 -#define OP_MASK_MM 0 -#define OP_SH_MM 0 -#define OP_MASK_MN 0 -#define OP_SH_MN 0 -#define OP_MASK_MP 0 -#define OP_SH_MP 0 -#define OP_MASK_MQ 0 -#define OP_SH_MQ 0 -#define OP_MASK_IMMA 0 -#define OP_SH_IMMA 0 -#define OP_MASK_IMMB 0 -#define OP_SH_IMMB 0 -#define OP_MASK_IMMC 0 -#define OP_SH_IMMC 0 -#define OP_MASK_IMMF 0 -#define OP_SH_IMMF 0 -#define OP_MASK_IMMG 0 -#define OP_SH_IMMG 0 -#define OP_MASK_IMMH 0 -#define OP_SH_IMMH 0 -#define OP_MASK_IMMI 0 -#define OP_SH_IMMI 0 -#define OP_MASK_IMMJ 0 -#define OP_SH_IMMJ 0 -#define OP_MASK_IMML 0 -#define OP_SH_IMML 0 -#define OP_MASK_IMMM 0 -#define OP_SH_IMMM 0 -#define OP_MASK_IMMN 0 -#define OP_SH_IMMN 0 -#define OP_MASK_IMMO 0 -#define OP_SH_IMMO 0 -#define OP_MASK_IMMP 0 -#define OP_SH_IMMP 0 -#define OP_MASK_IMMQ 0 -#define OP_SH_IMMQ 0 -#define OP_MASK_IMMU 0 -#define OP_SH_IMMU 0 -#define OP_MASK_IMMW 0 -#define OP_SH_IMMW 0 -#define OP_MASK_IMMX 0 -#define OP_SH_IMMX 0 -#define OP_MASK_IMMY 0 -#define OP_SH_IMMY 0 - -/* Enhanced VA Scheme */ -#define OP_SH_EVAOFFSET 7 -#define OP_MASK_EVAOFFSET 0x1ff - -/* Enumerates the various types of MIPS operand. */ -enum mips_operand_type { - /* Described by mips_int_operand. */ - OP_INT, - - /* Described by mips_mapped_int_operand. */ - OP_MAPPED_INT, - - /* Described by mips_msb_operand. */ - OP_MSB, - - /* Described by mips_reg_operand. */ - OP_REG, - - /* Like OP_REG, but can be omitted if the register is the same as the - previous operand. */ - OP_OPTIONAL_REG, - - /* Described by mips_reg_pair_operand. */ - OP_REG_PAIR, - - /* Described by mips_pcrel_operand. */ - OP_PCREL, - - /* A performance register. The field is 5 bits in size, but the supported - values are much more restricted. */ - OP_PERF_REG, - - /* The final operand in a microMIPS ADDIUSP instruction. It mostly acts - as a normal 9-bit signed offset that is multiplied by four, but there - are four special cases: - - -2 * 4 => -258 * 4 - -1 * 4 => -257 * 4 - 0 * 4 => 256 * 4 - 1 * 4 => 257 * 4. */ - OP_ADDIUSP_INT, - - /* The target of a (D)CLO or (D)CLZ instruction. The operand spans two - 5-bit register fields, both of which must be set to the destination - register. */ - OP_CLO_CLZ_DEST, - - /* A register list for a microMIPS LWM or SWM instruction. The operand - size determines whether the 16-bit or 32-bit encoding is required. */ - OP_LWM_SWM_LIST, - - /* The register list for an emulated MIPS16 ENTRY or EXIT instruction. */ - OP_ENTRY_EXIT_LIST, - - /* The register list and frame size for a MIPS16 SAVE or RESTORE - instruction. */ - OP_SAVE_RESTORE_LIST, - - /* A 10-bit field VVVVVNNNNN used for octobyte and quadhalf instructions: - - V Meaning - ----- ------- - 0EEE0 8 copies of $vN[E], OB format - 0EE01 4 copies of $vN[E], QH format - 10110 all 8 elements of $vN, OB format - 10101 all 4 elements of $vN, QH format - 11110 8 copies of immediate N, OB format - 11101 4 copies of immediate N, QH format. */ - OP_MDMX_IMM_REG, - - /* A register operand that must match the destination register. */ - OP_REPEAT_DEST_REG, - - /* A register operand that must match the previous register. */ - OP_REPEAT_PREV_REG, - - /* $pc, which has no encoding in the architectural instruction. */ - OP_PC, - - /* A 4-bit XYZW channel mask or 2-bit XYZW index; the size determines - which. */ - OP_VU0_SUFFIX, - - /* Like OP_VU0_SUFFIX, but used when the operand's value has already - been set. Any suffix used here must match the previous value. */ - OP_VU0_MATCH_SUFFIX -}; - -/* Enumerates the types of MIPS register. */ -enum mips_reg_operand_type { - /* General registers $0-$31. Software names like $at can also be used. */ - OP_REG_GP, - - /* Floating-point registers $f0-$f31. */ - OP_REG_FP, - - /* Coprocessor condition code registers $cc0-$cc7. FPU condition codes - can also be written $fcc0-$fcc7. */ - OP_REG_CCC, - - /* FPRs used in a vector capacity. They can be written $f0-$f31 - or $v0-$v31, although the latter form is not used for the VR5400 - vector instructions. */ - OP_REG_VEC, - - /* DSP accumulator registers $ac0-$ac3. */ - OP_REG_ACC, - - /* Coprocessor registers $0-$31. Mnemonic names like c0_cause can - also be used in some contexts. */ - OP_REG_COPRO, - - /* Hardware registers $0-$31. Mnemonic names like hwr_cpunum can - also be used in some contexts. */ - OP_REG_HW, - - /* Floating-point registers $vf0-$vf31. */ - OP_REG_VF, - - /* Integer registers $vi0-$vi31. */ - OP_REG_VI, - - /* R5900 VU0 registers $I, $Q, $R and $ACC. */ - OP_REG_R5900_I, - OP_REG_R5900_Q, - OP_REG_R5900_R, - OP_REG_R5900_ACC -}; - -/* Base class for all operands. */ -struct mips_operand -{ - /* The type of the operand. */ - enum mips_operand_type type; - - /* The operand occupies SIZE bits of the instruction, starting at LSB. */ - unsigned short size; - unsigned short lsb; -}; - -/* Describes an integer operand with a regular encoding pattern. */ -struct mips_int_operand -{ - struct mips_operand root; - - /* The low ROOT.SIZE bits of MAX_VAL encodes (MAX_VAL + BIAS) << SHIFT. - The cyclically previous field value encodes 1 << SHIFT less than that, - and so on. E.g. - - - for { { T, 4, L }, 14, 0, 0 }, field values 0...14 encode themselves, - but 15 encodes -1. - - - { { T, 8, L }, 127, 0, 2 } is a normal signed 8-bit operand that is - shifted left two places. - - - { { T, 3, L }, 8, 0, 0 } is a normal unsigned 3-bit operand except - that 0 encodes 8. - - - { { ... }, 0, 1, 3 } means that N encodes (N + 1) << 3. */ - unsigned int max_val; - int bias; - unsigned int shift; - - /* True if the operand should be printed as hex rather than decimal. */ - bfd_boolean print_hex; -}; - -/* Uses a lookup table to describe a small integer operand. */ -struct mips_mapped_int_operand -{ - struct mips_operand root; - - /* Maps each encoding value to the integer that it represents. */ - const int *int_map; - - /* True if the operand should be printed as hex rather than decimal. */ - bfd_boolean print_hex; -}; - -/* An operand that encodes the most significant bit position of a bitfield. - Given a bitfield that spans bits [MSB, LSB], some operands of this type - encode MSB directly while others encode MSB - LSB. Each operand of this - type is preceded by an integer operand that specifies LSB. - - The assembly form varies between instructions. For some instructions, - such as EXT, the operand is written as the bitfield size. For others, - such as EXTS, it is written in raw MSB - LSB form. */ -struct mips_msb_operand -{ - struct mips_operand root; - - /* The assembly-level operand encoded by a field value of 0. */ - int bias; - - /* True if the operand encodes MSB directly, false if it encodes - MSB - LSB. */ - bfd_boolean add_lsb; - - /* The maximum value of MSB + 1. */ - unsigned int opsize; -}; - -/* Describes a single register operand. */ -struct mips_reg_operand -{ - struct mips_operand root; - - /* The type of register. */ - enum mips_reg_operand_type reg_type; - - /* If nonnull, REG_MAP[N] gives the register associated with encoding N, - otherwise the encoding is the same as the register number. */ - const unsigned char *reg_map; -}; - -/* Describes an operand that encodes a pair of registers. */ -struct mips_reg_pair_operand -{ - struct mips_operand root; - - /* The type of register. */ - enum mips_reg_operand_type reg_type; - - /* Encoding N represents REG1_MAP[N], REG2_MAP[N]. */ - unsigned char *reg1_map; - unsigned char *reg2_map; -}; - -/* Describes an operand that is calculated relative to a base PC. - The base PC is usually the address of the following instruction, - but the rules for MIPS16 instructions like ADDIUPC are more complicated. */ -struct mips_pcrel_operand -{ - /* Encodes the offset. */ - struct mips_int_operand root; - - /* The low ALIGN_LOG2 bits of the base PC are cleared to give PC', - which is then added to the offset encoded by ROOT. */ - unsigned int align_log2 : 8; - - /* If INCLUDE_ISA_BIT, the ISA bit of the original base PC is then - reinstated. This is true for jumps and branches and false for - PC-relative data instructions. */ - unsigned int include_isa_bit : 1; - - /* If FLIP_ISA_BIT, the ISA bit of the result is inverted. - This is true for JALX and false otherwise. */ - unsigned int flip_isa_bit : 1; -}; - -/* Return true if the assembly syntax allows OPERAND to be omitted. */ - -static inline bfd_boolean -mips_optional_operand_p (const struct mips_operand *operand) -{ - return (operand->type == OP_OPTIONAL_REG - || operand->type == OP_REPEAT_PREV_REG); -} - -/* Return a version of INSN in which the field specified by OPERAND - has value UVAL. */ - -static inline unsigned int -mips_insert_operand (const struct mips_operand *operand, unsigned int insn, - unsigned int uval) -{ - unsigned int mask; - - mask = (1 << operand->size) - 1; - insn &= ~(mask << operand->lsb); - insn |= (uval & mask) << operand->lsb; - return insn; -} - -/* Extract OPERAND from instruction INSN. */ - -static inline unsigned int -mips_extract_operand (const struct mips_operand *operand, unsigned int insn) -{ - return (insn >> operand->lsb) & ((1 << operand->size) - 1); -} - -/* UVAL is the value encoded by OPERAND. Return it in signed form. */ - -static inline int -mips_signed_operand (const struct mips_operand *operand, unsigned int uval) -{ - unsigned int sign_bit, mask; - - mask = (1 << operand->size) - 1; - sign_bit = 1 << (operand->size - 1); - return ((uval + sign_bit) & mask) - sign_bit; -} - -/* Return the integer that OPERAND encodes as UVAL. */ - -static inline int -mips_decode_int_operand (const struct mips_int_operand *operand, - unsigned int uval) -{ - uval |= (operand->max_val - uval) & -(1 << operand->root.size); - uval += operand->bias; - uval <<= operand->shift; - return uval; -} - -/* Return the maximum value that can be encoded by OPERAND. */ - -static inline int -mips_int_operand_max (const struct mips_int_operand *operand) -{ - return (operand->max_val + operand->bias) << operand->shift; -} - -/* Return the minimum value that can be encoded by OPERAND. */ - -static inline int -mips_int_operand_min (const struct mips_int_operand *operand) -{ - unsigned int mask; - - mask = (1 << operand->root.size) - 1; - return mips_int_operand_max (operand) - (mask << operand->shift); -} - -/* Return the register that OPERAND encodes as UVAL. */ - -static inline int -mips_decode_reg_operand (const struct mips_reg_operand *operand, - unsigned int uval) -{ - if (operand->reg_map) - uval = operand->reg_map[uval]; - return uval; -} - -/* PC-relative operand OPERAND has value UVAL and is relative to BASE_PC. - Return the address that it encodes. */ - -static inline bfd_vma -mips_decode_pcrel_operand (const struct mips_pcrel_operand *operand, - bfd_vma base_pc, unsigned int uval) -{ - bfd_vma addr; - - addr = base_pc & -(1 << operand->align_log2); - addr += mips_decode_int_operand (&operand->root, uval); - if (operand->include_isa_bit) - addr |= base_pc & 1; - if (operand->flip_isa_bit) - addr ^= 1; - return addr; -} - -/* This structure holds information for a particular instruction. */ - -struct mips_opcode -{ - /* The name of the instruction. */ - const char *name; - /* A string describing the arguments for this instruction. */ - const char *args; - /* The basic opcode for the instruction. When assembling, this - opcode is modified by the arguments to produce the actual opcode - that is used. If pinfo is INSN_MACRO, then this is 0. */ - unsigned long match; - /* If pinfo is not INSN_MACRO, then this is a bit mask for the - relevant portions of the opcode when disassembling. If the - actual opcode anded with the match field equals the opcode field, - then we have found the correct instruction. If pinfo is - INSN_MACRO, then this field is the macro identifier. */ - unsigned long mask; - /* For a macro, this is INSN_MACRO. Otherwise, it is a collection - of bits describing the instruction, notably any relevant hazard - information. */ - unsigned long pinfo; - /* A collection of additional bits describing the instruction. */ - unsigned long pinfo2; - /* A collection of bits describing the instruction sets of which this - instruction or macro is a member. */ - unsigned long membership; - /* A collection of bits describing the ASE of which this instruction - or macro is a member. */ - unsigned long ase; - /* A collection of bits describing the instruction sets of which this - instruction or macro is not a member. */ - unsigned long exclusions; -}; - -/* These are the characters which may appear in the args field of an - instruction. They appear in the order in which the fields appear - when the instruction is used. Commas and parentheses in the args - string are ignored when assembling, and written into the output - when disassembling. - - Each of these characters corresponds to a mask field defined above. - - "1" 5 bit sync type (OP_*_STYPE) - "<" 5 bit shift amount (OP_*_SHAMT) - ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT) - "a" 26 bit target address (OP_*_TARGET) - "+i" likewise, but flips bit 0 - "b" 5 bit base register (OP_*_RS) - "c" 10 bit breakpoint code (OP_*_CODE) - "d" 5 bit destination register specifier (OP_*_RD) - "h" 5 bit prefx hint (OP_*_PREFX) - "i" 16 bit unsigned immediate (OP_*_IMMEDIATE) - "j" 16 bit signed immediate (OP_*_DELTA) - "k" 5 bit cache opcode in target register position (OP_*_CACHE) - "o" 16 bit signed offset (OP_*_DELTA) - "p" 16 bit PC relative branch target address (OP_*_DELTA) - "q" 10 bit extra breakpoint code (OP_*_CODE2) - "r" 5 bit same register used as both source and target (OP_*_RS) - "s" 5 bit source register specifier (OP_*_RS) - "t" 5 bit target register (OP_*_RT) - "u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE) - "v" 5 bit same register used as both source and destination (OP_*_RS) - "w" 5 bit same register used as both target and destination (OP_*_RT) - "U" 5 bit same destination register in both OP_*_RD and OP_*_RT - (used by clo and clz) - "C" 25 bit coprocessor function code (OP_*_COPZ) - "B" 20 bit syscall/breakpoint function code (OP_*_CODE20) - "J" 19 bit wait function code (OP_*_CODE19) - "x" accept and ignore register name - "z" must be zero register - "K" 5 bit Hardware Register (rdhwr instruction) (OP_*_RD) - "+A" 5 bit ins/ext/dins/dext/dinsm/dextm position, which becomes - LSB (OP_*_SHAMT; OP_*_EXTLSB or OP_*_STYPE may be used for - microMIPS compatibility). - Enforces: 0 <= pos < 32. - "+B" 5 bit ins/dins size, which becomes MSB (OP_*_INSMSB). - Requires that "+A" or "+E" occur first to set position. - Enforces: 0 < (pos+size) <= 32. - "+C" 5 bit ext/dext size, which becomes MSBD (OP_*_EXTMSBD). - Requires that "+A" or "+E" occur first to set position. - Enforces: 0 < (pos+size) <= 32. - (Also used by "dext" w/ different limits, but limits for - that are checked by the M_DEXT macro.) - "+E" 5 bit dinsu/dextu position, which becomes LSB-32 (OP_*_SHAMT). - Enforces: 32 <= pos < 64. - "+F" 5 bit "dinsm/dinsu" size, which becomes MSB-32 (OP_*_INSMSB). - Requires that "+A" or "+E" occur first to set position. - Enforces: 32 < (pos+size) <= 64. - "+G" 5 bit "dextm" size, which becomes MSBD-32 (OP_*_EXTMSBD). - Requires that "+A" or "+E" occur first to set position. - Enforces: 32 < (pos+size) <= 64. - "+H" 5 bit "dextu" size, which becomes MSBD (OP_*_EXTMSBD). - Requires that "+A" or "+E" occur first to set position. - Enforces: 32 < (pos+size) <= 64. - - Floating point instructions: - "D" 5 bit destination register (OP_*_FD) - "M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up) - "N" 3 bit branch condition code (OP_*_BCC) (only used for mips4 and up) - "S" 5 bit fs source 1 register (OP_*_FS) - "T" 5 bit ft source 2 register (OP_*_FT) - "R" 5 bit fr source 3 register (OP_*_FR) - "V" 5 bit same register used as floating source and destination (OP_*_FS) - "W" 5 bit same register used as floating target and destination (OP_*_FT) - - Coprocessor instructions: - "E" 5 bit target register (OP_*_RT) - "G" 5 bit destination register (OP_*_RD) - "H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL) - "P" 5 bit performance-monitor register (OP_*_PERFREG) - "e" 5 bit vector register byte specifier (OP_*_VECBYTE) - "%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN) - - Macro instructions: - "A" General 32 bit expression - "I" 32 bit immediate (value placed in imm_expr). - "F" 64 bit floating point constant in .rdata - "L" 64 bit floating point constant in .lit8 - "f" 32 bit floating point constant - "l" 32 bit floating point constant in .lit4 - - MDMX and VR5400 instruction operands (note that while these use the - FP register fields, the MDMX instructions accept both $fN and $vN names - for the registers): - "O" alignment offset (OP_*_ALN) - "Q" vector/scalar/immediate source (OP_*_VSEL and OP_*_FT) - "X" destination register (OP_*_FD) - "Y" source register (OP_*_FS) - "Z" source register (OP_*_FT) - - R5900 VU0 Macromode instructions: - "+5" 5 bit floating point register (FD) - "+6" 5 bit floating point register (FS) - "+7" 5 bit floating point register (FT) - "+8" 5 bit integer register (FD) - "+9" 5 bit integer register (FS) - "+0" 5 bit integer register (FT) - "+K" match an existing 4-bit channel mask starting at bit 21 - "+L" 2-bit channel index starting at bit 21 - "+M" 2-bit channel index starting at bit 23 - "+N" match an existing 2-bit channel index starting at bit 0 - "+f" 15 bit immediate for VCALLMS - "+g" 5 bit signed immediate for VIADDI - "+m" $ACC register (syntax only) - "+q" $Q register (syntax only) - "+r" $R register (syntax only) - "+y" $I register (syntax only) - "#+" "++" decorator in ($reg++) sequence - "#-" "--" decorator in (--$reg) sequence - - DSP ASE usage: - "2" 2 bit unsigned immediate for byte align (OP_*_BP) - "3" 3 bit unsigned immediate (OP_*_SA3) - "4" 4 bit unsigned immediate (OP_*_SA4) - "5" 8 bit unsigned immediate (OP_*_IMM8) - "6" 5 bit unsigned immediate (OP_*_RS) - "7" 2 bit dsp accumulator register (OP_*_DSPACC) - "8" 6 bit unsigned immediate (OP_*_WRDSP) - "9" 2 bit dsp accumulator register (OP_*_DSPACC_S) - "0" 6 bit signed immediate (OP_*_DSPSFT) - ":" 7 bit signed immediate (OP_*_DSPSFT_7) - "'" 6 bit unsigned immediate (OP_*_RDDSP) - "@" 10 bit signed immediate (OP_*_IMM10) - - MT ASE usage: - "!" 1 bit usermode flag (OP_*_MT_U) - "$" 1 bit load high flag (OP_*_MT_H) - "*" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_T) - "&" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_D) - "g" 5 bit coprocessor 1 and 2 destination register (OP_*_RD) - "+t" 5 bit coprocessor 0 destination register (OP_*_RT) - - MCU ASE usage: - "~" 12 bit offset (OP_*_OFFSET12) - "\" 3 bit position for aset and aclr (OP_*_3BITPOS) - - VIRT ASE usage: - "+J" 10-bit hypcall code (OP_*CODE10) - - UDI immediates: - "+1" UDI immediate bits 6-10 - "+2" UDI immediate bits 6-15 - "+3" UDI immediate bits 6-20 - "+4" UDI immediate bits 6-25 - - Octeon: - "+x" Bit index field of bbit. Enforces: 0 <= index < 32. - "+X" Bit index field of bbit aliasing bbit32. Matches if 32 <= index < 64, - otherwise skips to next candidate. - "+p" Position field of cins/cins32/exts/exts32. Enforces 0 <= pos < 32. - "+P" Position field of cins/exts aliasing cins32/exts32. Matches if - 32 <= pos < 64, otherwise skips to next candidate. - "+Q" Immediate field of seqi/snei. Enforces -512 <= imm < 512. - "+s" Length-minus-one field of cins32/exts32. Requires msb position - of the field to be <= 31. - "+S" Length-minus-one field of cins/exts. Requires msb position - of the field to be <= 63. - - Loongson-3A: - "+a" 8-bit signed offset in bit 6 (OP_*_OFFSET_A) - "+b" 8-bit signed offset in bit 3 (OP_*_OFFSET_B) - "+c" 9-bit signed offset in bit 6 (OP_*_OFFSET_C) - "+z" 5-bit rz register (OP_*_RZ) - "+Z" 5-bit fz register (OP_*_FZ) - - Enhanced VA Scheme: - "+j" 9-bit signed offset in bit 7 (OP_*_EVAOFFSET) - - Other: - "()" parens surrounding optional value - "," separates operands - "+" Start of extension sequence. - - Characters used so far, for quick reference when adding more: - "1234567890" - "%[]<>(),+:'@!#$*&\~" - "ABCDEFGHIJKLMNOPQRSTUVWXYZ" - "abcdefghijklopqrstuvwxz" - - Extension character sequences used so far ("+" followed by the - following), for quick reference when adding more: - "1234567890" - "ABCEFGHJKLMNPQSXZ" - "abcfgijmpqrstxyz" -*/ - -/* These are the bits which may be set in the pinfo field of an - instructions, if it is not equal to INSN_MACRO. */ - -/* Writes to operand number N. */ -#define INSN_WRITE_SHIFT 0 -#define INSN_WRITE_1 0x00000001 -#define INSN_WRITE_2 0x00000002 -#define INSN_WRITE_ALL 0x00000003 -/* Reads from operand number N. */ -#define INSN_READ_SHIFT 2 -#define INSN_READ_1 0x00000004 -#define INSN_READ_2 0x00000008 -#define INSN_READ_3 0x00000010 -#define INSN_READ_4 0x00000020 -#define INSN_READ_ALL 0x0000003c -/* Modifies general purpose register 31. */ -#define INSN_WRITE_GPR_31 0x00000040 -/* Modifies coprocessor condition code. */ -#define INSN_WRITE_COND_CODE 0x00000080 -/* Reads coprocessor condition code. */ -#define INSN_READ_COND_CODE 0x00000100 -/* TLB operation. */ -#define INSN_TLB 0x00000200 -/* Reads coprocessor register other than floating point register. */ -#define INSN_COP 0x00000400 -/* Instruction loads value from memory, requiring delay. */ -#define INSN_LOAD_MEMORY_DELAY 0x00000800 -/* Instruction loads value from coprocessor, requiring delay. */ -#define INSN_LOAD_COPROC_DELAY 0x00001000 -/* Instruction has unconditional branch delay slot. */ -#define INSN_UNCOND_BRANCH_DELAY 0x00002000 -/* Instruction has conditional branch delay slot. */ -#define INSN_COND_BRANCH_DELAY 0x00004000 -/* Conditional branch likely: if branch not taken, insn nullified. */ -#define INSN_COND_BRANCH_LIKELY 0x00008000 -/* Moves to coprocessor register, requiring delay. */ -#define INSN_COPROC_MOVE_DELAY 0x00010000 -/* Loads coprocessor register from memory, requiring delay. */ -#define INSN_COPROC_MEMORY_DELAY 0x00020000 -/* Reads the HI register. */ -#define INSN_READ_HI 0x00040000 -/* Reads the LO register. */ -#define INSN_READ_LO 0x00080000 -/* Modifies the HI register. */ -#define INSN_WRITE_HI 0x00100000 -/* Modifies the LO register. */ -#define INSN_WRITE_LO 0x00200000 -/* Not to be placed in a branch delay slot, either architecturally - or for ease of handling (such as with instructions that take a trap). */ -#define INSN_NO_DELAY_SLOT 0x00400000 -/* Instruction stores value into memory. */ -#define INSN_STORE_MEMORY 0x00800000 -/* Instruction uses single precision floating point. */ -#define FP_S 0x01000000 -/* Instruction uses double precision floating point. */ -#define FP_D 0x02000000 -/* Instruction is part of the tx39's integer multiply family. */ -#define INSN_MULT 0x04000000 -/* Reads general purpose register 24. */ -#define INSN_READ_GPR_24 0x08000000 -/* Writes to general purpose register 24. */ -#define INSN_WRITE_GPR_24 0x10000000 -/* A user-defined instruction. */ -#define INSN_UDI 0x20000000 -/* Instruction is actually a macro. It should be ignored by the - disassembler, and requires special treatment by the assembler. */ -#define INSN_MACRO 0xffffffff - -/* These are the bits which may be set in the pinfo2 field of an - instruction. */ - -/* Instruction is a simple alias (I.E. "move" for daddu/addu/or) */ -#define INSN2_ALIAS 0x00000001 -/* Instruction reads MDMX accumulator. */ -#define INSN2_READ_MDMX_ACC 0x00000002 -/* Instruction writes MDMX accumulator. */ -#define INSN2_WRITE_MDMX_ACC 0x00000004 -/* Macro uses single-precision floating-point instructions. This should - only be set for macros. For instructions, FP_S in pinfo carries the - same information. */ -#define INSN2_M_FP_S 0x00000008 -/* Macro uses double-precision floating-point instructions. This should - only be set for macros. For instructions, FP_D in pinfo carries the - same information. */ -#define INSN2_M_FP_D 0x00000010 -/* Instruction has a branch delay slot that requires a 16-bit instruction. */ -#define INSN2_BRANCH_DELAY_16BIT 0x00000020 -/* Instruction has a branch delay slot that requires a 32-bit instruction. */ -#define INSN2_BRANCH_DELAY_32BIT 0x00000040 -/* Writes to the stack pointer ($29). */ -#define INSN2_WRITE_SP 0x00000080 -/* Reads from the stack pointer ($29). */ -#define INSN2_READ_SP 0x00000100 -/* Reads the RA ($31) register. */ -#define INSN2_READ_GPR_31 0x00000200 -/* Reads the program counter ($pc). */ -#define INSN2_READ_PC 0x00000400 -/* Is an unconditional branch insn. */ -#define INSN2_UNCOND_BRANCH 0x00000800 -/* Is a conditional branch insn. */ -#define INSN2_COND_BRANCH 0x00001000 -/* Reads from $16. This is true of the MIPS16 0x6500 nop. */ -#define INSN2_READ_GPR_16 0x00002000 -/* Has an "\.x?y?z?w?" suffix based on mips_vu0_channel_mask. */ -#define INSN2_VU0_CHANNEL_SUFFIX 0x00004000 - -/* Masks used to mark instructions to indicate which MIPS ISA level - they were introduced in. INSN_ISA_MASK masks an enumeration that - specifies the base ISA level(s). The remainder of a 32-bit - word constructed using these macros is a bitmask of the remaining - INSN_* values below. */ - -#define INSN_ISA_MASK 0x0000000ful - -/* We cannot start at zero due to ISA_UNKNOWN below. */ -#define INSN_ISA1 1 -#define INSN_ISA2 2 -#define INSN_ISA3 3 -#define INSN_ISA4 4 -#define INSN_ISA5 5 -#define INSN_ISA32 6 -#define INSN_ISA32R2 7 -#define INSN_ISA64 8 -#define INSN_ISA64R2 9 -/* Below this point the INSN_* values correspond to combinations of ISAs. - They are only for use in the opcodes table to indicate membership of - a combination of ISAs that cannot be expressed using the usual inclusion - ordering on the above INSN_* values. */ -#define INSN_ISA3_32 10 -#define INSN_ISA3_32R2 11 -#define INSN_ISA4_32 12 -#define INSN_ISA4_32R2 13 -#define INSN_ISA5_32R2 14 - -/* Given INSN_ISA* values X and Y, where X ranges over INSN_ISA1 through - INSN_ISA5_32R2 and Y ranges over INSN_ISA1 through INSN_ISA64R2, - this table describes whether at least one of the ISAs described by X - is/are implemented by ISA Y. (Think of Y as the ISA level supported by - a particular core and X as the ISA level(s) at which a certain instruction - is defined.) The ISA(s) described by X is/are implemented by Y iff - (mips_isa_table[(Y & INSN_ISA_MASK) - 1] >> ((X & INSN_ISA_MASK) - 1)) & 1 - is non-zero. */ -static const unsigned int mips_isa_table[] = - { 0x0001, 0x0003, 0x0607, 0x1e0f, 0x3e1f, 0x0a23, 0x3e63, 0x3ebf, 0x3fff }; - -/* Masks used for Chip specific instructions. */ -#define INSN_CHIP_MASK 0xc3ff0f20 - -/* Cavium Networks Octeon instructions. */ -#define INSN_OCTEON 0x00000800 -#define INSN_OCTEONP 0x00000200 -#define INSN_OCTEON2 0x00000100 - -/* MIPS R5900 instruction */ -#define INSN_5900 0x00004000 - -/* MIPS R4650 instruction. */ -#define INSN_4650 0x00010000 -/* LSI R4010 instruction. */ -#define INSN_4010 0x00020000 -/* NEC VR4100 instruction. */ -#define INSN_4100 0x00040000 -/* Toshiba R3900 instruction. */ -#define INSN_3900 0x00080000 -/* MIPS R10000 instruction. */ -#define INSN_10000 0x00100000 -/* Broadcom SB-1 instruction. */ -#define INSN_SB1 0x00200000 -/* NEC VR4111/VR4181 instruction. */ -#define INSN_4111 0x00400000 -/* NEC VR4120 instruction. */ -#define INSN_4120 0x00800000 -/* NEC VR5400 instruction. */ -#define INSN_5400 0x01000000 -/* NEC VR5500 instruction. */ -#define INSN_5500 0x02000000 - -/* ST Microelectronics Loongson 2E. */ -#define INSN_LOONGSON_2E 0x40000000 -/* ST Microelectronics Loongson 2F. */ -#define INSN_LOONGSON_2F 0x80000000 -/* Loongson 3A. */ -#define INSN_LOONGSON_3A 0x00000400 -/* RMI Xlr instruction */ -#define INSN_XLR 0x00000020 - -/* DSP ASE */ -#define ASE_DSP 0x00000001 -#define ASE_DSP64 0x00000002 -/* DSP R2 ASE */ -#define ASE_DSPR2 0x00000004 -/* Enhanced VA Scheme */ -#define ASE_EVA 0x00000008 -/* MCU (MicroController) ASE */ -#define ASE_MCU 0x00000010 -/* MDMX ASE */ -#define ASE_MDMX 0x00000020 -/* MIPS-3D ASE */ -#define ASE_MIPS3D 0x00000040 -/* MT ASE */ -#define ASE_MT 0x00000080 -/* SmartMIPS ASE */ -#define ASE_SMARTMIPS 0x00000100 -/* Virtualization ASE */ -#define ASE_VIRT 0x00000200 -#define ASE_VIRT64 0x00000400 - -/* MIPS ISA defines, use instead of hardcoding ISA level. */ - -#define ISA_UNKNOWN 0 /* Gas internal use. */ -#define ISA_MIPS1 INSN_ISA1 -#define ISA_MIPS2 INSN_ISA2 -#define ISA_MIPS3 INSN_ISA3 -#define ISA_MIPS4 INSN_ISA4 -#define ISA_MIPS5 INSN_ISA5 - -#define ISA_MIPS32 INSN_ISA32 -#define ISA_MIPS64 INSN_ISA64 - -#define ISA_MIPS32R2 INSN_ISA32R2 -#define ISA_MIPS64R2 INSN_ISA64R2 - - -/* CPU defines, use instead of hardcoding processor number. Keep this - in sync with bfd/archures.c in order for machine selection to work. */ -#define CPU_UNKNOWN 0 /* Gas internal use. */ -#define CPU_R3000 3000 -#define CPU_R3900 3900 -#define CPU_R4000 4000 -#define CPU_R4010 4010 -#define CPU_VR4100 4100 -#define CPU_R4111 4111 -#define CPU_VR4120 4120 -#define CPU_R4300 4300 -#define CPU_R4400 4400 -#define CPU_R4600 4600 -#define CPU_R4650 4650 -#define CPU_R5000 5000 -#define CPU_VR5400 5400 -#define CPU_VR5500 5500 -#define CPU_R5900 5900 -#define CPU_R6000 6000 -#define CPU_RM7000 7000 -#define CPU_R8000 8000 -#define CPU_RM9000 9000 -#define CPU_R10000 10000 -#define CPU_R12000 12000 -#define CPU_R14000 14000 -#define CPU_R16000 16000 -#define CPU_MIPS16 16 -#define CPU_MIPS32 32 -#define CPU_MIPS32R2 33 -#define CPU_MIPS5 5 -#define CPU_MIPS64 64 -#define CPU_MIPS64R2 65 -#define CPU_SB1 12310201 /* octal 'SB', 01. */ -#define CPU_LOONGSON_2E 3001 -#define CPU_LOONGSON_2F 3002 -#define CPU_LOONGSON_3A 3003 -#define CPU_OCTEON 6501 -#define CPU_OCTEONP 6601 -#define CPU_OCTEON2 6502 -#define CPU_XLR 887682 /* decimal 'XLR' */ - -/* Return true if the given CPU is included in INSN_* mask MASK. */ - -static inline bfd_boolean -cpu_is_member (int cpu, unsigned int mask) -{ - switch (cpu) - { - case CPU_R4650: - case CPU_RM7000: - case CPU_RM9000: - return (mask & INSN_4650) != 0; - - case CPU_R4010: - return (mask & INSN_4010) != 0; - - case CPU_VR4100: - return (mask & INSN_4100) != 0; - - case CPU_R3900: - return (mask & INSN_3900) != 0; - - case CPU_R10000: - case CPU_R12000: - case CPU_R14000: - case CPU_R16000: - return (mask & INSN_10000) != 0; - - case CPU_SB1: - return (mask & INSN_SB1) != 0; - - case CPU_R4111: - return (mask & INSN_4111) != 0; - - case CPU_VR4120: - return (mask & INSN_4120) != 0; - - case CPU_VR5400: - return (mask & INSN_5400) != 0; - - case CPU_VR5500: - return (mask & INSN_5500) != 0; - - case CPU_R5900: - return (mask & INSN_5900) != 0; - - case CPU_LOONGSON_2E: - return (mask & INSN_LOONGSON_2E) != 0; - - case CPU_LOONGSON_2F: - return (mask & INSN_LOONGSON_2F) != 0; - - case CPU_LOONGSON_3A: - return (mask & INSN_LOONGSON_3A) != 0; - - case CPU_OCTEON: - return (mask & INSN_OCTEON) != 0; - - case CPU_OCTEONP: - return (mask & INSN_OCTEONP) != 0; - - case CPU_OCTEON2: - return (mask & INSN_OCTEON2) != 0; - - case CPU_XLR: - return (mask & INSN_XLR) != 0; - - default: - return FALSE; - } -} - -/* Test for membership in an ISA including chip specific ISAs. INSN - is pointer to an element of the opcode table; ISA is the specified - ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to - test, or zero if no CPU specific ISA test is desired. Return true - if instruction INSN is available to the given ISA and CPU. */ - -static inline bfd_boolean -opcode_is_member (const struct mips_opcode *insn, int isa, int ase, int cpu) -{ - if (!cpu_is_member (cpu, insn->exclusions)) - { - /* Test for ISA level compatibility. */ - if ((isa & INSN_ISA_MASK) != 0 - && (insn->membership & INSN_ISA_MASK) != 0 - && ((mips_isa_table[(isa & INSN_ISA_MASK) - 1] - >> ((insn->membership & INSN_ISA_MASK) - 1)) & 1) != 0) - return TRUE; - - /* Test for ASE compatibility. */ - if ((ase & insn->ase) != 0) - return TRUE; - - /* Test for processor-specific extensions. */ - if (cpu_is_member (cpu, insn->membership)) - return TRUE; - } - return FALSE; -} - -/* This is a list of macro expanded instructions. - - _I appended means immediate - _A appended means target address of a jump - _AB appended means address with (possibly zero) base register - _D appended means 64 bit floating point constant - _S appended means 32 bit floating point constant. */ - -enum -{ - M_ABS, - M_ACLR_AB, - M_ADD_I, - M_ADDU_I, - M_AND_I, - M_ASET_AB, - M_BALIGN, - M_BC1FL, - M_BC1TL, - M_BC2FL, - M_BC2TL, - M_BEQ, - M_BEQ_I, - M_BEQL, - M_BEQL_I, - M_BGE, - M_BGEL, - M_BGE_I, - M_BGEL_I, - M_BGEU, - M_BGEUL, - M_BGEU_I, - M_BGEUL_I, - M_BGEZ, - M_BGEZL, - M_BGEZALL, - M_BGT, - M_BGTL, - M_BGT_I, - M_BGTL_I, - M_BGTU, - M_BGTUL, - M_BGTU_I, - M_BGTUL_I, - M_BGTZ, - M_BGTZL, - M_BLE, - M_BLEL, - M_BLE_I, - M_BLEL_I, - M_BLEU, - M_BLEUL, - M_BLEU_I, - M_BLEUL_I, - M_BLEZ, - M_BLEZL, - M_BLT, - M_BLTL, - M_BLT_I, - M_BLTL_I, - M_BLTU, - M_BLTUL, - M_BLTU_I, - M_BLTUL_I, - M_BLTZ, - M_BLTZL, - M_BLTZALL, - M_BNE, - M_BNEL, - M_BNE_I, - M_BNEL_I, - M_CACHE_AB, - M_CACHEE_AB, - M_DABS, - M_DADD_I, - M_DADDU_I, - M_DDIV_3, - M_DDIV_3I, - M_DDIVU_3, - M_DDIVU_3I, - M_DIV_3, - M_DIV_3I, - M_DIVU_3, - M_DIVU_3I, - M_DLA_AB, - M_DLCA_AB, - M_DLI, - M_DMUL, - M_DMUL_I, - M_DMULO, - M_DMULO_I, - M_DMULOU, - M_DMULOU_I, - M_DREM_3, - M_DREM_3I, - M_DREMU_3, - M_DREMU_3I, - M_DSUB_I, - M_DSUBU_I, - M_DSUBU_I_2, - M_J_A, - M_JAL_1, - M_JAL_2, - M_JAL_A, - M_JALS_1, - M_JALS_2, - M_JALS_A, - M_JRADDIUSP, - M_JRC, - M_L_DAB, - M_LA_AB, - M_LB_AB, - M_LBE_AB, - M_LBU_AB, - M_LBUE_AB, - M_LCA_AB, - M_LD_AB, - M_LDC1_AB, - M_LDC2_AB, - M_LQC2_AB, - M_LDC3_AB, - M_LDL_AB, - M_LDM_AB, - M_LDP_AB, - M_LDR_AB, - M_LH_AB, - M_LHE_AB, - M_LHU_AB, - M_LHUE_AB, - M_LI, - M_LI_D, - M_LI_DD, - M_LI_S, - M_LI_SS, - M_LL_AB, - M_LLD_AB, - M_LLE_AB, - M_LQ_AB, - M_LW_AB, - M_LWE_AB, - M_LWC0_AB, - M_LWC1_AB, - M_LWC2_AB, - M_LWC3_AB, - M_LWL_AB, - M_LWLE_AB, - M_LWM_AB, - M_LWP_AB, - M_LWR_AB, - M_LWRE_AB, - M_LWU_AB, - M_MSGSND, - M_MSGLD, - M_MSGLD_T, - M_MSGWAIT, - M_MSGWAIT_T, - M_MOVE, - M_MOVEP, - M_MUL, - M_MUL_I, - M_MULO, - M_MULO_I, - M_MULOU, - M_MULOU_I, - M_NOR_I, - M_OR_I, - M_PREF_AB, - M_PREFE_AB, - M_REM_3, - M_REM_3I, - M_REMU_3, - M_REMU_3I, - M_DROL, - M_ROL, - M_DROL_I, - M_ROL_I, - M_DROR, - M_ROR, - M_DROR_I, - M_ROR_I, - M_S_DA, - M_S_DAB, - M_S_S, - M_SAA_AB, - M_SAAD_AB, - M_SC_AB, - M_SCD_AB, - M_SCE_AB, - M_SD_AB, - M_SDC1_AB, - M_SDC2_AB, - M_SQC2_AB, - M_SDC3_AB, - M_SDL_AB, - M_SDM_AB, - M_SDP_AB, - M_SDR_AB, - M_SEQ, - M_SEQ_I, - M_SGE, - M_SGE_I, - M_SGEU, - M_SGEU_I, - M_SGT, - M_SGT_I, - M_SGTU, - M_SGTU_I, - M_SLE, - M_SLE_I, - M_SLEU, - M_SLEU_I, - M_SLT_I, - M_SLTU_I, - M_SNE, - M_SNE_I, - M_SB_AB, - M_SBE_AB, - M_SH_AB, - M_SHE_AB, - M_SQ_AB, - M_SW_AB, - M_SWE_AB, - M_SWC0_AB, - M_SWC1_AB, - M_SWC2_AB, - M_SWC3_AB, - M_SWL_AB, - M_SWLE_AB, - M_SWM_AB, - M_SWP_AB, - M_SWR_AB, - M_SWRE_AB, - M_SUB_I, - M_SUBU_I, - M_SUBU_I_2, - M_TEQ_I, - M_TGE_I, - M_TGEU_I, - M_TLT_I, - M_TLTU_I, - M_TNE_I, - M_TRUNCWD, - M_TRUNCWS, - M_ULD_AB, - M_ULH_AB, - M_ULHU_AB, - M_ULW_AB, - M_USH_AB, - M_USW_AB, - M_USD_AB, - M_XOR_I, - M_COP0, - M_COP1, - M_COP2, - M_COP3, - M_NUM_MACROS -}; - - -/* The order of overloaded instructions matters. Label arguments and - register arguments look the same. Instructions that can have either - for arguments must apear in the correct order in this table for the - assembler to pick the right one. In other words, entries with - immediate operands must apear after the same instruction with - registers. - - Many instructions are short hand for other instructions (i.e., The - jal <register> instruction is short for jalr <register>). */ - -extern const struct mips_operand mips_vu0_channel_mask; -extern const struct mips_operand *decode_mips_operand (const char *); -extern const struct mips_opcode mips_builtin_opcodes[]; -extern const int bfd_mips_num_builtin_opcodes; -extern struct mips_opcode *mips_opcodes; -extern int bfd_mips_num_opcodes; -#define NUMOPCODES bfd_mips_num_opcodes - - -/* The rest of this file adds definitions for the mips16 TinyRISC - processor. */ - -/* These are the bitmasks and shift counts used for the different - fields in the instruction formats. Other than OP, no masks are - provided for the fixed portions of an instruction, since they are - not needed. - - The I format uses IMM11. - - The RI format uses RX and IMM8. - - The RR format uses RX, and RY. - - The RRI format uses RX, RY, and IMM5. - - The RRR format uses RX, RY, and RZ. - - The RRI_A format uses RX, RY, and IMM4. - - The SHIFT format uses RX, RY, and SHAMT. - - The I8 format uses IMM8. - - The I8_MOVR32 format uses RY and REGR32. - - The IR_MOV32R format uses REG32R and MOV32Z. - - The I64 format uses IMM8. - - The RI64 format uses RY and IMM5. - */ - -#define MIPS16OP_MASK_OP 0x1f -#define MIPS16OP_SH_OP 11 -#define MIPS16OP_MASK_IMM11 0x7ff -#define MIPS16OP_SH_IMM11 0 -#define MIPS16OP_MASK_RX 0x7 -#define MIPS16OP_SH_RX 8 -#define MIPS16OP_MASK_IMM8 0xff -#define MIPS16OP_SH_IMM8 0 -#define MIPS16OP_MASK_RY 0x7 -#define MIPS16OP_SH_RY 5 -#define MIPS16OP_MASK_IMM5 0x1f -#define MIPS16OP_SH_IMM5 0 -#define MIPS16OP_MASK_RZ 0x7 -#define MIPS16OP_SH_RZ 2 -#define MIPS16OP_MASK_IMM4 0xf -#define MIPS16OP_SH_IMM4 0 -#define MIPS16OP_MASK_REGR32 0x1f -#define MIPS16OP_SH_REGR32 0 -#define MIPS16OP_MASK_REG32R 0x1f -#define MIPS16OP_SH_REG32R 3 -#define MIPS16OP_EXTRACT_REG32R(i) ((((i) >> 5) & 7) | ((i) & 0x18)) -#define MIPS16OP_MASK_MOVE32Z 0x7 -#define MIPS16OP_SH_MOVE32Z 0 -#define MIPS16OP_MASK_IMM6 0x3f -#define MIPS16OP_SH_IMM6 5 - -/* These are the characters which may appears in the args field of a MIPS16 - instruction. They appear in the order in which the fields appear when the - instruction is used. Commas and parentheses in the args string are ignored - when assembling, and written into the output when disassembling. - - "y" 3 bit register (MIPS16OP_*_RY) - "x" 3 bit register (MIPS16OP_*_RX) - "z" 3 bit register (MIPS16OP_*_RZ) - "Z" 3 bit register (MIPS16OP_*_MOVE32Z) - "v" 3 bit same register as source and destination (MIPS16OP_*_RX) - "w" 3 bit same register as source and destination (MIPS16OP_*_RY) - "0" zero register ($0) - "S" stack pointer ($sp or $29) - "P" program counter - "R" return address register ($ra or $31) - "X" 5 bit MIPS register (MIPS16OP_*_REGR32) - "Y" 5 bit MIPS register (MIPS16OP_*_REG32R) - "6" 6 bit unsigned break code (MIPS16OP_*_IMM6) - "a" 26 bit jump address - "i" likewise, but flips bit 0 - "e" 11 bit extension value - "l" register list for entry instruction - "L" register list for exit instruction - - "I" an immediate value used for macros - - The remaining codes may be extended. Except as otherwise noted, - the full extended operand is a 16 bit signed value. - "<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned) - ">" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 5 bit unsigned) - "[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned) - "]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned) - "4" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed) - "5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5) - "H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5) - "W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5) - "D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5) - "j" 5 bit signed immediate * 0 (MIPS16OP_*_IMM5) - "8" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) - "V" 8 bit unsigned immediate * 4 (MIPS16OP_*_IMM8) - "C" 8 bit unsigned immediate * 8 (MIPS16OP_*_IMM8) - "U" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) (full 16 bit unsigned) - "k" 8 bit signed immediate * 0 (MIPS16OP_*_IMM8) - "K" 8 bit signed immediate * 8 (MIPS16OP_*_IMM8) - "p" 8 bit conditional branch address (MIPS16OP_*_IMM8) - "q" 11 bit branch address (MIPS16OP_*_IMM11) - "A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8) - "B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5) - "E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5) - "m" 7 bit register list for save instruction (18 bit extended) - "M" 7 bit register list for restore instruction (18 bit extended) - */ - -/* Save/restore encoding for the args field when all 4 registers are - either saved as arguments or saved/restored as statics. */ -#define MIPS16_ALL_ARGS 0xe -#define MIPS16_ALL_STATICS 0xb - -/* The following flags have the same value for the mips16 opcode - table: - - INSN_ISA3 - - INSN_UNCOND_BRANCH_DELAY - INSN_COND_BRANCH_DELAY - INSN_COND_BRANCH_LIKELY (never used) - INSN_READ_HI - INSN_READ_LO - INSN_WRITE_HI - INSN_WRITE_LO - INSN_TRAP - FP_D (never used) - */ - -extern const struct mips_operand *decode_mips16_operand (char, bfd_boolean); -extern const struct mips_opcode mips16_opcodes[]; -extern const int bfd_mips16_num_opcodes; - -/* These are the bit masks and shift counts used for the different fields - in the microMIPS instruction formats. No masks are provided for the - fixed portions of an instruction, since they are not needed. */ - -#define MICROMIPSOP_MASK_IMMEDIATE 0xffff -#define MICROMIPSOP_SH_IMMEDIATE 0 -#define MICROMIPSOP_MASK_DELTA 0xffff -#define MICROMIPSOP_SH_DELTA 0 -#define MICROMIPSOP_MASK_CODE10 0x3ff -#define MICROMIPSOP_SH_CODE10 16 /* 10-bit wait code. */ -#define MICROMIPSOP_MASK_TRAP 0xf -#define MICROMIPSOP_SH_TRAP 12 /* 4-bit trap code. */ -#define MICROMIPSOP_MASK_SHAMT 0x1f -#define MICROMIPSOP_SH_SHAMT 11 -#define MICROMIPSOP_MASK_TARGET 0x3ffffff -#define MICROMIPSOP_SH_TARGET 0 -#define MICROMIPSOP_MASK_EXTLSB 0x1f /* "ext" LSB. */ -#define MICROMIPSOP_SH_EXTLSB 6 -#define MICROMIPSOP_MASK_EXTMSBD 0x1f /* "ext" MSBD. */ -#define MICROMIPSOP_SH_EXTMSBD 11 -#define MICROMIPSOP_MASK_INSMSB 0x1f /* "ins" MSB. */ -#define MICROMIPSOP_SH_INSMSB 11 -#define MICROMIPSOP_MASK_CODE 0x3ff -#define MICROMIPSOP_SH_CODE 16 /* 10-bit higher break code. */ -#define MICROMIPSOP_MASK_CODE2 0x3ff -#define MICROMIPSOP_SH_CODE2 6 /* 10-bit lower break code. */ -#define MICROMIPSOP_MASK_CACHE 0x1f -#define MICROMIPSOP_SH_CACHE 21 /* 5-bit cache op. */ -#define MICROMIPSOP_MASK_SEL 0x7 -#define MICROMIPSOP_SH_SEL 11 -#define MICROMIPSOP_MASK_OFFSET12 0xfff -#define MICROMIPSOP_SH_OFFSET12 0 -#define MICROMIPSOP_MASK_3BITPOS 0x7 -#define MICROMIPSOP_SH_3BITPOS 21 -#define MICROMIPSOP_MASK_STYPE 0x1f -#define MICROMIPSOP_SH_STYPE 16 -#define MICROMIPSOP_MASK_OFFSET10 0x3ff -#define MICROMIPSOP_SH_OFFSET10 6 -#define MICROMIPSOP_MASK_RS 0x1f -#define MICROMIPSOP_SH_RS 16 -#define MICROMIPSOP_MASK_RT 0x1f -#define MICROMIPSOP_SH_RT 21 -#define MICROMIPSOP_MASK_RD 0x1f -#define MICROMIPSOP_SH_RD 11 -#define MICROMIPSOP_MASK_FS 0x1f -#define MICROMIPSOP_SH_FS 16 -#define MICROMIPSOP_MASK_FT 0x1f -#define MICROMIPSOP_SH_FT 21 -#define MICROMIPSOP_MASK_FD 0x1f -#define MICROMIPSOP_SH_FD 11 -#define MICROMIPSOP_MASK_FR 0x1f -#define MICROMIPSOP_SH_FR 6 -#define MICROMIPSOP_MASK_RS3 0x1f -#define MICROMIPSOP_SH_RS3 6 -#define MICROMIPSOP_MASK_PREFX 0x1f -#define MICROMIPSOP_SH_PREFX 11 -#define MICROMIPSOP_MASK_BCC 0x7 -#define MICROMIPSOP_SH_BCC 18 -#define MICROMIPSOP_MASK_CCC 0x7 -#define MICROMIPSOP_SH_CCC 13 -#define MICROMIPSOP_MASK_COPZ 0x7fffff -#define MICROMIPSOP_SH_COPZ 3 - -#define MICROMIPSOP_MASK_MB 0x7 -#define MICROMIPSOP_SH_MB 23 -#define MICROMIPSOP_MASK_MC 0x7 -#define MICROMIPSOP_SH_MC 4 -#define MICROMIPSOP_MASK_MD 0x7 -#define MICROMIPSOP_SH_MD 7 -#define MICROMIPSOP_MASK_ME 0x7 -#define MICROMIPSOP_SH_ME 1 -#define MICROMIPSOP_MASK_MF 0x7 -#define MICROMIPSOP_SH_MF 3 -#define MICROMIPSOP_MASK_MG 0x7 -#define MICROMIPSOP_SH_MG 0 -#define MICROMIPSOP_MASK_MH 0x7 -#define MICROMIPSOP_SH_MH 7 -#define MICROMIPSOP_MASK_MJ 0x1f -#define MICROMIPSOP_SH_MJ 0 -#define MICROMIPSOP_MASK_ML 0x7 -#define MICROMIPSOP_SH_ML 4 -#define MICROMIPSOP_MASK_MM 0x7 -#define MICROMIPSOP_SH_MM 1 -#define MICROMIPSOP_MASK_MN 0x7 -#define MICROMIPSOP_SH_MN 4 -#define MICROMIPSOP_MASK_MP 0x1f -#define MICROMIPSOP_SH_MP 5 -#define MICROMIPSOP_MASK_MQ 0x7 -#define MICROMIPSOP_SH_MQ 7 - -#define MICROMIPSOP_MASK_IMMA 0x7f -#define MICROMIPSOP_SH_IMMA 0 -#define MICROMIPSOP_MASK_IMMB 0x7 -#define MICROMIPSOP_SH_IMMB 1 -#define MICROMIPSOP_MASK_IMMC 0xf -#define MICROMIPSOP_SH_IMMC 0 -#define MICROMIPSOP_MASK_IMMD 0x3ff -#define MICROMIPSOP_SH_IMMD 0 -#define MICROMIPSOP_MASK_IMME 0x7f -#define MICROMIPSOP_SH_IMME 0 -#define MICROMIPSOP_MASK_IMMF 0xf -#define MICROMIPSOP_SH_IMMF 0 -#define MICROMIPSOP_MASK_IMMG 0xf -#define MICROMIPSOP_SH_IMMG 0 -#define MICROMIPSOP_MASK_IMMH 0xf -#define MICROMIPSOP_SH_IMMH 0 -#define MICROMIPSOP_MASK_IMMI 0x7f -#define MICROMIPSOP_SH_IMMI 0 -#define MICROMIPSOP_MASK_IMMJ 0xf -#define MICROMIPSOP_SH_IMMJ 0 -#define MICROMIPSOP_MASK_IMML 0xf -#define MICROMIPSOP_SH_IMML 0 -#define MICROMIPSOP_MASK_IMMM 0x7 -#define MICROMIPSOP_SH_IMMM 1 -#define MICROMIPSOP_MASK_IMMN 0x3 -#define MICROMIPSOP_SH_IMMN 4 -#define MICROMIPSOP_MASK_IMMO 0xf -#define MICROMIPSOP_SH_IMMO 0 -#define MICROMIPSOP_MASK_IMMP 0x1f -#define MICROMIPSOP_SH_IMMP 0 -#define MICROMIPSOP_MASK_IMMQ 0x7fffff -#define MICROMIPSOP_SH_IMMQ 0 -#define MICROMIPSOP_MASK_IMMU 0x1f -#define MICROMIPSOP_SH_IMMU 0 -#define MICROMIPSOP_MASK_IMMW 0x3f -#define MICROMIPSOP_SH_IMMW 1 -#define MICROMIPSOP_MASK_IMMX 0xf -#define MICROMIPSOP_SH_IMMX 1 -#define MICROMIPSOP_MASK_IMMY 0x1ff -#define MICROMIPSOP_SH_IMMY 1 - -/* MIPS DSP ASE */ -#define MICROMIPSOP_MASK_DSPACC 0x3 -#define MICROMIPSOP_SH_DSPACC 14 -#define MICROMIPSOP_MASK_DSPSFT 0x3f -#define MICROMIPSOP_SH_DSPSFT 16 -#define MICROMIPSOP_MASK_SA3 0x7 -#define MICROMIPSOP_SH_SA3 13 -#define MICROMIPSOP_MASK_SA4 0xf -#define MICROMIPSOP_SH_SA4 12 -#define MICROMIPSOP_MASK_IMM8 0xff -#define MICROMIPSOP_SH_IMM8 13 -#define MICROMIPSOP_MASK_IMM10 0x3ff -#define MICROMIPSOP_SH_IMM10 16 -#define MICROMIPSOP_MASK_WRDSP 0x3f -#define MICROMIPSOP_SH_WRDSP 14 -#define MICROMIPSOP_MASK_BP 0x3 -#define MICROMIPSOP_SH_BP 14 - -/* Placeholders for fields that only exist in the traditional 32-bit - instruction encoding; see the comment above for details. */ -#define MICROMIPSOP_MASK_CODE20 0 -#define MICROMIPSOP_SH_CODE20 0 -#define MICROMIPSOP_MASK_PERFREG 0 -#define MICROMIPSOP_SH_PERFREG 0 -#define MICROMIPSOP_MASK_CODE19 0 -#define MICROMIPSOP_SH_CODE19 0 -#define MICROMIPSOP_MASK_ALN 0 -#define MICROMIPSOP_SH_ALN 0 -#define MICROMIPSOP_MASK_VECBYTE 0 -#define MICROMIPSOP_SH_VECBYTE 0 -#define MICROMIPSOP_MASK_VECALIGN 0 -#define MICROMIPSOP_SH_VECALIGN 0 -#define MICROMIPSOP_MASK_DSPACC_S 0 -#define MICROMIPSOP_SH_DSPACC_S 0 -#define MICROMIPSOP_MASK_DSPSFT_7 0 -#define MICROMIPSOP_SH_DSPSFT_7 0 -#define MICROMIPSOP_MASK_RDDSP 0 -#define MICROMIPSOP_SH_RDDSP 0 -#define MICROMIPSOP_MASK_MT_U 0 -#define MICROMIPSOP_SH_MT_U 0 -#define MICROMIPSOP_MASK_MT_H 0 -#define MICROMIPSOP_SH_MT_H 0 -#define MICROMIPSOP_MASK_MTACC_T 0 -#define MICROMIPSOP_SH_MTACC_T 0 -#define MICROMIPSOP_MASK_MTACC_D 0 -#define MICROMIPSOP_SH_MTACC_D 0 -#define MICROMIPSOP_MASK_BBITIND 0 -#define MICROMIPSOP_SH_BBITIND 0 -#define MICROMIPSOP_MASK_CINSPOS 0 -#define MICROMIPSOP_SH_CINSPOS 0 -#define MICROMIPSOP_MASK_CINSLM1 0 -#define MICROMIPSOP_SH_CINSLM1 0 -#define MICROMIPSOP_MASK_SEQI 0 -#define MICROMIPSOP_SH_SEQI 0 -#define MICROMIPSOP_SH_OFFSET_A 0 -#define MICROMIPSOP_MASK_OFFSET_A 0 -#define MICROMIPSOP_SH_OFFSET_B 0 -#define MICROMIPSOP_MASK_OFFSET_B 0 -#define MICROMIPSOP_SH_OFFSET_C 0 -#define MICROMIPSOP_MASK_OFFSET_C 0 -#define MICROMIPSOP_SH_RZ 0 -#define MICROMIPSOP_MASK_RZ 0 -#define MICROMIPSOP_SH_FZ 0 -#define MICROMIPSOP_MASK_FZ 0 - -/* microMIPS Enhanced VA Scheme */ -#define MICROMIPSOP_SH_EVAOFFSET 0 -#define MICROMIPSOP_MASK_EVAOFFSET 0x1ff - -/* These are the characters which may appears in the args field of a microMIPS - instruction. They appear in the order in which the fields appear - when the instruction is used. Commas and parentheses in the args - string are ignored when assembling, and written into the output - when disassembling. - - The followings are for 16-bit microMIPS instructions. - - "ma" must be $28 - "mc" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MC) at bit 4 - The same register used as both source and target. - "md" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MD) at bit 7 - "me" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_ME) at bit 1 - The same register used as both source and target. - "mf" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MF) at bit 3 - "mg" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MG) at bit 0 - "mh" 3-bit MIPS register pair (MICROMIPSOP_*_MH) at bit 7 - "mj" 5-bit MIPS registers (MICROMIPSOP_*_MJ) at bit 0 - "ml" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_ML) at bit 4 - "mm" 3-bit MIPS registers 0, 2, 3, 16-20 (MICROMIPSOP_*_MM) at bit 1 - "mn" 3-bit MIPS registers 0, 2, 3, 16-20 (MICROMIPSOP_*_MN) at bit 4 - "mp" 5-bit MIPS registers (MICROMIPSOP_*_MP) at bit 5 - "mq" 3-bit MIPS registers 0, 2-7, 17 (MICROMIPSOP_*_MQ) at bit 7 - "mr" must be program counter - "ms" must be $29 - "mt" must be the same as the previous register - "mx" must be the same as the destination register - "my" must be $31 - "mz" must be $0 - - "mA" 7-bit immediate (-64 .. 63) << 2 (MICROMIPSOP_*_IMMA) - "mB" 3-bit immediate (-1, 1, 4, 8, 12, 16, 20, 24) (MICROMIPSOP_*_IMMB) - "mC" 4-bit immediate (1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 128, 255, - 32768, 65535) (MICROMIPSOP_*_IMMC) - "mD" 10-bit branch address (-512 .. 511) << 1 (MICROMIPSOP_*_IMMD) - "mE" 7-bit branch address (-64 .. 63) << 1 (MICROMIPSOP_*_IMME) - "mF" 4-bit immediate (0 .. 15) (MICROMIPSOP_*_IMMF) - "mG" 4-bit immediate (-1 .. 14) (MICROMIPSOP_*_IMMG) - "mH" 4-bit immediate (0 .. 15) << 1 (MICROMIPSOP_*_IMMH) - "mI" 7-bit immediate (-1 .. 126) (MICROMIPSOP_*_IMMI) - "mJ" 4-bit immediate (0 .. 15) << 2 (MICROMIPSOP_*_IMMJ) - "mL" 4-bit immediate (0 .. 15) (MICROMIPSOP_*_IMML) - "mM" 3-bit immediate (1 .. 8) (MICROMIPSOP_*_IMMM) - "mN" 2-bit immediate (0 .. 3) for register list (MICROMIPSOP_*_IMMN) - "mO" 4-bit immediate (0 .. 15) (MICROMIPSOP_*_IMML) - "mP" 5-bit immediate (0 .. 31) << 2 (MICROMIPSOP_*_IMMP) - "mU" 5-bit immediate (0 .. 31) << 2 (MICROMIPSOP_*_IMMU) - "mW" 6-bit immediate (0 .. 63) << 2 (MICROMIPSOP_*_IMMW) - "mX" 4-bit immediate (-8 .. 7) (MICROMIPSOP_*_IMMX) - "mY" 9-bit immediate (-258 .. -3, 2 .. 257) << 2 (MICROMIPSOP_*_IMMY) - "mZ" must be zero - - In most cases 32-bit microMIPS instructions use the same characters - as MIPS (with ADDIUPC being a notable exception, but there are some - others too). - - "." 10-bit signed offset/number (MICROMIPSOP_*_OFFSET10) - "1" 5-bit sync type (MICROMIPSOP_*_STYPE) - "<" 5-bit shift amount (MICROMIPSOP_*_SHAMT) - ">" shift amount between 32 and 63, stored after subtracting 32 - (MICROMIPSOP_*_SHAMT) - "\" 3-bit position for ASET and ACLR (MICROMIPSOP_*_3BITPOS) - "|" 4-bit trap code (MICROMIPSOP_*_TRAP) - "~" 12-bit signed offset (MICROMIPSOP_*_OFFSET12) - "a" 26-bit target address (MICROMIPSOP_*_TARGET) - "+i" likewise, but flips bit 0 - "b" 5-bit base register (MICROMIPSOP_*_RS) - "c" 10-bit higher breakpoint code (MICROMIPSOP_*_CODE) - "d" 5-bit destination register specifier (MICROMIPSOP_*_RD) - "h" 5-bit PREFX hint (MICROMIPSOP_*_PREFX) - "i" 16-bit unsigned immediate (MICROMIPSOP_*_IMMEDIATE) - "j" 16-bit signed immediate (MICROMIPSOP_*_DELTA) - "k" 5-bit cache opcode in target register position (MICROMIPSOP_*_CACHE) - "n" register list for 32-bit LWM/SWM instruction (MICROMIPSOP_*_RT) - "o" 16-bit signed offset (MICROMIPSOP_*_DELTA) - "p" 16-bit PC-relative branch target address (MICROMIPSOP_*_DELTA) - "q" 10-bit lower breakpoint code (MICROMIPSOP_*_CODE2) - "r" 5-bit same register used as both source and target (MICROMIPSOP_*_RS) - "s" 5-bit source register specifier (MICROMIPSOP_*_RS) - "t" 5-bit target register (MICROMIPSOP_*_RT) - "u" 16-bit upper 16 bits of address (MICROMIPSOP_*_IMMEDIATE) - "v" 5-bit same register used as both source and destination - (MICROMIPSOP_*_RS) - "w" 5-bit same register used as both target and destination - (MICROMIPSOP_*_RT) - "y" 5-bit source 3 register for ALNV.PS (MICROMIPSOP_*_RS3) - "z" must be zero register - "C" 23-bit coprocessor function code (MICROMIPSOP_*_COPZ) - "B" 10-bit syscall/wait function code (MICROMIPSOP_*_CODE10) - "K" 5-bit Hardware Register (RDHWR instruction) (MICROMIPSOP_*_RS) - - "+A" 5-bit INS/EXT/DINS/DEXT/DINSM/DEXTM position, which becomes - LSB (MICROMIPSOP_*_EXTLSB). - Enforces: 0 <= pos < 32. - "+B" 5-bit INS/DINS size, which becomes MSB (MICROMIPSOP_*_INSMSB). - Requires that "+A" or "+E" occur first to set position. - Enforces: 0 < (pos+size) <= 32. - "+C" 5-bit EXT/DEXT size, which becomes MSBD (MICROMIPSOP_*_EXTMSBD). - Requires that "+A" or "+E" occur first to set position. - Enforces: 0 < (pos+size) <= 32. - (Also used by DEXT w/ different limits, but limits for - that are checked by the M_DEXT macro.) - "+E" 5-bit DINSU/DEXTU position, which becomes LSB-32 (MICROMIPSOP_*_EXTLSB). - Enforces: 32 <= pos < 64. - "+F" 5-bit DINSM/DINSU size, which becomes MSB-32 (MICROMIPSOP_*_INSMSB). - Requires that "+A" or "+E" occur first to set position. - Enforces: 32 < (pos+size) <= 64. - "+G" 5-bit DEXTM size, which becomes MSBD-32 (MICROMIPSOP_*_EXTMSBD). - Requires that "+A" or "+E" occur first to set position. - Enforces: 32 < (pos+size) <= 64. - "+H" 5-bit DEXTU size, which becomes MSBD (MICROMIPSOP_*_EXTMSBD). - Requires that "+A" or "+E" occur first to set position. - Enforces: 32 < (pos+size) <= 64. - - PC-relative addition (ADDIUPC) instruction: - "mQ" 23-bit offset (-4194304 .. 4194303) << 2 (MICROMIPSOP_*_IMMQ) - "mb" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MB) at bit 23 - - Floating point instructions: - "D" 5-bit destination register (MICROMIPSOP_*_FD) - "M" 3-bit compare condition code (MICROMIPSOP_*_CCC) - "N" 3-bit branch condition code (MICROMIPSOP_*_BCC) - "R" 5-bit fr source 3 register (MICROMIPSOP_*_FR) - "S" 5-bit fs source 1 register (MICROMIPSOP_*_FS) - "T" 5-bit ft source 2 register (MICROMIPSOP_*_FT) - "V" 5-bit same register used as floating source and destination or target - (MICROMIPSOP_*_FS) - - Coprocessor instructions: - "E" 5-bit target register (MICROMIPSOP_*_RT) - "G" 5-bit source register (MICROMIPSOP_*_RS) - "H" 3-bit sel field for (D)MTC* and (D)MFC* (MICROMIPSOP_*_SEL) - - Macro instructions: - "A" general 32 bit expression - "I" 32-bit immediate (value placed in imm_expr). - "F" 64-bit floating point constant in .rdata - "L" 64-bit floating point constant in .lit8 - "f" 32-bit floating point constant - "l" 32-bit floating point constant in .lit4 - - DSP ASE usage: - "2" 2-bit unsigned immediate for byte align (MICROMIPSOP_*_BP) - "3" 3-bit unsigned immediate (MICROMIPSOP_*_SA3) - "4" 4-bit unsigned immediate (MICROMIPSOP_*_SA4) - "5" 8-bit unsigned immediate (MICROMIPSOP_*_IMM8) - "6" 5-bit unsigned immediate (MICROMIPSOP_*_RS) - "7" 2-bit DSP accumulator register (MICROMIPSOP_*_DSPACC) - "8" 6-bit unsigned immediate (MICROMIPSOP_*_WRDSP) - "0" 6-bit signed immediate (MICROMIPSOP_*_DSPSFT) - "@" 10-bit signed immediate (MICROMIPSOP_*_IMM10) - "^" 5-bit unsigned immediate (MICROMIPSOP_*_RD) - - microMIPS Enhanced VA Scheme: - "+j" 9-bit signed offset in bit 0 (OP_*_EVAOFFSET) - - Other: - "()" parens surrounding optional value - "," separates operands - "+" start of extension sequence - "m" start of microMIPS extension sequence - - Characters used so far, for quick reference when adding more: - "12345678 0" - "<>(),+.@\^|~" - "ABCDEFGHI KLMN RST V " - "abcd f hijklmnopqrstuvw yz" - - Extension character sequences used so far ("+" followed by the - following), for quick reference when adding more: - "" - "" - "ABCEFGH" - "ij" - - Extension character sequences used so far ("m" followed by the - following), for quick reference when adding more: - "" - "" - " BCDEFGHIJ LMNOPQ U WXYZ" - " bcdefghij lmn pq st xyz" -*/ - -extern const struct mips_operand *decode_micromips_operand (const char *); -extern const struct mips_opcode micromips_opcodes[]; -extern const int bfd_micromips_num_opcodes; - -/* A NOP insn impemented as "or at,at,zero". - Used to implement -mfix-loongson2f. */ -#define LOONGSON2F_NOP_INSN 0x00200825 - -#endif /* _MIPS_H_ */ diff --git a/include/opcode/mmix.h b/include/opcode/mmix.h deleted file mode 100644 index f931545..0000000 --- a/include/opcode/mmix.h +++ /dev/null @@ -1,187 +0,0 @@ -/* mmix.h -- Header file for MMIX opcode table - Copyright (C) 2001, 2003, 2010 Free Software Foundation, Inc. - Written by Hans-Peter Nilsson (hp@bitrange.com) - - This file is part of GDB, GAS, and the GNU binutils. - - GDB, GAS, and the GNU binutils are free software; you can redistribute - them and/or modify them under the terms of the GNU General Public - License as published by the Free Software Foundation; either version 3, - or (at your option) any later version. - - GDB, GAS, and the GNU binutils are distributed in the hope that they - will be useful, but WITHOUT ANY WARRANTY; without even the implied - warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See - the GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this file; see the file COPYING3. If not, write to the Free - Software Foundation, 51 Franklin Street - Fifth Floor, Boston, - MA 02110-1301, USA. */ - -/* We could have just a char*[] table indexed by the register number, but - that would not allow for synonyms. The table is terminated with an - entry with a NULL name. */ -struct mmix_spec_reg -{ - const char *name; - unsigned int number; -}; - -/* General indication of the type of instruction. */ -enum mmix_insn_type - { - mmix_type_pseudo, - mmix_type_normal, - mmix_type_branch, - mmix_type_condbranch, - mmix_type_memaccess_octa, - mmix_type_memaccess_tetra, - mmix_type_memaccess_wyde, - mmix_type_memaccess_byte, - mmix_type_memaccess_block, - mmix_type_jsr - }; - -/* Type of operands an instruction takes. Use when parsing assembly code - and disassembling. */ -enum mmix_operands_type - { - mmix_operands_none = 0, - - /* All operands are registers: "$X,$Y,$Z". */ - mmix_operands_regs, - - /* "$X,YZ", like SETH. */ - mmix_operands_reg_yz, - - /* The regular "$X,$Y,$Z|Z". - The Z is optional; if only "$X,$Y" is given, then "$X,$Y,0" is - assumed. */ - mmix_operands_regs_z_opt, - - /* The regular "$X,$Y,$Z|Z". */ - mmix_operands_regs_z, - - /* "Address"; only JMP. Zero operands allowed unless GNU syntax. */ - mmix_operands_jmp, - - /* "$X|X,$Y,$Z|Z": PUSHGO; like "3", but X can be expressed as an - integer. */ - mmix_operands_pushgo, - - /* Two registers or a register and a byte, like FLOT, possibly with - rounding: "$X,$Z|Z" or "$X,ROUND_MODE,$Z|Z". */ - mmix_operands_roundregs_z, - - /* "X,YZ", POP. Unless GNU syntax, zero or one operand is allowed. */ - mmix_operands_pop, - - /* Two registers, possibly with rounding: "$X,$Z" or - "$X,ROUND_MODE,$Z". */ - mmix_operands_roundregs, - - /* "XYZ", like SYNC. */ - mmix_operands_sync, - - /* "X,$Y,$Z|Z", like SYNCD. */ - mmix_operands_x_regs_z, - - /* "$X,Y,$Z|Z", like NEG and NEGU. The Y field is optional, default 0. */ - mmix_operands_neg, - - /* "$X,Address, like GETA or branches. */ - mmix_operands_regaddr, - - /* "$X|X,Address, like PUSHJ. */ - mmix_operands_pushj, - - /* "$X,spec_reg"; GET. */ - mmix_operands_get, - - /* "spec_reg,$Z|Z"; PUT. */ - mmix_operands_put, - - /* Two registers, "$X,$Y". */ - mmix_operands_set, - - /* "$X,0"; SAVE. */ - mmix_operands_save, - - /* "0,$Z"; UNSAVE. */ - mmix_operands_unsave, - - /* "X,Y,Z"; like SWYM or TRAP. Zero (or 1 if GNU syntax) to three - operands, interpreted as 0; XYZ; X, YZ and X, Y, Z. */ - mmix_operands_xyz_opt, - - /* Just "Z", like RESUME. Unless GNU syntax, the operand can be omitted - and will then be assumed zero. */ - mmix_operands_resume, - - /* These are specials to handle that pseudo-directives are specified - like ordinary insns when being mmixal-compatible. They signify the - specific pseudo-directive rather than the operands type. */ - - /* LOC. */ - mmix_operands_loc, - - /* PREFIX. */ - mmix_operands_prefix, - - /* BYTE. */ - mmix_operands_byte, - - /* WYDE. */ - mmix_operands_wyde, - - /* TETRA. */ - mmix_operands_tetra, - - /* OCTA. */ - mmix_operands_octa, - - /* LOCAL. */ - mmix_operands_local, - - /* BSPEC. */ - mmix_operands_bspec, - - /* ESPEC. */ - mmix_operands_espec, - }; - -struct mmix_opcode - { - const char *name; - unsigned long match; - unsigned long lose; - enum mmix_operands_type operands; - - /* This is used by the disassembly function. */ - enum mmix_insn_type type; - }; - -/* Declare the actual tables. */ -extern const struct mmix_opcode mmix_opcodes[]; - -/* This one is terminated with an entry with a NULL name. */ -extern const struct mmix_spec_reg mmix_spec_regs[]; - -/* Some insn values we use when padding and synthesizing address loads. */ -#define IMM_OFFSET_BIT 1 -#define COND_INV_BIT 0x8 -#define PRED_INV_BIT 0x10 - -#define PUSHGO_INSN_BYTE 0xbe -#define GO_INSN_BYTE 0x9e -#define SETL_INSN_BYTE 0xe3 -#define INCML_INSN_BYTE 0xe6 -#define INCMH_INSN_BYTE 0xe5 -#define INCH_INSN_BYTE 0xe4 -#define SWYM_INSN_BYTE 0xfd -#define JMP_INSN_BYTE 0xf0 - -/* We can have 256 - 32 (local registers) - 1 ($255 is not allocatable) - global registers. */ -#define MAX_GREGS 223 diff --git a/include/opcode/mn10200.h b/include/opcode/mn10200.h deleted file mode 100644 index b597d7b..0000000 --- a/include/opcode/mn10200.h +++ /dev/null @@ -1,111 +0,0 @@ -/* mn10200.h -- Header file for Matsushita 10200 opcode table - Copyright 1996, 1997, 2010 Free Software Foundation, Inc. - Written by Jeff Law, Cygnus Support - - This file is part of GDB, GAS, and the GNU binutils. - - GDB, GAS, and the GNU binutils are free software; you can redistribute - them and/or modify them under the terms of the GNU General Public - License as published by the Free Software Foundation; either version 3, - or (at your option) any later version. - - GDB, GAS, and the GNU binutils are distributed in the hope that they - will be useful, but WITHOUT ANY WARRANTY; without even the implied - warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See - the GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this file; see the file COPYING3. If not, write to the Free - Software Foundation, 51 Franklin Street - Fifth Floor, Boston, - MA 02110-1301, USA. */ - -#ifndef MN10200_H -#define MN10200_H - -/* The opcode table is an array of struct mn10200_opcode. */ - -struct mn10200_opcode -{ - /* The opcode name. */ - const char *name; - - /* The opcode itself. Those bits which will be filled in with - operands are zeroes. */ - unsigned long opcode; - - /* The opcode mask. This is used by the disassembler. This is a - mask containing ones indicating those bits which must match the - opcode field, and zeroes indicating those bits which need not - match (and are presumably filled in by operands). */ - unsigned long mask; - - /* The format of this opcode. */ - unsigned char format; - - /* An array of operand codes. Each code is an index into the - operand table. They appear in the order which the operands must - appear in assembly code, and are terminated by a zero. */ - unsigned char operands[8]; -}; - -/* The table itself is sorted by major opcode number, and is otherwise - in the order in which the disassembler should consider - instructions. */ -extern const struct mn10200_opcode mn10200_opcodes[]; -extern const int mn10200_num_opcodes; - - -/* The operands table is an array of struct mn10200_operand. */ - -struct mn10200_operand -{ - /* The number of bits in the operand. */ - int bits; - - /* How far the operand is left shifted in the instruction. */ - int shift; - - /* One bit syntax flags. */ - int flags; -}; - -/* Elements in the table are retrieved by indexing with values from - the operands field of the mn10200_opcodes table. */ - -extern const struct mn10200_operand mn10200_operands[]; - -/* Values defined for the flags field of a struct mn10200_operand. */ -#define MN10200_OPERAND_DREG 0x1 - -#define MN10200_OPERAND_AREG 0x2 - -#define MN10200_OPERAND_PSW 0x4 - -#define MN10200_OPERAND_MDR 0x8 - -#define MN10200_OPERAND_SIGNED 0x10 - -#define MN10200_OPERAND_PROMOTE 0x20 - -#define MN10200_OPERAND_PAREN 0x40 - -#define MN10200_OPERAND_REPEATED 0x80 - -#define MN10200_OPERAND_EXTENDED 0x100 - -#define MN10200_OPERAND_NOCHECK 0x200 - -#define MN10200_OPERAND_PCREL 0x400 - -#define MN10200_OPERAND_MEMADDR 0x800 - -#define MN10200_OPERAND_RELAX 0x1000 - -#define FMT_1 1 -#define FMT_2 2 -#define FMT_3 3 -#define FMT_4 4 -#define FMT_5 5 -#define FMT_6 6 -#define FMT_7 7 -#endif /* MN10200_H */ diff --git a/include/opcode/mn10300.h b/include/opcode/mn10300.h deleted file mode 100644 index 16a139b..0000000 --- a/include/opcode/mn10300.h +++ /dev/null @@ -1,170 +0,0 @@ -/* mn10300.h -- Header file for Matsushita 10300 opcode table - Copyright 1996, 1997, 1998, 1999, 2003, 2010 Free Software Foundation, Inc. - Written by Jeff Law, Cygnus Support - - This file is part of GDB, GAS, and the GNU binutils. - - GDB, GAS, and the GNU binutils are free software; you can redistribute - them and/or modify them under the terms of the GNU General Public - License as published by the Free Software Foundation; either version 3, - or (at your option) any later version. - - GDB, GAS, and the GNU binutils are distributed in the hope that they - will be useful, but WITHOUT ANY WARRANTY; without even the implied - warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See - the GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this file; see the file COPYING3. If not, write to the Free - Software Foundation, 51 Franklin Street - Fifth Floor, Boston, - MA 02110-1301, USA. */ - -#ifndef MN10300_H -#define MN10300_H - -/* The opcode table is an array of struct mn10300_opcode. */ - -#define MN10300_MAX_OPERANDS 8 -struct mn10300_opcode -{ - /* The opcode name. */ - const char *name; - - /* The opcode itself. Those bits which will be filled in with - operands are zeroes. */ - unsigned long opcode; - - /* The opcode mask. This is used by the disassembler. This is a - mask containing ones indicating those bits which must match the - opcode field, and zeroes indicating those bits which need not - match (and are presumably filled in by operands). */ - unsigned long mask; - - /* A bitmask. For each operand, nonzero if it must not have the same - register specification as all other operands with a nonzero bit in - this flag. ie 0x81 would indicate that operands 7 and 0 must not - match. Note that we count operands from left to right as they appear - in the operands specification below. */ - unsigned int no_match_operands; - - /* The format of this opcode. */ - unsigned char format; - - /* Bitmask indicating what cpu variants this opcode is available on. - We assume mn10300 base opcodes are available everywhere, so we only - have to note opcodes which are available on other variants. */ - unsigned int machine; - - /* An array of operand codes. Each code is an index into the - operand table. They appear in the order which the operands must - appear in assembly code, and are terminated by a zero. */ - unsigned char operands[MN10300_MAX_OPERANDS]; -}; - -/* The table itself is sorted by major opcode number, and is otherwise - in the order in which the disassembler should consider - instructions. */ -extern const struct mn10300_opcode mn10300_opcodes[]; -extern const int mn10300_num_opcodes; - - -/* The operands table is an array of struct mn10300_operand. */ - -struct mn10300_operand -{ - /* The number of bits in the operand. */ - int bits; - - /* How far the operand is left shifted in the instruction. */ - int shift; - - /* One bit syntax flags. */ - int flags; -}; - -/* Elements in the table are retrieved by indexing with values from - the operands field of the mn10300_opcodes table. */ - -extern const struct mn10300_operand mn10300_operands[]; - -/* Values defined for the flags field of a struct mn10300_operand. */ -#define MN10300_OPERAND_DREG 0x1 - -#define MN10300_OPERAND_AREG 0x2 - -#define MN10300_OPERAND_SP 0x4 - -#define MN10300_OPERAND_PSW 0x8 - -#define MN10300_OPERAND_MDR 0x10 - -#define MN10300_OPERAND_SIGNED 0x20 - -#define MN10300_OPERAND_PROMOTE 0x40 - -#define MN10300_OPERAND_PAREN 0x80 - -#define MN10300_OPERAND_REPEATED 0x100 - -#define MN10300_OPERAND_EXTENDED 0x200 - -#define MN10300_OPERAND_SPLIT 0x400 - -#define MN10300_OPERAND_REG_LIST 0x800 - -#define MN10300_OPERAND_PCREL 0x1000 - -#define MN10300_OPERAND_MEMADDR 0x2000 - -#define MN10300_OPERAND_RELAX 0x4000 - -#define MN10300_OPERAND_USP 0x8000 - -#define MN10300_OPERAND_SSP 0x10000 - -#define MN10300_OPERAND_MSP 0x20000 - -#define MN10300_OPERAND_PC 0x40000 - -#define MN10300_OPERAND_EPSW 0x80000 - -#define MN10300_OPERAND_RREG 0x100000 - -#define MN10300_OPERAND_XRREG 0x200000 - -#define MN10300_OPERAND_PLUS 0x400000 - -#define MN10300_OPERAND_24BIT 0x800000 - -#define MN10300_OPERAND_FSREG 0x1000000 - -#define MN10300_OPERAND_FDREG 0x2000000 - -#define MN10300_OPERAND_FPCR 0x4000000 - -/* Opcode Formats. */ -#define FMT_S0 1 -#define FMT_S1 2 -#define FMT_S2 3 -#define FMT_S4 4 -#define FMT_S6 5 -#define FMT_D0 6 -#define FMT_D1 7 -#define FMT_D2 8 -#define FMT_D4 9 -#define FMT_D5 10 -#define FMT_D6 11 -#define FMT_D7 12 -#define FMT_D8 13 -#define FMT_D9 14 -#define FMT_D10 15 -#define FMT_D3 16 - -/* Variants of the mn10300 which have additional opcodes. */ -#define MN103 300 -#define AM30 300 - -#define AM33 330 -#define AM33_2 332 - -#endif /* MN10300_H */ diff --git a/include/opcode/moxie.h b/include/opcode/moxie.h deleted file mode 100644 index dae40c8..0000000 --- a/include/opcode/moxie.h +++ /dev/null @@ -1,74 +0,0 @@ -/* Definitions for decoding the moxie opcode table. - Copyright 2009 Free Software Foundation, Inc. - Contributed by Anthony Green (green@moxielogic.com). - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA - 02110-1301, USA. */ - -/* Form 1 instructions come in different flavors: - - Some have no arguments (MOXIE_F1_NARG) - Some only use the A operand (MOXIE_F1_A) - Some use A and B registers (MOXIE_F1_AB) - Some use A and consume a 4 byte immediate value (MOXIE_F1_A4) - Some use just a 4 byte immediate value (MOXIE_F1_4) - Some use just a 4 byte memory address (MOXIE_F1_M) - Some use B and an indirect A (MOXIE_F1_AiB) - Some use A and an indirect B (MOXIE_F1_ABi) - Some consume a 4 byte immediate value and use X (MOXIE_F1_4A) - Some use B and an indirect A plus 4 bytes (MOXIE_F1_AiB4) - Some use A and an indirect B plus 4 bytes (MOXIE_F1_ABi4) - - Form 2 instructions also come in different flavors: - - Some have no arguments (MOXIE_F2_NARG) - Some use the A register and an 8-bit value (MOXIE_F2_A8V) - - Form 3 instructions also come in different flavors: - - Some have no arguments (MOXIE_F3_NARG) - Some have a 10-bit PC relative operand (MOXIE_F3_PCREL). */ - -#define MOXIE_F1_NARG 0x100 -#define MOXIE_F1_A 0x101 -#define MOXIE_F1_AB 0x102 -/* #define MOXIE_F1_ABC 0x103 */ -#define MOXIE_F1_A4 0x104 -#define MOXIE_F1_4 0x105 -#define MOXIE_F1_AiB 0x106 -#define MOXIE_F1_ABi 0x107 -#define MOXIE_F1_4A 0x108 -#define MOXIE_F1_AiB4 0x109 -#define MOXIE_F1_ABi4 0x10a -#define MOXIE_F1_M 0x10b - -#define MOXIE_F2_NARG 0x200 -#define MOXIE_F2_A8V 0x201 - -#define MOXIE_F3_NARG 0x300 -#define MOXIE_F3_PCREL 0x301 - -#define MOXIE_BAD 0x400 - -typedef struct moxie_opc_info_t -{ - short opcode; - unsigned itype; - const char * name; -} moxie_opc_info_t; - -extern const moxie_opc_info_t moxie_form1_opc_info[128]; -extern const moxie_opc_info_t moxie_form2_opc_info[4]; -extern const moxie_opc_info_t moxie_form3_opc_info[16]; diff --git a/include/opcode/msp430-decode.h b/include/opcode/msp430-decode.h deleted file mode 100644 index 0653ade..0000000 --- a/include/opcode/msp430-decode.h +++ /dev/null @@ -1,130 +0,0 @@ -/* Opcode decoder for the TI MSP430 - Copyright 2012-2013 Free Software Foundation, Inc. - Written by DJ Delorie <dj@redhat.com> - - This file is part of GDB, the GNU Debugger. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA - 02110-1301, USA. */ - -typedef enum -{ - MSO_unknown, - /* Double-operand instructions - all repeat .REPEATS times. */ - MSO_mov, /* dest = src */ - MSO_add, /* dest += src */ - MSO_addc, /* dest += src + carry */ - MSO_subc, /* dest -= (src-1) + carry */ - MSO_sub, /* dest -= src */ - MSO_cmp, /* dest - src -> status */ - MSO_dadd, /* dest += src (as BCD) */ - MSO_bit, /* dest & src -> status */ - MSO_bic, /* dest &= ~src (bit clear) */ - MSO_bis, /* dest |= src (bit set, OR) */ - MSO_xor, /* dest ^= src */ - MSO_and, /* dest &= src */ - - /* Single-operand instructions. */ - MSO_rrc, /* Rotate through carry, dest >>= .REPEATS. */ - MSO_swpb, /* Swap lower bytes of operand. */ - MSO_rra, /* Signed shift dest >>= .REPEATS. */ - MSO_sxt, /* Sign extend lower byte. */ - MSO_push, /* Push .REPEATS registers (or other op) starting at SRC going towards R0. */ - MSO_pop, /* Pop .REPEATS registers starting at DEST going towards R15. */ - MSO_call, - MSO_reti, - - /* Jumps. */ - MSO_jmp, /* PC = SRC if .COND true. */ - - /* Extended single-operand instructions. */ - MSO_rru, /* Unsigned shift right, dest >>= .REPEATS. */ - -} MSP430_Opcode_ID; - -typedef enum -{ - MSP430_Operand_None, - MSP430_Operand_Immediate, - MSP430_Operand_Register, - MSP430_Operand_Indirect, - MSP430_Operand_Indirect_Postinc -} MSP430_Operand_Type; - -typedef enum -{ - MSR_0 = 0, - MSR_PC = 0, - MSR_SP = 1, - MSR_SR = 2, - MSR_CG = 3, - MSR_None = 16, -} MSP430_Register; - -typedef struct -{ - MSP430_Operand_Type type; - int addend; - MSP430_Register reg : 8; - MSP430_Register reg2 : 8; - unsigned char bit_number : 4; - unsigned char condition : 3; -} MSP430_Opcode_Operand; - -typedef enum -{ - MSP430_Byte = 0, - MSP430_Word, - MSP430_Addr -} MSP430_Size; - -/* These numerically match the bit encoding. */ -typedef enum -{ - MSC_nz = 0, - MSC_z, - MSC_nc, - MSC_c, - MSC_n, - MSC_ge, - MSC_l, - MSC_true, -} MSP430_Condition; - -#define MSP430_FLAG_C 0x01 -#define MSP430_FLAG_Z 0x02 -#define MSP430_FLAG_N 0x04 -#define MSP430_FLAG_V 0x80 - -typedef struct -{ - int lineno; - MSP430_Opcode_ID id; - unsigned flags_1:8; /* These flags are set to '1' by the insn. */ - unsigned flags_0:8; /* These flags are set to '0' by the insn. */ - unsigned flags_set:8; /* These flags are set appropriately by the insn. */ - unsigned zc:1; /* If set, pretend the carry bit is zero. */ - unsigned repeat_reg:1; /* If set, count is in REG[repeats]. */ - unsigned ofs_430x:1; /* If set, the offset in any operand is 430x (else use 430 compatibility mode). */ - unsigned repeats:5; /* Contains COUNT-1, or register number. */ - int n_bytes; /* Opcode size in BYTES. */ - char * syntax; - MSP430_Size size; /* Operand size in BITS. */ - MSP430_Condition cond; - /* By convention, these are [0]destination, [1]source. */ - MSP430_Opcode_Operand op[2]; -} MSP430_Opcode_Decoded; - -int msp430_decode_opcode (unsigned long, MSP430_Opcode_Decoded *, int (*)(void *), void *); diff --git a/include/opcode/msp430.h b/include/opcode/msp430.h deleted file mode 100644 index caddc42..0000000 --- a/include/opcode/msp430.h +++ /dev/null @@ -1,194 +0,0 @@ -/* Opcode table for the TI MSP430 microcontrollers - - Copyright 2002-2013 Free Software Foundation, Inc. - Contributed by Dmitry Diky <diwil@mail.ru> - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3, or (at your option) - any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, - MA 02110-1301, USA. */ - -#ifndef __MSP430_H_ -#define __MSP430_H_ - -struct msp430_operand_s -{ - int ol; /* Operand length words. */ - int am; /* Addr mode. */ - int reg; /* Register. */ - int mode; /* Pperand mode. */ -#define OP_REG 0 -#define OP_EXP 1 -#ifndef DASM_SECTION - expressionS exp; -#endif -}; - -#define BYTE_OPERATION (1 << 6) /* Byte operation flag for all instructions. */ - -struct msp430_opcode_s -{ - char *name; - int fmt; - int insn_opnumb; - int bin_opcode; - int bin_mask; -}; - -#define MSP_INSN(name, size, numb, bin, mask) { #name, size, numb, bin, mask } - -static struct msp430_opcode_s msp430_opcodes[] = -{ - MSP_INSN (and, 1, 2, 0xf000, 0xf000), - MSP_INSN (inv, 0, 1, 0xe330, 0xfff0), - MSP_INSN (xor, 1, 2, 0xe000, 0xf000), - MSP_INSN (setz, 0, 0, 0xd322, 0xffff), - MSP_INSN (setc, 0, 0, 0xd312, 0xffff), - MSP_INSN (eint, 0, 0, 0xd232, 0xffff), - MSP_INSN (setn, 0, 0, 0xd222, 0xffff), - MSP_INSN (bis, 1, 2, 0xd000, 0xf000), - MSP_INSN (clrz, 0, 0, 0xc322, 0xffff), - MSP_INSN (clrc, 0, 0, 0xc312, 0xffff), - MSP_INSN (dint, 0, 0, 0xc232, 0xffff), - MSP_INSN (clrn, 0, 0, 0xc222, 0xffff), - MSP_INSN (bic, 1, 2, 0xc000, 0xf000), - MSP_INSN (bit, 1, 2, 0xb000, 0xf000), - MSP_INSN (dadc, 0, 1, 0xa300, 0xff30), - MSP_INSN (dadd, 1, 2, 0xa000, 0xf000), - MSP_INSN (tst, 0, 1, 0x9300, 0xff30), - MSP_INSN (cmp, 1, 2, 0x9000, 0xf000), - MSP_INSN (decd, 0, 1, 0x8320, 0xff30), - MSP_INSN (dec, 0, 1, 0x8310, 0xff30), - MSP_INSN (sub, 1, 2, 0x8000, 0xf000), - MSP_INSN (sbc, 0, 1, 0x7300, 0xff30), - MSP_INSN (subc, 1, 2, 0x7000, 0xf000), - MSP_INSN (adc, 0, 1, 0x6300, 0xff30), - MSP_INSN (rlc, 0, 2, 0x6000, 0xf000), - MSP_INSN (addc, 1, 2, 0x6000, 0xf000), - MSP_INSN (incd, 0, 1, 0x5320, 0xff30), - MSP_INSN (inc, 0, 1, 0x5310, 0xff30), - MSP_INSN (rla, 0, 2, 0x5000, 0xf000), - MSP_INSN (add, 1, 2, 0x5000, 0xf000), - MSP_INSN (nop, 0, 0, 0x4303, 0xffff), - MSP_INSN (clr, 0, 1, 0x4300, 0xff30), - MSP_INSN (ret, 0, 0, 0x4130, 0xff30), - MSP_INSN (pop, 0, 1, 0x4130, 0xff30), - MSP_INSN (br, 0, 3, 0x4000, 0xf000), - MSP_INSN (mov, 1, 2, 0x4000, 0xf000), - MSP_INSN (jmp, 3, 1, 0x3c00, 0xfc00), - MSP_INSN (jl, 3, 1, 0x3800, 0xfc00), - MSP_INSN (jge, 3, 1, 0x3400, 0xfc00), - MSP_INSN (jn, 3, 1, 0x3000, 0xfc00), - MSP_INSN (jc, 3, 1, 0x2c00, 0xfc00), - MSP_INSN (jhs, 3, 1, 0x2c00, 0xfc00), - MSP_INSN (jnc, 3, 1, 0x2800, 0xfc00), - MSP_INSN (jlo, 3, 1, 0x2800, 0xfc00), - MSP_INSN (jz, 3, 1, 0x2400, 0xfc00), - MSP_INSN (jeq, 3, 1, 0x2400, 0xfc00), - MSP_INSN (jnz, 3, 1, 0x2000, 0xfc00), - MSP_INSN (jne, 3, 1, 0x2000, 0xfc00), - MSP_INSN (reti, 2, 0, 0x1300, 0xffc0), - MSP_INSN (call, 2, 1, 0x1280, 0xffc0), - MSP_INSN (push, 2, 1, 0x1200, 0xff80), - MSP_INSN (sxt, 2, 1, 0x1180, 0xffc0), - MSP_INSN (rra, 2, 1, 0x1100, 0xff80), - MSP_INSN (swpb, 2, 1, 0x1080, 0xffc0), - MSP_INSN (rrc, 2, 1, 0x1000, 0xff80), - /* Simple polymorphs. */ - MSP_INSN (beq, 4, 0, 0, 0xffff), - MSP_INSN (bne, 4, 1, 0, 0xffff), - MSP_INSN (blt, 4, 2, 0, 0xffff), - MSP_INSN (bltu, 4, 3, 0, 0xffff), - MSP_INSN (bge, 4, 4, 0, 0xffff), - MSP_INSN (bgeu, 4, 5, 0, 0xffff), - MSP_INSN (bltn, 4, 6, 0, 0xffff), - MSP_INSN (jump, 4, 7, 0, 0xffff), - /* Long polymorphs. */ - MSP_INSN (bgt, 5, 0, 0, 0xffff), - MSP_INSN (bgtu, 5, 1, 0, 0xffff), - MSP_INSN (bleu, 5, 2, 0, 0xffff), - MSP_INSN (ble, 5, 3, 0, 0xffff), - - /* MSP430X instructions - these ones use an extension word. - A negative format indicates an MSP430X instruction. */ - MSP_INSN (addcx, -2, 2, 0x6000, 0xf000), - MSP_INSN (addx, -2, 2, 0x5000, 0xf000), - MSP_INSN (andx, -2, 2, 0xf000, 0xf000), - MSP_INSN (bicx, -2, 2, 0xc000, 0xf000), - MSP_INSN (bisx, -2, 2, 0xd000, 0xf000), - MSP_INSN (bitx, -2, 2, 0xb000, 0xf000), - MSP_INSN (cmpx, -2, 2, 0x9000, 0xf000), - MSP_INSN (daddx, -2, 2, 0xa000, 0xf000), - MSP_INSN (movx, -2, 2, 0x4000, 0xf000), - MSP_INSN (subcx, -2, 2, 0x7000, 0xf000), - MSP_INSN (subx, -2, 2, 0x8000, 0xf000), - MSP_INSN (xorx, -2, 2, 0xe000, 0xf000), - - /* MSP430X Synthetic instructions. */ - MSP_INSN (adcx, -1, 1, 0x6300, 0xff30), - MSP_INSN (clra, -1, 1, 0x4300, 0xff30), - MSP_INSN (clrx, -1, 1, 0x4300, 0xff30), - MSP_INSN (dadcx, -1, 1, 0xa300, 0xff30), - MSP_INSN (decx, -1, 1, 0x8310, 0xff30), - MSP_INSN (decda, -1, 1, 0x8320, 0xff30), - MSP_INSN (decdx, -1, 1, 0x8320, 0xff30), - MSP_INSN (incx, -1, 1, 0x5310, 0xff30), - MSP_INSN (incda, -1, 1, 0x5320, 0xff30), - MSP_INSN (incdx, -1, 1, 0x5320, 0xff30), - MSP_INSN (invx, -1, 1, 0xe330, 0xfff0), - MSP_INSN (popx, -1, 1, 0x4130, 0xff30), - MSP_INSN (rlax, -1, 2, 0x5000, 0xf000), - MSP_INSN (rlcx, -1, 2, 0x6000, 0xf000), - MSP_INSN (sbcx, -1, 1, 0x7300, 0xff30), - MSP_INSN (tsta, -1, 1, 0x9300, 0xff30), - MSP_INSN (tstx, -1, 1, 0x9300, 0xff30), - - MSP_INSN (pushx, -3, 1, 0x1200, 0xff80), - MSP_INSN (rrax, -3, 1, 0x1100, 0xff80), - MSP_INSN (rrcx, -3, 1, 0x1000, 0xff80), - MSP_INSN (swpbx, -3, 1, 0x1080, 0xffc0), - MSP_INSN (sxtx, -3, 1, 0x1180, 0xffc0), - - /* MSP430X Address instructions - no extension word needed. - The insn_opnumb field is used to encode the nature of the - instruction for assembly and disassembly purposes. */ - MSP_INSN (calla, -1, 4, 0x1300, 0xff00), - - MSP_INSN (popm, -1, 5, 0x1600, 0xfe00), - MSP_INSN (pushm, -1, 5, 0x1400, 0xfe00), - - MSP_INSN (rrcm, -1, 6, 0x0040, 0xf3e0), - MSP_INSN (rram, -1, 6, 0x0140, 0xf3e0), - MSP_INSN (rlam, -1, 6, 0x0240, 0xf3e0), - MSP_INSN (rrum, -1, 6, 0x0340, 0xf3e0), - - MSP_INSN (rrux, -1, 7, 0x0340, 0xffe0), /* Synthesized in terms of RRUM. */ - - MSP_INSN (adda, -1, 8, 0x00a0, 0xf0b0), - MSP_INSN (cmpa, -1, 8, 0x0090, 0xf0b0), - MSP_INSN (suba, -1, 8, 0x00b0, 0xf0b0), - - MSP_INSN (reta, -1, 9, 0x0110, 0xffff), - MSP_INSN (bra, -1, 9, 0x0000, 0xf0cf), - MSP_INSN (mova, -1, 9, 0x0000, 0xf080), - MSP_INSN (mova, -1, 9, 0x0080, 0xf0b0), - MSP_INSN (mova, -1, 9, 0x00c0, 0xf0f0), - - /* Pseudo instruction to set the repeat field in the extension word. */ - MSP_INSN (rpt, -1, 10, 0x0000, 0x0000), - - /* End of instruction set. */ - { NULL, 0, 0, 0, 0 } -}; - -#endif diff --git a/include/opcode/nios2.h b/include/opcode/nios2.h deleted file mode 100644 index aa67098..0000000 --- a/include/opcode/nios2.h +++ /dev/null @@ -1,522 +0,0 @@ -/* Nios II opcode list for GAS, the GNU assembler. - Copyright (C) 2012, 2013 Free Software Foundation, Inc. - Contributed by Nigel Gray (ngray@altera.com). - Contributed by Mentor Graphics, Inc. - - This file is part of GAS, the GNU Assembler, and GDB, the GNU disassembler. - - GAS/GDB is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3, or (at your option) - any later version. - - GAS/GDB is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with GAS or GDB; see the file COPYING3. If not, write to - the Free Software Foundation, 51 Franklin Street - Fifth Floor, - Boston, MA 02110-1301, USA. */ - -#ifndef _NIOS2_H_ -#define _NIOS2_H_ - -#include "bfd.h" - -/**************************************************************************** - * This file contains structures, bit masks and shift counts used - * by the GNU toolchain to define the Nios II instruction set and - * access various opcode fields. - ****************************************************************************/ - -/* Identify different overflow situations for error messages. */ -enum overflow_type -{ - call_target_overflow = 0, - branch_target_overflow, - address_offset_overflow, - signed_immed16_overflow, - unsigned_immed16_overflow, - unsigned_immed5_overflow, - custom_opcode_overflow, - no_overflow -}; - -/* This structure holds information for a particular instruction. - - The args field is a string describing the operands. The following - letters can appear in the args: - c - a 5-bit control register index - d - a 5-bit destination register index - s - a 5-bit left source register index - t - a 5-bit right source register index - i - a 16-bit signed immediate - u - a 16-bit unsigned immediate - o - a 16-bit signed program counter relative offset - j - a 5-bit unsigned immediate - b - a 5-bit break instruction constant - l - a 8-bit custom instruction constant - m - a 26-bit unsigned immediate - Literal ',', '(', and ')' characters may also appear in the args as - delimiters. - - The pinfo field is INSN_MACRO for a macro. Otherwise, it is a collection - of bits describing the instruction, notably any relevant hazard - information. - - When assembling, the match field contains the opcode template, which - is modified by the arguments to produce the actual opcode - that is emitted. If pinfo is INSN_MACRO, then this is 0. - - If pinfo is INSN_MACRO, the mask field stores the macro identifier. - Otherwise this is a bit mask for the relevant portions of the opcode - when disassembling. If the actual opcode anded with the match field - equals the opcode field, then we have found the correct instruction. */ - -struct nios2_opcode -{ - const char *name; /* The name of the instruction. */ - const char *args; /* A string describing the arguments for this - instruction. */ - const char *args_test; /* Like args, but with an extra argument for - the expected opcode. */ - unsigned long num_args; /* The number of arguments the instruction - takes. */ - unsigned long match; /* The basic opcode for the instruction. */ - unsigned long mask; /* Mask for the opcode field of the - instruction. */ - unsigned long pinfo; /* Is this a real instruction or instruction - macro? */ - enum overflow_type overflow_msg; /* Used to generate informative - message when fixup overflows. */ -}; - -/* This value is used in the nios2_opcode.pinfo field to indicate that the - instruction is a macro or pseudo-op. This requires special treatment by - the assembler, and is used by the disassembler to determine whether to - check for a nop. */ -#define NIOS2_INSN_MACRO 0x80000000 -#define NIOS2_INSN_MACRO_MOV 0x80000001 -#define NIOS2_INSN_MACRO_MOVI 0x80000002 -#define NIOS2_INSN_MACRO_MOVIA 0x80000004 - -#define NIOS2_INSN_RELAXABLE 0x40000000 -#define NIOS2_INSN_UBRANCH 0x00000010 -#define NIOS2_INSN_CBRANCH 0x00000020 -#define NIOS2_INSN_CALL 0x00000040 - -#define NIOS2_INSN_ADDI 0x00000080 -#define NIOS2_INSN_ANDI 0x00000100 -#define NIOS2_INSN_ORI 0x00000200 -#define NIOS2_INSN_XORI 0x00000400 - - -/* Associates a register name ($6) with a 5-bit index (eg 6). */ -struct nios2_reg -{ - const char *name; - const int index; -}; - - -/* These are bit masks and shift counts for accessing the various - fields of a Nios II instruction. */ - -/* Macros for getting and setting an instruction field. */ -#define GET_INSN_FIELD(X, i) \ - (((i) & OP_MASK_##X) >> OP_SH_##X) -#define SET_INSN_FIELD(X, i, j) \ - ((i) = (((i) & ~OP_MASK_##X) | (((j) << OP_SH_##X) & OP_MASK_##X))) - -/* Instruction field definitions. */ -#define IW_A_LSB 27 -#define IW_A_MSB 31 -#define IW_A_SZ 5 -#define IW_A_MASK 0x1f - -#define IW_B_LSB 22 -#define IW_B_MSB 26 -#define IW_B_SZ 5 -#define IW_B_MASK 0x1f - -#define IW_C_LSB 17 -#define IW_C_MSB 21 -#define IW_C_SZ 5 -#define IW_C_MASK 0x1f - -#define IW_IMM16_LSB 6 -#define IW_IMM16_MSB 21 -#define IW_IMM16_SZ 16 -#define IW_IMM16_MASK 0xffff - -#define IW_IMM26_LSB 6 -#define IW_IMM26_MSB 31 -#define IW_IMM26_SZ 26 -#define IW_IMM26_MASK 0x3ffffff - -#define IW_OP_LSB 0 -#define IW_OP_MSB 5 -#define IW_OP_SZ 6 -#define IW_OP_MASK 0x3f - -#define IW_OPX_LSB 11 -#define IW_OPX_MSB 16 -#define IW_OPX_SZ 6 -#define IW_OPX_MASK 0x3f - -#define IW_SHIFT_IMM5_LSB 6 -#define IW_SHIFT_IMM5_MSB 10 -#define IW_SHIFT_IMM5_SZ 5 -#define IW_SHIFT_IMM5_MASK 0x1f - -#define IW_CONTROL_REGNUM_LSB 6 -#define IW_CONTROL_REGNUM_MSB 9 -#define IW_CONTROL_REGNUM_SZ 4 -#define IW_CONTROL_REGNUM_MASK 0xf - -/* Operator mask and shift. */ -#define OP_MASK_OP (IW_OP_MASK << IW_OP_LSB) -#define OP_SH_OP IW_OP_LSB - -/* Masks and shifts for I-type instructions. */ -#define OP_MASK_IOP (IW_OP_MASK << IW_OP_LSB) -#define OP_SH_IOP IW_OP_LSB - -#define OP_MASK_IMM16 (IW_IMM16_MASK << IW_IMM16_LSB) -#define OP_SH_IMM16 IW_IMM16_LSB - -#define OP_MASK_IRD (IW_B_MASK << IW_B_LSB) -#define OP_SH_IRD IW_B_LSB /* The same as T for I-type. */ - -#define OP_MASK_IRT (IW_B_MASK << IW_B_LSB) -#define OP_SH_IRT IW_B_LSB - -#define OP_MASK_IRS (IW_A_MASK << IW_A_LSB) -#define OP_SH_IRS IW_A_LSB - -/* Masks and shifts for R-type instructions. */ -#define OP_MASK_ROP (IW_OP_MASK << IW_OP_LSB) -#define OP_SH_ROP IW_OP_LSB - -#define OP_MASK_ROPX (IW_OPX_MASK << IW_OPX_LSB) -#define OP_SH_ROPX IW_OPX_LSB - -#define OP_MASK_RRD (IW_C_MASK << IW_C_LSB) -#define OP_SH_RRD IW_C_LSB - -#define OP_MASK_RRT (IW_B_MASK << IW_B_LSB) -#define OP_SH_RRT IW_B_LSB - -#define OP_MASK_RRS (IW_A_MASK << IW_A_LSB) -#define OP_SH_RRS IW_A_LSB - -/* Masks and shifts for J-type instructions. */ -#define OP_MASK_JOP (IW_OP_MASK << IW_OP_LSB) -#define OP_SH_JOP IW_OP_LSB - -#define OP_MASK_IMM26 (IW_IMM26_MASK << IW_IMM26_LSB) -#define OP_SH_IMM26 IW_IMM26_LSB - -/* Masks and shifts for CTL instructions. */ -#define OP_MASK_RCTL 0x000007c0 -#define OP_SH_RCTL 6 - -/* Break instruction imm5 field. */ -#define OP_MASK_TRAP_IMM5 0x000007c0 -#define OP_SH_TRAP_IMM5 6 - -/* Instruction imm5 field. */ -#define OP_MASK_IMM5 (IW_SHIFT_IMM5_MASK << IW_SHIFT_IMM5_LSB) -#define OP_SH_IMM5 IW_SHIFT_IMM5_LSB - -/* Cache operation fields (type j,i(s)). */ -#define OP_MASK_CACHE_OPX (IW_B_MASK << IW_B_LSB) -#define OP_SH_CACHE_OPX IW_B_LSB -#define OP_MASK_CACHE_RRS (IW_A_MASK << IW_A_LSB) -#define OP_SH_CACHE_RRS IW_A_LSB - -/* Custom instruction masks. */ -#define OP_MASK_CUSTOM_A 0x00010000 -#define OP_SH_CUSTOM_A 16 - -#define OP_MASK_CUSTOM_B 0x00008000 -#define OP_SH_CUSTOM_B 15 - -#define OP_MASK_CUSTOM_C 0x00004000 -#define OP_SH_CUSTOM_C 14 - -#define OP_MASK_CUSTOM_N 0x00003fc0 -#define OP_SH_CUSTOM_N 6 -#define OP_MAX_CUSTOM_N 255 - -/* OP instruction values. */ -#define OP_ADDI 4 -#define OP_ANDHI 44 -#define OP_ANDI 12 -#define OP_BEQ 38 -#define OP_BGE 14 -#define OP_BGEU 46 -#define OP_BLT 22 -#define OP_BLTU 54 -#define OP_BNE 30 -#define OP_BR 6 -#define OP_CALL 0 -#define OP_CMPEQI 32 -#define OP_CMPGEI 8 -#define OP_CMPGEUI 40 -#define OP_CMPLTI 16 -#define OP_CMPLTUI 48 -#define OP_CMPNEI 24 -#define OP_CUSTOM 50 -#define OP_FLUSHD 59 -#define OP_FLUSHDA 27 -#define OP_INITD 51 -#define OP_INITDA 19 -#define OP_JMPI 1 -#define OP_LDB 7 -#define OP_LDBIO 39 -#define OP_LDBU 3 -#define OP_LDBUIO 35 -#define OP_LDH 15 -#define OP_LDHIO 47 -#define OP_LDHU 11 -#define OP_LDHUIO 43 -#define OP_LDL 31 -#define OP_LDW 23 -#define OP_LDWIO 55 -#define OP_MULI 36 -#define OP_OPX 58 -#define OP_ORHI 52 -#define OP_ORI 20 -#define OP_RDPRS 56 -#define OP_STB 5 -#define OP_STBIO 37 -#define OP_STC 29 -#define OP_STH 13 -#define OP_STHIO 45 -#define OP_STW 21 -#define OP_STWIO 53 -#define OP_XORHI 60 -#define OP_XORI 28 - -/* OPX instruction values. */ -#define OPX_ADD 49 -#define OPX_AND 14 -#define OPX_BREAK 52 -#define OPX_BRET 9 -#define OPX_CALLR 29 -#define OPX_CMPEQ 32 -#define OPX_CMPGE 8 -#define OPX_CMPGEU 40 -#define OPX_CMPLT 16 -#define OPX_CMPLTU 48 -#define OPX_CMPNE 24 -#define OPX_CRST 62 -#define OPX_DIV 37 -#define OPX_DIVU 36 -#define OPX_ERET 1 -#define OPX_FLUSHI 12 -#define OPX_FLUSHP 4 -#define OPX_HBREAK 53 -#define OPX_INITI 41 -#define OPX_INTR 61 -#define OPX_JMP 13 -#define OPX_MUL 39 -#define OPX_MULXSS 31 -#define OPX_MULXSU 23 -#define OPX_MULXUU 7 -#define OPX_NEXTPC 28 -#define OPX_NOR 6 -#define OPX_OR 22 -#define OPX_RDCTL 38 -#define OPX_RET 5 -#define OPX_ROL 3 -#define OPX_ROLI 2 -#define OPX_ROR 11 -#define OPX_SLL 19 -#define OPX_SLLI 18 -#define OPX_SRA 59 -#define OPX_SRAI 58 -#define OPX_SRL 27 -#define OPX_SRLI 26 -#define OPX_SUB 57 -#define OPX_SYNC 54 -#define OPX_TRAP 45 -#define OPX_WRCTL 46 -#define OPX_WRPRS 20 -#define OPX_XOR 30 - -/* The following macros define the opcode matches for each - instruction code & OP_MASK_INST == OP_MATCH_INST. */ - -/* OP instruction matches. */ -#define OP_MATCH_ADDI OP_ADDI -#define OP_MATCH_ANDHI OP_ANDHI -#define OP_MATCH_ANDI OP_ANDI -#define OP_MATCH_BEQ OP_BEQ -#define OP_MATCH_BGE OP_BGE -#define OP_MATCH_BGEU OP_BGEU -#define OP_MATCH_BLT OP_BLT -#define OP_MATCH_BLTU OP_BLTU -#define OP_MATCH_BNE OP_BNE -#define OP_MATCH_BR OP_BR -#define OP_MATCH_FLUSHD OP_FLUSHD -#define OP_MATCH_FLUSHDA OP_FLUSHDA -#define OP_MATCH_INITD OP_INITD -#define OP_MATCH_INITDA OP_INITDA -#define OP_MATCH_CALL OP_CALL -#define OP_MATCH_CMPEQI OP_CMPEQI -#define OP_MATCH_CMPGEI OP_CMPGEI -#define OP_MATCH_CMPGEUI OP_CMPGEUI -#define OP_MATCH_CMPLTI OP_CMPLTI -#define OP_MATCH_CMPLTUI OP_CMPLTUI -#define OP_MATCH_CMPNEI OP_CMPNEI -#define OP_MATCH_JMPI OP_JMPI -#define OP_MATCH_LDB OP_LDB -#define OP_MATCH_LDBIO OP_LDBIO -#define OP_MATCH_LDBU OP_LDBU -#define OP_MATCH_LDBUIO OP_LDBUIO -#define OP_MATCH_LDH OP_LDH -#define OP_MATCH_LDHIO OP_LDHIO -#define OP_MATCH_LDHU OP_LDHU -#define OP_MATCH_LDHUIO OP_LDHUIO -#define OP_MATCH_LDL OP_LDL -#define OP_MATCH_LDW OP_LDW -#define OP_MATCH_LDWIO OP_LDWIO -#define OP_MATCH_MULI OP_MULI -#define OP_MATCH_OPX OP_OPX -#define OP_MATCH_ORHI OP_ORHI -#define OP_MATCH_ORI OP_ORI -#define OP_MATCH_RDPRS OP_RDPRS -#define OP_MATCH_STB OP_STB -#define OP_MATCH_STBIO OP_STBIO -#define OP_MATCH_STC OP_STC -#define OP_MATCH_STH OP_STH -#define OP_MATCH_STHIO OP_STHIO -#define OP_MATCH_STW OP_STW -#define OP_MATCH_STWIO OP_STWIO -#define OP_MATCH_CUSTOM OP_CUSTOM -#define OP_MATCH_XORHI OP_XORHI -#define OP_MATCH_XORI OP_XORI -#define OP_MATCH_OPX OP_OPX - -/* OPX instruction values. */ -#define OPX_MATCH(code) ((code << IW_OPX_LSB) | OP_OPX) - -#define OP_MATCH_ADD OPX_MATCH (OPX_ADD) -#define OP_MATCH_AND OPX_MATCH (OPX_AND) -#define OP_MATCH_BREAK ((0x1e << 17) | OPX_MATCH (OPX_BREAK)) -#define OP_MATCH_BRET (0xf0000000 | OPX_MATCH (OPX_BRET)) -#define OP_MATCH_CALLR ((0x1f << 17) | OPX_MATCH (OPX_CALLR)) -#define OP_MATCH_CMPEQ OPX_MATCH (OPX_CMPEQ) -#define OP_MATCH_CMPGE OPX_MATCH (OPX_CMPGE) -#define OP_MATCH_CMPGEU OPX_MATCH (OPX_CMPGEU) -#define OP_MATCH_CMPLT OPX_MATCH (OPX_CMPLT) -#define OP_MATCH_CMPLTU OPX_MATCH (OPX_CMPLTU) -#define OP_MATCH_CMPNE OPX_MATCH (OPX_CMPNE) -#define OP_MATCH_DIV OPX_MATCH (OPX_DIV) -#define OP_MATCH_DIVU OPX_MATCH (OPX_DIVU) -#define OP_MATCH_JMP OPX_MATCH (OPX_JMP) -#define OP_MATCH_MUL OPX_MATCH (OPX_MUL) -#define OP_MATCH_MULXSS OPX_MATCH (OPX_MULXSS) -#define OP_MATCH_MULXSU OPX_MATCH (OPX_MULXSU) -#define OP_MATCH_MULXUU OPX_MATCH (OPX_MULXUU) -#define OP_MATCH_NEXTPC OPX_MATCH (OPX_NEXTPC) -#define OP_MATCH_NOR OPX_MATCH (OPX_NOR) -#define OP_MATCH_OR OPX_MATCH (OPX_OR) -#define OP_MATCH_RDCTL OPX_MATCH (OPX_RDCTL) -#define OP_MATCH_RET (0xf8000000 | OPX_MATCH (OPX_RET)) -#define OP_MATCH_ROL OPX_MATCH (OPX_ROL) -#define OP_MATCH_ROLI OPX_MATCH (OPX_ROLI) -#define OP_MATCH_ROR OPX_MATCH (OPX_ROR) -#define OP_MATCH_SLL OPX_MATCH (OPX_SLL) -#define OP_MATCH_SLLI OPX_MATCH (OPX_SLLI) -#define OP_MATCH_SRA OPX_MATCH (OPX_SRA) -#define OP_MATCH_SRAI OPX_MATCH (OPX_SRAI) -#define OP_MATCH_SRL OPX_MATCH (OPX_SRL) -#define OP_MATCH_SRLI OPX_MATCH (OPX_SRLI) -#define OP_MATCH_SUB OPX_MATCH (OPX_SUB) -#define OP_MATCH_SYNC OPX_MATCH (OPX_SYNC) -#define OP_MATCH_TRAP ((0x1d << 17) | OPX_MATCH (OPX_TRAP)) -#define OP_MATCH_ERET (0xef800000 | OPX_MATCH (OPX_ERET)) -#define OP_MATCH_WRCTL OPX_MATCH (OPX_WRCTL) -#define OP_MATCH_WRPRS OPX_MATCH (OPX_WRPRS) -#define OP_MATCH_XOR OPX_MATCH (OPX_XOR) -#define OP_MATCH_FLUSHI OPX_MATCH (OPX_FLUSHI) -#define OP_MATCH_FLUSHP OPX_MATCH (OPX_FLUSHP) -#define OP_MATCH_INITI OPX_MATCH (OPX_INITI) - -/* Some unusual op masks. */ -#define OP_MASK_BREAK ((OP_MASK_RRS | OP_MASK_RRT | OP_MASK_RRD \ - | OP_MASK_ROPX | OP_MASK_OP) \ - & 0xfffff03f) -#define OP_MASK_CALLR ((OP_MASK_RRT | OP_MASK_RRD | OP_MASK_ROPX \ - | OP_MASK_OP)) -#define OP_MASK_JMP ((OP_MASK_RRT | OP_MASK_RRD | OP_MASK_ROPX \ - | OP_MASK_OP)) -#define OP_MASK_SYNC ((OP_MASK_RRT | OP_MASK_RRD | OP_MASK_ROPX \ - | OP_MASK_OP)) -#define OP_MASK_TRAP ((OP_MASK_RRS | OP_MASK_RRT | OP_MASK_RRD \ - | OP_MASK_ROPX | OP_MASK_OP) \ - & 0xfffff83f) -#define OP_MASK_WRCTL ((OP_MASK_RRT | OP_MASK_RRD | OP_MASK_ROPX \ - | OP_MASK_OP)) /*& 0xfffff83f */ -#define OP_MASK_NEXTPC ((OP_MASK_RRS | OP_MASK_RRT | OP_MASK_ROPX \ - | OP_MASK_OP)) -#define OP_MASK_FLUSHI ((OP_MASK_RRT | OP_MASK_RRD | OP_MASK_ROPX \ - | OP_MASK_OP)) -#define OP_MASK_INITI ((OP_MASK_RRT | OP_MASK_RRD | OP_MASK_ROPX \ - | OP_MASK_OP)) - -#define OP_MASK_ROLI ((OP_MASK_RRT | OP_MASK_ROPX | OP_MASK_OP)) -#define OP_MASK_SLLI ((OP_MASK_RRT | OP_MASK_ROPX | OP_MASK_OP)) -#define OP_MASK_SRAI ((OP_MASK_RRT | OP_MASK_ROPX | OP_MASK_OP)) -#define OP_MASK_SRLI ((OP_MASK_RRT | OP_MASK_ROPX | OP_MASK_OP)) -#define OP_MASK_RDCTL ((OP_MASK_RRS | OP_MASK_RRT | OP_MASK_ROPX \ - | OP_MASK_OP)) /*& 0xfffff83f */ - -#ifndef OP_MASK -#define OP_MASK 0xffffffff -#endif - -/* These convenience macros to extract instruction fields are used by GDB. */ -#define GET_IW_A(Iw) \ - (((Iw) >> IW_A_LSB) & IW_A_MASK) -#define GET_IW_B(Iw) \ - (((Iw) >> IW_B_LSB) & IW_B_MASK) -#define GET_IW_C(Iw) \ - (((Iw) >> IW_C_LSB) & IW_C_MASK) -#define GET_IW_CONTROL_REGNUM(Iw) \ - (((Iw) >> IW_CONTROL_REGNUM_LSB) & IW_CONTROL_REGNUM_MASK) -#define GET_IW_IMM16(Iw) \ - (((Iw) >> IW_IMM16_LSB) & IW_IMM16_MASK) -#define GET_IW_IMM26(Iw) \ - (((Iw) >> IW_IMM26_LSB) & IW_IMM26_MASK) -#define GET_IW_OP(Iw) \ - (((Iw) >> IW_OP_LSB) & IW_OP_MASK) -#define GET_IW_OPX(Iw) \ - (((Iw) >> IW_OPX_LSB) & IW_OPX_MASK) - -/* These are the data structures we use to hold the instruction information. */ -extern const struct nios2_opcode nios2_builtin_opcodes[]; -extern const int bfd_nios2_num_builtin_opcodes; -extern struct nios2_opcode *nios2_opcodes; -extern int bfd_nios2_num_opcodes; - -/* These are the data structures used to hold the register information. */ -extern const struct nios2_reg nios2_builtin_regs[]; -extern struct nios2_reg *nios2_regs; -extern const int nios2_num_builtin_regs; -extern int nios2_num_regs; - -/* Machine-independent macro for number of opcodes. */ -#define NUMOPCODES bfd_nios2_num_opcodes -#define NUMREGISTERS nios2_num_regs; - -/* This is made extern so that the assembler can use it to find out - what instruction caused an error. */ -extern const struct nios2_opcode *nios2_find_opcode_hash (unsigned long); - -#endif /* _NIOS2_H */ diff --git a/include/opcode/np1.h b/include/opcode/np1.h deleted file mode 100644 index 6dadafd..0000000 --- a/include/opcode/np1.h +++ /dev/null @@ -1,421 +0,0 @@ -/* Print GOULD NPL instructions for GDB, the GNU debugger. - Copyright 1986, 1987, 1989, 1991, 2010 Free Software Foundation, Inc. - - This file is part of GDB. - - GDB is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3, or (at your option) - any later version. - - GDB is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with GDB; see the file COPYING3. If not, write to - the Free Software Foundation, 51 Franklin Street - Fifth Floor, - Boston, MA 02110-1301, USA. */ - -struct gld_opcode -{ - char *name; - unsigned long opcode; - unsigned long mask; - char *args; - int length; -}; - -/* We store four bytes of opcode for all opcodes because that - is the most any of them need. The actual length of an instruction - is always at least 2 bytes, and at most four. The length of the - instruction is based on the opcode. - - The mask component is a mask saying which bits must match - particular opcode in order for an instruction to be an instance - of that opcode. - - The args component is a string containing characters - that are used to format the arguments to the instruction. */ - -/* Kinds of operands: - r Register in first field - R Register in second field - b Base register in first field - B Base register in second field - v Vector register in first field - V Vector register in first field - A Optional address register (base register) - X Optional index register - I Immediate data (16bits signed) - O Offset field (16bits signed) - h Offset field (15bits signed) - d Offset field (14bits signed) - S Shift count field - - any other characters are printed as is... */ - -/* The assembler requires that this array be sorted as follows: - all instances of the same mnemonic must be consecutive. - All instances of the same mnemonic with the same number of operands - must be consecutive. */ -struct gld_opcode gld_opcodes[] = -{ -{ "lb", 0xb4080000, 0xfc080000, "r,xOA,X", 4 }, -{ "lnb", 0xb8080000, 0xfc080000, "r,xOA,X", 4 }, -{ "lbs", 0xec080000, 0xfc080000, "r,xOA,X", 4 }, -{ "lh", 0xb4000001, 0xfc080001, "r,xOA,X", 4 }, -{ "lnh", 0xb8000001, 0xfc080001, "r,xOA,X", 4 }, -{ "lw", 0xb4000000, 0xfc080000, "r,xOA,X", 4 }, -{ "lnw", 0xb8000000, 0xfc080000, "r,xOA,X", 4 }, -{ "ld", 0xb4000002, 0xfc080002, "r,xOA,X", 4 }, -{ "lnd", 0xb8000002, 0xfc080002, "r,xOA,X", 4 }, -{ "li", 0xf8000000, 0xfc7f0000, "r,I", 4 }, -{ "lpa", 0x50080000, 0xfc080000, "r,xOA,X", 4 }, -{ "la", 0x50000000, 0xfc080000, "r,xOA,X", 4 }, -{ "labr", 0x58080000, 0xfc080000, "b,xOA,X", 4 }, -{ "lbp", 0x90080000, 0xfc080000, "r,xOA,X", 4 }, -{ "lhp", 0x90000001, 0xfc080001, "r,xOA,X", 4 }, -{ "lwp", 0x90000000, 0xfc080000, "r,xOA,X", 4 }, -{ "ldp", 0x90000002, 0xfc080002, "r,xOA,X", 4 }, -{ "suabr", 0x58000000, 0xfc080000, "b,xOA,X", 4 }, -{ "lf", 0xbc000000, 0xfc080000, "r,xOA,X", 4 }, -{ "lfbr", 0xbc080000, 0xfc080000, "b,xOA,X", 4 }, -{ "lwbr", 0x5c000000, 0xfc080000, "b,xOA,X", 4 }, -{ "stb", 0xd4080000, 0xfc080000, "r,xOA,X", 4 }, -{ "sth", 0xd4000001, 0xfc080001, "r,xOA,X", 4 }, -{ "stw", 0xd4000000, 0xfc080000, "r,xOA,X", 4 }, -{ "std", 0xd4000002, 0xfc080002, "r,xOA,X", 4 }, -{ "stf", 0xdc000000, 0xfc080000, "r,xOA,X", 4 }, -{ "stfbr", 0xdc080000, 0xfc080000, "b,xOA,X", 4 }, -{ "stwbr", 0x54000000, 0xfc080000, "b,xOA,X", 4 }, -{ "zmb", 0xd8080000, 0xfc080000, "r,xOA,X", 4 }, -{ "zmh", 0xd8000001, 0xfc080001, "r,xOA,X", 4 }, -{ "zmw", 0xd8000000, 0xfc080000, "r,xOA,X", 4 }, -{ "zmd", 0xd8000002, 0xfc080002, "r,xOA,X", 4 }, -{ "stbp", 0x94080000, 0xfc080000, "r,xOA,X", 4 }, -{ "sthp", 0x94000001, 0xfc080001, "r,xOA,X", 4 }, -{ "stwp", 0x94000000, 0xfc080000, "r,xOA,X", 4 }, -{ "stdp", 0x94000002, 0xfc080002, "r,xOA,X", 4 }, -{ "lil", 0xf80b0000, 0xfc7f0000, "r,D", 4 }, -{ "lwsl1", 0xec000000, 0xfc080000, "r,xOA,X", 4 }, -{ "lwsl2", 0xfc000000, 0xfc080000, "r,xOA,X", 4 }, -{ "lwsl3", 0xfc080000, 0xfc080000, "r,xOA,X", 4 }, - -{ "lvb", 0xb0080000, 0xfc080000, "v,xOA,X", 4 }, -{ "lvh", 0xb0000001, 0xfc080001, "v,xOA,X", 4 }, -{ "lvw", 0xb0000000, 0xfc080000, "v,xOA,X", 4 }, -{ "lvd", 0xb0000002, 0xfc080002, "v,xOA,X", 4 }, -{ "liv", 0x3c040000, 0xfc0f0000, "v,R", 2 }, -{ "livf", 0x3c080000, 0xfc0f0000, "v,R", 2 }, -{ "stvb", 0xd0080000, 0xfc080000, "v,xOA,X", 4 }, -{ "stvh", 0xd0000001, 0xfc080001, "v,xOA,X", 4 }, -{ "stvw", 0xd0000000, 0xfc080000, "v,xOA,X", 4 }, -{ "stvd", 0xd0000002, 0xfc080002, "v,xOA,X", 4 }, - -{ "trr", 0x2c000000, 0xfc0f0000, "r,R", 2 }, -{ "trn", 0x2c040000, 0xfc0f0000, "r,R", 2 }, -{ "trnd", 0x2c0c0000, 0xfc0f0000, "r,R", 2 }, -{ "trabs", 0x2c010000, 0xfc0f0000, "r,R", 2 }, -{ "trabsd", 0x2c090000, 0xfc0f0000, "r,R", 2 }, -{ "trc", 0x2c030000, 0xfc0f0000, "r,R", 2 }, -{ "xcr", 0x28040000, 0xfc0f0000, "r,R", 2 }, -{ "cxcr", 0x2c060000, 0xfc0f0000, "r,R", 2 }, -{ "cxcrd", 0x2c0e0000, 0xfc0f0000, "r,R", 2 }, -{ "tbrr", 0x2c020000, 0xfc0f0000, "r,B", 2 }, -{ "trbr", 0x28030000, 0xfc0f0000, "b,R", 2 }, -{ "xcbr", 0x28020000, 0xfc0f0000, "b,B", 2 }, -{ "tbrbr", 0x28010000, 0xfc0f0000, "b,B", 2 }, - -{ "trvv", 0x28050000, 0xfc0f0000, "v,V", 2 }, -{ "trvvn", 0x2c050000, 0xfc0f0000, "v,V", 2 }, -{ "trvvnd", 0x2c0d0000, 0xfc0f0000, "v,V", 2 }, -{ "trvab", 0x2c070000, 0xfc0f0000, "v,V", 2 }, -{ "trvabd", 0x2c0f0000, 0xfc0f0000, "v,V", 2 }, -{ "cmpv", 0x14060000, 0xfc0f0000, "v,V", 2 }, -{ "expv", 0x14070000, 0xfc0f0000, "v,V", 2 }, -{ "mrvvlt", 0x10030000, 0xfc0f0000, "v,V", 2 }, -{ "mrvvle", 0x10040000, 0xfc0f0000, "v,V", 2 }, -{ "mrvvgt", 0x14030000, 0xfc0f0000, "v,V", 2 }, -{ "mrvvge", 0x14040000, 0xfc0f0000, "v,V", 2 }, -{ "mrvveq", 0x10050000, 0xfc0f0000, "v,V", 2 }, -{ "mrvvne", 0x10050000, 0xfc0f0000, "v,V", 2 }, -{ "mrvrlt", 0x100d0000, 0xfc0f0000, "v,R", 2 }, -{ "mrvrle", 0x100e0000, 0xfc0f0000, "v,R", 2 }, -{ "mrvrgt", 0x140d0000, 0xfc0f0000, "v,R", 2 }, -{ "mrvrge", 0x140e0000, 0xfc0f0000, "v,R", 2 }, -{ "mrvreq", 0x100f0000, 0xfc0f0000, "v,R", 2 }, -{ "mrvrne", 0x140f0000, 0xfc0f0000, "v,R", 2 }, -{ "trvr", 0x140b0000, 0xfc0f0000, "r,V", 2 }, -{ "trrv", 0x140c0000, 0xfc0f0000, "v,R", 2 }, - -{ "bu", 0x40000000, 0xff880000, "xOA,X", 4 }, -{ "bns", 0x70080000, 0xff880000, "xOA,X", 4 }, -{ "bnco", 0x70880000, 0xff880000, "xOA,X", 4 }, -{ "bge", 0x71080000, 0xff880000, "xOA,X", 4 }, -{ "bne", 0x71880000, 0xff880000, "xOA,X", 4 }, -{ "bunge", 0x72080000, 0xff880000, "xOA,X", 4 }, -{ "bunle", 0x72880000, 0xff880000, "xOA,X", 4 }, -{ "bgt", 0x73080000, 0xff880000, "xOA,X", 4 }, -{ "bnany", 0x73880000, 0xff880000, "xOA,X", 4 }, -{ "bs" , 0x70000000, 0xff880000, "xOA,X", 4 }, -{ "bco", 0x70800000, 0xff880000, "xOA,X", 4 }, -{ "blt", 0x71000000, 0xff880000, "xOA,X", 4 }, -{ "beq", 0x71800000, 0xff880000, "xOA,X", 4 }, -{ "buge", 0x72000000, 0xff880000, "xOA,X", 4 }, -{ "bult", 0x72800000, 0xff880000, "xOA,X", 4 }, -{ "ble", 0x73000000, 0xff880000, "xOA,X", 4 }, -{ "bany", 0x73800000, 0xff880000, "xOA,X", 4 }, -{ "brlnk", 0x44000000, 0xfc080000, "r,xOA,X", 4 }, -{ "bib", 0x48000000, 0xfc080000, "r,xOA,X", 4 }, -{ "bih", 0x48080000, 0xfc080000, "r,xOA,X", 4 }, -{ "biw", 0x4c000000, 0xfc080000, "r,xOA,X", 4 }, -{ "bid", 0x4c080000, 0xfc080000, "r,xOA,X", 4 }, -{ "bivb", 0x60000000, 0xfc080000, "r,xOA,X", 4 }, -{ "bivh", 0x60080000, 0xfc080000, "r,xOA,X", 4 }, -{ "bivw", 0x64000000, 0xfc080000, "r,xOA,X", 4 }, -{ "bivd", 0x64080000, 0xfc080000, "r,xOA,X", 4 }, -{ "bvsb", 0x68000000, 0xfc080000, "r,xOA,X", 4 }, -{ "bvsh", 0x68080000, 0xfc080000, "r,xOA,X", 4 }, -{ "bvsw", 0x6c000000, 0xfc080000, "r,xOA,X", 4 }, -{ "bvsd", 0x6c080000, 0xfc080000, "r,xOA,X", 4 }, - -{ "camb", 0x80080000, 0xfc080000, "r,xOA,X", 4 }, -{ "camh", 0x80000001, 0xfc080001, "r,xOA,X", 4 }, -{ "camw", 0x80000000, 0xfc080000, "r,xOA,X", 4 }, -{ "camd", 0x80000002, 0xfc080002, "r,xOA,X", 4 }, -{ "car", 0x10000000, 0xfc0f0000, "r,R", 2 }, -{ "card", 0x14000000, 0xfc0f0000, "r,R", 2 }, -{ "ci", 0xf8050000, 0xfc7f0000, "r,I", 4 }, -{ "chkbnd", 0x5c080000, 0xfc080000, "r,xOA,X", 4 }, - -{ "cavv", 0x10010000, 0xfc0f0000, "v,V", 2 }, -{ "cavr", 0x10020000, 0xfc0f0000, "v,R", 2 }, -{ "cavvd", 0x10090000, 0xfc0f0000, "v,V", 2 }, -{ "cavrd", 0x100b0000, 0xfc0f0000, "v,R", 2 }, - -{ "anmb", 0x84080000, 0xfc080000, "r,xOA,X", 4 }, -{ "anmh", 0x84000001, 0xfc080001, "r,xOA,X", 4 }, -{ "anmw", 0x84000000, 0xfc080000, "r,xOA,X", 4 }, -{ "anmd", 0x84000002, 0xfc080002, "r,xOA,X", 4 }, -{ "anr", 0x04000000, 0xfc0f0000, "r,R", 2 }, -{ "ani", 0xf8080000, 0xfc7f0000, "r,I", 4 }, -{ "ormb", 0xb8080000, 0xfc080000, "r,xOA,X", 4 }, -{ "ormh", 0xb8000001, 0xfc080001, "r,xOA,X", 4 }, -{ "ormw", 0xb8000000, 0xfc080000, "r,xOA,X", 4 }, -{ "ormd", 0xb8000002, 0xfc080002, "r,xOA,X", 4 }, -{ "orr", 0x08000000, 0xfc0f0000, "r,R", 2 }, -{ "oi", 0xf8090000, 0xfc7f0000, "r,I", 4 }, -{ "eomb", 0x8c080000, 0xfc080000, "r,xOA,X", 4 }, -{ "eomh", 0x8c000001, 0xfc080001, "r,xOA,X", 4 }, -{ "eomw", 0x8c000000, 0xfc080000, "r,xOA,X", 4 }, -{ "eomd", 0x8c000002, 0xfc080002, "r,xOA,X", 4 }, -{ "eor", 0x0c000000, 0xfc0f0000, "r,R", 2 }, -{ "eoi", 0xf80a0000, 0xfc7f0000, "r,I", 4 }, - -{ "anvv", 0x04010000, 0xfc0f0000, "v,V", 2 }, -{ "anvr", 0x04020000, 0xfc0f0000, "v,R", 2 }, -{ "orvv", 0x08010000, 0xfc0f0000, "v,V", 2 }, -{ "orvr", 0x08020000, 0xfc0f0000, "v,R", 2 }, -{ "eovv", 0x0c010000, 0xfc0f0000, "v,V", 2 }, -{ "eovr", 0x0c020000, 0xfc0f0000, "v,R", 2 }, - -{ "sacz", 0x100c0000, 0xfc0f0000, "r,R", 2 }, -{ "sla", 0x1c400000, 0xfc600000, "r,S", 2 }, -{ "sll", 0x1c600000, 0xfc600000, "r,S", 2 }, -{ "slc", 0x24400000, 0xfc600000, "r,S", 2 }, -{ "slad", 0x20400000, 0xfc600000, "r,S", 2 }, -{ "slld", 0x20600000, 0xfc600000, "r,S", 2 }, -{ "sra", 0x1c000000, 0xfc600000, "r,S", 2 }, -{ "srl", 0x1c200000, 0xfc600000, "r,S", 2 }, -{ "src", 0x24000000, 0xfc600000, "r,S", 2 }, -{ "srad", 0x20000000, 0xfc600000, "r,S", 2 }, -{ "srld", 0x20200000, 0xfc600000, "r,S", 2 }, -{ "sda", 0x3c030000, 0xfc0f0000, "r,R", 2 }, -{ "sdl", 0x3c020000, 0xfc0f0000, "r,R", 2 }, -{ "sdc", 0x3c010000, 0xfc0f0000, "r,R", 2 }, -{ "sdad", 0x3c0b0000, 0xfc0f0000, "r,R", 2 }, -{ "sdld", 0x3c0a0000, 0xfc0f0000, "r,R", 2 }, - -{ "svda", 0x3c070000, 0xfc0f0000, "v,R", 2 }, -{ "svdl", 0x3c060000, 0xfc0f0000, "v,R", 2 }, -{ "svdc", 0x3c050000, 0xfc0f0000, "v,R", 2 }, -{ "svdad", 0x3c0e0000, 0xfc0f0000, "v,R", 2 }, -{ "svdld", 0x3c0d0000, 0xfc0f0000, "v,R", 2 }, - -{ "sbm", 0xac080000, 0xfc080000, "f,xOA,X", 4 }, -{ "zbm", 0xac000000, 0xfc080000, "f,xOA,X", 4 }, -{ "tbm", 0xa8080000, 0xfc080000, "f,xOA,X", 4 }, -{ "incmb", 0xa0000000, 0xfc080000, "xOA,X", 4 }, -{ "incmh", 0xa0080000, 0xfc080000, "xOA,X", 4 }, -{ "incmw", 0xa4000000, 0xfc080000, "xOA,X", 4 }, -{ "incmd", 0xa4080000, 0xfc080000, "xOA,X", 4 }, -{ "sbmd", 0x7c080000, 0xfc080000, "r,xOA,X", 4 }, -{ "zbmd", 0x7c000000, 0xfc080000, "r,xOA,X", 4 }, -{ "tbmd", 0x78080000, 0xfc080000, "r,xOA,X", 4 }, - -{ "ssm", 0x9c080000, 0xfc080000, "f,xOA,X", 4 }, -{ "zsm", 0x9c000000, 0xfc080000, "f,xOA,X", 4 }, -{ "tsm", 0x98080000, 0xfc080000, "f,xOA,X", 4 }, - -{ "admb", 0xc8080000, 0xfc080000, "r,xOA,X", 4 }, -{ "admh", 0xc8000001, 0xfc080001, "r,xOA,X", 4 }, -{ "admw", 0xc8000000, 0xfc080000, "r,xOA,X", 4 }, -{ "admd", 0xc8000002, 0xfc080002, "r,xOA,X", 4 }, -{ "adr", 0x38000000, 0xfc0f0000, "r,R", 2 }, -{ "armb", 0xe8080000, 0xfc080000, "r,xOA,X", 4 }, -{ "armh", 0xe8000001, 0xfc080001, "r,xOA,X", 4 }, -{ "armw", 0xe8000000, 0xfc080000, "r,xOA,X", 4 }, -{ "armd", 0xe8000002, 0xfc080002, "r,xOA,X", 4 }, -{ "adi", 0xf8010000, 0xfc0f0000, "r,I", 4 }, -{ "sumb", 0xcc080000, 0xfc080000, "r,xOA,X", 4 }, -{ "sumh", 0xcc000001, 0xfc080001, "r,xOA,X", 4 }, -{ "sumw", 0xcc000000, 0xfc080000, "r,xOA,X", 4 }, -{ "sumd", 0xcc000002, 0xfc080002, "r,xOA,X", 4 }, -{ "sur", 0x3c000000, 0xfc0f0000, "r,R", 2 }, -{ "sui", 0xf8020000, 0xfc0f0000, "r,I", 4 }, -{ "mpmb", 0xc0080000, 0xfc080000, "r,xOA,X", 4 }, -{ "mpmh", 0xc0000001, 0xfc080001, "r,xOA,X", 4 }, -{ "mpmw", 0xc0000000, 0xfc080000, "r,xOA,X", 4 }, -{ "mpr", 0x38020000, 0xfc0f0000, "r,R", 2 }, -{ "mprd", 0x3c0f0000, 0xfc0f0000, "r,R", 2 }, -{ "mpi", 0xf8030000, 0xfc0f0000, "r,I", 4 }, -{ "dvmb", 0xc4080000, 0xfc080000, "r,xOA,X", 4 }, -{ "dvmh", 0xc4000001, 0xfc080001, "r,xOA,X", 4 }, -{ "dvmw", 0xc4000000, 0xfc080000, "r,xOA,X", 4 }, -{ "dvr", 0x380a0000, 0xfc0f0000, "r,R", 2 }, -{ "dvi", 0xf8040000, 0xfc0f0000, "r,I", 4 }, -{ "exs", 0x38080000, 0xfc0f0000, "r,R", 2 }, - -{ "advv", 0x30000000, 0xfc0f0000, "v,V", 2 }, -{ "advvd", 0x30080000, 0xfc0f0000, "v,V", 2 }, -{ "adrv", 0x34000000, 0xfc0f0000, "v,R", 2 }, -{ "adrvd", 0x34080000, 0xfc0f0000, "v,R", 2 }, -{ "suvv", 0x30010000, 0xfc0f0000, "v,V", 2 }, -{ "suvvd", 0x30090000, 0xfc0f0000, "v,V", 2 }, -{ "surv", 0x34010000, 0xfc0f0000, "v,R", 2 }, -{ "survd", 0x34090000, 0xfc0f0000, "v,R", 2 }, -{ "mpvv", 0x30020000, 0xfc0f0000, "v,V", 2 }, -{ "mprv", 0x34020000, 0xfc0f0000, "v,R", 2 }, - -{ "adfw", 0xe0080000, 0xfc080000, "r,xOA,X", 4 }, -{ "adfd", 0xe0080002, 0xfc080002, "r,xOA,X", 4 }, -{ "adrfw", 0x38010000, 0xfc0f0000, "r,R", 2 }, -{ "adrfd", 0x38090000, 0xfc0f0000, "r,R", 2 }, -{ "surfw", 0xe0000000, 0xfc080000, "r,xOA,X", 4 }, -{ "surfd", 0xe0000002, 0xfc080002, "r,xOA,X", 4 }, -{ "surfw", 0x38030000, 0xfc0f0000, "r,R", 2 }, -{ "surfd", 0x380b0000, 0xfc0f0000, "r,R", 2 }, -{ "mpfw", 0xe4080000, 0xfc080000, "r,xOA,X", 4 }, -{ "mpfd", 0xe4080002, 0xfc080002, "r,xOA,X", 4 }, -{ "mprfw", 0x38060000, 0xfc0f0000, "r,R", 2 }, -{ "mprfd", 0x380e0000, 0xfc0f0000, "r,R", 2 }, -{ "rfw", 0xe4000000, 0xfc080000, "r,xOA,X", 4 }, -{ "rfd", 0xe4000002, 0xfc080002, "r,xOA,X", 4 }, -{ "rrfw", 0x0c0e0000, 0xfc0f0000, "r", 2 }, -{ "rrfd", 0x0c0f0000, 0xfc0f0000, "r", 2 }, - -{ "advvfw", 0x30040000, 0xfc0f0000, "v,V", 2 }, -{ "advvfd", 0x300c0000, 0xfc0f0000, "v,V", 2 }, -{ "adrvfw", 0x34040000, 0xfc0f0000, "v,R", 2 }, -{ "adrvfd", 0x340c0000, 0xfc0f0000, "v,R", 2 }, -{ "suvvfw", 0x30050000, 0xfc0f0000, "v,V", 2 }, -{ "suvvfd", 0x300d0000, 0xfc0f0000, "v,V", 2 }, -{ "survfw", 0x34050000, 0xfc0f0000, "v,R", 2 }, -{ "survfd", 0x340d0000, 0xfc0f0000, "v,R", 2 }, -{ "mpvvfw", 0x30060000, 0xfc0f0000, "v,V", 2 }, -{ "mpvvfd", 0x300e0000, 0xfc0f0000, "v,V", 2 }, -{ "mprvfw", 0x34060000, 0xfc0f0000, "v,R", 2 }, -{ "mprvfd", 0x340e0000, 0xfc0f0000, "v,R", 2 }, -{ "rvfw", 0x30070000, 0xfc0f0000, "v", 2 }, -{ "rvfd", 0x300f0000, 0xfc0f0000, "v", 2 }, - -{ "fltw", 0x38070000, 0xfc0f0000, "r,R", 2 }, -{ "fltd", 0x380f0000, 0xfc0f0000, "r,R", 2 }, -{ "fixw", 0x38050000, 0xfc0f0000, "r,R", 2 }, -{ "fixd", 0x380d0000, 0xfc0f0000, "r,R", 2 }, -{ "cfpds", 0x3c090000, 0xfc0f0000, "r,R", 2 }, - -{ "fltvw", 0x080d0000, 0xfc0f0000, "v,V", 2 }, -{ "fltvd", 0x080f0000, 0xfc0f0000, "v,V", 2 }, -{ "fixvw", 0x080c0000, 0xfc0f0000, "v,V", 2 }, -{ "fixvd", 0x080e0000, 0xfc0f0000, "v,V", 2 }, -{ "cfpvds", 0x0c0d0000, 0xfc0f0000, "v,V", 2 }, - -{ "orvrn", 0x000a0000, 0xfc0f0000, "r,V", 2 }, -{ "andvrn", 0x00080000, 0xfc0f0000, "r,V", 2 }, -{ "frsteq", 0x04090000, 0xfc0f0000, "r,V", 2 }, -{ "sigma", 0x0c080000, 0xfc0f0000, "r,V", 2 }, -{ "sigmad", 0x0c0a0000, 0xfc0f0000, "r,V", 2 }, -{ "sigmf", 0x08080000, 0xfc0f0000, "r,V", 2 }, -{ "sigmfd", 0x080a0000, 0xfc0f0000, "r,V", 2 }, -{ "prodf", 0x04080000, 0xfc0f0000, "r,V", 2 }, -{ "prodfd", 0x040a0000, 0xfc0f0000, "r,V", 2 }, -{ "maxv", 0x10080000, 0xfc0f0000, "r,V", 2 }, -{ "maxvd", 0x100a0000, 0xfc0f0000, "r,V", 2 }, -{ "minv", 0x14080000, 0xfc0f0000, "r,V", 2 }, -{ "minvd", 0x140a0000, 0xfc0f0000, "r,V", 2 }, - -{ "lpsd", 0xf0000000, 0xfc080000, "xOA,X", 4 }, -{ "ldc", 0xf0080000, 0xfc080000, "xOA,X", 4 }, -{ "spm", 0x040c0000, 0xfc0f0000, "r", 2 }, -{ "rpm", 0x040d0000, 0xfc0f0000, "r", 2 }, -{ "tritr", 0x00070000, 0xfc0f0000, "r", 2 }, -{ "trrit", 0x00060000, 0xfc0f0000, "r", 2 }, -{ "rpswt", 0x04080000, 0xfc0f0000, "r", 2 }, -{ "exr", 0xf8070000, 0xfc0f0000, "", 4 }, -{ "halt", 0x00000000, 0xfc0f0000, "", 2 }, -{ "wait", 0x00010000, 0xfc0f0000, "", 2 }, -{ "nop", 0x00020000, 0xfc0f0000, "", 2 }, -{ "eiae", 0x00030000, 0xfc0f0000, "", 2 }, -{ "efae", 0x000d0000, 0xfc0f0000, "", 2 }, -{ "diae", 0x000e0000, 0xfc0f0000, "", 2 }, -{ "dfae", 0x000f0000, 0xfc0f0000, "", 2 }, -{ "spvc", 0xf8060000, 0xfc0f0000, "r,T,N", 4 }, -{ "rdsts", 0x00090000, 0xfc0f0000, "r", 2 }, -{ "setcpu", 0x000c0000, 0xfc0f0000, "r", 2 }, -{ "cmc", 0x000b0000, 0xfc0f0000, "r", 2 }, -{ "trrcu", 0x00040000, 0xfc0f0000, "r", 2 }, -{ "attnio", 0x00050000, 0xfc0f0000, "", 2 }, -{ "fudit", 0x28080000, 0xfc0f0000, "", 2 }, -{ "break", 0x28090000, 0xfc0f0000, "", 2 }, -{ "frzss", 0x280a0000, 0xfc0f0000, "", 2 }, -{ "ripi", 0x04040000, 0xfc0f0000, "r,R", 2 }, -{ "xcp", 0x04050000, 0xfc0f0000, "r", 2 }, -{ "block", 0x04060000, 0xfc0f0000, "", 2 }, -{ "unblock", 0x04070000, 0xfc0f0000, "", 2 }, -{ "trsc", 0x08060000, 0xfc0f0000, "r,R", 2 }, -{ "tscr", 0x08070000, 0xfc0f0000, "r,R", 2 }, -{ "fq", 0x04080000, 0xfc0f0000, "r", 2 }, -{ "flupte", 0x2c080000, 0xfc0f0000, "r", 2 }, -{ "rviu", 0x040f0000, 0xfc0f0000, "", 2 }, -{ "ldel", 0x280c0000, 0xfc0f0000, "r,R", 2 }, -{ "ldu", 0x280d0000, 0xfc0f0000, "r,R", 2 }, -{ "stdecc", 0x280b0000, 0xfc0f0000, "r,R", 2 }, -{ "trpc", 0x08040000, 0xfc0f0000, "r", 2 }, -{ "tpcr", 0x08050000, 0xfc0f0000, "r", 2 }, -{ "ghalt", 0x0c050000, 0xfc0f0000, "r", 2 }, -{ "grun", 0x0c040000, 0xfc0f0000, "", 2 }, -{ "tmpr", 0x2c0a0000, 0xfc0f0000, "r,R", 2 }, -{ "trmp", 0x2c0b0000, 0xfc0f0000, "r,R", 2 }, - -{ "trrve", 0x28060000, 0xfc0f0000, "r", 2 }, -{ "trver", 0x28070000, 0xfc0f0000, "r", 2 }, -{ "trvlr", 0x280f0000, 0xfc0f0000, "r", 2 }, - -{ "linkfl", 0x18000000, 0xfc0f0000, "r,R", 2 }, -{ "linkbl", 0x18020000, 0xfc0f0000, "r,R", 2 }, -{ "linkfp", 0x18010000, 0xfc0f0000, "r,R", 2 }, -{ "linkbp", 0x18030000, 0xfc0f0000, "r,R", 2 }, -{ "linkpl", 0x18040000, 0xfc0f0000, "r,R", 2 }, -{ "ulinkl", 0x18080000, 0xfc0f0000, "r,R", 2 }, -{ "ulinkp", 0x18090000, 0xfc0f0000, "r,R", 2 }, -{ "ulinktl", 0x180a0000, 0xfc0f0000, "r,R", 2 }, -{ "ulinktp", 0x180b0000, 0xfc0f0000, "r,R", 2 }, -}; - -int numopcodes = sizeof(gld_opcodes) / sizeof(gld_opcodes[0]); - -struct gld_opcode *endop = gld_opcodes + sizeof(gld_opcodes) / - sizeof(gld_opcodes[0]); diff --git a/include/opcode/ns32k.h b/include/opcode/ns32k.h deleted file mode 100644 index 34c42f8..0000000 --- a/include/opcode/ns32k.h +++ /dev/null @@ -1,487 +0,0 @@ -/* ns32k-opcode.h -- Opcode table for National Semi 32k processor - Copyright 1987, 1991, 1994, 2002, 2010 Free Software Foundation, Inc. - - This file is part of GAS, the GNU Assembler. - - GAS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3, or (at your option) - any later version. - - GAS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with GAS; see the file COPYING3. If not, write to - the Free Software Foundation, 51 Franklin Street - Fifth Floor, - Boston, MA 02110-1301, USA. */ - -#ifdef SEQUENT_COMPATABILITY -#define DEF_MODEC 20 -#define DEF_MODEL 21 -#endif - -#ifndef DEF_MODEC -#define DEF_MODEC 20 -#endif - -#ifndef DEF_MODEL -#define DEF_MODEL 20 -#endif -/* - After deciding the instruction entry (via hash.c) the instruction parser - will try to match the operands after the instruction to the required set - given in the entry operandfield. Every operand will result in a change in - the opcode or the addition of data to the opcode. - The operands in the source instruction are checked for inconsistent - semantics. - - F : 32 bit float general form - L : 64 bit float " - B : byte " - W : word " - D : double-word " - A : double-word gen-address-form ie no regs, no immediate - I : integer writeable gen int except immediate (A + reg) - Z : floating writeable gen float except immediate (Z + freg) - d : displacement - b : displacement - pc relative addressing acb - p : displacement - pc relative addressing br bcond bsr cxp - q : quick - i : immediate (8 bits) - This is not a standard ns32k operandtype, it is used to build - instructions like svc arg1,arg2 - Svc is the instruction SuperVisorCall and is sometimes used to - call OS-routines from usermode. Some args might be handy! - r : register number (3 bits) - O : setcfg instruction optionslist - C : cinv instruction optionslist - S : stringinstruction optionslist - U : registerlist save,enter - u : registerlist restore,exit - M : mmu register - P : cpu register - g : 3:rd operand of inss or exts instruction - G : 4:th operand of inss or exts instruction - Those operands are encoded in the same byte. - This byte is placed last in the instruction. - f : operand of sfsr - H : sequent-hack for bsr (Warning) - -column 1 instructions - 2 number of bits in opcode. - 3 number of bits in opcode explicitly - determined by the instruction type. - 4 opcodeseed, the number we build our opcode - from. - 5 operandtypes, used by operandparser. - 6 size in bytes of immediate -*/ -struct ns32k_opcode { - const char *name; - unsigned char opcode_id_size; /* not used by the assembler */ - unsigned char opcode_size; - unsigned long opcode_seed; - const char *operands; - unsigned char im_size; /* not used by dissassembler */ - const char *default_args; /* default to those args when none given */ - char default_modec; /* default to this addr-mode when ambigous - ie when the argument of a general addr-mode - is a plain constant */ - char default_model; /* is a plain label */ -}; - -#ifdef comment -/* This section was from the gdb version of this file. */ - -#ifndef ns32k_opcodeT -#define ns32k_opcodeT int -#endif /* no ns32k_opcodeT */ - -struct not_wot /* ns32k opcode table: wot to do with this */ - /* particular opcode */ -{ - int obits; /* number of opcode bits */ - int ibits; /* number of instruction bits */ - ns32k_opcodeT code; /* op-code (may be > 8 bits!) */ - const char *args; /* how to compile said opcode */ -}; - -struct not /* ns32k opcode text */ -{ - const char *name; /* opcode name: lowercase string [key] */ - struct not_wot detail; /* rest of opcode table [datum] */ -}; - -/* Instructions look like this: - - basic instruction--1, 2, or 3 bytes - index byte for operand A, if operand A is indexed--1 byte - index byte for operand B, if operand B is indexed--1 byte - addressing extension for operand A - addressing extension for operand B - implied operands - - Operand A is the operand listed first in the following opcode table. - Operand B is the operand listed second in the following opcode table. - All instructions have at most 2 general operands, so this is enough. - The implied operands are associated with operands other than A and B. - - Each operand has a digit and a letter. - - The digit gives the position in the assembly language. The letter, - one of the following, tells us what kind of operand it is. */ - -/* F : 32 bit float - * L : 64 bit float - * B : byte - * W : word - * D : double-word - * I : integer not immediate - * Z : floating not immediate - * d : displacement - * q : quick - * i : immediate (8 bits) - * r : register number (3 bits) - * p : displacement - pc relative addressing -*/ - - -#endif /* comment */ - -static const struct ns32k_opcode ns32k_opcodes[]= -{ - { "absf", 14,24, 0x35be, "1F2Z", 4, "", DEF_MODEC,DEF_MODEL }, - { "absl", 14,24, 0x34be, "1L2Z", 8, "", DEF_MODEC,DEF_MODEL }, - { "absb", 14,24, 0x304e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, - { "absw", 14,24, 0x314e, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, - { "absd", 14,24, 0x334e, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, - { "acbb", 7,16, 0x4c, "2I1q3p", 1, "", DEF_MODEC,DEF_MODEL }, - { "acbw", 7,16, 0x4d, "2I1q3p", 2, "", DEF_MODEC,DEF_MODEL }, - { "acbd", 7,16, 0x4f, "2I1q3p", 4, "", DEF_MODEC,DEF_MODEL }, - { "addf", 14,24, 0x01be, "1F2Z", 4, "", DEF_MODEC,DEF_MODEL }, - { "addl", 14,24, 0x00be, "1L2Z", 8, "", DEF_MODEC,DEF_MODEL }, - { "addb", 6,16, 0x00, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, - { "addw", 6,16, 0x01, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, - { "addd", 6,16, 0x03, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, - { "addcb", 6,16, 0x10, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, - { "addcw", 6,16, 0x11, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, - { "addcd", 6,16, 0x13, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, - { "addpb", 14,24, 0x3c4e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, - { "addpw", 14,24, 0x3d4e, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, - { "addpd", 14,24, 0x3f4e, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, - { "addqb", 7,16, 0x0c, "2I1q", 1, "", DEF_MODEC,DEF_MODEL }, - { "addqw", 7,16, 0x0d, "2I1q", 2, "", DEF_MODEC,DEF_MODEL }, - { "addqd", 7,16, 0x0f, "2I1q", 4, "", DEF_MODEC,DEF_MODEL }, - { "addr", 6,16, 0x27, "1A2I", 4, "", 21,21 }, - { "adjspb", 11,16, 0x057c, "1B", 1, "", DEF_MODEC,DEF_MODEL }, - { "adjspw", 11,16, 0x057d, "1W", 2, "", DEF_MODEC,DEF_MODEL }, - { "adjspd", 11,16, 0x057f, "1D", 4, "", DEF_MODEC,DEF_MODEL }, - { "andb", 6,16, 0x28, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, - { "andw", 6,16, 0x29, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, - { "andd", 6,16, 0x2b, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, - { "ashb", 14,24, 0x044e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, - { "ashw", 14,24, 0x054e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, - { "ashd", 14,24, 0x074e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, - { "beq", 8,8, 0x0a, "1p", 0, "", 21,21 }, - { "bne", 8,8, 0x1a, "1p", 0, "", 21,21 }, - { "bcs", 8,8, 0x2a, "1p", 0, "", 21,21 }, - { "bcc", 8,8, 0x3a, "1p", 0, "", 21,21 }, - { "bhi", 8,8, 0x4a, "1p", 0, "", 21,21 }, - { "bls", 8,8, 0x5a, "1p", 0, "", 21,21 }, - { "bgt", 8,8, 0x6a, "1p", 0, "", 21,21 }, - { "ble", 8,8, 0x7a, "1p", 0, "", 21,21 }, - { "bfs", 8,8, 0x8a, "1p", 0, "", 21,21 }, - { "bfc", 8,8, 0x9a, "1p", 0, "", 21,21 }, - { "blo", 8,8, 0xaa, "1p", 0, "", 21,21 }, - { "bhs", 8,8, 0xba, "1p", 0, "", 21,21 }, - { "blt", 8,8, 0xca, "1p", 0, "", 21,21 }, - { "bge", 8,8, 0xda, "1p", 0, "", 21,21 }, - { "but", 8,8, 0xea, "1p", 0, "", 21,21 }, - { "buf", 8,8, 0xfa, "1p", 0, "", 21,21 }, - { "bicb", 6,16, 0x08, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, - { "bicw", 6,16, 0x09, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, - { "bicd", 6,16, 0x0b, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, - { "bicpsrb", 11,16, 0x17c, "1B", 1, "", DEF_MODEC,DEF_MODEL }, - { "bicpsrw", 11,16, 0x17d, "1W", 2, "", DEF_MODEC,DEF_MODEL }, - { "bispsrb", 11,16, 0x37c, "1B", 1, "", DEF_MODEC,DEF_MODEL }, - { "bispsrw", 11,16, 0x37d, "1W", 2, "", DEF_MODEC,DEF_MODEL }, - { "bpt", 8,8, 0xf2, "", 0, "", DEF_MODEC,DEF_MODEL }, - { "br", 8,8, 0xea, "1p", 0, "", 21,21 }, -#ifdef SEQUENT_COMPATABILITY - { "bsr", 8,8, 0x02, "1H", 0, "", 21,21 }, -#else - { "bsr", 8,8, 0x02, "1p", 0, "", 21,21 }, -#endif - { "caseb", 11,16, 0x77c, "1B", 1, "", DEF_MODEC,DEF_MODEL }, - { "casew", 11,16, 0x77d, "1W", 2, "", DEF_MODEC,DEF_MODEL }, - { "cased", 11,16, 0x77f, "1D", 4, "", DEF_MODEC,DEF_MODEL }, - { "cbitb", 14,24, 0x084e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, - { "cbitw", 14,24, 0x094e, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, - { "cbitd", 14,24, 0x0b4e, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, - { "cbitib", 14,24, 0x0c4e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, - { "cbitiw", 14,24, 0x0d4e, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, - { "cbitid", 14,24, 0x0f4e, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, - { "checkb", 11,24, 0x0ee, "2A3B1r", 1, "", DEF_MODEC,DEF_MODEL }, - { "checkw", 11,24, 0x1ee, "2A3W1r", 2, "", DEF_MODEC,DEF_MODEL }, - { "checkd", 11,24, 0x3ee, "2A3D1r", 4, "", DEF_MODEC,DEF_MODEL }, - { "cinv", 14,24, 0x271e, "2D1C", 4, "", DEF_MODEC,DEF_MODEL }, - { "cmpf", 14,24, 0x09be, "1F2F", 4, "", DEF_MODEC,DEF_MODEL }, - { "cmpl", 14,24, 0x08be, "1L2L", 8, "", DEF_MODEC,DEF_MODEL }, - { "cmpb", 6,16, 0x04, "1B2B", 1, "", DEF_MODEC,DEF_MODEL }, - { "cmpw", 6,16, 0x05, "1W2W", 2, "", DEF_MODEC,DEF_MODEL }, - { "cmpd", 6,16, 0x07, "1D2D", 4, "", DEF_MODEC,DEF_MODEL }, - { "cmpmb", 14,24, 0x04ce, "1A2A3b", 1, "", DEF_MODEC,DEF_MODEL }, - { "cmpmw", 14,24, 0x05ce, "1A2A3b", 2, "", DEF_MODEC,DEF_MODEL }, - { "cmpmd", 14,24, 0x07ce, "1A2A3b", 4, "", DEF_MODEC,DEF_MODEL }, - { "cmpqb", 7,16, 0x1c, "2B1q", 1, "", DEF_MODEC,DEF_MODEL }, - { "cmpqw", 7,16, 0x1d, "2W1q", 2, "", DEF_MODEC,DEF_MODEL }, - { "cmpqd", 7,16, 0x1f, "2D1q", 4, "", DEF_MODEC,DEF_MODEL }, - { "cmpsb", 16,24, 0x040e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL }, - { "cmpsw", 16,24, 0x050e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL }, - { "cmpsd", 16,24, 0x070e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL }, - { "cmpst", 16,24, 0x840e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL }, - { "comb", 14,24, 0x344e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, - { "comw", 14,24, 0x354e, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, - { "comd", 14,24, 0x374e, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, - { "cvtp", 11,24, 0x036e, "2A3D1r", 4, "", DEF_MODEC,DEF_MODEL }, - { "cxp", 8,8, 0x22, "1p", 0, "", 21,21 }, - { "cxpd", 11,16, 0x07f, "1A", 4, "", DEF_MODEC,DEF_MODEL }, - { "deib", 14,24, 0x2cce, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, - { "deiw", 14,24, 0x2dce, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, - { "deid", 14,24, 0x2fce, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, - { "dia", 8,8, 0xc2, "", 1, "", DEF_MODEC,DEF_MODEL }, - { "divf", 14,24, 0x21be, "1F2Z", 4, "", DEF_MODEC,DEF_MODEL }, - { "divl", 14,24, 0x20be, "1L2Z", 8, "", DEF_MODEC,DEF_MODEL }, - { "divb", 14,24, 0x3cce, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, - { "divw", 14,24, 0x3dce, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, - { "divd", 14,24, 0x3fce, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, - { "enter", 8,8, 0x82, "1U2d", 0, "", DEF_MODEC,DEF_MODEL }, - { "exit", 8,8, 0x92, "1u", 0, "", DEF_MODEC,DEF_MODEL }, - { "extb", 11,24, 0x02e, "2I3B1r4d", 1, "", DEF_MODEC,DEF_MODEL }, - { "extw", 11,24, 0x12e, "2I3W1r4d", 2, "", DEF_MODEC,DEF_MODEL }, - { "extd", 11,24, 0x32e, "2I3D1r4d", 4, "", DEF_MODEC,DEF_MODEL }, - { "extsb", 14,24, 0x0cce, "1I2I4G3g", 1, "", DEF_MODEC,DEF_MODEL }, - { "extsw", 14,24, 0x0dce, "1I2I4G3g", 2, "", DEF_MODEC,DEF_MODEL }, - { "extsd", 14,24, 0x0fce, "1I2I4G3g", 4, "", DEF_MODEC,DEF_MODEL }, - { "ffsb", 14,24, 0x046e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, - { "ffsw", 14,24, 0x056e, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, - { "ffsd", 14,24, 0x076e, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, - { "flag", 8,8, 0xd2, "", 0, "", DEF_MODEC,DEF_MODEL }, - { "floorfb", 14,24, 0x3c3e, "1F2I", 4, "", DEF_MODEC,DEF_MODEL }, - { "floorfw", 14,24, 0x3d3e, "1F2I", 4, "", DEF_MODEC,DEF_MODEL }, - { "floorfd", 14,24, 0x3f3e, "1F2I", 4, "", DEF_MODEC,DEF_MODEL }, - { "floorlb", 14,24, 0x383e, "1L2I", 8, "", DEF_MODEC,DEF_MODEL }, - { "floorlw", 14,24, 0x393e, "1L2I", 8, "", DEF_MODEC,DEF_MODEL }, - { "floorld", 14,24, 0x3b3e, "1L2I", 8, "", DEF_MODEC,DEF_MODEL }, - { "ibitb", 14,24, 0x384e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, - { "ibitw", 14,24, 0x394e, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, - { "ibitd", 14,24, 0x3b4e, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, - { "indexb", 11,24, 0x42e, "2B3B1r", 1, "", DEF_MODEC,DEF_MODEL }, - { "indexw", 11,24, 0x52e, "2W3W1r", 2, "", DEF_MODEC,DEF_MODEL }, - { "indexd", 11,24, 0x72e, "2D3D1r", 4, "", DEF_MODEC,DEF_MODEL }, - { "insb", 11,24, 0x0ae, "2B3I1r4d", 1, "", DEF_MODEC,DEF_MODEL }, - { "insw", 11,24, 0x1ae, "2W3I1r4d", 2, "", DEF_MODEC,DEF_MODEL }, - { "insd", 11,24, 0x3ae, "2D3I1r4d", 4, "", DEF_MODEC,DEF_MODEL }, - { "inssb", 14,24, 0x08ce, "1B2I4G3g", 1, "", DEF_MODEC,DEF_MODEL }, - { "inssw", 14,24, 0x09ce, "1W2I4G3g", 2, "", DEF_MODEC,DEF_MODEL }, - { "inssd", 14,24, 0x0bce, "1D2I4G3g", 4, "", DEF_MODEC,DEF_MODEL }, - { "jsr", 11,16, 0x67f, "1A", 4, "", 21,21 }, - { "jump", 11,16, 0x27f, "1A", 4, "", 21,21 }, - { "lfsr", 19,24, 0x00f3e,"1D", 4, "", DEF_MODEC,DEF_MODEL }, - { "lmr", 15,24, 0x0b1e, "2D1M", 4, "", DEF_MODEC,DEF_MODEL }, - { "lprb", 7,16, 0x6c, "2B1P", 1, "", DEF_MODEC,DEF_MODEL }, - { "lprw", 7,16, 0x6d, "2W1P", 2, "", DEF_MODEC,DEF_MODEL }, - { "lprd", 7,16, 0x6f, "2D1P", 4, "", DEF_MODEC,DEF_MODEL }, - { "lshb", 14,24, 0x144e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, - { "lshw", 14,24, 0x154e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, - { "lshd", 14,24, 0x174e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, - { "meib", 14,24, 0x24ce, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, - { "meiw", 14,24, 0x25ce, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, - { "meid", 14,24, 0x27ce, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, - { "modb", 14,24, 0x38ce, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, - { "modw", 14,24, 0x39ce, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, - { "modd", 14,24, 0x3bce, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, - { "movf", 14,24, 0x05be, "1F2Z", 4, "", DEF_MODEC,DEF_MODEL }, - { "movl", 14,24, 0x04be, "1L2Z", 8, "", DEF_MODEC,DEF_MODEL }, - { "movb", 6,16, 0x14, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, - { "movw", 6,16, 0x15, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, - { "movd", 6,16, 0x17, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, - { "movbf", 14,24, 0x043e, "1B2Z", 1, "", DEF_MODEC,DEF_MODEL }, - { "movwf", 14,24, 0x053e, "1W2Z", 2, "", DEF_MODEC,DEF_MODEL }, - { "movdf", 14,24, 0x073e, "1D2Z", 4, "", DEF_MODEC,DEF_MODEL }, - { "movbl", 14,24, 0x003e, "1B2Z", 1, "", DEF_MODEC,DEF_MODEL }, - { "movwl", 14,24, 0x013e, "1W2Z", 2, "", DEF_MODEC,DEF_MODEL }, - { "movdl", 14,24, 0x033e, "1D2Z", 4, "", DEF_MODEC,DEF_MODEL }, - { "movfl", 14,24, 0x1b3e, "1F2Z", 4, "", DEF_MODEC,DEF_MODEL }, - { "movlf", 14,24, 0x163e, "1L2Z", 8, "", DEF_MODEC,DEF_MODEL }, - { "movmb", 14,24, 0x00ce, "1A2A3b", 1, "", DEF_MODEC,DEF_MODEL }, - { "movmw", 14,24, 0x01ce, "1A2A3b", 2, "", DEF_MODEC,DEF_MODEL }, - { "movmd", 14,24, 0x03ce, "1A2A3b", 4, "", DEF_MODEC,DEF_MODEL }, - { "movqb", 7,16, 0x5c, "2I1q", 1, "", DEF_MODEC,DEF_MODEL }, - { "movqw", 7,16, 0x5d, "2I1q", 2, "", DEF_MODEC,DEF_MODEL }, - { "movqd", 7,16, 0x5f, "2I1q", 4, "", DEF_MODEC,DEF_MODEL }, - { "movsb", 16,24, 0x000e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL }, - { "movsw", 16,24, 0x010e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL }, - { "movsd", 16,24, 0x030e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL }, - { "movst", 16,24, 0x800e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL }, - { "movsub", 14,24, 0x0cae, "1A2A", 1, "", DEF_MODEC,DEF_MODEL }, - { "movsuw", 14,24, 0x0dae, "1A2A", 2, "", DEF_MODEC,DEF_MODEL }, - { "movsud", 14,24, 0x0fae, "1A2A", 4, "", DEF_MODEC,DEF_MODEL }, - { "movusb", 14,24, 0x1cae, "1A2A", 1, "", DEF_MODEC,DEF_MODEL }, - { "movusw", 14,24, 0x1dae, "1A2A", 2, "", DEF_MODEC,DEF_MODEL }, - { "movusd", 14,24, 0x1fae, "1A2A", 4, "", DEF_MODEC,DEF_MODEL }, - { "movxbd", 14,24, 0x1cce, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, - { "movxwd", 14,24, 0x1dce, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, - { "movxbw", 14,24, 0x10ce, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, - { "movzbd", 14,24, 0x18ce, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, - { "movzwd", 14,24, 0x19ce, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, - { "movzbw", 14,24, 0x14ce, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, - { "mulf", 14,24, 0x31be, "1F2Z", 4, "", DEF_MODEC,DEF_MODEL }, - { "mull", 14,24, 0x30be, "1L2Z", 8, "", DEF_MODEC,DEF_MODEL }, - { "mulb", 14,24, 0x20ce, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, - { "mulw", 14,24, 0x21ce, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, - { "muld", 14,24, 0x23ce, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, - { "negf", 14,24, 0x15be, "1F2Z", 4, "", DEF_MODEC,DEF_MODEL }, - { "negl", 14,24, 0x14be, "1L2Z", 8, "", DEF_MODEC,DEF_MODEL }, - { "negb", 14,24, 0x204e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, - { "negw", 14,24, 0x214e, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, - { "negd", 14,24, 0x234e, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, - { "nop", 8,8, 0xa2, "", 0, "", DEF_MODEC,DEF_MODEL }, - { "notb", 14,24, 0x244e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, - { "notw", 14,24, 0x254e, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, - { "notd", 14,24, 0x274e, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, - { "orb", 6,16, 0x18, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, - { "orw", 6,16, 0x19, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, - { "ord", 6,16, 0x1b, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, - { "quob", 14,24, 0x30ce, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, - { "quow", 14,24, 0x31ce, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, - { "quod", 14,24, 0x33ce, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, - { "rdval", 19,24, 0x0031e,"1A", 4, "", DEF_MODEC,DEF_MODEL }, - { "remb", 14,24, 0x34ce, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, - { "remw", 14,24, 0x35ce, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, - { "remd", 14,24, 0x37ce, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, - { "restore", 8,8, 0x72, "1u", 0, "", DEF_MODEC,DEF_MODEL }, - { "ret", 8,8, 0x12, "1d", 0, "", DEF_MODEC,DEF_MODEL }, - { "reti", 8,8, 0x52, "", 0, "", DEF_MODEC,DEF_MODEL }, - { "rett", 8,8, 0x42, "1d", 0, "", DEF_MODEC,DEF_MODEL }, - { "rotb", 14,24, 0x004e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, - { "rotw", 14,24, 0x014e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, - { "rotd", 14,24, 0x034e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, - { "roundfb", 14,24, 0x243e, "1F2I", 4, "", DEF_MODEC,DEF_MODEL }, - { "roundfw", 14,24, 0x253e, "1F2I", 4, "", DEF_MODEC,DEF_MODEL }, - { "roundfd", 14,24, 0x273e, "1F2I", 4, "", DEF_MODEC,DEF_MODEL }, - { "roundlb", 14,24, 0x203e, "1L2I", 8, "", DEF_MODEC,DEF_MODEL }, - { "roundlw", 14,24, 0x213e, "1L2I", 8, "", DEF_MODEC,DEF_MODEL }, - { "roundld", 14,24, 0x233e, "1L2I", 8, "", DEF_MODEC,DEF_MODEL }, - { "rxp", 8,8, 0x32, "1d", 0, "", DEF_MODEC,DEF_MODEL }, - { "seqb", 11,16, 0x3c, "1B", 0, "", DEF_MODEC,DEF_MODEL }, - { "seqw", 11,16, 0x3d, "1W", 0, "", DEF_MODEC,DEF_MODEL }, - { "seqd", 11,16, 0x3f, "1D", 0, "", DEF_MODEC,DEF_MODEL }, - { "sneb", 11,16, 0xbc, "1B", 0, "", DEF_MODEC,DEF_MODEL }, - { "snew", 11,16, 0xbd, "1W", 0, "", DEF_MODEC,DEF_MODEL }, - { "sned", 11,16, 0xbf, "1D", 0, "", DEF_MODEC,DEF_MODEL }, - { "scsb", 11,16, 0x13c, "1B", 0, "", DEF_MODEC,DEF_MODEL }, - { "scsw", 11,16, 0x13d, "1W", 0, "", DEF_MODEC,DEF_MODEL }, - { "scsd", 11,16, 0x13f, "1D", 0, "", DEF_MODEC,DEF_MODEL }, - { "sccb", 11,16, 0x1bc, "1B", 0, "", DEF_MODEC,DEF_MODEL }, - { "sccw", 11,16, 0x1bd, "1W", 0, "", DEF_MODEC,DEF_MODEL }, - { "sccd", 11,16, 0x1bf, "1D", 0, "", DEF_MODEC,DEF_MODEL }, - { "shib", 11,16, 0x23c, "1B", 0, "", DEF_MODEC,DEF_MODEL }, - { "shiw", 11,16, 0x23d, "1W", 0, "", DEF_MODEC,DEF_MODEL }, - { "shid", 11,16, 0x23f, "1D", 0, "", DEF_MODEC,DEF_MODEL }, - { "slsb", 11,16, 0x2bc, "1B", 0, "", DEF_MODEC,DEF_MODEL }, - { "slsw", 11,16, 0x2bd, "1W", 0, "", DEF_MODEC,DEF_MODEL }, - { "slsd", 11,16, 0x2bf, "1D", 0, "", DEF_MODEC,DEF_MODEL }, - { "sgtb", 11,16, 0x33c, "1B", 0, "", DEF_MODEC,DEF_MODEL }, - { "sgtw", 11,16, 0x33d, "1W", 0, "", DEF_MODEC,DEF_MODEL }, - { "sgtd", 11,16, 0x33f, "1D", 0, "", DEF_MODEC,DEF_MODEL }, - { "sleb", 11,16, 0x3bc, "1B", 0, "", DEF_MODEC,DEF_MODEL }, - { "slew", 11,16, 0x3bd, "1W", 0, "", DEF_MODEC,DEF_MODEL }, - { "sled", 11,16, 0x3bf, "1D", 0, "", DEF_MODEC,DEF_MODEL }, - { "sfsb", 11,16, 0x43c, "1B", 0, "", DEF_MODEC,DEF_MODEL }, - { "sfsw", 11,16, 0x43d, "1W", 0, "", DEF_MODEC,DEF_MODEL }, - { "sfsd", 11,16, 0x43f, "1D", 0, "", DEF_MODEC,DEF_MODEL }, - { "sfcb", 11,16, 0x4bc, "1B", 0, "", DEF_MODEC,DEF_MODEL }, - { "sfcw", 11,16, 0x4bd, "1W", 0, "", DEF_MODEC,DEF_MODEL }, - { "sfcd", 11,16, 0x4bf, "1D", 0, "", DEF_MODEC,DEF_MODEL }, - { "slob", 11,16, 0x53c, "1B", 0, "", DEF_MODEC,DEF_MODEL }, - { "slow", 11,16, 0x53d, "1W", 0, "", DEF_MODEC,DEF_MODEL }, - { "slod", 11,16, 0x53f, "1D", 0, "", DEF_MODEC,DEF_MODEL }, - { "shsb", 11,16, 0x5bc, "1B", 0, "", DEF_MODEC,DEF_MODEL }, - { "shsw", 11,16, 0x5bd, "1W", 0, "", DEF_MODEC,DEF_MODEL }, - { "shsd", 11,16, 0x5bf, "1D", 0, "", DEF_MODEC,DEF_MODEL }, - { "sltb", 11,16, 0x63c, "1B", 0, "", DEF_MODEC,DEF_MODEL }, - { "sltw", 11,16, 0x63d, "1W", 0, "", DEF_MODEC,DEF_MODEL }, - { "sltd", 11,16, 0x63f, "1D", 0, "", DEF_MODEC,DEF_MODEL }, - { "sgeb", 11,16, 0x6bc, "1B", 0, "", DEF_MODEC,DEF_MODEL }, - { "sgew", 11,16, 0x6bd, "1W", 0, "", DEF_MODEC,DEF_MODEL }, - { "sged", 11,16, 0x6bf, "1D", 0, "", DEF_MODEC,DEF_MODEL }, - { "sutb", 11,16, 0x73c, "1B", 0, "", DEF_MODEC,DEF_MODEL }, - { "sutw", 11,16, 0x73d, "1W", 0, "", DEF_MODEC,DEF_MODEL }, - { "sutd", 11,16, 0x73f, "1D", 0, "", DEF_MODEC,DEF_MODEL }, - { "sufb", 11,16, 0x7bc, "1B", 0, "", DEF_MODEC,DEF_MODEL }, - { "sufw", 11,16, 0x7bd, "1W", 0, "", DEF_MODEC,DEF_MODEL }, - { "sufd", 11,16, 0x7bf, "1D", 0, "", DEF_MODEC,DEF_MODEL }, - { "save", 8,8, 0x62, "1U", 0, "", DEF_MODEC,DEF_MODEL }, - { "sbitb", 14,24, 0x184e, "1B2A", 1, "", DEF_MODEC,DEF_MODEL }, - { "sbitw", 14,24, 0x194e, "1W2A", 2, "", DEF_MODEC,DEF_MODEL }, - { "sbitd", 14,24, 0x1b4e, "1D2A", 4, "", DEF_MODEC,DEF_MODEL }, - { "sbitib", 14,24, 0x1c4e, "1B2A", 1, "", DEF_MODEC,DEF_MODEL }, - { "sbitiw", 14,24, 0x1d4e, "1W2A", 2, "", DEF_MODEC,DEF_MODEL }, - { "sbitid", 14,24, 0x1f4e, "1D2A", 4, "", DEF_MODEC,DEF_MODEL }, - { "setcfg", 15,24, 0x0b0e, "1O", 0, "", DEF_MODEC,DEF_MODEL }, - { "sfsr", 14,24, 0x373e, "1f", 0, "", DEF_MODEC,DEF_MODEL }, - { "skpsb", 16,24, 0x0c0e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL }, - { "skpsw", 16,24, 0x0d0e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL }, - { "skpsd", 16,24, 0x0f0e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL }, - { "skpst", 16,24, 0x8c0e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL }, - { "smr", 15,24, 0x0f1e, "2I1M", 4, "", DEF_MODEC,DEF_MODEL }, - { "sprb", 7,16, 0x2c, "2I1P", 1, "", DEF_MODEC,DEF_MODEL }, - { "sprw", 7,16, 0x2d, "2I1P", 2, "", DEF_MODEC,DEF_MODEL }, - { "sprd", 7,16, 0x2f, "2I1P", 4, "", DEF_MODEC,DEF_MODEL }, - { "subf", 14,24, 0x11be, "1F2Z", 4, "", DEF_MODEC,DEF_MODEL }, - { "subl", 14,24, 0x10be, "1L2Z", 8, "", DEF_MODEC,DEF_MODEL }, - { "subb", 6,16, 0x20, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, - { "subw", 6,16, 0x21, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, - { "subd", 6,16, 0x23, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, - { "subcb", 6,16, 0x30, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, - { "subcw", 6,16, 0x31, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, - { "subcd", 6,16, 0x33, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, - { "subpb", 14,24, 0x2c4e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, - { "subpw", 14,24, 0x2d4e, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, - { "subpd", 14,24, 0x2f4e, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, -#ifdef NS32K_SVC_IMMED_OPERANDS - { "svc", 8,8, 0xe2, "2i1i", 1, "", DEF_MODEC,DEF_MODEL }, /* not really, but some unix uses it */ -#else - { "svc", 8,8, 0xe2, "", 0, "", DEF_MODEC,DEF_MODEL }, -#endif - { "tbitb", 6,16, 0x34, "1B2A", 1, "", DEF_MODEC,DEF_MODEL }, - { "tbitw", 6,16, 0x35, "1W2A", 2, "", DEF_MODEC,DEF_MODEL }, - { "tbitd", 6,16, 0x37, "1D2A", 4, "", DEF_MODEC,DEF_MODEL }, - { "truncfb", 14,24, 0x2c3e, "1F2I", 4, "", DEF_MODEC,DEF_MODEL }, - { "truncfw", 14,24, 0x2d3e, "1F2I", 4, "", DEF_MODEC,DEF_MODEL }, - { "truncfd", 14,24, 0x2f3e, "1F2I", 4, "", DEF_MODEC,DEF_MODEL }, - { "trunclb", 14,24, 0x283e, "1L2I", 8, "", DEF_MODEC,DEF_MODEL }, - { "trunclw", 14,24, 0x293e, "1L2I", 8, "", DEF_MODEC,DEF_MODEL }, - { "truncld", 14,24, 0x2b3e, "1L2I", 8, "", DEF_MODEC,DEF_MODEL }, - { "wait", 8,8, 0xb2, "", 0, "", DEF_MODEC,DEF_MODEL }, - { "wrval", 19,24, 0x0071e,"1A", 0, "", DEF_MODEC,DEF_MODEL }, - { "xorb", 6,16, 0x38, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, - { "xorw", 6,16, 0x39, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, - { "xord", 6,16, 0x3b, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, - { "dotf", 14,24, 0x0dfe, "1F2F", 4, "", DEF_MODEC,DEF_MODEL }, - { "dotl", 14,24, 0x0cfe, "1L2L", 8, "", DEF_MODEC,DEF_MODEL }, - { "logbf", 14,24, 0x15fe, "1F2Z", 4, "", DEF_MODEC,DEF_MODEL }, - { "logbl", 14,24, 0x14fe, "1L2Z", 8, "", DEF_MODEC,DEF_MODEL }, - { "polyf", 14,24, 0x09fe, "1F2F", 4, "", DEF_MODEC,DEF_MODEL }, - { "polyl", 14,24, 0x08fe, "1L2L", 8, "", DEF_MODEC,DEF_MODEL }, - { "scalbf", 14,24, 0x11fe, "1F2Z", 4, "", DEF_MODEC,DEF_MODEL }, - { "scalbl", 14,24, 0x10fe, "1L2Z", 8, "", DEF_MODEC,DEF_MODEL }, -}; - -#define MAX_ARGS 4 -#define ARG_LEN 50 - diff --git a/include/opcode/or32.h b/include/opcode/or32.h deleted file mode 100644 index 153d91e..0000000 --- a/include/opcode/or32.h +++ /dev/null @@ -1,181 +0,0 @@ -/* Table of opcodes for the OpenRISC 1000 ISA. - Copyright 2002, 2003, 2010 Free Software Foundation, Inc. - Contributed by Damjan Lampret (lampret@opencores.org). - - This file is part of or1k_gen_isa, or1ksim, GDB and GAS. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, - MA 02110-1301, USA. */ - -/* We treat all letters the same in encode/decode routines so - we need to assign some characteristics to them like signess etc. */ - -#ifndef OR32_H_ISA -#define OR32_H_ISA - -#define NUM_UNSIGNED (0) -#define NUM_SIGNED (1) - -#define MAX_GPRS 32 -#define PAGE_SIZE 4096 -#undef __HALF_WORD_INSN__ - -#define OPERAND_DELIM (',') - -#define OR32_IF_DELAY (1) -#define OR32_W_FLAG (2) -#define OR32_R_FLAG (4) - -struct or32_letter -{ - char letter; - int sign; - /* int reloc; relocation per letter ?? */ -}; - -/* Main instruction specification array. */ -struct or32_opcode -{ - /* Name of the instruction. */ - char *name; - - /* A string of characters which describe the operands. - Valid characters are: - ,() Itself. Characters appears in the assembly code. - rA Register operand. - rB Register operand. - rD Register operand. - I An immediate operand, range -32768 to 32767. - J An immediate operand, range . (unused) - K An immediate operand, range 0 to 65535. - L An immediate operand, range 0 to 63. - M An immediate operand, range . (unused) - N An immediate operand, range -33554432 to 33554431. - O An immediate operand, range . (unused). */ - char *args; - - /* Opcode and operand encoding. */ - char *encoding; - void (*exec) (void); - unsigned int flags; -}; - -#define OPTYPE_LAST (0x80000000) -#define OPTYPE_OP (0x40000000) -#define OPTYPE_REG (0x20000000) -#define OPTYPE_SIG (0x10000000) -#define OPTYPE_DIS (0x08000000) -#define OPTYPE_DST (0x04000000) -#define OPTYPE_SBIT (0x00001F00) -#define OPTYPE_SHR (0x0000001F) -#define OPTYPE_SBIT_SHR (8) - -/* MM: Data how to decode operands. */ -extern struct insn_op_struct -{ - unsigned long type; - unsigned long data; -} **op_start; - -#ifdef HAS_EXECUTION -extern void l_invalid (void); -extern void l_sfne (void); -extern void l_bf (void); -extern void l_add (void); -extern void l_sw (void); -extern void l_sb (void); -extern void l_sh (void); -extern void l_lwz (void); -extern void l_lbs (void); -extern void l_lbz (void); -extern void l_lhs (void); -extern void l_lhz (void); -extern void l_movhi (void); -extern void l_and (void); -extern void l_or (void); -extern void l_xor (void); -extern void l_sub (void); -extern void l_mul (void); -extern void l_div (void); -extern void l_divu (void); -extern void l_sll (void); -extern void l_sra (void); -extern void l_srl (void); -extern void l_j (void); -extern void l_jal (void); -extern void l_jalr (void); -extern void l_jr (void); -extern void l_rfe (void); -extern void l_nop (void); -extern void l_bnf (void); -extern void l_sfeq (void); -extern void l_sfgts (void); -extern void l_sfges (void); -extern void l_sflts (void); -extern void l_sfles (void); -extern void l_sfgtu (void); -extern void l_sfgeu (void); -extern void l_sfltu (void); -extern void l_sfleu (void); -extern void l_mtspr (void); -extern void l_mfspr (void); -extern void l_sys (void); -extern void l_trap (void); /* CZ 21/06/01. */ -extern void l_macrc (void); -extern void l_mac (void); -extern void l_msb (void); -extern void l_invalid (void); -extern void l_cust1 (void); -extern void l_cust2 (void); -extern void l_cust3 (void); -extern void l_cust4 (void); -#endif -extern void l_none (void); - -extern const struct or32_letter or32_letters[]; - -extern const struct or32_opcode or32_opcodes[]; - -extern const unsigned int or32_num_opcodes; - -/* Calculates instruction length in bytes. Always 4 for OR32. */ -extern int insn_len (int); - -/* Is individual insn's operand signed or unsigned? */ -extern int letter_signed (char); - -/* Number of letters in the individual lettered operand. */ -extern int letter_range (char); - -/* MM: Returns index of given instruction name. */ -extern int insn_index (char *); - -/* MM: Returns instruction name from index. */ -extern const char *insn_name (int); - -/* MM: Constructs new FSM, based on or32_opcodes. */ -extern void build_automata (void); - -/* MM: Destructs FSM. */ -extern void destruct_automata (void); - -/* MM: Decodes instruction using FSM. Call build_automata first. */ -extern int insn_decode (unsigned int); - -/* Disassemble one instruction from insn to disassemble. - Return the size of the instruction. */ -int disassemble_insn (unsigned long); - -#endif diff --git a/include/opcode/pdp11.h b/include/opcode/pdp11.h deleted file mode 100644 index 24e13b2..0000000 --- a/include/opcode/pdp11.h +++ /dev/null @@ -1,84 +0,0 @@ -/* PDP-11 opcde list. - Copyright 2001, 2002, 2010 Free Software Foundation, Inc. - - This file is part of GDB and GAS. - - GDB and GAS are free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3, or (at your option) - any later version. - - GDB and GAS are distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with GDB or GAS; see the file COPYING3. If not, write to - the Free Software Foundation, 51 Franklin Street - Fifth Floor, - Boston, MA 02110-1301, USA. */ - -/* PDP-11 opcode types. */ - -#define PDP11_OPCODE_NO_OPS 0 -#define PDP11_OPCODE_REG 1 /* register */ -#define PDP11_OPCODE_OP 2 /* generic operand */ -#define PDP11_OPCODE_REG_OP 3 /* register and generic operand */ -#define PDP11_OPCODE_REG_OP_REV 4 /* register and generic operand, - reversed syntax */ -#define PDP11_OPCODE_AC_FOP 5 /* fpu accumulator and generic float - operand */ -#define PDP11_OPCODE_OP_OP 6 /* two generic operands */ -#define PDP11_OPCODE_DISPL 7 /* pc-relative displacement */ -#define PDP11_OPCODE_REG_DISPL 8 /* redister and pc-relative - displacement */ -#define PDP11_OPCODE_IMM8 9 /* 8-bit immediate */ -#define PDP11_OPCODE_IMM6 10 /* 6-bit immediate */ -#define PDP11_OPCODE_IMM3 11 /* 3-bit immediate */ -#define PDP11_OPCODE_ILLEGAL 12 /* illegal instruction */ -#define PDP11_OPCODE_FOP_AC 13 /* generic float argument, then fpu - accumulator */ -#define PDP11_OPCODE_FOP 14 /* generic float operand */ -#define PDP11_OPCODE_AC_OP 15 /* fpu accumulator and generic int - operand */ -#define PDP11_OPCODE_OP_AC 16 /* generic int argument, then fpu - accumulator */ - -/* - * PDP-11 instruction set extensions. - * - * Please keep the numbers low, as they are used as indices into - * an array. - */ - -#define PDP11_NONE 0 /* not in instruction set */ -#define PDP11_BASIC 1 /* basic instruction set (11/20 etc) */ -#define PDP11_CSM 2 /* commercial instruction set */ -#define PDP11_CIS 3 /* commercial instruction set */ -#define PDP11_EIS 4 /* extended instruction set (11/45 etc) */ -#define PDP11_FIS 5 /* KEV11 floating-point instructions */ -#define PDP11_FPP 6 /* FP-11 floating-point instructions */ -#define PDP11_LEIS 7 /* limited extended instruction set - (11/40 etc) */ -#define PDP11_MFPT 8 /* move from processor type */ -#define PDP11_MPROC 9 /* multiprocessor instructions: tstset, - wrtlck */ -#define PDP11_MXPS 10 /* move from/to processor status */ -#define PDP11_SPL 11 /* set priority level */ -#define PDP11_UCODE 12 /* microcode instructions: ldub, med, xfc */ -#define PDP11_EXT_NUM 13 /* total number of extension types */ - -struct pdp11_opcode -{ - const char *name; - int opcode; - int mask; - int type; - int extension; -}; - -extern const struct pdp11_opcode pdp11_opcodes[]; -extern const struct pdp11_opcode pdp11_aliases[]; -extern const int pdp11_num_opcodes, pdp11_num_aliases; - -/* end of pdp11.h */ diff --git a/include/opcode/pj.h b/include/opcode/pj.h deleted file mode 100644 index e6ffacc..0000000 --- a/include/opcode/pj.h +++ /dev/null @@ -1,49 +0,0 @@ -/* Definitions for decoding the picoJava opcode table. - Copyright 1999, 2002, 2003, 2010 Free Software Foundation, Inc. - Contributed by Steve Chamberlain of Transmeta (sac@pobox.com). - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, - MA 02110-1301, USA. */ - -/* Names used to describe the type of instruction arguments, used by - the assembler and disassembler. Attributes are encoded in various fields. */ - -/* reloc size pcrel uns */ -#define O_N 0 -#define O_16 (1<<4 | 2 | (0<<6) | (0<<3)) -#define O_U16 (1<<4 | 2 | (0<<6) | (1<<3)) -#define O_R16 (2<<4 | 2 | (1<<6) | (0<<3)) -#define O_8 (3<<4 | 1 | (0<<6) | (0<<3)) -#define O_U8 (3<<4 | 1 | (0<<6) | (1<<3)) -#define O_R8 (4<<4 | 1 | (0<<6) | (0<<3)) -#define O_R32 (5<<4 | 4 | (1<<6) | (0<<3)) -#define O_32 (6<<4 | 4 | (0<<6) | (0<<3)) - -#define ASIZE(x) ((x) & 0x7) -#define PCREL(x) (!!((x) & (1<<6))) -#define UNS(x) (!!((x) & (1<<3))) - - -typedef struct pj_opc_info_t -{ - short opcode; - short opcode_next; - char len; - unsigned char arg[2]; - union { - const char *name; - void (*func) (struct pj_opc_info_t *, char *); - } u; -} pj_opc_info_t; diff --git a/include/opcode/pn.h b/include/opcode/pn.h deleted file mode 100644 index 6674030..0000000 --- a/include/opcode/pn.h +++ /dev/null @@ -1,283 +0,0 @@ -/* Print GOULD PN (PowerNode) instructions for GDB, the GNU debugger. - Copyright 1986, 1987, 1989, 1991, 2010 Free Software Foundation, Inc. - - This file is part of GDB. - - GDB is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3, or (at your option) - any later version. - - GDB is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with GDB; see the file COPYING3. If not, write to - the Free Software Foundation, 51 Franklin Street - Fifth Floor, - Boston, MA 02110-1301, USA. */ - -struct gld_opcode -{ - char *name; - unsigned long opcode; - unsigned long mask; - char *args; - int length; -}; - -/* We store four bytes of opcode for all opcodes because that - is the most any of them need. The actual length of an instruction - is always at least 2 bytes, and at most four. The length of the - instruction is based on the opcode. - - The mask component is a mask saying which bits must match - particular opcode in order for an instruction to be an instance - of that opcode. - - The args component is a string containing characters - that are used to format the arguments to the instruction. */ - -/* Kinds of operands: - r Register in first field - R Register in second field - b Base register in first field - B Base register in second field - v Vector register in first field - V Vector register in first field - A Optional address register (base register) - X Optional index register - I Immediate data (16bits signed) - O Offset field (16bits signed) - h Offset field (15bits signed) - d Offset field (14bits signed) - S Shift count field - - any other characters are printed as is... -*/ - -/* The assembler requires that this array be sorted as follows: - all instances of the same mnemonic must be consecutive. - All instances of the same mnemonic with the same number of operands - must be consecutive. - */ -struct gld_opcode gld_opcodes[] = -{ -{ "abm", 0xa0080000, 0xfc080000, "f,xOA,X", 4 }, -{ "abr", 0x18080000, 0xfc0c0000, "r,f", 2 }, -{ "aci", 0xfc770000, 0xfc7f8000, "r,I", 4 }, -{ "adfd", 0xe0080002, 0xfc080002, "r,xOA,X", 4 }, -{ "adfw", 0xe0080000, 0xfc080000, "r,xOA,X", 4 }, -{ "adi", 0xc8010000, 0xfc7f0000, "r,I", 4 }, -{ "admb", 0xb8080000, 0xfc080000, "r,xOA,X", 4 }, -{ "admd", 0xb8000002, 0xfc080002, "r,xOA,X", 4 }, -{ "admh", 0xb8000001, 0xfc080001, "r,xOA,X", 4 }, -{ "admw", 0xb8000000, 0xfc080000, "r,xOA,X", 4 }, -{ "adr", 0x38000000, 0xfc0f0000, "r,R", 2 }, -{ "adrfd", 0x38090000, 0xfc0f0000, "r,R", 2 }, -{ "adrfw", 0x38010000, 0xfc0f0000, "r,R", 2 }, -{ "adrm", 0x38080000, 0xfc0f0000, "r,R", 2 }, -{ "ai", 0xfc030000, 0xfc07ffff, "I", 4 }, -{ "anmb", 0x84080000, 0xfc080000, "r,xOA,X", 4 }, -{ "anmd", 0x84000002, 0xfc080002, "r,xOA,X", 4 }, -{ "anmh", 0x84000001, 0xfc080001, "r,xOA,X", 4 }, -{ "anmw", 0x84000000, 0xfc080000, "r,xOA,X", 4 }, -{ "anr", 0x04000000, 0xfc0f0000, "r,R", 2 }, -{ "armb", 0xe8080000, 0xfc080000, "r,xOA,X", 4 }, -{ "armd", 0xe8000002, 0xfc080002, "r,xOA,X", 4 }, -{ "armh", 0xe8000001, 0xfc080001, "r,xOA,X", 4 }, -{ "armw", 0xe8000000, 0xfc080000, "r,xOA,X", 4 }, -{ "bcf", 0xf0000000, 0xfc080000, "I,xOA,X", 4 }, -{ "bct", 0xec000000, 0xfc080000, "I,xOA,X", 4 }, -{ "bei", 0x00060000, 0xffff0000, "", 2 }, -{ "bft", 0xf0000000, 0xff880000, "xOA,X", 4 }, -{ "bib", 0xf4000000, 0xfc780000, "r,xOA", 4 }, -{ "bid", 0xf4600000, 0xfc780000, "r,xOA", 4 }, -{ "bih", 0xf4200000, 0xfc780000, "r,xOA", 4 }, -{ "biw", 0xf4400000, 0xfc780000, "r,xOA", 4 }, -{ "bl", 0xf8800000, 0xff880000, "xOA,X", 4 }, -{ "bsub", 0x5c080000, 0xff8f0000, "", 2 }, -{ "bsubm", 0x28080000, 0xfc080000, "", 4 }, -{ "bu", 0xec000000, 0xff880000, "xOA,X", 4 }, -{ "call", 0x28080000, 0xfc0f0000, "", 2 }, -{ "callm", 0x5c080000, 0xff880000, "", 4 }, -{ "camb", 0x90080000, 0xfc080000, "r,xOA,X", 4 }, -{ "camd", 0x90000002, 0xfc080002, "r,xOA,X", 4 }, -{ "camh", 0x90000001, 0xfc080001, "r,xOA,X", 4 }, -{ "camw", 0x90000000, 0xfc080000, "r.xOA,X", 4 }, -{ "car", 0x10000000, 0xfc0f0000, "r,R", 2 }, -{ "cd", 0xfc060000, 0xfc070000, "r,f", 4 }, -{ "cea", 0x000f0000, 0xffff0000, "", 2 }, -{ "ci", 0xc8050000, 0xfc7f0000, "r,I", 4 }, -{ "cmc", 0x040a0000, 0xfc7f0000, "r", 2 }, -{ "cmmb", 0x94080000, 0xfc080000, "r,xOA,X", 4 }, -{ "cmmd", 0x94000002, 0xfc080002, "r,xOA,X", 4 }, -{ "cmmh", 0x94000001, 0xfc080001, "r,xOA,X", 4 }, -{ "cmmw", 0x94000000, 0xfc080000, "r,xOA,X", 4 }, -{ "cmr", 0x14000000, 0xfc0f0000, "r,R", 2 }, -{ "daci", 0xfc7f0000, 0xfc7f8000, "r,I", 4 }, -{ "dae", 0x000e0000, 0xffff0000, "", 2 }, -{ "dai", 0xfc040000, 0xfc07ffff, "I", 4 }, -{ "dci", 0xfc6f0000, 0xfc7f8000, "r,I", 4 }, -{ "di", 0xfc010000, 0xfc07ffff, "I", 4 }, -{ "dvfd", 0xe4000002, 0xfc080002, "r,xOA,X", 4 }, -{ "dvfw", 0xe4000000, 0xfc080000, "r,xOA,X", 4 }, -{ "dvi", 0xc8040000, 0xfc7f0000, "r,I", 4 }, -{ "dvmb", 0xc4080000, 0xfc080000, "r,xOA,X", 4 }, -{ "dvmh", 0xc4000001, 0xfc080001, "r,xOA,X", 4 }, -{ "dvmw", 0xc4000000, 0xfc080000, "r,xOA,X", 4 }, -{ "dvr", 0x380a0000, 0xfc0f0000, "r,R", 2 }, -{ "dvrfd", 0x380c0000, 0xfc0f0000, "r,R", 4 }, -{ "dvrfw", 0x38040000, 0xfc0f0000, "r,xOA,X", 4 }, -{ "eae", 0x00080000, 0xffff0000, "", 2 }, -{ "eci", 0xfc670000, 0xfc7f8080, "r,I", 4 }, -{ "ecwcs", 0xfc4f0000, 0xfc7f8000, "", 4 }, -{ "ei", 0xfc000000, 0xfc07ffff, "I", 4 }, -{ "eomb", 0x8c080000, 0xfc080000, "r,xOA,X", 4 }, -{ "eomd", 0x8c000002, 0xfc080002, "r,xOA,X", 4 }, -{ "eomh", 0x8c000001, 0xfc080001, "r,xOA,X", 4 }, -{ "eomw", 0x8c000000, 0xfc080000, "r,xOA,X", 4 }, -{ "eor", 0x0c000000, 0xfc0f0000, "r,R", 2 }, -{ "eorm", 0x0c080000, 0xfc0f0000, "r,R", 2 }, -{ "es", 0x00040000, 0xfc7f0000, "r", 2 }, -{ "exm", 0xa8000000, 0xff880000, "xOA,X", 4 }, -{ "exr", 0xc8070000, 0xfc7f0000, "r", 2 }, -{ "exrr", 0xc8070002, 0xfc7f0002, "r", 2 }, -{ "fixd", 0x380d0000, 0xfc0f0000, "r,R", 2 }, -{ "fixw", 0x38050000, 0xfc0f0000, "r,R", 2 }, -{ "fltd", 0x380f0000, 0xfc0f0000, "r,R", 2 }, -{ "fltw", 0x38070000, 0xfc0f0000, "r,R", 2 }, -{ "grio", 0xfc3f0000, 0xfc7f8000, "r,I", 4 }, -{ "halt", 0x00000000, 0xffff0000, "", 2 }, -{ "hio", 0xfc370000, 0xfc7f8000, "r,I", 4 }, -{ "jwcs", 0xfa080000, 0xff880000, "xOA,X", 4 }, -{ "la", 0x50000000, 0xfc000000, "r,xOA,X", 4 }, -{ "labr", 0x58080000, 0xfc080000, "b,xOA,X", 4 }, -{ "lb", 0xac080000, 0xfc080000, "r,xOA,X", 4 }, -{ "lcs", 0x00030000, 0xfc7f0000, "r", 2 }, -{ "ld", 0xac000002, 0xfc080002, "r,xOA,X", 4 }, -{ "lear", 0x80000000, 0xfc080000, "r,xOA,X", 4 }, -{ "lf", 0xcc000000, 0xfc080000, "r,xOA,X", 4 }, -{ "lfbr", 0xcc080000, 0xfc080000, "b,xOA,X", 4 }, -{ "lh", 0xac000001, 0xfc080001, "r,xOA,X", 4 }, -{ "li", 0xc8000000, 0xfc7f0000, "r,I", 4 }, -{ "lmap", 0x2c070000, 0xfc7f0000, "r", 2 }, -{ "lmb", 0xb0080000, 0xfc080000, "r,xOA,X", 4 }, -{ "lmd", 0xb0000002, 0xfc080002, "r,xOA,X", 4 }, -{ "lmh", 0xb0000001, 0xfc080001, "r,xOA,X", 4 }, -{ "lmw", 0xb0000000, 0xfc080000, "r,xOA,X", 4 }, -{ "lnb", 0xb4080000, 0xfc080000, "r,xOA,X", 4 }, -{ "lnd", 0xb4000002, 0xfc080002, "r,xOA,X", 4 }, -{ "lnh", 0xb4000001, 0xfc080001, "r,xOA,X", 4 }, -{ "lnw", 0xb4000000, 0xfc080000, "r,xOA,X", 4 }, -{ "lpsd", 0xf9800000, 0xff880000, "r,xOA,X", 4 }, -{ "lpsdcm", 0xfa800000, 0xff880000, "r,xOA,X", 4 }, -{ "lw", 0xac000000, 0xfc080000, "r,xOA,X", 4 }, -{ "lwbr", 0x5c000000, 0xfc080000, "b,xOA,X", 4 }, -{ "mpfd", 0xe4080002, 0xfc080002, "r,xOA,X", 4 }, -{ "mpfw", 0xe4080000, 0xfc080000, "r,xOA,X", 4 }, -{ "mpi", 0xc8030000, 0xfc7f0000, "r,I", 4 }, -{ "mpmb", 0xc0080000, 0xfc080000, "r,xOA,X", 4 }, -{ "mpmh", 0xc0000001, 0xfc080001, "r,xOA,X", 4 }, -{ "mpmw", 0xc0000000, 0xfc080000, "r,xOA,X", 4 }, -{ "mpr", 0x38020000, 0xfc0f0000, "r,R", 2 }, -{ "mprfd", 0x380e0000, 0xfc0f0000, "r,R", 2 }, -{ "mprfw", 0x38060000, 0xfc0f0000, "r,R", 2 }, -{ "nop", 0x00020000, 0xffff0000, "", 2 }, -{ "ormb", 0x88080000, 0xfc080000, "r,xOA,X", 4 }, -{ "ormd", 0x88000002, 0xfc080002, "r,xOA,X", 4 }, -{ "ormh", 0x88000001, 0xfc080001, "r,xOA,X", 4 }, -{ "ormw", 0x88000000, 0xfc080000, "r,xOA,X", 4 }, -{ "orr", 0x08000000, 0xfc0f0000, "r,R", 2 }, -{ "orrm", 0x08080000, 0xfc0f0000, "r,R", 2 }, -{ "rdsts", 0x00090000, 0xfc7f0000, "r", 2 }, -{ "return", 0x280e0000, 0xfc7f0000, "", 2 }, -{ "ri", 0xfc020000, 0xfc07ffff, "I", 4 }, -{ "rnd", 0x00050000, 0xfc7f0000, "r", 2 }, -{ "rpswt", 0x040b0000, 0xfc7f0000, "r", 2 }, -{ "rschnl", 0xfc2f0000, 0xfc7f8000, "r,I", 4 }, -{ "rsctl", 0xfc470000, 0xfc7f8000, "r,I", 4 }, -{ "rwcs", 0x000b0000, 0xfc0f0000, "r,R", 2 }, -{ "sacz", 0x10080000, 0xfc0f0000, "r,R", 2 }, -{ "sbm", 0x98080000, 0xfc080000, "f,xOA,X", 4 }, -{ "sbr", 0x18000000, 0xfc0c0000, "r,f", 4 }, -{ "sea", 0x000d0000, 0xffff0000, "", 2 }, -{ "setcpu", 0x2c090000, 0xfc7f0000, "r", 2 }, -{ "sio", 0xfc170000, 0xfc7f8000, "r,I", 4 }, -{ "sipu", 0x000a0000, 0xffff0000, "", 2 }, -{ "sla", 0x1c400000, 0xfc600000, "r,S", 2 }, -{ "slad", 0x20400000, 0xfc600000, "r,S", 2 }, -{ "slc", 0x24400000, 0xfc600000, "r,S", 2 }, -{ "sll", 0x1c600000, 0xfc600000, "r,S", 2 }, -{ "slld", 0x20600000, 0xfc600000, "r,S", 2 }, -{ "smc", 0x04070000, 0xfc070000, "", 2 }, -{ "sra", 0x1c000000, 0xfc600000, "r,S", 2 }, -{ "srad", 0x20000000, 0xfc600000, "r,S", 2 }, -{ "src", 0x24000000, 0xfc600000, "r,S", 2 }, -{ "srl", 0x1c200000, 0xfc600000, "r,S", 2 }, -{ "srld", 0x20200000, 0xfc600000, "r,S", 2 }, -{ "stb", 0xd4080000, 0xfc080000, "r,xOA,X", 4 }, -{ "std", 0xd4000002, 0xfc080002, "r,xOA,X", 4 }, -{ "stf", 0xdc000000, 0xfc080000, "r,xOA,X", 4 }, -{ "stfbr", 0x54000000, 0xfc080000, "b,xOA,X", 4 }, -{ "sth", 0xd4000001, 0xfc080001, "r,xOA,X", 4 }, -{ "stmb", 0xd8080000, 0xfc080000, "r,xOA,X", 4 }, -{ "stmd", 0xd8000002, 0xfc080002, "r,xOA,X", 4 }, -{ "stmh", 0xd8000001, 0xfc080001, "r,xOA,X", 4 }, -{ "stmw", 0xd8000000, 0xfc080000, "r,xOA,X", 4 }, -{ "stpio", 0xfc270000, 0xfc7f8000, "r,I", 4 }, -{ "stw", 0xd4000000, 0xfc080000, "r,xOA,X", 4 }, -{ "stwbr", 0x54000000, 0xfc080000, "b,xOA,X", 4 }, -{ "suabr", 0x58000000, 0xfc080000, "b,xOA,X", 4 }, -{ "sufd", 0xe0000002, 0xfc080002, "r,xOA,X", 4 }, -{ "sufw", 0xe0000000, 0xfc080000, "r,xOA,X", 4 }, -{ "sui", 0xc8020000, 0xfc7f0000, "r,I", 4 }, -{ "sumb", 0xbc080000, 0xfc080000, "r,xOA,X", 4 }, -{ "sumd", 0xbc000002, 0xfc080002, "r,xOA,X", 4 }, -{ "sumh", 0xbc000001, 0xfc080001, "r,xOA,X", 4 }, -{ "sumw", 0xbc000000, 0xfc080000, "r,xOA,X", 4 }, -{ "sur", 0x3c000000, 0xfc0f0000, "r,R", 2 }, -{ "surfd", 0x380b0000, 0xfc0f0000, "r,xOA,X", 4 }, -{ "surfw", 0x38030000, 0xfc0f0000, "r,R", 2 }, -{ "surm", 0x3c080000, 0xfc0f0000, "r,R", 2 }, -{ "svc", 0xc8060000, 0xffff0000, "", 4 }, -{ "tbm", 0xa4080000, 0xfc080000, "f,xOA,X", 4 }, -{ "tbr", 0x180c0000, 0xfc0c0000, "r,f", 2 }, -{ "tbrr", 0x2c020000, 0xfc0f0000, "r,B", 2 }, -{ "tccr", 0x28040000, 0xfc7f0000, "", 2 }, -{ "td", 0xfc050000, 0xfc070000, "r,f", 4 }, -{ "tio", 0xfc1f0000, 0xfc7f8000, "r,I", 4 }, -{ "tmapr", 0x2c0a0000, 0xfc0f0000, "r,R", 2 }, -{ "tpcbr", 0x280c0000, 0xfc7f0000, "r", 2 }, -{ "trbr", 0x2c010000, 0xfc0f0000, "b,R", 2 }, -{ "trc", 0x2c030000, 0xfc0f0000, "r,R", 2 }, -{ "trcc", 0x28050000, 0xfc7f0000, "", 2 }, -{ "trcm", 0x2c0b0000, 0xfc0f0000, "r,R", 2 }, -{ "trn", 0x2c040000, 0xfc0f0000, "r,R", 2 }, -{ "trnm", 0x2c0c0000, 0xfc0f0000, "r,R", 2 }, -{ "trr", 0x2c000000, 0xfc0f0000, "r,R", 2 }, -{ "trrm", 0x2c080000, 0xfc0f0000, "r,R", 2 }, -{ "trsc", 0x2c0e0000, 0xfc0f0000, "r,R", 2 }, -{ "trsw", 0x28000000, 0xfc7f0000, "r", 2 }, -{ "tscr", 0x2c0f0000, 0xfc0f0000, "r,R", 2 }, -{ "uei", 0x00070000, 0xffff0000, "", 2 }, -{ "wait", 0x00010000, 0xffff0000, "", 2 }, -{ "wcwcs", 0xfc5f0000, 0xfc7f8000, "", 4 }, -{ "wwcs", 0x000c0000, 0xfc0f0000, "r,R", 2 }, -{ "xcbr", 0x28020000, 0xfc0f0000, "b,B", 2 }, -{ "xcr", 0x2c050000, 0xfc0f0000, "r,R", 2 }, -{ "xcrm", 0x2c0d0000, 0xfc0f0000, "r,R", 2 }, -{ "zbm", 0x9c080000, 0xfc080000, "f,xOA,X", 4 }, -{ "zbr", 0x18040000, 0xfc0c0000, "r,f", 2 }, -{ "zmb", 0xf8080000, 0xfc080000, "r,xOA,X", 4 }, -{ "zmd", 0xf8000002, 0xfc080002, "r,xOA,X", 4 }, -{ "zmh", 0xf8000001, 0xfc080001, "r,xOA,X", 4 }, -{ "zmw", 0xf8000000, 0xfc080000, "r,xOA,X", 4 }, -{ "zr", 0x0c000000, 0xfc0f0000, "r", 2 }, -}; - -int numopcodes = sizeof(gld_opcodes) / sizeof(gld_opcodes[0]); - -struct gld_opcode *endop = gld_opcodes + sizeof(gld_opcodes) / - sizeof(gld_opcodes[0]); diff --git a/include/opcode/ppc.h b/include/opcode/ppc.h deleted file mode 100644 index df97130..0000000 --- a/include/opcode/ppc.h +++ /dev/null @@ -1,413 +0,0 @@ -/* ppc.h -- Header file for PowerPC opcode table - Copyright 1994, 1995, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, - 2007, 2008, 2009, 2010, 2012 Free Software Foundation, Inc. - Written by Ian Lance Taylor, Cygnus Support - - This file is part of GDB, GAS, and the GNU binutils. - - GDB, GAS, and the GNU binutils are free software; you can redistribute - them and/or modify them under the terms of the GNU General Public - License as published by the Free Software Foundation; either version 3, - or (at your option) any later version. - - GDB, GAS, and the GNU binutils are distributed in the hope that they - will be useful, but WITHOUT ANY WARRANTY; without even the implied - warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See - the GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this file; see the file COPYING3. If not, write to the Free - Software Foundation, 51 Franklin Street - Fifth Floor, Boston, - MA 02110-1301, USA. */ - -#ifndef PPC_H -#define PPC_H - -#include "bfd_stdint.h" - -typedef uint64_t ppc_cpu_t; - -/* The opcode table is an array of struct powerpc_opcode. */ - -struct powerpc_opcode -{ - /* The opcode name. */ - const char *name; - - /* The opcode itself. Those bits which will be filled in with - operands are zeroes. */ - unsigned long opcode; - - /* The opcode mask. This is used by the disassembler. This is a - mask containing ones indicating those bits which must match the - opcode field, and zeroes indicating those bits which need not - match (and are presumably filled in by operands). */ - unsigned long mask; - - /* One bit flags for the opcode. These are used to indicate which - specific processors support the instructions. The defined values - are listed below. */ - ppc_cpu_t flags; - - /* One bit flags for the opcode. These are used to indicate which - specific processors no longer support the instructions. The defined - values are listed below. */ - ppc_cpu_t deprecated; - - /* An array of operand codes. Each code is an index into the - operand table. They appear in the order which the operands must - appear in assembly code, and are terminated by a zero. */ - unsigned char operands[8]; -}; - -/* The table itself is sorted by major opcode number, and is otherwise - in the order in which the disassembler should consider - instructions. */ -extern const struct powerpc_opcode powerpc_opcodes[]; -extern const int powerpc_num_opcodes; -extern const struct powerpc_opcode vle_opcodes[]; -extern const int vle_num_opcodes; - -/* Values defined for the flags field of a struct powerpc_opcode. */ - -/* Opcode is defined for the PowerPC architecture. */ -#define PPC_OPCODE_PPC 1 - -/* Opcode is defined for the POWER (RS/6000) architecture. */ -#define PPC_OPCODE_POWER 2 - -/* Opcode is defined for the POWER2 (Rios 2) architecture. */ -#define PPC_OPCODE_POWER2 4 - -/* Opcode is supported by the Motorola PowerPC 601 processor. The 601 - is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions, - but it also supports many additional POWER instructions. */ -#define PPC_OPCODE_601 8 - -/* Opcode is supported in both the Power and PowerPC architectures - (ie, compiler's -mcpu=common or assembler's -mcom). More than just - the intersection of PPC_OPCODE_PPC with the union of PPC_OPCODE_POWER - and PPC_OPCODE_POWER2 because many instructions changed mnemonics - between POWER and POWERPC. */ -#define PPC_OPCODE_COMMON 0x10 - -/* Opcode is supported for any Power or PowerPC platform (this is - for the assembler's -many option, and it eliminates duplicates). */ -#define PPC_OPCODE_ANY 0x20 - -/* Opcode is only defined on 64 bit architectures. */ -#define PPC_OPCODE_64 0x40 - -/* Opcode is supported as part of the 64-bit bridge. */ -#define PPC_OPCODE_64_BRIDGE 0x80 - -/* Opcode is supported by Altivec Vector Unit */ -#define PPC_OPCODE_ALTIVEC 0x100 - -/* Opcode is supported by PowerPC 403 processor. */ -#define PPC_OPCODE_403 0x200 - -/* Opcode is supported by PowerPC BookE processor. */ -#define PPC_OPCODE_BOOKE 0x400 - -/* Opcode is supported by PowerPC 440 processor. */ -#define PPC_OPCODE_440 0x800 - -/* Opcode is only supported by Power4 architecture. */ -#define PPC_OPCODE_POWER4 0x1000 - -/* Opcode is only supported by Power7 architecture. */ -#define PPC_OPCODE_POWER7 0x2000 - -/* Opcode is only supported by e500x2 Core. */ -#define PPC_OPCODE_SPE 0x4000 - -/* Opcode is supported by e500x2 Integer select APU. */ -#define PPC_OPCODE_ISEL 0x8000 - -/* Opcode is an e500 SPE floating point instruction. */ -#define PPC_OPCODE_EFS 0x10000 - -/* Opcode is supported by branch locking APU. */ -#define PPC_OPCODE_BRLOCK 0x20000 - -/* Opcode is supported by performance monitor APU. */ -#define PPC_OPCODE_PMR 0x40000 - -/* Opcode is supported by cache locking APU. */ -#define PPC_OPCODE_CACHELCK 0x80000 - -/* Opcode is supported by machine check APU. */ -#define PPC_OPCODE_RFMCI 0x100000 - -/* Opcode is only supported by Power5 architecture. */ -#define PPC_OPCODE_POWER5 0x200000 - -/* Opcode is supported by PowerPC e300 family. */ -#define PPC_OPCODE_E300 0x400000 - -/* Opcode is only supported by Power6 architecture. */ -#define PPC_OPCODE_POWER6 0x800000 - -/* Opcode is only supported by PowerPC Cell family. */ -#define PPC_OPCODE_CELL 0x1000000 - -/* Opcode is supported by CPUs with paired singles support. */ -#define PPC_OPCODE_PPCPS 0x2000000 - -/* Opcode is supported by Power E500MC */ -#define PPC_OPCODE_E500MC 0x4000000 - -/* Opcode is supported by PowerPC 405 processor. */ -#define PPC_OPCODE_405 0x8000000 - -/* Opcode is supported by Vector-Scalar (VSX) Unit */ -#define PPC_OPCODE_VSX 0x10000000 - -/* Opcode is supported by A2. */ -#define PPC_OPCODE_A2 0x20000000 - -/* Opcode is supported by PowerPC 476 processor. */ -#define PPC_OPCODE_476 0x40000000 - -/* Opcode is supported by AppliedMicro Titan core */ -#define PPC_OPCODE_TITAN 0x80000000 - -/* Opcode which is supported by the e500 family */ -#define PPC_OPCODE_E500 0x100000000ull - -/* Opcode is supported by Extended Altivec Vector Unit */ -#define PPC_OPCODE_ALTIVEC2 0x200000000ull - -/* Opcode is supported by Power E6500 */ -#define PPC_OPCODE_E6500 0x400000000ull - -/* Opcode is supported by Thread management APU */ -#define PPC_OPCODE_TMR 0x800000000ull - -/* Opcode which is supported by the VLE extension. */ -#define PPC_OPCODE_VLE 0x1000000000ull - -/* Opcode is only supported by Power8 architecture. */ -#define PPC_OPCODE_POWER8 0x2000000000ull - -/* Opcode which is supported by the Hardware Transactional Memory extension. */ -/* Currently, this is the same as the POWER8 mask. If another cpu comes out - that isn't a superset of POWER8, we can define this to its own mask. */ -#define PPC_OPCODE_HTM PPC_OPCODE_POWER8 - -/* A macro to extract the major opcode from an instruction. */ -#define PPC_OP(i) (((i) >> 26) & 0x3f) - -/* A macro to determine if the instruction is a 2-byte VLE insn. */ -#define PPC_OP_SE_VLE(m) ((m) <= 0xffff) - -/* A macro to extract the major opcode from a VLE instruction. */ -#define VLE_OP(i,m) (((i) >> ((m) <= 0xffff ? 10 : 26)) & 0x3f) - -/* A macro to convert a VLE opcode to a VLE opcode segment. */ -#define VLE_OP_TO_SEG(i) ((i) >> 1) - -/* The operands table is an array of struct powerpc_operand. */ - -struct powerpc_operand -{ - /* A bitmask of bits in the operand. */ - unsigned int bitm; - - /* The shift operation to be applied to the operand. No shift - is made if this is zero. For positive values, the operand - is shifted left by SHIFT. For negative values, the operand - is shifted right by -SHIFT. Use PPC_OPSHIFT_INV to indicate - that BITM and SHIFT cannot be used to determine where the - operand goes in the insn. */ - int shift; - - /* Insertion function. This is used by the assembler. To insert an - operand value into an instruction, check this field. - - If it is NULL, execute - if (o->shift >= 0) - i |= (op & o->bitm) << o->shift; - else - i |= (op & o->bitm) >> -o->shift; - (i is the instruction which we are filling in, o is a pointer to - this structure, and op is the operand value). - - If this field is not NULL, then simply call it with the - instruction and the operand value. It will return the new value - of the instruction. If the ERRMSG argument is not NULL, then if - the operand value is illegal, *ERRMSG will be set to a warning - string (the operand will be inserted in any case). If the - operand value is legal, *ERRMSG will be unchanged (most operands - can accept any value). */ - unsigned long (*insert) - (unsigned long instruction, long op, ppc_cpu_t dialect, const char **errmsg); - - /* Extraction function. This is used by the disassembler. To - extract this operand type from an instruction, check this field. - - If it is NULL, compute - if (o->shift >= 0) - op = (i >> o->shift) & o->bitm; - else - op = (i << -o->shift) & o->bitm; - if ((o->flags & PPC_OPERAND_SIGNED) != 0) - sign_extend (op); - (i is the instruction, o is a pointer to this structure, and op - is the result). - - If this field is not NULL, then simply call it with the - instruction value. It will return the value of the operand. If - the INVALID argument is not NULL, *INVALID will be set to - non-zero if this operand type can not actually be extracted from - this operand (i.e., the instruction does not match). If the - operand is valid, *INVALID will not be changed. */ - long (*extract) (unsigned long instruction, ppc_cpu_t dialect, int *invalid); - - /* One bit syntax flags. */ - unsigned long flags; -}; - -/* Elements in the table are retrieved by indexing with values from - the operands field of the powerpc_opcodes table. */ - -extern const struct powerpc_operand powerpc_operands[]; -extern const unsigned int num_powerpc_operands; - -/* Use with the shift field of a struct powerpc_operand to indicate - that BITM and SHIFT cannot be used to determine where the operand - goes in the insn. */ -#define PPC_OPSHIFT_INV (-1 << 31) - -/* Values defined for the flags field of a struct powerpc_operand. */ - -/* This operand takes signed values. */ -#define PPC_OPERAND_SIGNED (0x1) - -/* This operand takes signed values, but also accepts a full positive - range of values when running in 32 bit mode. That is, if bits is - 16, it takes any value from -0x8000 to 0xffff. In 64 bit mode, - this flag is ignored. */ -#define PPC_OPERAND_SIGNOPT (0x2) - -/* This operand does not actually exist in the assembler input. This - is used to support extended mnemonics such as mr, for which two - operands fields are identical. The assembler should call the - insert function with any op value. The disassembler should call - the extract function, ignore the return value, and check the value - placed in the valid argument. */ -#define PPC_OPERAND_FAKE (0x4) - -/* The next operand should be wrapped in parentheses rather than - separated from this one by a comma. This is used for the load and - store instructions which want their operands to look like - reg,displacement(reg) - */ -#define PPC_OPERAND_PARENS (0x8) - -/* This operand may use the symbolic names for the CR fields, which - are - lt 0 gt 1 eq 2 so 3 un 3 - cr0 0 cr1 1 cr2 2 cr3 3 - cr4 4 cr5 5 cr6 6 cr7 7 - These may be combined arithmetically, as in cr2*4+gt. These are - only supported on the PowerPC, not the POWER. */ -#define PPC_OPERAND_CR_BIT (0x10) - -/* This operand names a register. The disassembler uses this to print - register names with a leading 'r'. */ -#define PPC_OPERAND_GPR (0x20) - -/* Like PPC_OPERAND_GPR, but don't print a leading 'r' for r0. */ -#define PPC_OPERAND_GPR_0 (0x40) - -/* This operand names a floating point register. The disassembler - prints these with a leading 'f'. */ -#define PPC_OPERAND_FPR (0x80) - -/* This operand is a relative branch displacement. The disassembler - prints these symbolically if possible. */ -#define PPC_OPERAND_RELATIVE (0x100) - -/* This operand is an absolute branch address. The disassembler - prints these symbolically if possible. */ -#define PPC_OPERAND_ABSOLUTE (0x200) - -/* This operand is optional, and is zero if omitted. This is used for - example, in the optional BF field in the comparison instructions. The - assembler must count the number of operands remaining on the line, - and the number of operands remaining for the opcode, and decide - whether this operand is present or not. The disassembler should - print this operand out only if it is not zero. */ -#define PPC_OPERAND_OPTIONAL (0x400) - -/* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand - is omitted, then for the next operand use this operand value plus - 1, ignoring the next operand field for the opcode. This wretched - hack is needed because the Power rotate instructions can take - either 4 or 5 operands. The disassembler should print this operand - out regardless of the PPC_OPERAND_OPTIONAL field. */ -#define PPC_OPERAND_NEXT (0x800) - -/* This operand should be regarded as a negative number for the - purposes of overflow checking (i.e., the normal most negative - number is disallowed and one more than the normal most positive - number is allowed). This flag will only be set for a signed - operand. */ -#define PPC_OPERAND_NEGATIVE (0x1000) - -/* This operand names a vector unit register. The disassembler - prints these with a leading 'v'. */ -#define PPC_OPERAND_VR (0x2000) - -/* This operand is for the DS field in a DS form instruction. */ -#define PPC_OPERAND_DS (0x4000) - -/* This operand is for the DQ field in a DQ form instruction. */ -#define PPC_OPERAND_DQ (0x8000) - -/* Valid range of operand is 0..n rather than 0..n-1. */ -#define PPC_OPERAND_PLUS1 (0x10000) - -/* Xilinx APU and FSL related operands */ -#define PPC_OPERAND_FSL (0x20000) -#define PPC_OPERAND_FCR (0x40000) -#define PPC_OPERAND_UDI (0x80000) - -/* This operand names a vector-scalar unit register. The disassembler - prints these with a leading 'vs'. */ -#define PPC_OPERAND_VSR (0x100000) - -/* This is a CR FIELD that does not use symbolic names. */ -#define PPC_OPERAND_CR_REG (0x200000) - -/* The POWER and PowerPC assemblers use a few macros. We keep them - with the operands table for simplicity. The macro table is an - array of struct powerpc_macro. */ - -struct powerpc_macro -{ - /* The macro name. */ - const char *name; - - /* The number of operands the macro takes. */ - unsigned int operands; - - /* One bit flags for the opcode. These are used to indicate which - specific processors support the instructions. The values are the - same as those for the struct powerpc_opcode flags field. */ - ppc_cpu_t flags; - - /* A format string to turn the macro into a normal instruction. - Each %N in the string is replaced with operand number N (zero - based). */ - const char *format; -}; - -extern const struct powerpc_macro powerpc_macros[]; -extern const int powerpc_num_macros; - -extern ppc_cpu_t ppc_parse_cpu (ppc_cpu_t, ppc_cpu_t *, const char *); - -#endif /* PPC_H */ diff --git a/include/opcode/pyr.h b/include/opcode/pyr.h deleted file mode 100644 index 2fffd94..0000000 --- a/include/opcode/pyr.h +++ /dev/null @@ -1,305 +0,0 @@ -/* pyramid.opcode.h -- gdb initial attempt. - - Copyright 2001, 2010 Free Software Foundation, Inc. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3, or (at your option) - any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, - Boston, MA 02110-1301, USA. */ - -/* pyramid opcode table: wot to do with this - particular opcode */ - -struct pyr_datum -{ - char nargs; - char * args; /* how to compile said opcode */ - unsigned long mask; /* Bit vector: which operand modes are valid - for this opcode */ - unsigned char code; /* op-code (always 6(?) bits */ -}; - -typedef struct pyr_insn_format -{ - unsigned int mode :4; - unsigned int operator :8; - unsigned int index_scale :2; - unsigned int index_reg :6; - unsigned int operand_1 :6; - unsigned int operand_2:6; -} pyr_insn_format; - - -/* We store four bytes of opcode for all opcodes. - Pyramid is sufficiently RISCy that: - - insns are always an integral number of words; - - the length of any insn can be told from the first word of - the insn. (ie, if there are zero, one, or two words of - immediate operand/offset). - - - The args component is a string containing two characters for each - operand of the instruction. The first specifies the kind of operand; - the second, the place it is stored. */ - -/* Kinds of operands: - mask assembler syntax description - 0x0001: movw Rn,Rn register to register - 0x0002: movw K,Rn quick immediate to register - 0x0004: movw I,Rn long immediate to register - 0x0008: movw (Rn),Rn register indirect to register - movw (Rn)[x],Rn register indirect to register - 0x0010: movw I(Rn),Rn offset register indirect to register - movw I(Rn)[x],Rn offset register indirect, indexed, to register - - 0x0020: movw Rn,(Rn) register to register indirect - 0x0040: movw K,(Rn) quick immediate to register indirect - 0x0080: movw I,(Rn) long immediate to register indirect - 0x0100: movw (Rn),(Rn) register indirect to-register indirect - 0x0100: movw (Rn),(Rn) register indirect to-register indirect - 0x0200: movw I(Rn),(Rn) register indirect+offset to register indirect - 0x0200: movw I(Rn),(Rn) register indirect+offset to register indirect - - 0x0400: movw Rn,I(Rn) register to register indirect+offset - 0x0800: movw K,I(Rn) quick immediate to register indirect+offset - 0x1000: movw I,I(Rn) long immediate to register indirect+offset - 0x1000: movw (Rn),I(Rn) register indirect to-register indirect+offset - 0x1000: movw I(Rn),I(Rn) register indirect+offset to register indirect - +offset - 0x0000: (irregular) ??? - - - Each insn has a four-bit field encoding the type(s) of its operands. -*/ - -/* Some common combinations - */ - -/* the first 5,(0x1|0x2|0x4|0x8|0x10) ie (1|2|4|8|16), ie ( 32 -1)*/ -#define GEN_TO_REG (31) - -#define UNKNOWN ((unsigned long)-1) -#define ANY (GEN_TO_REG | (GEN_TO_REG << 5) | (GEN_TO_REG << 15)) - -#define CONVERT (1|8|0x10|0x20|0x200) - -#define K_TO_REG (2) -#define I_TO_REG (4) -#define NOTK_TO_REG (GEN_TO_REG & ~K_TO_REG) -#define NOTI_TO_REG (GEN_TO_REG & ~I_TO_REG) - -/* The assembler requires that this array be sorted as follows: - all instances of the same mnemonic must be consecutive. - All instances of the same mnemonic with the same number of operands - must be consecutive. - */ - -struct pyr_opcode /* pyr opcode text */ -{ - char * name; /* opcode name: lowercase string [key] */ - struct pyr_datum datum; /* rest of opcode table [datum] */ -}; - -#define pyr_how args -#define pyr_nargs nargs -#define pyr_mask mask -#define pyr_name name - -struct pyr_opcode pyr_opcodes[] = -{ - {"movb", { 2, "", UNKNOWN, 0x11}, }, - {"movh", { 2, "", UNKNOWN, 0x12} }, - {"movw", { 2, "", ANY, 0x10} }, - {"movl", { 2, "", ANY, 0x13} }, - {"mnegw", { 2, "", (0x1|0x8|0x10), 0x14} }, - {"mnegf", { 2, "", 0x1, 0x15} }, - {"mnegd", { 2, "", 0x1, 0x16} }, - {"mcomw", { 2, "", (0x1|0x8|0x10), 0x17} }, - {"mabsw", { 2, "", (0x1|0x8|0x10), 0x18} }, - {"mabsf", { 2, "", 0x1, 0x19} }, - {"mabsd", { 2, "", 0x1, 0x1a} }, - {"mtstw", { 2, "", (0x1|0x8|0x10), 0x1c} }, - {"mtstf", { 2, "", 0x1, 0x1d} }, - {"mtstd", { 2, "", 0x1, 0x1e} }, - {"mova", { 2, "", 0x8|0x10, 0x1f} }, - {"movzbw", { 2, "", (0x1|0x8|0x10), 0x20} }, - {"movzhw", { 2, "", (0x1|0x8|0x10), 0x21} }, - /* 2 insns out of order here */ - {"movbl", { 2, "", 1, 0x4f} }, - {"filbl", { 2, "", 1, 0x4e} }, - - {"cvtbw", { 2, "", CONVERT, 0x22} }, - {"cvthw", { 2, "", CONVERT, 0x23} }, - {"cvtwb", { 2, "", CONVERT, 0x24} }, - {"cvtwh", { 2, "", CONVERT, 0x25} }, - {"cvtwf", { 2, "", CONVERT, 0x26} }, - {"cvtwd", { 2, "", CONVERT, 0x27} }, - {"cvtfw", { 2, "", CONVERT, 0x28} }, - {"cvtfd", { 2, "", CONVERT, 0x29} }, - {"cvtdw", { 2, "", CONVERT, 0x2a} }, - {"cvtdf", { 2, "", CONVERT, 0x2b} }, - - {"addw", { 2, "", GEN_TO_REG, 0x40} }, - {"addwc", { 2, "", GEN_TO_REG, 0x41} }, - {"subw", { 2, "", GEN_TO_REG, 0x42} }, - {"subwb", { 2, "", GEN_TO_REG, 0x43} }, - {"rsubw", { 2, "", GEN_TO_REG, 0x44} }, - {"mulw", { 2, "", GEN_TO_REG, 0x45} }, - {"emul", { 2, "", GEN_TO_REG, 0x47} }, - {"umulw", { 2, "", GEN_TO_REG, 0x46} }, - {"divw", { 2, "", GEN_TO_REG, 0x48} }, - {"ediv", { 2, "", GEN_TO_REG, 0x4a} }, - {"rdivw", { 2, "", GEN_TO_REG, 0x4b} }, - {"udivw", { 2, "", GEN_TO_REG, 0x49} }, - {"modw", { 2, "", GEN_TO_REG, 0x4c} }, - {"umodw", { 2, "", GEN_TO_REG, 0x4d} }, - - - {"addf", { 2, "", 1, 0x50} }, - {"addd", { 2, "", 1, 0x51} }, - {"subf", { 2, "", 1, 0x52} }, - {"subd", { 2, "", 1, 0x53} }, - {"mulf", { 2, "", 1, 0x56} }, - {"muld", { 2, "", 1, 0x57} }, - {"divf", { 2, "", 1, 0x58} }, - {"divd", { 2, "", 1, 0x59} }, - - - {"cmpb", { 2, "", UNKNOWN, 0x61} }, - {"cmph", { 2, "", UNKNOWN, 0x62} }, - {"cmpw", { 2, "", UNKNOWN, 0x60} }, - {"ucmpb", { 2, "", UNKNOWN, 0x66} }, - /* WHY no "ucmph"??? */ - {"ucmpw", { 2, "", UNKNOWN, 0x65} }, - {"xchw", { 2, "", UNKNOWN, 0x0f} }, - - - {"andw", { 2, "", GEN_TO_REG, 0x30} }, - {"orw", { 2, "", GEN_TO_REG, 0x31} }, - {"xorw", { 2, "", GEN_TO_REG, 0x32} }, - {"bicw", { 2, "", GEN_TO_REG, 0x33} }, - {"lshlw", { 2, "", GEN_TO_REG, 0x38} }, - {"ashlw", { 2, "", GEN_TO_REG, 0x3a} }, - {"ashll", { 2, "", GEN_TO_REG, 0x3c} }, - {"ashrw", { 2, "", GEN_TO_REG, 0x3b} }, - {"ashrl", { 2, "", GEN_TO_REG, 0x3d} }, - {"rotlw", { 2, "", GEN_TO_REG, 0x3e} }, - {"rotrw", { 2, "", GEN_TO_REG, 0x3f} }, - - /* push and pop insns are "going away next release". */ - {"pushw", { 2, "", GEN_TO_REG, 0x0c} }, - {"popw", { 2, "", (0x1|0x8|0x10), 0x0d} }, - {"pusha", { 2, "", (0x8|0x10), 0x0e} }, - - {"bitsw", { 2, "", UNKNOWN, 0x35} }, - {"bitcw", { 2, "", UNKNOWN, 0x36} }, - /* some kind of ibra/dbra insns??*/ - {"icmpw", { 2, "", UNKNOWN, 0x67} }, - {"dcmpw", { 2, "", (1|4|0x20|0x80|0x400|0x1000), 0x69} },/*FIXME*/ - {"acmpw", { 2, "", 1, 0x6b} }, - - /* Call is written as a 1-op insn, but is always (dis)assembled as a 2-op - insn with a 2nd op of tr14. The assembler will have to grok this. */ - {"call", { 2, "", GEN_TO_REG, 0x04} }, - {"call", { 1, "", GEN_TO_REG, 0x04} }, - - {"callk", { 1, "", UNKNOWN, 0x06} },/* system call?*/ - /* Ret is usually written as a 0-op insn, but gets disassembled as a - 1-op insn. The operand is always tr15. */ - {"ret", { 0, "", UNKNOWN, 0x09} }, - {"ret", { 1, "", UNKNOWN, 0x09} }, - {"adsf", { 2, "", (1|2|4), 0x08} }, - {"retd", { 2, "", UNKNOWN, 0x0a} }, - {"btc", { 2, "", UNKNOWN, 0x01} }, - {"bfc", { 2, "", UNKNOWN, 0x02} }, - /* Careful: halt is 0x00000000. Jump must have some other (mode?)bit set?? */ - {"jump", { 1, "", UNKNOWN, 0x00} }, - {"btp", { 2, "", UNKNOWN, 0xf00} }, - /* read control-stack pointer is another 1-or-2 operand insn. */ - {"rcsp", { 2, "", UNKNOWN, 0x01f} }, - {"rcsp", { 1, "", UNKNOWN, 0x01f} } -}; - -/* end: pyramid.opcode.h */ -/* One day I will have to take the time to find out what operands - are valid for these insns, and guess at what they mean. - - I can't imagine what the "I???" insns (iglob, etc) do. - - the arithmetic-sounding insns ending in "p" sound awfully like BCD - arithmetic insns: - dshlp -> Decimal SHift Left Packed - dshrp -> Decimal SHift Right Packed - and cvtlp would be convert long to packed. - I have no idea how the operands are interpreted; but having them be - a long register with (address, length) of an in-memory packed BCD operand - would not be surprising. - They are unlikely to be a packed bcd string: 64 bits of long give - is only 15 digits+sign, which isn't enough for COBOL. - */ -#if 0 - {"wcsp", { 2, "", UNKNOWN, 0x00} }, /*write csp?*/ - /* The OSx Operating System Porting Guide claims SSL does things - with tr12 (a register reserved to it) to do with static block-structure - references. SSL=Set Static Link? It's "Going away next release". */ - {"ssl", { 2, "", UNKNOWN, 0x00} }, - {"ccmps", { 2, "", UNKNOWN, 0x00} }, - {"lcd", { 2, "", UNKNOWN, 0x00} }, - {"uemul", { 2, "", UNKNOWN, 0x00} }, /*unsigned emul*/ - {"srf", { 2, "", UNKNOWN, 0x00} }, /*Gidget time???*/ - {"mnegp", { 2, "", UNKNOWN, 0x00} }, /move-neg phys?*/ - {"ldp", { 2, "", UNKNOWN, 0x00} }, /*load phys?*/ - {"ldti", { 2, "", UNKNOWN, 0x00} }, - {"ldb", { 2, "", UNKNOWN, 0x00} }, - {"stp", { 2, "", UNKNOWN, 0x00} }, - {"stti", { 2, "", UNKNOWN, 0x00} }, - {"stb", { 2, "", UNKNOWN, 0x00} }, - {"stu", { 2, "", UNKNOWN, 0x00} }, - {"addp", { 2, "", UNKNOWN, 0x00} }, - {"subp", { 2, "", UNKNOWN, 0x00} }, - {"mulp", { 2, "", UNKNOWN, 0x00} }, - {"divp", { 2, "", UNKNOWN, 0x00} }, - {"dshlp", { 2, "", UNKNOWN, 0x00} }, /* dec shl packed? */ - {"dshrp", { 2, "", UNKNOWN, 0x00} }, /* dec shr packed? */ - {"movs", { 2, "", UNKNOWN, 0x00} }, /*move (string?)?*/ - {"cmpp", { 2, "", UNKNOWN, 0x00} }, /* cmp phys?*/ - {"cmps", { 2, "", UNKNOWN, 0x00} }, /* cmp (string?)?*/ - {"cvtlp", { 2, "", UNKNOWN, 0x00} }, /* cvt long to p??*/ - {"cvtpl", { 2, "", UNKNOWN, 0x00} }, /* cvt p to l??*/ - {"dintr", { 2, "", UNKNOWN, 0x00} }, /* ?? intr ?*/ - {"rphysw", { 2, "", UNKNOWN, 0x00} }, /* read phys word?*/ - {"wphysw", { 2, "", UNKNOWN, 0x00} }, /* write phys word?*/ - {"cmovs", { 2, "", UNKNOWN, 0x00} }, - {"rsubw", { 2, "", UNKNOWN, 0x00} }, - {"bicpsw", { 2, "", UNKNOWN, 0x00} }, /* clr bit in psw? */ - {"bispsw", { 2, "", UNKNOWN, 0x00} }, /* set bit in psw? */ - {"eio", { 2, "", UNKNOWN, 0x00} }, /* ?? ?io ? */ - {"callp", { 2, "", UNKNOWN, 0x00} }, /* call phys?*/ - {"callr", { 2, "", UNKNOWN, 0x00} }, - {"lpcxt", { 2, "", UNKNOWN, 0x00} }, /*load proc context*/ - {"rei", { 2, "", UNKNOWN, 0x00} }, /*ret from intrpt*/ - {"rport", { 2, "", UNKNOWN, 0x00} }, /*read-port?*/ - {"rtod", { 2, "", UNKNOWN, 0x00} }, /*read-time-of-day?*/ - {"ssi", { 2, "", UNKNOWN, 0x00} }, - {"vtpa", { 2, "", UNKNOWN, 0x00} }, /*virt-to-phys-addr?*/ - {"wicl", { 2, "", UNKNOWN, 0x00} }, /* write icl ? */ - {"wport", { 2, "", UNKNOWN, 0x00} }, /*write-port?*/ - {"wtod", { 2, "", UNKNOWN, 0x00} }, /*write-time-of-day?*/ - {"flic", { 2, "", UNKNOWN, 0x00} }, - {"iglob", { 2, "", UNKNOWN, 0x00} }, /* I global? */ - {"iphys", { 2, "", UNKNOWN, 0x00} }, /* I physical? */ - {"ipid", { 2, "", UNKNOWN, 0x00} }, /* I pid? */ - {"ivect", { 2, "", UNKNOWN, 0x00} }, /* I vector? */ - {"lamst", { 2, "", UNKNOWN, 0x00} }, - {"tio", { 2, "", UNKNOWN, 0x00} }, -#endif diff --git a/include/opcode/rl78.h b/include/opcode/rl78.h deleted file mode 100644 index 0f3c64d..0000000 --- a/include/opcode/rl78.h +++ /dev/null @@ -1,168 +0,0 @@ -/* Opcode decoder for the Renesas RL78 - Copyright 2011 - Free Software Foundation, Inc. - Written by DJ Delorie <dj@redhat.com> - - This file is part of GDB, the GNU Debugger and GAS, the GNU Assembler. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA - 02110-1301, USA. */ - -/* The RL78 decoder in libopcodes is used by the simulator, gdb's - analyzer, and the disassembler. Given an opcode data source, it - decodes the next opcode into the following structures. */ - -#ifndef RL78_OPCODES_H_INCLUDED -#define RL78_OPCODES_H_INCLUDED - -/* For the purposes of these structures, the RL78 registers are as - follows, despite most of these being memory-mapped and - bank-switched: */ -typedef enum { - RL78_Reg_None, - /* The order of these matches the encodings. */ - RL78_Reg_X, - RL78_Reg_A, - RL78_Reg_C, - RL78_Reg_B, - RL78_Reg_E, - RL78_Reg_D, - RL78_Reg_L, - RL78_Reg_H, - /* The order of these matches the encodings. */ - RL78_Reg_AX, - RL78_Reg_BC, - RL78_Reg_DE, - RL78_Reg_HL, - /* Unordered. */ - RL78_Reg_SP, - RL78_Reg_PSW, - RL78_Reg_CS, - RL78_Reg_ES, - RL78_Reg_PMC, - RL78_Reg_MEM -} RL78_Register; - -typedef enum -{ - RL78_Byte = 0, - RL78_Word -} RL78_Size; - -typedef enum { - RL78_Condition_T, - RL78_Condition_F, - RL78_Condition_C, - RL78_Condition_NC, - RL78_Condition_H, - RL78_Condition_NH, - RL78_Condition_Z, - RL78_Condition_NZ -} RL78_Condition; - -typedef enum { - RL78_Operand_None = 0, - RL78_Operand_Immediate, /* #addend */ - RL78_Operand_Register, /* reg */ - RL78_Operand_Indirect, /* [reg + reg2 + addend] */ - RL78_Operand_Bit, /* reg.bit */ - RL78_Operand_BitIndirect, /* [reg+reg2+addend].bit */ - RL78_Operand_PreDec, /* [--reg] = push */ - RL78_Operand_PostInc /* [reg++] = pop */ -} RL78_Operand_Type; - -typedef enum -{ - RLO_unknown, - RLO_add, /* d += s */ - RLO_addc, /* d += s + CY */ - RLO_and, /* d &= s (byte, word, bit) */ - RLO_branch, /* pc = d */ - RLO_branch_cond, /* pc = d if cond(src) */ - RLO_branch_cond_clear, /* pc = d if cond(src), and clear(src) */ - RLO_break, /* BRK */ - RLO_call, /* call */ - RLO_cmp, /* cmp d, s */ - RLO_divhu, /* DIVHU */ - RLO_divwu, /* DIVWU */ - RLO_halt, /* HALT */ - RLO_mov, /* d = s */ - RLO_mach, /* MACH */ - RLO_machu, /* MACHU */ - RLO_mulu, /* MULU */ - RLO_mulh, /* MULH */ - RLO_mulhu, /* MULHU */ - RLO_nop, /* NOP */ - RLO_or, /* d |= s */ - RLO_ret, /* RET */ - RLO_reti, /* RETI */ - RLO_rol, /* d <<= s, MSB to LSB and CY */ - RLO_rolc, /* d <<= s, MSB to CY, CY, to LSB */ - RLO_ror, /* d >>= s, LSB to MSB and CY */ - RLO_rorc, /* d >>= s, LSB to CY, CY, to MSB */ - RLO_sar, /* d >>= s, signed */ - RLO_sel, /* rb = s */ - RLO_shr, /* d >>= s, unsigned */ - RLO_shl, /* d <<= s */ - RLO_skip, /* skip next insn is cond(s) */ - RLO_stop, /* STOP */ - RLO_sub, /* d -= s */ - RLO_subc, /* d -= s - CY */ - RLO_xch, /* swap d, s */ - RLO_xor, /* d ^= s */ -} RL78_Opcode_ID; - -typedef struct { - RL78_Operand_Type type; - int addend; - RL78_Register reg : 8; - RL78_Register reg2 : 8; - unsigned char bit_number : 4; - unsigned char condition : 3; - unsigned char use_es : 1; -} RL78_Opcode_Operand; - -/* PSW flag bits */ -#define RL78_PSW_IE 0x80 -#define RL78_PSW_Z 0x40 -#define RL78_PSW_RBS1 0x20 -#define RL78_PSW_AC 0x10 -#define RL78_PSW_RBS0 0x08 -#define RL78_PSW_ISP1 0x04 -#define RL78_PSW_ISP0 0x02 -#define RL78_PSW_CY 0x01 - -#define RL78_SFR_SP 0xffff8 -#define RL78_SFR_PSW 0xffffa -#define RL78_SFR_CS 0xffffc -#define RL78_SFR_ES 0xffffd -#define RL78_SFR_PMC 0xffffe -#define RL78_SFR_MEM 0xfffff - -typedef struct -{ - int lineno; - RL78_Opcode_ID id:24; - unsigned flags:8; /* PSW mask, for side effects only */ - int n_bytes; - char * syntax; - RL78_Size size; - /* By convention, these are destination, source. */ - RL78_Opcode_Operand op[2]; -} RL78_Opcode_Decoded; - -int rl78_decode_opcode (unsigned long, RL78_Opcode_Decoded *, int (*)(void *), void *); - -#endif diff --git a/include/opcode/rx.h b/include/opcode/rx.h deleted file mode 100644 index aa85fe4..0000000 --- a/include/opcode/rx.h +++ /dev/null @@ -1,215 +0,0 @@ -/* Opcode decoder for the Renesas RX - Copyright 2008, 2009, 2010 - Free Software Foundation, Inc. - Written by DJ Delorie <dj@redhat.com> - - This file is part of GDB, the GNU Debugger and GAS, the GNU Assembler. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA - 02110-1301, USA. */ - -/* The RX decoder in libopcodes is used by the simulator, gdb's - analyzer, and the disassembler. Given an opcode data source, - it decodes the next opcode into the following structures. */ - -typedef enum -{ - RX_AnySize = 0, - RX_Byte, /* undefined extension */ - RX_UByte, - RX_SByte, - RX_Word, /* undefined extension */ - RX_UWord, - RX_SWord, - RX_3Byte, - RX_Long, -} RX_Size; - -typedef enum -{ - RX_Operand_None, - RX_Operand_Immediate, /* #addend */ - RX_Operand_Register, /* Rn */ - RX_Operand_Indirect, /* [Rn + addend] */ - RX_Operand_Postinc, /* [Rn+] */ - RX_Operand_Predec, /* [-Rn] */ - RX_Operand_Condition, /* eq, gtu, etc */ - RX_Operand_Flag, /* [UIOSZC] */ - RX_Operand_TwoReg, /* [Rn + scale*R2] */ -} RX_Operand_Type; - -typedef enum -{ - RXO_unknown, - RXO_mov, /* d = s (signed) */ - RXO_movbi, /* d = [s,s2] (signed) */ - RXO_movbir, /* [s,s2] = d (signed) */ - RXO_pushm, /* s..s2 */ - RXO_popm, /* s..s2 */ - RXO_xchg, /* s <-> d */ - RXO_stcc, /* d = s if cond(s2) */ - RXO_rtsd, /* rtsd, 1=imm, 2-0 = reg if reg type */ - - /* These are all either d OP= s or, if s2 is set, d = s OP s2. Note - that d may be "None". */ - RXO_and, - RXO_or, - RXO_xor, - RXO_add, - RXO_sub, - RXO_mul, - RXO_div, - RXO_divu, - RXO_shll, - RXO_shar, - RXO_shlr, - - RXO_adc, /* d = d + s + carry */ - RXO_sbb, /* d = d - s - ~carry */ - RXO_abs, /* d = |s| */ - RXO_max, /* d = max(d,s) */ - RXO_min, /* d = min(d,s) */ - RXO_emul, /* d:64 = d:32 * s */ - RXO_emulu, /* d:64 = d:32 * s (unsigned) */ - - RXO_rolc, /* d <<= 1 through carry */ - RXO_rorc, /* d >>= 1 through carry*/ - RXO_rotl, /* d <<= #s without carry */ - RXO_rotr, /* d >>= #s without carry*/ - RXO_revw, /* d = revw(s) */ - RXO_revl, /* d = revl(s) */ - RXO_branch, /* pc = d if cond(s) */ - RXO_branchrel,/* pc += d if cond(s) */ - RXO_jsr, /* pc = d */ - RXO_jsrrel, /* pc += d */ - RXO_rts, - RXO_nop, - RXO_nop2, - RXO_nop3, - - RXO_scmpu, - RXO_smovu, - RXO_smovb, - RXO_suntil, - RXO_swhile, - RXO_smovf, - RXO_sstr, - - RXO_rmpa, - RXO_mulhi, - RXO_mullo, - RXO_machi, - RXO_maclo, - RXO_mvtachi, - RXO_mvtaclo, - RXO_mvfachi, - RXO_mvfacmi, - RXO_mvfaclo, - RXO_racw, - - RXO_sat, /* sat(d) */ - RXO_satr, - - RXO_fadd, /* d op= s */ - RXO_fcmp, - RXO_fsub, - RXO_ftoi, - RXO_fmul, - RXO_fdiv, - RXO_round, - RXO_itof, - - RXO_bset, /* d |= (1<<s) */ - RXO_bclr, /* d &= ~(1<<s) */ - RXO_btst, /* s & (1<<s2) */ - RXO_bnot, /* d ^= (1<<s) */ - RXO_bmcc, /* d<s> = cond(s2) */ - - RXO_clrpsw, /* flag index in d */ - RXO_setpsw, /* flag index in d */ - RXO_mvtipl, /* new IPL in s */ - - RXO_rtfi, - RXO_rte, - RXO_rtd, /* undocumented */ - RXO_brk, - RXO_dbt, /* undocumented */ - RXO_int, /* vector id in s */ - RXO_stop, - RXO_wait, - - RXO_sccnd, /* d = cond(s) ? 1 : 0 */ -} RX_Opcode_ID; - -/* Condition bitpatterns, as registers. */ -#define RXC_eq 0 -#define RXC_z 0 -#define RXC_ne 1 -#define RXC_nz 1 -#define RXC_c 2 -#define RXC_nc 3 -#define RXC_gtu 4 -#define RXC_leu 5 -#define RXC_pz 6 -#define RXC_n 7 -#define RXC_ge 8 -#define RXC_lt 9 -#define RXC_gt 10 -#define RXC_le 11 -#define RXC_o 12 -#define RXC_no 13 -#define RXC_always 14 -#define RXC_never 15 - -typedef struct -{ - RX_Operand_Type type; - int reg; - int addend; - RX_Size size; -} RX_Opcode_Operand; - -typedef struct -{ - RX_Opcode_ID id; - int n_bytes; - int prefix; - char * syntax; - RX_Size size; - /* By convention, these are destination, source1, source2. */ - RX_Opcode_Operand op[3]; - - /* The logic here is: - newflags = (oldflags & ~(int)flags_0) | flags_1 | (op_flags & flags_s) - Only the O, S, Z, and C flags are affected. */ - char flags_0; /* This also clears out flags-to-be-set. */ - char flags_1; - char flags_s; -} RX_Opcode_Decoded; - -/* Within the syntax, %c-style format specifiers are as follows: - - %% = '%' character - %0 = operand[0] (destination) - %1 = operand[1] (source) - %2 = operand[2] (2nd source) - %s = operation size (b/w/l) - %SN = operand size [N] (N=0,1,2) - %aN = op[N] as an address (N=0,1,2) - - Register numbers 0..15 are general registers. 16..31 are control - registers. 32..47 are condition codes. */ - -int rx_decode_opcode (unsigned long, RX_Opcode_Decoded *, int (*)(void *), void *); diff --git a/include/opcode/s390.h b/include/opcode/s390.h deleted file mode 100644 index 531011e..0000000 --- a/include/opcode/s390.h +++ /dev/null @@ -1,154 +0,0 @@ -/* s390.h -- Header file for S390 opcode table - Copyright 2000, 2001, 2003, 2010 Free Software Foundation, Inc. - Contributed by Martin Schwidefsky (schwidefsky@de.ibm.com). - - This file is part of BFD, the Binary File Descriptor library. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA - 02110-1301, USA. */ - -#ifndef S390_H -#define S390_H - -/* List of instruction sets variations. */ - -enum s390_opcode_mode_val - { - S390_OPCODE_ESA = 0, - S390_OPCODE_ZARCH - }; - -enum s390_opcode_cpu_val - { - S390_OPCODE_G5 = 0, - S390_OPCODE_G6, - S390_OPCODE_Z900, - S390_OPCODE_Z990, - S390_OPCODE_Z9_109, - S390_OPCODE_Z9_EC, - S390_OPCODE_Z10, - S390_OPCODE_Z196, - S390_OPCODE_ZEC12, - S390_OPCODE_MAXCPU - }; - -/* The opcode table is an array of struct s390_opcode. */ - -struct s390_opcode - { - /* The opcode name. */ - const char * name; - - /* The opcode itself. Those bits which will be filled in with - operands are zeroes. */ - unsigned char opcode[6]; - - /* The opcode mask. This is used by the disassembler. This is a - mask containing ones indicating those bits which must match the - opcode field, and zeroes indicating those bits which need not - match (and are presumably filled in by operands). */ - unsigned char mask[6]; - - /* The opcode length in bytes. */ - int oplen; - - /* An array of operand codes. Each code is an index into the - operand table. They appear in the order which the operands must - appear in assembly code, and are terminated by a zero. */ - unsigned char operands[6]; - - /* Bitmask of execution modes this opcode is available for. */ - unsigned int modes; - - /* First cpu this opcode is available for. */ - enum s390_opcode_cpu_val min_cpu; - }; - -/* The table itself is sorted by major opcode number, and is otherwise - in the order in which the disassembler should consider - instructions. */ -extern const struct s390_opcode s390_opcodes[]; -extern const int s390_num_opcodes; - -/* A opcode format table for the .insn pseudo mnemonic. */ -extern const struct s390_opcode s390_opformats[]; -extern const int s390_num_opformats; - -/* Values defined for the flags field of a struct powerpc_opcode. */ - -/* The operands table is an array of struct s390_operand. */ - -struct s390_operand - { - /* The number of bits in the operand. */ - int bits; - - /* How far the operand is left shifted in the instruction. */ - int shift; - - /* One bit syntax flags. */ - unsigned long flags; - }; - -/* Elements in the table are retrieved by indexing with values from - the operands field of the powerpc_opcodes table. */ - -extern const struct s390_operand s390_operands[]; - -/* Values defined for the flags field of a struct s390_operand. */ - -/* This operand names a register. The disassembler uses this to print - register names with a leading 'r'. */ -#define S390_OPERAND_GPR 0x1 - -/* This operand names a floating point register. The disassembler - prints these with a leading 'f'. */ -#define S390_OPERAND_FPR 0x2 - -/* This operand names an access register. The disassembler - prints these with a leading 'a'. */ -#define S390_OPERAND_AR 0x4 - -/* This operand names a control register. The disassembler - prints these with a leading 'c'. */ -#define S390_OPERAND_CR 0x8 - -/* This operand is a displacement. */ -#define S390_OPERAND_DISP 0x10 - -/* This operand names a base register. */ -#define S390_OPERAND_BASE 0x20 - -/* This operand names an index register, it can be skipped. */ -#define S390_OPERAND_INDEX 0x40 - -/* This operand is a relative branch displacement. The disassembler - prints these symbolically if possible. */ -#define S390_OPERAND_PCREL 0x80 - -/* This operand takes signed values. */ -#define S390_OPERAND_SIGNED 0x100 - -/* This operand is a length. */ -#define S390_OPERAND_LENGTH 0x200 - -/* This operand is optional. Only a single operand at the end of - the instruction may be optional. */ -#define S390_OPERAND_OPTIONAL 0x400 - -/* The operand needs to be a valid GP or FP register pair. */ -#define S390_OPERAND_REG_PAIR 0x800 - - #endif /* S390_H */ diff --git a/include/opcode/score-datadep.h b/include/opcode/score-datadep.h deleted file mode 100644 index 10ddf32..0000000 --- a/include/opcode/score-datadep.h +++ /dev/null @@ -1,65 +0,0 @@ -/* score-datadep.h -- Score Instructions data dependency table - Copyright 2006, 2007, 2008, 2009, 2010 Free Software Foundation, Inc. - Contributed by: - Brain.lin (brain.lin@sunplusct.com) - Mei Ligang (ligang@sunnorth.com.cn) - Pei-Lin Tsai (pltsai@sunplus.com) - - This file is part of GAS, the GNU Assembler. - - GAS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3, or (at your option) - any later version. - - GAS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with GAS; see the file COPYING3. If not, write to the Free - Software Foundation, Inc., 51 Franklin Street - Fifth Floor, - Boston, MA 02110-1301, USA. */ - -#ifndef SCORE_DATA_DEPENDENCY_H -#define SCORE_DATA_DEPENDENCY_H - -#define INSN_NAME_LEN 16 - -enum insn_type_for_dependency -{ - D_mtcr, - D_all_insn -}; - -struct insn_to_dependency -{ - char *insn_name; - enum insn_type_for_dependency type; -}; - -struct data_dependency -{ - enum insn_type_for_dependency pre_insn_type; - char pre_reg[6]; - enum insn_type_for_dependency cur_insn_type; - char cur_reg[6]; - int bubblenum_7; - int bubblenum_3; - int warn_or_error; /* warning - 0; error - 1 */ -}; - -static const struct insn_to_dependency insn_to_dependency_table[] = -{ - /* move spectial instruction. */ - {"mtcr", D_mtcr}, -}; - -static const struct data_dependency data_dependency_table[] = -{ - /* Status regiser. */ - {D_mtcr, "cr0", D_all_insn, "", 5, 1, 0}, -}; - -#endif diff --git a/include/opcode/score-inst.h b/include/opcode/score-inst.h deleted file mode 100644 index ecb18da..0000000 --- a/include/opcode/score-inst.h +++ /dev/null @@ -1,236 +0,0 @@ -/* score-inst.h -- Score Instructions Table - Copyright 2006, 2007, 2008, 2009, 2010 Free Software Foundation, Inc. - Contributed by: - Brain.lin (brain.lin@sunplusct.com) - Mei Ligang (ligang@sunnorth.com.cn) - Pei-Lin Tsai (pltsai@sunplus.com) - - This file is part of GAS, the GNU Assembler. - - GAS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3, or (at your option) - any later version. - - GAS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with GAS; see the file COPYING3. If not, write to the Free - Software Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA - 02110-1301, USA. */ - -#ifndef SCORE_INST_H -#define SCORE_INST_H - -#define LDST_UNALIGN_MASK 0x0000007f -#define UA_LCB 0x00000060 -#define UA_LCW 0x00000062 -#define UA_LCE 0x00000066 -#define UA_SCB 0x00000068 -#define UA_SCW 0x0000006a -#define UA_SCE 0x0000006e -#define UA_LL 0x0000000c -#define UA_SC 0x0000000e -#define LDST16_RR_MASK 0x0000000f -#define N16_LW 8 -#define N16_LH 9 -#define N16_POP 10 -#define N16_LBU 11 -#define N16_SW 12 -#define N16_SH 13 -#define N16_PUSH 14 -#define N16_SB 15 -#define LDST16_RI_MASK 0x7007 -#define N16_LWP 0x7000 -#define N16_LHP 0x7001 -#define N16_LBUP 0x7003 -#define N16_SWP 0x7004 -#define N16_SHP 0x7005 -#define N16_SBP 0x7007 -#define N16_LIU 0x5000 - -#define OPC_PSEUDOLDST_MASK 0x00000007 - -enum -{ - INSN_LW = 0, - INSN_LH = 1, - INSN_LHU = 2, - INSN_LB = 3, - INSN_SW = 4, - INSN_SH = 5, - INSN_LBU = 6, - INSN_SB = 7, -}; - -/* Sub opcdoe opcode. */ -enum -{ - INSN16_LBU = 11, - INSN16_LH = 9, - INSN16_LW = 8, - INSN16_SB = 15, - INSN16_SH = 13, - INSN16_SW = 12, -}; - -enum -{ - LDST_NOUPDATE = 0, - LDST_PRE = 1, - LDST_POST = 2, -}; - -enum score_insn_type -{ - Rd_I4, - Rd_I5, - Rd_rvalueBP_I5, - Rd_lvalueBP_I5, - Rd_Rs_I5, - x_Rs_I5, - x_I5_x, - Rd_I8, - Rd_Rs_I14, - I15, - Rd_I16, - Rd_I30, - Rd_I32, - Rd_rvalueRs_SI10, - Rd_lvalueRs_SI10, - Rd_rvalueRs_preSI12, - Rd_rvalueRs_postSI12, - Rd_lvalueRs_preSI12, - Rd_lvalueRs_postSI12, - Rd_Rs_SI14, - Rd_rvalueRs_SI15, - Rd_lvalueRs_SI15, - Rd_SI5, - Rd_SI6, - Rd_SI16, - PC_DISP8div2, - PC_DISP11div2, - PC_DISP19div2, - PC_DISP24div2, - Rd_Rs_Rs, - x_Rs_x, - x_Rs_Rs, - Rd_Rs_x, - Rd_x_Rs, - Rd_x_x, - Rd_Rs, - Rd_HighRs, - Rd_lvalueRs, - Rd_rvalueRs, - Rd_lvalue32Rs, - Rd_rvalue32Rs, - x_Rs, - NO_OPD, - NO16_OPD, - OP5_rvalueRs_SI15, - I5_Rs_Rs_I5_OP5, - x_rvalueRs_post4, - Rd_rvalueRs_post4, - Rd_x_I5, - Rd_lvalueRs_post4, - x_lvalueRs_post4, - Rd_LowRs, - Rd_Rs_Rs_imm, - Insn_Type_PCE, - Insn_Type_SYN, - Insn_GP, - Insn_PIC, - Insn_internal, - Insn_BCMP, - Ra_I9_I5, -}; - -enum score_data_type -{ - _IMM4 = 0, - _IMM5, - _IMM8, - _IMM14, - _IMM15, - _IMM16, - _SIMM10 = 6, - _SIMM12, - _SIMM14, - _SIMM15, - _SIMM16, - _SIMM14_NEG = 11, - _IMM16_NEG, - _SIMM16_NEG, - _IMM20, - _IMM25, - _DISP8div2 = 16, - _DISP11div2, - _DISP19div2, - _DISP24div2, - _VALUE, - _VALUE_HI16, - _VALUE_LO16, - _VALUE_LDST_LO16 = 23, - _SIMM16_LA, - _IMM5_RSHIFT_1, - _IMM5_RSHIFT_2, - _SIMM16_LA_POS, - _IMM5_RANGE_8_31, - _IMM10_RSHIFT_2, - _GP_IMM15 = 30, - _GP_IMM14 = 31, - _SIMM16_pic = 42, /* Index in score_df_range. */ - _IMM16_LO16_pic = 43, - _IMM16_pic = 44, - - _SIMM5 = 45, - _SIMM6 = 46, - _IMM32 = 47, - _SIMM32 = 48, - _IMM11 = 49, - _IMM5_MULTI_LOAD = 50, -}; - -#define REG_TMP 1 - -#define OP_REG_TYPE (1 << 6) -#define OP_IMM_TYPE (1 << 7) -#define OP_SH_REGD (OP_REG_TYPE |20) -#define OP_SH_REGS1 (OP_REG_TYPE |15) -#define OP_SH_REGS2 (OP_REG_TYPE |10) -#define OP_SH_I (OP_IMM_TYPE | 1) -#define OP_SH_RI15 (OP_IMM_TYPE | 0) -#define OP_SH_I12 (OP_IMM_TYPE | 3) -#define OP_SH_DISP24 (OP_IMM_TYPE | 1) -#define OP_SH_DISP19_p1 (OP_IMM_TYPE |15) -#define OP_SH_DISP19_p2 (OP_IMM_TYPE | 1) -#define OP_SH_I5 (OP_IMM_TYPE |10) -#define OP_SH_I10 (OP_IMM_TYPE | 5) -#define OP_SH_COPID (OP_IMM_TYPE | 5) -#define OP_SH_TRAPI5 (OP_IMM_TYPE |15) -#define OP_SH_I15 (OP_IMM_TYPE |10) - -#define OP16_SH_REGD (OP_REG_TYPE | 8) -#define OP16_SH_REGS1 (OP_REG_TYPE | 4) -#define OP16_SH_I45 (OP_IMM_TYPE | 3) -#define OP16_SH_I8 (OP_IMM_TYPE | 0) -#define OP16_SH_DISP8 (OP_IMM_TYPE | 0) -#define OP16_SH_DISP11 (OP_IMM_TYPE | 1) - -enum insn_class -{ - INSN_CLASS_16, - INSN_CLASS_32, - INSN_CLASS_48, - INSN_CLASS_PCE, - INSN_CLASS_SYN -}; - -/* s3_s7: Globals for both tc-score.c and elf32-score.c. */ -extern int score3; -extern int score7; - -#endif diff --git a/include/opcode/sparc.h b/include/opcode/sparc.h deleted file mode 100644 index f05909f..0000000 --- a/include/opcode/sparc.h +++ /dev/null @@ -1,280 +0,0 @@ -/* Definitions for opcode table for the sparc. - Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 2000, 2002, - 2003, 2005, 2010, 2011 Free Software Foundation, Inc. - - This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and - the GNU Binutils. - - GAS/GDB is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3, or (at your option) - any later version. - - GAS/GDB is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with GAS or GDB; see the file COPYING3. If not, write to - the Free Software Foundation, 51 Franklin Street - Fifth Floor, - Boston, MA 02110-1301, USA. */ - -#include "ansidecl.h" - -/* The SPARC opcode table (and other related data) is defined in - the opcodes library in sparc-opc.c. If you change anything here, make - sure you fix up that file, and vice versa. */ - - /* FIXME-someday: perhaps the ,a's and such should be embedded in the - instruction's name rather than the args. This would make gas faster, pinsn - slower, but would mess up some macros a bit. xoxorich. */ - -/* List of instruction sets variations. - These values are such that each element is either a superset of a - preceding each one or they conflict in which case SPARC_OPCODE_CONFLICT_P - returns non-zero. - The values are indices into `sparc_opcode_archs' defined in sparc-opc.c. - Don't change this without updating sparc-opc.c. */ - -enum sparc_opcode_arch_val -{ - SPARC_OPCODE_ARCH_V6 = 0, - SPARC_OPCODE_ARCH_V7, - SPARC_OPCODE_ARCH_V8, - SPARC_OPCODE_ARCH_LEON, - SPARC_OPCODE_ARCH_SPARCLET, - SPARC_OPCODE_ARCH_SPARCLITE, - /* V9 variants must appear last. */ - SPARC_OPCODE_ARCH_V9, - SPARC_OPCODE_ARCH_V9A, /* V9 with ultrasparc additions. */ - SPARC_OPCODE_ARCH_V9B, /* V9 with ultrasparc and cheetah additions. */ - SPARC_OPCODE_ARCH_BAD /* Error return from sparc_opcode_lookup_arch. */ -}; - -/* The highest architecture in the table. */ -#define SPARC_OPCODE_ARCH_MAX (SPARC_OPCODE_ARCH_BAD - 1) - -/* Given an enum sparc_opcode_arch_val, return the bitmask to use in - insn encoding/decoding. */ -#define SPARC_OPCODE_ARCH_MASK(arch) (1 << (arch)) - -/* Given a valid sparc_opcode_arch_val, return non-zero if it's v9. */ -#define SPARC_OPCODE_ARCH_V9_P(arch) ((arch) >= SPARC_OPCODE_ARCH_V9) - -/* Table of cpu variants. */ - -typedef struct sparc_opcode_arch -{ - const char *name; - /* Mask of sparc_opcode_arch_val's supported. - EG: For v7 this would be - (SPARC_OPCODE_ARCH_MASK (..._V6) | SPARC_OPCODE_ARCH_MASK (..._V7)). - These are short's because sparc_opcode.architecture is. */ - short supported; -} sparc_opcode_arch; - -extern const struct sparc_opcode_arch sparc_opcode_archs[]; - -/* Given architecture name, look up it's sparc_opcode_arch_val value. */ -extern enum sparc_opcode_arch_val sparc_opcode_lookup_arch (const char *); - -/* Return the bitmask of supported architectures for ARCH. */ -#define SPARC_OPCODE_SUPPORTED(ARCH) (sparc_opcode_archs[ARCH].supported) - -/* Non-zero if ARCH1 conflicts with ARCH2. - IE: ARCH1 as a supported bit set that ARCH2 doesn't, and vice versa. */ -#define SPARC_OPCODE_CONFLICT_P(ARCH1, ARCH2) \ - (((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \ - != SPARC_OPCODE_SUPPORTED (ARCH1)) \ - && ((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \ - != SPARC_OPCODE_SUPPORTED (ARCH2))) - -/* Structure of an opcode table entry. */ - -typedef struct sparc_opcode -{ - const char *name; - unsigned long match; /* Bits that must be set. */ - unsigned long lose; /* Bits that must not be set. */ - const char *args; - /* This was called "delayed" in versions before the flags. */ - unsigned int flags; - unsigned int hwcaps; - short architecture; /* Bitmask of sparc_opcode_arch_val's. */ -} sparc_opcode; - -/* FIXME: Add F_ANACHRONISTIC flag for v9. */ -#define F_DELAYED 0x00000001 /* Delayed branch. */ -#define F_ALIAS 0x00000002 /* Alias for a "real" instruction. */ -#define F_UNBR 0x00000004 /* Unconditional branch. */ -#define F_CONDBR 0x00000008 /* Conditional branch. */ -#define F_JSR 0x00000010 /* Subroutine call. */ -#define F_FLOAT 0x00000020 /* Floating point instruction (not a branch). */ -#define F_FBR 0x00000040 /* Floating point branch. */ -#define F_PREFERRED 0x00000080 /* A preferred alias. */ - -#define F_PREF_ALIAS (F_ALIAS|F_PREFERRED) - -/* These must match the HWCAP_* values precisely. */ -#define HWCAP_MUL32 0x00000001 /* umul/umulcc/smul/smulcc insns */ -#define HWCAP_DIV32 0x00000002 /* udiv/udivcc/sdiv/sdivcc insns */ -#define HWCAP_FSMULD 0x00000004 /* 'fsmuld' insn */ -#define HWCAP_V8PLUS 0x00000008 /* v9 insns available to 32bit */ -#define HWCAP_POPC 0x00000010 /* 'popc' insn */ -#define HWCAP_VIS 0x00000020 /* VIS insns */ -#define HWCAP_VIS2 0x00000040 /* VIS2 insns */ -#define HWCAP_ASI_BLK_INIT \ - 0x00000080 /* block init ASIs */ -#define HWCAP_FMAF 0x00000100 /* fused multiply-add */ -#define HWCAP_VIS3 0x00000400 /* VIS3 insns */ -#define HWCAP_HPC 0x00000800 /* HPC insns */ -#define HWCAP_RANDOM 0x00001000 /* 'random' insn */ -#define HWCAP_TRANS 0x00002000 /* transaction insns */ -#define HWCAP_FJFMAU 0x00004000 /* unfused multiply-add */ -#define HWCAP_IMA 0x00008000 /* integer multiply-add */ -#define HWCAP_ASI_CACHE_SPARING \ - 0x00010000 /* cache sparing ASIs */ -#define HWCAP_AES 0x00020000 /* AES crypto insns */ -#define HWCAP_DES 0x00040000 /* DES crypto insns */ -#define HWCAP_KASUMI 0x00080000 /* KASUMI crypto insns */ -#define HWCAP_CAMELLIA 0x00100000 /* CAMELLIA crypto insns */ -#define HWCAP_MD5 0x00200000 /* MD5 hashing insns */ -#define HWCAP_SHA1 0x00400000 /* SHA1 hashing insns */ -#define HWCAP_SHA256 0x00800000 /* SHA256 hashing insns */ -#define HWCAP_SHA512 0x01000000 /* SHA512 hashing insns */ -#define HWCAP_MPMUL 0x02000000 /* Multiple Precision Multiply */ -#define HWCAP_MONT 0x04000000 /* Montgomery Mult/Sqrt */ -#define HWCAP_PAUSE 0x08000000 /* Pause insn */ -#define HWCAP_CBCOND 0x10000000 /* Compare and Branch insns */ -#define HWCAP_CRC32C 0x20000000 /* CRC32C insn */ - -/* All sparc opcodes are 32 bits, except for the `set' instruction (really a - macro), which is 64 bits. It is handled as a special case. - - The match component is a mask saying which bits must match a particular - opcode in order for an instruction to be an instance of that opcode. - - The args component is a string containing one character for each operand of the - instruction. - - Kinds of operands: - # Number used by optimizer. It is ignored. - 1 rs1 register. - 2 rs2 register. - d rd register. - e frs1 floating point register. - v frs1 floating point register (double/even). - V frs1 floating point register (quad/multiple of 4). - f frs2 floating point register. - B frs2 floating point register (double/even). - R frs2 floating point register (quad/multiple of 4). - 4 frs3 floating point register. - 5 frs3 floating point register (doube/even). - g frsd floating point register. - H frsd floating point register (double/even). - J frsd floating point register (quad/multiple of 4). - b crs1 coprocessor register - c crs2 coprocessor register - D crsd coprocessor register - m alternate space register (asr) in rd - M alternate space register (asr) in rs1 - h 22 high bits. - X 5 bit unsigned immediate - Y 6 bit unsigned immediate - 3 SIAM mode (3 bits). (v9b) - K MEMBAR mask (7 bits). (v9) - j 10 bit Immediate. (v9) - I 11 bit Immediate. (v9) - i 13 bit Immediate. - n 22 bit immediate. - k 2+14 bit PC relative immediate. (v9) - G 19 bit PC relative immediate. (v9) - l 22 bit PC relative immediate. - L 30 bit PC relative immediate. - a Annul. The annul bit is set. - A Alternate address space. Stored as 8 bits. - C Coprocessor state register. - F floating point state register. - p Processor state register. - N Branch predict clear ",pn" (v9) - T Branch predict set ",pt" (v9) - z %icc. (v9) - Z %xcc. (v9) - q Floating point queue. - r Single register that is both rs1 and rd. - O Single register that is both rs2 and rd. - Q Coprocessor queue. - S Special case. - t Trap base register. - w Window invalid mask register. - y Y register. - u sparclet coprocessor registers in rd position - U sparclet coprocessor registers in rs1 position - E %ccr. (v9) - s %fprs. (v9) - P %pc. (v9) - W %tick. (v9) - o %asi. (v9) - 6 %fcc0. (v9) - 7 %fcc1. (v9) - 8 %fcc2. (v9) - 9 %fcc3. (v9) - ! Privileged Register in rd (v9) - ? Privileged Register in rs1 (v9) - * Prefetch function constant. (v9) - x OPF field (v9 impdep). - 0 32/64 bit immediate for set or setx (v9) insns - _ Ancillary state register in rd (v9a) - / Ancillary state register in rs1 (v9a) - ( entire floating point state register (%efsr) - ) 5 bit immediate placed in RS3 field - = 2+8 bit PC relative immediate. (v9) */ - -#define OP2(x) (((x) & 0x7) << 22) /* Op2 field of format2 insns. */ -#define OP3(x) (((x) & 0x3f) << 19) /* Op3 field of format3 insns. */ -#define OP(x) ((unsigned) ((x) & 0x3) << 30) /* Op field of all insns. */ -#define OPF(x) (((x) & 0x1ff) << 5) /* Opf field of float insns. */ -#define OPF_LOW5(x) OPF ((x) & 0x1f) /* V9. */ -#define OPF_LOW4(x) OPF ((x) & 0xf) /* V9. */ -#define F3F(x, y, z) (OP (x) | OP3 (y) | OPF (z)) /* Format3 float insns. */ -#define F3F4(x, y, z) (OP (x) | OP3 (y) | OPF_LOW4 (z)) -#define F3I(x) (((x) & 0x1) << 13) /* Immediate field of format 3 insns. */ -#define F2(x, y) (OP (x) | OP2(y)) /* Format 2 insns. */ -#define F3(x, y, z) (OP (x) | OP3(y) | F3I(z)) /* Format3 insns. */ -#define F1(x) (OP (x)) -#define DISP30(x) ((x) & 0x3fffffff) -#define ASI(x) (((x) & 0xff) << 5) /* Asi field of format3 insns. */ -#define RS2(x) ((x) & 0x1f) /* Rs2 field. */ -#define SIMM13(x) ((x) & 0x1fff) /* Simm13 field. */ -#define RD(x) (((x) & 0x1f) << 25) /* Destination register field. */ -#define RS1(x) (((x) & 0x1f) << 14) /* Rs1 field. */ -#define RS3(x) (((x) & 0x1f) << 9) /* Rs3 field. */ -#define ASI_RS2(x) (SIMM13 (x)) -#define MEMBAR(x) ((x) & 0x7f) -#define SLCPOP(x) (((x) & 0x7f) << 6) /* Sparclet cpop. */ - -#define ANNUL (1 << 29) -#define BPRED (1 << 19) /* V9. */ -#define IMMED F3I (1) -#define RD_G0 RD (~0) -#define RS1_G0 RS1 (~0) -#define RS2_G0 RS2 (~0) - -extern const struct sparc_opcode sparc_opcodes[]; -extern const int sparc_num_opcodes; - -extern int sparc_encode_asi (const char *); -extern const char *sparc_decode_asi (int); -extern int sparc_encode_membar (const char *); -extern const char *sparc_decode_membar (int); -extern int sparc_encode_prefetch (const char *); -extern const char *sparc_decode_prefetch (int); -extern int sparc_encode_sparclet_cpreg (const char *); -extern const char *sparc_decode_sparclet_cpreg (int); - -/* Local Variables: - fill-column: 131 - comment-column: 0 - End: */ - diff --git a/include/opcode/spu-insns.h b/include/opcode/spu-insns.h deleted file mode 100644 index d6c260a..0000000 --- a/include/opcode/spu-insns.h +++ /dev/null @@ -1,417 +0,0 @@ -/* SPU ELF support for BFD. - - Copyright 2006, 2007, 2010 Free Software Foundation, Inc. - - This file is part of BFD, the Binary File Descriptor library. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software Foundation, - Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ - -/* SPU Opcode Table - --=-=-= FORMAT =-=-=- - - +----+-------+-------+-------+-------+ +------------+-------+-------+-------+ -RRR | op | RC | RB | RA | RT | RI7 | op | I7 | RA | RT | - +----+-------+-------+-------+-------+ +------------+-------+-------+-------+ - 0 3 1 1 2 3 0 1 1 2 3 - 0 7 4 1 0 7 4 1 - - +-----------+--------+-------+-------+ +---------+----------+-------+-------+ -RI8 | op | I8 | RA | RT | RI10 | op | I10 | RA | RT | - +-----------+--------+-------+-------+ +---------+----------+-------+-------+ - 0 9 1 2 3 0 7 1 2 3 - 7 4 1 7 4 1 - - +----------+-----------------+-------+ +--------+-------------------+-------+ -RI16 | op | I16 | RT | RI18 | op | I18 | RT | - +----------+-----------------+-------+ +--------+-------------------+-------+ - 0 8 2 3 0 6 2 3 - 4 1 4 1 - - +------------+-------+-------+-------+ +-------+--+-----------------+-------+ -RR | op | RB | RA | RT | LBT | op |RO| I16 | RO | - +------------+-------+-------+-------+ +-------+--+-----------------+-------+ - 0 1 1 2 3 0 6 8 2 3 - 0 7 4 1 4 1 - - +------------+----+--+-------+-------+ - LBTI | op | // |RO| RA | RO | - +------------+----+--+-------+-------+ - 0 1 1 1 2 3 - 0 5 7 4 1 - --=-=-= OPCODE =-=-=- - -OPCODE field specifies the most significant 11bit of the instruction. Some formats don't have 11bits for opcode field, and in this -case, bit field other than op are defined as 0s. For example, opcode of fma instruction which is RRR format is defined as 0x700, -since 0x700 -> 11'b11100000000, this means opcode is 4'b1110, and other 7bits are defined as 7'b0000000. - --=-=-= ASM_FORMAT =-=-=- - -RRR category RI7 category - ASM_RRR mnemonic RC, RA, RB, RT ASM_RI4 mnemonic RT, RA, I4 - ASM_RI7 mnemonic RT, RA, I7 - -RI8 category RI10 category - ASM_RUI8 mnemonic RT, RA, UI8 ASM_AI10 mnemonic RA, I10 - ASM_RI10 mnemonic RT, RA, R10 - ASM_RI10IDX mnemonic RT, I10(RA) - -RI16 category RI18 category - ASM_I16W mnemonic I16W ASM_RI18 mnemonic RT, I18 - ASM_RI16 mnemonic RT, I16 - ASM_RI16W mnemonic RT, I16W - -RR category LBT category - ASM_MFSPR mnemonic RT, SA ASM_LBT mnemonic brinst, brtarg - ASM_MTSPR mnemonic SA, RT - ASM_NOOP mnemonic LBTI category - ASM_RA mnemonic RA ASM_LBTI mnemonic brinst, RA - ASM_RAB mnemonic RA, RB - ASM_RDCH mnemonic RT, CA - ASM_RR mnemonic RT, RA, RB - ASM_RT mnemonic RT - ASM_RTA mnemonic RT, RA - ASM_WRCH mnemonic CA, RT - -Note that RRR instructions have the names for RC and RT reversed from -what's in the ISA, in order to put RT in the same position it appears -for other formats. - --=-=-= DEPENDENCY =-=-=- - -DEPENDENCY filed consists of 5 digits. This represents which register is used as source and which register is used as target. -The first(most significant) digit is always 0. Then it is followd by RC, RB, RA and RT digits. -If the digit is 0, this means the corresponding register is not used in the instruction. -If the digit is 1, this means the corresponding register is used as a source in the instruction. -If the digit is 2, this means the corresponding register is used as a target in the instruction. -If the digit is 3, this means the corresponding register is used as both source and target in the instruction. -For example, fms instruction has 00113 as the DEPENDENCY field. This means RC is not used in this operation, RB and RA are -used as sources and RT is the target. - --=-=-= PIPE =-=-=- - -This field shows which execution pipe is used for the instruction - -pipe0 execution pipelines: - FP6 SP floating pipeline - FP7 integer operations executed in SP floating pipeline - FPD DP floating pipeline - FX2 FXU pipeline - FX3 Rotate/Shift pipeline - FXB Byte pipeline - NOP No pipeline - -pipe1 execution pipelines: - BR Branch pipeline - LNOP No pipeline - LS Load/Store pipeline - SHUF Shuffle pipeline - SPR SPR/CH pipeline - -*/ - -#define _A0() {0} -#define _A1(a) {1,a} -#define _A2(a,b) {2,a,b} -#define _A3(a,b,c) {3,a,b,c} -#define _A4(a,b,c,d) {4,a,b,c,d} - -/* TAG FORMAT OPCODE MNEMONIC ASM_FORMAT DEPENDENCY PIPE COMMENT */ -/* 0[RC][RB][RA][RT] */ -/* 1:src, 2:target */ - -APUOP(M_BR, RI16, 0x190, "br", _A1(A_R18), 00000, BR) /* BRel IP<-IP+I16 */ -APUOP(M_BRSL, RI16, 0x198, "brsl", _A2(A_T,A_R18), 00002, BR) /* BRelSetLink RT,IP<-IP,IP+I16 */ -APUOP(M_BRA, RI16, 0x180, "bra", _A1(A_S18), 00000, BR) /* BRAbs IP<-I16 */ -APUOP(M_BRASL, RI16, 0x188, "brasl", _A2(A_T,A_S18), 00002, BR) /* BRAbsSetLink RT,IP<-IP,I16 */ -APUOP(M_FSMBI, RI16, 0x194, "fsmbi", _A2(A_T,A_X16), 00002, SHUF) /* FormSelMask%I RT<-fsm(I16) */ -APUOP(M_LQA, RI16, 0x184, "lqa", _A2(A_T,A_S18), 00002, LS) /* LoadQAbs RT<-M[I16] */ -APUOP(M_LQR, RI16, 0x19C, "lqr", _A2(A_T,A_R18), 00002, LS) /* LoadQRel RT<-M[IP+I16] */ -APUOP(M_STOP, RR, 0x000, "stop", _A0(), 00000, BR) /* STOP stop */ -APUOP(M_STOP2, RR, 0x000, "stop", _A1(A_U14), 00000, BR) /* STOP stop */ -APUOP(M_STOPD, RR, 0x140, "stopd", _A3(A_T,A_A,A_B), 00111, BR) /* STOPD stop (with register dependencies) */ -APUOP(M_LNOP, RR, 0x001, "lnop", _A0(), 00000, LNOP) /* LNOP no_operation */ -APUOP(M_SYNC, RR, 0x002, "sync", _A0(), 00000, BR) /* SYNC flush_pipe */ -APUOP(M_DSYNC, RR, 0x003, "dsync", _A0(), 00000, BR) /* DSYNC flush_store_queue */ -APUOP(M_MFSPR, RR, 0x00c, "mfspr", _A2(A_T,A_S), 00002, SPR) /* MFSPR RT<-SA */ -APUOP(M_RDCH, RR, 0x00d, "rdch", _A2(A_T,A_H), 00002, SPR) /* ReaDCHannel RT<-CA:data */ -APUOP(M_RCHCNT, RR, 0x00f, "rchcnt", _A2(A_T,A_H), 00002, SPR) /* ReaDCHanCouNT RT<-CA:count */ -APUOP(M_HBRA, LBT, 0x080, "hbra", _A2(A_S11,A_S18), 00000, LS) /* HBRA BTB[B9]<-M[I16] */ -APUOP(M_HBRR, LBT, 0x090, "hbrr", _A2(A_S11,A_R18), 00000, LS) /* HBRR BTB[B9]<-M[IP+I16] */ -APUOP(M_BRZ, RI16, 0x100, "brz", _A2(A_T,A_R18), 00001, BR) /* BRZ IP<-IP+I16_if(RT) */ -APUOP(M_BRNZ, RI16, 0x108, "brnz", _A2(A_T,A_R18), 00001, BR) /* BRNZ IP<-IP+I16_if(RT) */ -APUOP(M_BRHZ, RI16, 0x110, "brhz", _A2(A_T,A_R18), 00001, BR) /* BRHZ IP<-IP+I16_if(RT) */ -APUOP(M_BRHNZ, RI16, 0x118, "brhnz", _A2(A_T,A_R18), 00001, BR) /* BRHNZ IP<-IP+I16_if(RT) */ -APUOP(M_STQA, RI16, 0x104, "stqa", _A2(A_T,A_S18), 00001, LS) /* SToreQAbs M[I16]<-RT */ -APUOP(M_STQR, RI16, 0x11C, "stqr", _A2(A_T,A_R18), 00001, LS) /* SToreQRel M[IP+I16]<-RT */ -APUOP(M_MTSPR, RR, 0x10c, "mtspr", _A2(A_S,A_T), 00001, SPR) /* MTSPR SA<-RT */ -APUOP(M_WRCH, RR, 0x10d, "wrch", _A2(A_H,A_T), 00001, SPR) /* ChanWRite CA<-RT */ -APUOP(M_LQD, RI10, 0x1a0, "lqd", _A4(A_T,A_S14,A_P,A_A), 00012, LS) /* LoadQDisp RT<-M[Ra+I10] */ -APUOP(M_BI, RR, 0x1a8, "bi", _A1(A_A), 00010, BR) /* BI IP<-RA */ -APUOP(M_BISL, RR, 0x1a9, "bisl", _A2(A_T,A_A), 00012, BR) /* BISL RT,IP<-IP,RA */ -APUOP(M_IRET, RR, 0x1aa, "iret", _A1(A_A), 00010, BR) /* IRET IP<-SRR0 */ -APUOP(M_IRET2, RR, 0x1aa, "iret", _A0(), 00010, BR) /* IRET IP<-SRR0 */ -APUOP(M_BISLED, RR, 0x1ab, "bisled", _A2(A_T,A_A), 00012, BR) /* BISLED RT,IP<-IP,RA_if(ext) */ -APUOP(M_HBR, LBTI, 0x1ac, "hbr", _A2(A_S11I,A_A), 00010, LS) /* HBR BTB[B9]<-M[Ra] */ -APUOP(M_FREST, RR, 0x1b8, "frest", _A2(A_T,A_A), 00012, SHUF) /* FREST RT<-recip(RA) */ -APUOP(M_FRSQEST, RR, 0x1b9, "frsqest", _A2(A_T,A_A), 00012, SHUF) /* FRSQEST RT<-rsqrt(RA) */ -APUOP(M_FSM, RR, 0x1b4, "fsm", _A2(A_T,A_A), 00012, SHUF) /* FormSelMask% RT<-expand(Ra) */ -APUOP(M_FSMH, RR, 0x1b5, "fsmh", _A2(A_T,A_A), 00012, SHUF) /* FormSelMask% RT<-expand(Ra) */ -APUOP(M_FSMB, RR, 0x1b6, "fsmb", _A2(A_T,A_A), 00012, SHUF) /* FormSelMask% RT<-expand(Ra) */ -APUOP(M_GB, RR, 0x1b0, "gb", _A2(A_T,A_A), 00012, SHUF) /* GatherBits% RT<-gather(RA) */ -APUOP(M_GBH, RR, 0x1b1, "gbh", _A2(A_T,A_A), 00012, SHUF) /* GatherBits% RT<-gather(RA) */ -APUOP(M_GBB, RR, 0x1b2, "gbb", _A2(A_T,A_A), 00012, SHUF) /* GatherBits% RT<-gather(RA) */ -APUOP(M_CBD, RI7, 0x1f4, "cbd", _A4(A_T,A_U7,A_P,A_A), 00012, SHUF) /* genCtl%%insD RT<-sta(Ra+I4,siz) */ -APUOP(M_CHD, RI7, 0x1f5, "chd", _A4(A_T,A_U7,A_P,A_A), 00012, SHUF) /* genCtl%%insD RT<-sta(Ra+I4,siz) */ -APUOP(M_CWD, RI7, 0x1f6, "cwd", _A4(A_T,A_U7,A_P,A_A), 00012, SHUF) /* genCtl%%insD RT<-sta(Ra+I4,siz) */ -APUOP(M_CDD, RI7, 0x1f7, "cdd", _A4(A_T,A_U7,A_P,A_A), 00012, SHUF) /* genCtl%%insD RT<-sta(Ra+I4,siz) */ -APUOP(M_ROTQBII, RI7, 0x1f8, "rotqbii", _A3(A_T,A_A,A_U3), 00012, SHUF) /* ROTQBII RT<-RA<<<I7 */ -APUOP(M_ROTQBYI, RI7, 0x1fc, "rotqbyi", _A3(A_T,A_A,A_S7N), 00012, SHUF) /* ROTQBYI RT<-RA<<<(I7*8) */ -APUOP(M_ROTQMBII, RI7, 0x1f9, "rotqmbii", _A3(A_T,A_A,A_S3), 00012, SHUF) /* ROTQMBII RT<-RA<<I7 */ -APUOP(M_ROTQMBYI, RI7, 0x1fd, "rotqmbyi", _A3(A_T,A_A,A_S6), 00012, SHUF) /* ROTQMBYI RT<-RA<<I7 */ -APUOP(M_SHLQBII, RI7, 0x1fb, "shlqbii", _A3(A_T,A_A,A_U3), 00012, SHUF) /* SHLQBII RT<-RA<<I7 */ -APUOP(M_SHLQBYI, RI7, 0x1ff, "shlqbyi", _A3(A_T,A_A,A_U5), 00012, SHUF) /* SHLQBYI RT<-RA<<I7 */ -APUOP(M_STQD, RI10, 0x120, "stqd", _A4(A_T,A_S14,A_P,A_A), 00011, LS) /* SToreQDisp M[Ra+I10]<-RT */ -APUOP(M_BIHNZ, RR, 0x12b, "bihnz", _A2(A_T,A_A), 00011, BR) /* BIHNZ IP<-RA_if(RT) */ -APUOP(M_BIHZ, RR, 0x12a, "bihz", _A2(A_T,A_A), 00011, BR) /* BIHZ IP<-RA_if(RT) */ -APUOP(M_BINZ, RR, 0x129, "binz", _A2(A_T,A_A), 00011, BR) /* BINZ IP<-RA_if(RT) */ -APUOP(M_BIZ, RR, 0x128, "biz", _A2(A_T,A_A), 00011, BR) /* BIZ IP<-RA_if(RT) */ -APUOP(M_CBX, RR, 0x1d4, "cbx", _A3(A_T,A_A,A_B), 00112, SHUF) /* genCtl%%insX RT<-sta(Ra+Rb,siz) */ -APUOP(M_CHX, RR, 0x1d5, "chx", _A3(A_T,A_A,A_B), 00112, SHUF) /* genCtl%%insX RT<-sta(Ra+Rb,siz) */ -APUOP(M_CWX, RR, 0x1d6, "cwx", _A3(A_T,A_A,A_B), 00112, SHUF) /* genCtl%%insX RT<-sta(Ra+Rb,siz) */ -APUOP(M_CDX, RR, 0x1d7, "cdx", _A3(A_T,A_A,A_B), 00112, SHUF) /* genCtl%%insX RT<-sta(Ra+Rb,siz) */ -APUOP(M_LQX, RR, 0x1c4, "lqx", _A3(A_T,A_A,A_B), 00112, LS) /* LoadQindeX RT<-M[Ra+Rb] */ -APUOP(M_ROTQBI, RR, 0x1d8, "rotqbi", _A3(A_T,A_A,A_B), 00112, SHUF) /* ROTQBI RT<-RA<<<Rb */ -APUOP(M_ROTQMBI, RR, 0x1d9, "rotqmbi", _A3(A_T,A_A,A_B), 00112, SHUF) /* ROTQMBI RT<-RA<<Rb */ -APUOP(M_SHLQBI, RR, 0x1db, "shlqbi", _A3(A_T,A_A,A_B), 00112, SHUF) /* SHLQBI RT<-RA<<Rb */ -APUOP(M_ROTQBY, RR, 0x1dc, "rotqby", _A3(A_T,A_A,A_B), 00112, SHUF) /* ROTQBY RT<-RA<<<(Rb*8) */ -APUOP(M_ROTQMBY, RR, 0x1dd, "rotqmby", _A3(A_T,A_A,A_B), 00112, SHUF) /* ROTQMBY RT<-RA<<Rb */ -APUOP(M_SHLQBY, RR, 0x1df, "shlqby", _A3(A_T,A_A,A_B), 00112, SHUF) /* SHLQBY RT<-RA<<Rb */ -APUOP(M_ROTQBYBI, RR, 0x1cc, "rotqbybi", _A3(A_T,A_A,A_B), 00112, SHUF) /* ROTQBYBI RT<-RA<<Rb */ -APUOP(M_ROTQMBYBI, RR, 0x1cd, "rotqmbybi", _A3(A_T,A_A,A_B), 00112, SHUF) /* ROTQMBYBI RT<-RA<<Rb */ -APUOP(M_SHLQBYBI, RR, 0x1cf, "shlqbybi", _A3(A_T,A_A,A_B), 00112, SHUF) /* SHLQBYBI RT<-RA<<Rb */ -APUOP(M_STQX, RR, 0x144, "stqx", _A3(A_T,A_A,A_B), 00111, LS) /* SToreQindeX M[Ra+Rb]<-RT */ -APUOP(M_SHUFB, RRR, 0x580, "shufb", _A4(A_C,A_A,A_B,A_T), 02111, SHUF) /* SHUFfleBytes RC<-f(RA,RB,RT) */ -APUOP(M_IL, RI16, 0x204, "il", _A2(A_T,A_S16), 00002, FX2) /* ImmLoad RT<-sxt(I16) */ -APUOP(M_ILH, RI16, 0x20c, "ilh", _A2(A_T,A_X16), 00002, FX2) /* ImmLoadH RT<-I16 */ -APUOP(M_ILHU, RI16, 0x208, "ilhu", _A2(A_T,A_X16), 00002, FX2) /* ImmLoadHUpper RT<-I16<<16 */ -APUOP(M_ILA, RI18, 0x210, "ila", _A2(A_T,A_U18), 00002, FX2) /* ImmLoadAddr RT<-zxt(I18) */ -APUOP(M_NOP, RR, 0x201, "nop", _A1(A_T), 00000, NOP) /* XNOP no_operation */ -APUOP(M_NOP2, RR, 0x201, "nop", _A0(), 00000, NOP) /* XNOP no_operation */ -APUOP(M_IOHL, RI16, 0x304, "iohl", _A2(A_T,A_X16), 00003, FX2) /* AddImmeXt RT<-RT+sxt(I16) */ -APUOP(M_ANDBI, RI10, 0x0b0, "andbi", _A3(A_T,A_A,A_S10B), 00012, FX2) /* AND%I RT<-RA&I10 */ -APUOP(M_ANDHI, RI10, 0x0a8, "andhi", _A3(A_T,A_A,A_S10), 00012, FX2) /* AND%I RT<-RA&I10 */ -APUOP(M_ANDI, RI10, 0x0a0, "andi", _A3(A_T,A_A,A_S10), 00012, FX2) /* AND%I RT<-RA&I10 */ -APUOP(M_ORBI, RI10, 0x030, "orbi", _A3(A_T,A_A,A_S10B), 00012, FX2) /* OR%I RT<-RA|I10 */ -APUOP(M_ORHI, RI10, 0x028, "orhi", _A3(A_T,A_A,A_S10), 00012, FX2) /* OR%I RT<-RA|I10 */ -APUOP(M_ORI, RI10, 0x020, "ori", _A3(A_T,A_A,A_S10), 00012, FX2) /* OR%I RT<-RA|I10 */ -APUOP(M_ORX, RR, 0x1f0, "orx", _A2(A_T,A_A), 00012, BR) /* ORX RT<-RA.w0|RA.w1|RA.w2|RA.w3 */ -APUOP(M_XORBI, RI10, 0x230, "xorbi", _A3(A_T,A_A,A_S10B), 00012, FX2) /* XOR%I RT<-RA^I10 */ -APUOP(M_XORHI, RI10, 0x228, "xorhi", _A3(A_T,A_A,A_S10), 00012, FX2) /* XOR%I RT<-RA^I10 */ -APUOP(M_XORI, RI10, 0x220, "xori", _A3(A_T,A_A,A_S10), 00012, FX2) /* XOR%I RT<-RA^I10 */ -APUOP(M_AHI, RI10, 0x0e8, "ahi", _A3(A_T,A_A,A_S10), 00012, FX2) /* Add%Immed RT<-RA+I10 */ -APUOP(M_AI, RI10, 0x0e0, "ai", _A3(A_T,A_A,A_S10), 00012, FX2) /* Add%Immed RT<-RA+I10 */ -APUOP(M_SFHI, RI10, 0x068, "sfhi", _A3(A_T,A_A,A_S10), 00012, FX2) /* SubFrom%Imm RT<-I10-RA */ -APUOP(M_SFI, RI10, 0x060, "sfi", _A3(A_T,A_A,A_S10), 00012, FX2) /* SubFrom%Imm RT<-I10-RA */ -APUOP(M_CGTBI, RI10, 0x270, "cgtbi", _A3(A_T,A_A,A_S10B), 00012, FX2) /* CGT%I RT<-(RA>I10) */ -APUOP(M_CGTHI, RI10, 0x268, "cgthi", _A3(A_T,A_A,A_S10), 00012, FX2) /* CGT%I RT<-(RA>I10) */ -APUOP(M_CGTI, RI10, 0x260, "cgti", _A3(A_T,A_A,A_S10), 00012, FX2) /* CGT%I RT<-(RA>I10) */ -APUOP(M_CLGTBI, RI10, 0x2f0, "clgtbi", _A3(A_T,A_A,A_S10B), 00012, FX2) /* CLGT%I RT<-(RA>I10) */ -APUOP(M_CLGTHI, RI10, 0x2e8, "clgthi", _A3(A_T,A_A,A_S10), 00012, FX2) /* CLGT%I RT<-(RA>I10) */ -APUOP(M_CLGTI, RI10, 0x2e0, "clgti", _A3(A_T,A_A,A_S10), 00012, FX2) /* CLGT%I RT<-(RA>I10) */ -APUOP(M_CEQBI, RI10, 0x3f0, "ceqbi", _A3(A_T,A_A,A_S10B), 00012, FX2) /* CEQ%I RT<-(RA=I10) */ -APUOP(M_CEQHI, RI10, 0x3e8, "ceqhi", _A3(A_T,A_A,A_S10), 00012, FX2) /* CEQ%I RT<-(RA=I10) */ -APUOP(M_CEQI, RI10, 0x3e0, "ceqi", _A3(A_T,A_A,A_S10), 00012, FX2) /* CEQ%I RT<-(RA=I10) */ -APUOP(M_HGTI, RI10, 0x278, "hgti", _A3(A_T,A_A,A_S10), 00010, FX2) /* HaltGTI halt_if(RA>I10) */ -APUOP(M_HGTI2, RI10, 0x278, "hgti", _A2(A_A,A_S10), 00010, FX2) /* HaltGTI halt_if(RA>I10) */ -APUOP(M_HLGTI, RI10, 0x2f8, "hlgti", _A3(A_T,A_A,A_S10), 00010, FX2) /* HaltLGTI halt_if(RA>I10) */ -APUOP(M_HLGTI2, RI10, 0x2f8, "hlgti", _A2(A_A,A_S10), 00010, FX2) /* HaltLGTI halt_if(RA>I10) */ -APUOP(M_HEQI, RI10, 0x3f8, "heqi", _A3(A_T,A_A,A_S10), 00010, FX2) /* HaltEQImm halt_if(RA=I10) */ -APUOP(M_HEQI2, RI10, 0x3f8, "heqi", _A2(A_A,A_S10), 00010, FX2) /* HaltEQImm halt_if(RA=I10) */ -APUOP(M_MPYI, RI10, 0x3a0, "mpyi", _A3(A_T,A_A,A_S10), 00012, FP7) /* MPYI RT<-RA*I10 */ -APUOP(M_MPYUI, RI10, 0x3a8, "mpyui", _A3(A_T,A_A,A_S10), 00012, FP7) /* MPYUI RT<-RA*I10 */ -APUOP(M_CFLTS, RI8, 0x3b0, "cflts", _A3(A_T,A_A,A_U7A), 00012, FP7) /* CFLTS RT<-int(RA,I8) */ -APUOP(M_CFLTU, RI8, 0x3b2, "cfltu", _A3(A_T,A_A,A_U7A), 00012, FP7) /* CFLTU RT<-int(RA,I8) */ -APUOP(M_CSFLT, RI8, 0x3b4, "csflt", _A3(A_T,A_A,A_U7B), 00012, FP7) /* CSFLT RT<-flt(RA,I8) */ -APUOP(M_CUFLT, RI8, 0x3b6, "cuflt", _A3(A_T,A_A,A_U7B), 00012, FP7) /* CUFLT RT<-flt(RA,I8) */ -APUOP(M_FESD, RR, 0x3b8, "fesd", _A2(A_T,A_A), 00012, FPD) /* FESD RT<-double(RA) */ -APUOP(M_FRDS, RR, 0x3b9, "frds", _A2(A_T,A_A), 00012, FPD) /* FRDS RT<-single(RA) */ -APUOP(M_FSCRRD, RR, 0x398, "fscrrd", _A1(A_T), 00002, FPD) /* FSCRRD RT<-FP_status */ -APUOP(M_FSCRWR, RR, 0x3ba, "fscrwr", _A2(A_T,A_A), 00010, FP7) /* FSCRWR FP_status<-RA */ -APUOP(M_FSCRWR2, RR, 0x3ba, "fscrwr", _A1(A_A), 00010, FP7) /* FSCRWR FP_status<-RA */ -APUOP(M_CLZ, RR, 0x2a5, "clz", _A2(A_T,A_A), 00012, FX2) /* CLZ RT<-clz(RA) */ -APUOP(M_CNTB, RR, 0x2b4, "cntb", _A2(A_T,A_A), 00012, FXB) /* CNT RT<-pop(RA) */ -APUOP(M_XSBH, RR, 0x2b6, "xsbh", _A2(A_T,A_A), 00012, FX2) /* eXtSignBtoH RT<-sign_ext(RA) */ -APUOP(M_XSHW, RR, 0x2ae, "xshw", _A2(A_T,A_A), 00012, FX2) /* eXtSignHtoW RT<-sign_ext(RA) */ -APUOP(M_XSWD, RR, 0x2a6, "xswd", _A2(A_T,A_A), 00012, FX2) /* eXtSignWtoD RT<-sign_ext(RA) */ -APUOP(M_ROTI, RI7, 0x078, "roti", _A3(A_T,A_A,A_S7N), 00012, FX3) /* ROT%I RT<-RA<<<I7 */ -APUOP(M_ROTMI, RI7, 0x079, "rotmi", _A3(A_T,A_A,A_S7), 00012, FX3) /* ROT%MI RT<-RA<<I7 */ -APUOP(M_ROTMAI, RI7, 0x07a, "rotmai", _A3(A_T,A_A,A_S7), 00012, FX3) /* ROTMA%I RT<-RA<<I7 */ -APUOP(M_SHLI, RI7, 0x07b, "shli", _A3(A_T,A_A,A_U6), 00012, FX3) /* SHL%I RT<-RA<<I7 */ -APUOP(M_ROTHI, RI7, 0x07c, "rothi", _A3(A_T,A_A,A_S7N), 00012, FX3) /* ROT%I RT<-RA<<<I7 */ -APUOP(M_ROTHMI, RI7, 0x07d, "rothmi", _A3(A_T,A_A,A_S6), 00012, FX3) /* ROT%MI RT<-RA<<I7 */ -APUOP(M_ROTMAHI, RI7, 0x07e, "rotmahi", _A3(A_T,A_A,A_S6), 00012, FX3) /* ROTMA%I RT<-RA<<I7 */ -APUOP(M_SHLHI, RI7, 0x07f, "shlhi", _A3(A_T,A_A,A_U5), 00012, FX3) /* SHL%I RT<-RA<<I7 */ -APUOP(M_A, RR, 0x0c0, "a", _A3(A_T,A_A,A_B), 00112, FX2) /* Add% RT<-RA+RB */ -APUOP(M_AH, RR, 0x0c8, "ah", _A3(A_T,A_A,A_B), 00112, FX2) /* Add% RT<-RA+RB */ -APUOP(M_SF, RR, 0x040, "sf", _A3(A_T,A_A,A_B), 00112, FX2) /* SubFrom% RT<-RB-RA */ -APUOP(M_SFH, RR, 0x048, "sfh", _A3(A_T,A_A,A_B), 00112, FX2) /* SubFrom% RT<-RB-RA */ -APUOP(M_CGT, RR, 0x240, "cgt", _A3(A_T,A_A,A_B), 00112, FX2) /* CGT% RT<-(RA>RB) */ -APUOP(M_CGTB, RR, 0x250, "cgtb", _A3(A_T,A_A,A_B), 00112, FX2) /* CGT% RT<-(RA>RB) */ -APUOP(M_CGTH, RR, 0x248, "cgth", _A3(A_T,A_A,A_B), 00112, FX2) /* CGT% RT<-(RA>RB) */ -APUOP(M_CLGT, RR, 0x2c0, "clgt", _A3(A_T,A_A,A_B), 00112, FX2) /* CLGT% RT<-(RA>RB) */ -APUOP(M_CLGTB, RR, 0x2d0, "clgtb", _A3(A_T,A_A,A_B), 00112, FX2) /* CLGT% RT<-(RA>RB) */ -APUOP(M_CLGTH, RR, 0x2c8, "clgth", _A3(A_T,A_A,A_B), 00112, FX2) /* CLGT% RT<-(RA>RB) */ -APUOP(M_CEQ, RR, 0x3c0, "ceq", _A3(A_T,A_A,A_B), 00112, FX2) /* CEQ% RT<-(RA=RB) */ -APUOP(M_CEQB, RR, 0x3d0, "ceqb", _A3(A_T,A_A,A_B), 00112, FX2) /* CEQ% RT<-(RA=RB) */ -APUOP(M_CEQH, RR, 0x3c8, "ceqh", _A3(A_T,A_A,A_B), 00112, FX2) /* CEQ% RT<-(RA=RB) */ -APUOP(M_HGT, RR, 0x258, "hgt", _A3(A_T,A_A,A_B), 00110, FX2) /* HaltGT halt_if(RA>RB) */ -APUOP(M_HGT2, RR, 0x258, "hgt", _A2(A_A,A_B), 00110, FX2) /* HaltGT halt_if(RA>RB) */ -APUOP(M_HLGT, RR, 0x2d8, "hlgt", _A3(A_T,A_A,A_B), 00110, FX2) /* HaltLGT halt_if(RA>RB) */ -APUOP(M_HLGT2, RR, 0x2d8, "hlgt", _A2(A_A,A_B), 00110, FX2) /* HaltLGT halt_if(RA>RB) */ -APUOP(M_HEQ, RR, 0x3d8, "heq", _A3(A_T,A_A,A_B), 00110, FX2) /* HaltEQ halt_if(RA=RB) */ -APUOP(M_HEQ2, RR, 0x3d8, "heq", _A2(A_A,A_B), 00110, FX2) /* HaltEQ halt_if(RA=RB) */ -APUOP(M_FCEQ, RR, 0x3c2, "fceq", _A3(A_T,A_A,A_B), 00112, FX2) /* FCEQ RT<-(RA=RB) */ -APUOP(M_FCMEQ, RR, 0x3ca, "fcmeq", _A3(A_T,A_A,A_B), 00112, FX2) /* FCMEQ RT<-(|RA|=|RB|) */ -APUOP(M_FCGT, RR, 0x2c2, "fcgt", _A3(A_T,A_A,A_B), 00112, FX2) /* FCGT RT<-(RA<RB) */ -APUOP(M_FCMGT, RR, 0x2ca, "fcmgt", _A3(A_T,A_A,A_B), 00112, FX2) /* FCMGT RT<-(|RA|<|RB|) */ -APUOP(M_AND, RR, 0x0c1, "and", _A3(A_T,A_A,A_B), 00112, FX2) /* AND RT<-RA&RB */ -APUOP(M_NAND, RR, 0x0c9, "nand", _A3(A_T,A_A,A_B), 00112, FX2) /* NAND RT<-!(RA&RB) */ -APUOP(M_OR, RR, 0x041, "or", _A3(A_T,A_A,A_B), 00112, FX2) /* OR RT<-RA|RB */ -APUOP(M_NOR, RR, 0x049, "nor", _A3(A_T,A_A,A_B), 00112, FX2) /* NOR RT<-!(RA&RB) */ -APUOP(M_XOR, RR, 0x241, "xor", _A3(A_T,A_A,A_B), 00112, FX2) /* XOR RT<-RA^RB */ -APUOP(M_EQV, RR, 0x249, "eqv", _A3(A_T,A_A,A_B), 00112, FX2) /* EQuiValent RT<-!(RA^RB) */ -APUOP(M_ANDC, RR, 0x2c1, "andc", _A3(A_T,A_A,A_B), 00112, FX2) /* ANDComplement RT<-RA&!RB */ -APUOP(M_ORC, RR, 0x2c9, "orc", _A3(A_T,A_A,A_B), 00112, FX2) /* ORComplement RT<-RA|!RB */ -APUOP(M_ABSDB, RR, 0x053, "absdb", _A3(A_T,A_A,A_B), 00112, FXB) /* ABSoluteDiff RT<-|RA-RB| */ -APUOP(M_AVGB, RR, 0x0d3, "avgb", _A3(A_T,A_A,A_B), 00112, FXB) /* AVG% RT<-(RA+RB+1)/2 */ -APUOP(M_SUMB, RR, 0x253, "sumb", _A3(A_T,A_A,A_B), 00112, FXB) /* SUM% RT<-f(RA,RB) */ -APUOP(M_DFA, RR, 0x2cc, "dfa", _A3(A_T,A_A,A_B), 00112, FPD) /* DFAdd RT<-RA+RB */ -APUOP(M_DFM, RR, 0x2ce, "dfm", _A3(A_T,A_A,A_B), 00112, FPD) /* DFMul RT<-RA*RB */ -APUOP(M_DFS, RR, 0x2cd, "dfs", _A3(A_T,A_A,A_B), 00112, FPD) /* DFSub RT<-RA-RB */ -APUOP(M_FA, RR, 0x2c4, "fa", _A3(A_T,A_A,A_B), 00112, FP6) /* FAdd RT<-RA+RB */ -APUOP(M_FM, RR, 0x2c6, "fm", _A3(A_T,A_A,A_B), 00112, FP6) /* FMul RT<-RA*RB */ -APUOP(M_FS, RR, 0x2c5, "fs", _A3(A_T,A_A,A_B), 00112, FP6) /* FSub RT<-RA-RB */ -APUOP(M_MPY, RR, 0x3c4, "mpy", _A3(A_T,A_A,A_B), 00112, FP7) /* MPY RT<-RA*RB */ -APUOP(M_MPYH, RR, 0x3c5, "mpyh", _A3(A_T,A_A,A_B), 00112, FP7) /* MPYH RT<-(RAh*RB)<<16 */ -APUOP(M_MPYHH, RR, 0x3c6, "mpyhh", _A3(A_T,A_A,A_B), 00112, FP7) /* MPYHH RT<-RAh*RBh */ -APUOP(M_MPYHHU, RR, 0x3ce, "mpyhhu", _A3(A_T,A_A,A_B), 00112, FP7) /* MPYHHU RT<-RAh*RBh */ -APUOP(M_MPYS, RR, 0x3c7, "mpys", _A3(A_T,A_A,A_B), 00112, FP7) /* MPYS RT<-(RA*RB)>>16 */ -APUOP(M_MPYU, RR, 0x3cc, "mpyu", _A3(A_T,A_A,A_B), 00112, FP7) /* MPYU RT<-RA*RB */ -APUOP(M_FI, RR, 0x3d4, "fi", _A3(A_T,A_A,A_B), 00112, FP7) /* FInterpolate RT<-f(RA,RB) */ -APUOP(M_ROT, RR, 0x058, "rot", _A3(A_T,A_A,A_B), 00112, FX3) /* ROT% RT<-RA<<<RB */ -APUOP(M_ROTM, RR, 0x059, "rotm", _A3(A_T,A_A,A_B), 00112, FX3) /* ROT%M RT<-RA<<Rb */ -APUOP(M_ROTMA, RR, 0x05a, "rotma", _A3(A_T,A_A,A_B), 00112, FX3) /* ROTMA% RT<-RA<<Rb */ -APUOP(M_SHL, RR, 0x05b, "shl", _A3(A_T,A_A,A_B), 00112, FX3) /* SHL% RT<-RA<<Rb */ -APUOP(M_ROTH, RR, 0x05c, "roth", _A3(A_T,A_A,A_B), 00112, FX3) /* ROT% RT<-RA<<<RB */ -APUOP(M_ROTHM, RR, 0x05d, "rothm", _A3(A_T,A_A,A_B), 00112, FX3) /* ROT%M RT<-RA<<Rb */ -APUOP(M_ROTMAH, RR, 0x05e, "rotmah", _A3(A_T,A_A,A_B), 00112, FX3) /* ROTMA% RT<-RA<<Rb */ -APUOP(M_SHLH, RR, 0x05f, "shlh", _A3(A_T,A_A,A_B), 00112, FX3) /* SHL% RT<-RA<<Rb */ -APUOP(M_MPYHHA, RR, 0x346, "mpyhha", _A3(A_T,A_A,A_B), 00113, FP7) /* MPYHHA RT<-RAh*RBh+RT */ -APUOP(M_MPYHHAU, RR, 0x34e, "mpyhhau", _A3(A_T,A_A,A_B), 00113, FP7) /* MPYHHAU RT<-RAh*RBh+RT */ -APUOP(M_DFMA, RR, 0x35c, "dfma", _A3(A_T,A_A,A_B), 00113, FPD) /* DFMAdd RT<-RT+RA*RB */ -APUOP(M_DFMS, RR, 0x35d, "dfms", _A3(A_T,A_A,A_B), 00113, FPD) /* DFMSub RT<-RA*RB-RT */ -APUOP(M_DFNMS, RR, 0x35e, "dfnms", _A3(A_T,A_A,A_B), 00113, FPD) /* DFNMSub RT<-RT-RA*RB */ -APUOP(M_DFNMA, RR, 0x35f, "dfnma", _A3(A_T,A_A,A_B), 00113, FPD) /* DFNMAdd RT<-(-RT)-RA*RB */ -APUOP(M_FMA, RRR, 0x700, "fma", _A4(A_C,A_A,A_B,A_T), 02111, FP6) /* FMAdd RC<-RT+RA*RB */ -APUOP(M_FMS, RRR, 0x780, "fms", _A4(A_C,A_A,A_B,A_T), 02111, FP6) /* FMSub RC<-RA*RB-RT */ -APUOP(M_FNMS, RRR, 0x680, "fnms", _A4(A_C,A_A,A_B,A_T), 02111, FP6) /* FNMSub RC<-RT-RA*RB */ -APUOP(M_MPYA, RRR, 0x600, "mpya", _A4(A_C,A_A,A_B,A_T), 02111, FP7) /* MPYA RC<-RA*RB+RT */ -APUOP(M_SELB, RRR, 0x400, "selb", _A4(A_C,A_A,A_B,A_T), 02111, FX2) /* SELectBits RC<-RA&RT|RB&!RT */ -/* for system function call, this uses op-code of mtspr */ -APUOP(M_SYSCALL, RI7, 0x10c, "syscall", _A3(A_T,A_A,A_S7N), 00002, SPR) /* System Call */ -/* -pseudo instruction: -system call -value of I9 operation -0 halt -1 rt[0] = open(MEM[ra[0]], ra[1]) -2 rt[0] = close(ra[0]) -3 rt[0] = read(ra[0], MEM[ra[1]], ra[2]) -4 rt[0] = write(ra[0], MEM[ra[1]], ra[2]) -5 printf(MEM[ra[0]], ra[1], ra[2], ra[3]) -42 rt[0] = clock() -52 rt[0] = lseek(ra0, ra1, ra2) - -*/ - - -/* new multiprecision add/sub */ -APUOP(M_ADDX, RR, 0x340, "addx", _A3(A_T,A_A,A_B), 00113, FX2) /* Add_eXtended RT<-RA+RB+RT */ -APUOP(M_CG, RR, 0x0c2, "cg", _A3(A_T,A_A,A_B), 00112, FX2) /* CarryGenerate RT<-cout(RA+RB) */ -APUOP(M_CGX, RR, 0x342, "cgx", _A3(A_T,A_A,A_B), 00113, FX2) /* CarryGen_eXtd RT<-cout(RA+RB+RT) */ -APUOP(M_SFX, RR, 0x341, "sfx", _A3(A_T,A_A,A_B), 00113, FX2) /* Add_eXtended RT<-RA+RB+RT */ -APUOP(M_BG, RR, 0x042, "bg", _A3(A_T,A_A,A_B), 00112, FX2) /* CarryGenerate RT<-cout(RA+RB) */ -APUOP(M_BGX, RR, 0x343, "bgx", _A3(A_T,A_A,A_B), 00113, FX2) /* CarryGen_eXtd RT<-cout(RA+RB+RT) */ - -/* - -The following ops are a subset of above except with feature bits set. -Feature bits are bits 11-17 of the instruction: - - 11 - C & P feature bit - 12 - disable interrupts - 13 - enable interrupts - -*/ -APUOPFB(M_BID, RR, 0x1a8, 0x20, "bid", _A1(A_A), 00010, BR) /* BI IP<-RA */ -APUOPFB(M_BIE, RR, 0x1a8, 0x10, "bie", _A1(A_A), 00010, BR) /* BI IP<-RA */ -APUOPFB(M_BISLD, RR, 0x1a9, 0x20, "bisld", _A2(A_T,A_A), 00012, BR) /* BISL RT,IP<-IP,RA */ -APUOPFB(M_BISLE, RR, 0x1a9, 0x10, "bisle", _A2(A_T,A_A), 00012, BR) /* BISL RT,IP<-IP,RA */ -APUOPFB(M_IRETD, RR, 0x1aa, 0x20, "iretd", _A1(A_A), 00010, BR) /* IRET IP<-SRR0 */ -APUOPFB(M_IRETD2, RR, 0x1aa, 0x20, "iretd", _A0(), 00010, BR) /* IRET IP<-SRR0 */ -APUOPFB(M_IRETE, RR, 0x1aa, 0x10, "irete", _A1(A_A), 00010, BR) /* IRET IP<-SRR0 */ -APUOPFB(M_IRETE2, RR, 0x1aa, 0x10, "irete", _A0(), 00010, BR) /* IRET IP<-SRR0 */ -APUOPFB(M_BISLEDD, RR, 0x1ab, 0x20, "bisledd", _A2(A_T,A_A), 00012, BR) /* BISLED RT,IP<-IP,RA_if(ext) */ -APUOPFB(M_BISLEDE, RR, 0x1ab, 0x10, "bislede", _A2(A_T,A_A), 00012, BR) /* BISLED RT,IP<-IP,RA_if(ext) */ -APUOPFB(M_BIHNZD, RR, 0x12b, 0x20, "bihnzd", _A2(A_T,A_A), 00011, BR) /* BIHNZ IP<-RA_if(RT) */ -APUOPFB(M_BIHNZE, RR, 0x12b, 0x10, "bihnze", _A2(A_T,A_A), 00011, BR) /* BIHNZ IP<-RA_if(RT) */ -APUOPFB(M_BIHZD, RR, 0x12a, 0x20, "bihzd", _A2(A_T,A_A), 00011, BR) /* BIHZ IP<-RA_if(RT) */ -APUOPFB(M_BIHZE, RR, 0x12a, 0x10, "bihze", _A2(A_T,A_A), 00011, BR) /* BIHZ IP<-RA_if(RT) */ -APUOPFB(M_BINZD, RR, 0x129, 0x20, "binzd", _A2(A_T,A_A), 00011, BR) /* BINZ IP<-RA_if(RT) */ -APUOPFB(M_BINZE, RR, 0x129, 0x10, "binze", _A2(A_T,A_A), 00011, BR) /* BINZ IP<-RA_if(RT) */ -APUOPFB(M_BIZD, RR, 0x128, 0x20, "bizd", _A2(A_T,A_A), 00011, BR) /* BIZ IP<-RA_if(RT) */ -APUOPFB(M_BIZE, RR, 0x128, 0x10, "bize", _A2(A_T,A_A), 00011, BR) /* BIZ IP<-RA_if(RT) */ -APUOPFB(M_SYNCC, RR, 0x002, 0x40, "syncc", _A0(), 00000, BR) /* SYNCC flush_pipe */ -APUOPFB(M_HBRP, LBTI, 0x1ac, 0x40, "hbrp", _A0(), 00010, LS) /* HBR BTB[B9]<-M[Ra] */ - -/* Synonyms required by the AS manual. */ -APUOP(M_LR, RI10, 0x020, "lr", _A2(A_T,A_A), 00012, FX2) /* OR%I RT<-RA|I10 */ -APUOP(M_BIHT, RR, 0x12b, "biht", _A2(A_T,A_A), 00011, BR) /* BIHNZ IP<-RA_if(RT) */ -APUOP(M_BIHF, RR, 0x12a, "bihf", _A2(A_T,A_A), 00011, BR) /* BIHZ IP<-RA_if(RT) */ -APUOP(M_BIT, RR, 0x129, "bit", _A2(A_T,A_A), 00011, BR) /* BINZ IP<-RA_if(RT) */ -APUOP(M_BIF, RR, 0x128, "bif", _A2(A_T,A_A), 00011, BR) /* BIZ IP<-RA_if(RT) */ -APUOPFB(M_BIHTD, RR, 0x12b, 0x20, "bihtd", _A2(A_T,A_A), 00011, BR) /* BIHNF IP<-RA_if(RT) */ -APUOPFB(M_BIHTE, RR, 0x12b, 0x10, "bihte", _A2(A_T,A_A), 00011, BR) /* BIHNF IP<-RA_if(RT) */ -APUOPFB(M_BIHFD, RR, 0x12a, 0x20, "bihfd", _A2(A_T,A_A), 00011, BR) /* BIHZ IP<-RA_if(RT) */ -APUOPFB(M_BIHFE, RR, 0x12a, 0x10, "bihfe", _A2(A_T,A_A), 00011, BR) /* BIHZ IP<-RA_if(RT) */ -APUOPFB(M_BITD, RR, 0x129, 0x20, "bitd", _A2(A_T,A_A), 00011, BR) /* BINF IP<-RA_if(RT) */ -APUOPFB(M_BITE, RR, 0x129, 0x10, "bite", _A2(A_T,A_A), 00011, BR) /* BINF IP<-RA_if(RT) */ -APUOPFB(M_BIFD, RR, 0x128, 0x20, "bifd", _A2(A_T,A_A), 00011, BR) /* BIZ IP<-RA_if(RT) */ -APUOPFB(M_BIFE, RR, 0x128, 0x10, "bife", _A2(A_T,A_A), 00011, BR) /* BIZ IP<-RA_if(RT) */ - -/* New soma double-float insns. */ -APUOP(M_DFCEQ, RR, 0x3c3, "dfceq", _A3(A_T,A_A,A_B), 00112, FX2) /* DFCEQ RT<-(RA=RB) */ -APUOP(M_DFCMEQ, RR, 0x3cb, "dfcmeq", _A3(A_T,A_A,A_B), 00112, FX2) /* DFCMEQ RT<-(|RA|=|RB|) */ -APUOP(M_DFCGT, RR, 0x2c3, "dfcgt", _A3(A_T,A_A,A_B), 00112, FX2) /* DFCGT RT<-(RA>RB) */ -APUOP(M_DFCMGT, RR, 0x2cb, "dfcmgt", _A3(A_T,A_A,A_B), 00112, FX2) /* DFCMGT RT<-(|RA|>|RB|) */ -APUOP(M_DFTSV, RI7, 0x3bf, "dftsv", _A3(A_T,A_A,A_U7), 00012, FX2) /* DFTSV RT<-testspecial(RA,I7) */ - -#undef _A0 -#undef _A1 -#undef _A2 -#undef _A3 -#undef _A4 diff --git a/include/opcode/spu.h b/include/opcode/spu.h deleted file mode 100644 index c646830..0000000 --- a/include/opcode/spu.h +++ /dev/null @@ -1,125 +0,0 @@ -/* SPU ELF support for BFD. - - Copyright 2006, 2010 Free Software Foundation, Inc. - - This file is part of GDB, GAS, and the GNU binutils. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software Foundation, - Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ - -/* These two enums are from rel_apu/common/spu_asm_format.h */ -/* definition of instruction format */ -typedef enum { - RRR, - RI18, - RI16, - RI10, - RI8, - RI7, - RR, - LBT, - LBTI, - IDATA, - UNKNOWN_IFORMAT -} spu_iformat; - -/* These values describe assembly instruction arguments. They indicate - * how to encode, range checking and which relocation to use. */ -typedef enum { - A_T, /* register at pos 0 */ - A_A, /* register at pos 7 */ - A_B, /* register at pos 14 */ - A_C, /* register at pos 21 */ - A_S, /* special purpose register at pos 7 */ - A_H, /* channel register at pos 7 */ - A_P, /* parenthesis, this has to separate regs from immediates */ - A_S3, - A_S6, - A_S7N, - A_S7, - A_U7A, - A_U7B, - A_S10B, - A_S10, - A_S11, - A_S11I, - A_S14, - A_S16, - A_S18, - A_R18, - A_U3, - A_U5, - A_U6, - A_U7, - A_U14, - A_X16, - A_U18, - A_MAX -} spu_aformat; - -enum spu_insns { -#define APUOP(TAG,MACFORMAT,OPCODE,MNEMONIC,ASMFORMAT,DEP,PIPE) \ - TAG, -#define APUOPFB(TAG,MACFORMAT,OPCODE,FB,MNEMONIC,ASMFORMAT,DEP,PIPE) \ - TAG, -#include "opcode/spu-insns.h" -#undef APUOP -#undef APUOPFB - M_SPU_MAX -}; - -struct spu_opcode -{ - spu_iformat insn_type; - unsigned int opcode; - char *mnemonic; - int arg[5]; -}; - -#define SIGNED_EXTRACT(insn,size,pos) (((int)((insn) << (32-size-pos))) >> (32-size)) -#define UNSIGNED_EXTRACT(insn,size,pos) (((insn) >> pos) & ((1 << size)-1)) - -#define DECODE_INSN_RT(insn) (insn & 0x7f) -#define DECODE_INSN_RA(insn) ((insn >> 7) & 0x7f) -#define DECODE_INSN_RB(insn) ((insn >> 14) & 0x7f) -#define DECODE_INSN_RC(insn) ((insn >> 21) & 0x7f) - -#define DECODE_INSN_I10(insn) SIGNED_EXTRACT(insn,10,14) -#define DECODE_INSN_U10(insn) UNSIGNED_EXTRACT(insn,10,14) - -/* For branching, immediate loads, hbr and lqa/stqa. */ -#define DECODE_INSN_I16(insn) SIGNED_EXTRACT(insn,16,7) -#define DECODE_INSN_U16(insn) UNSIGNED_EXTRACT(insn,16,7) - -/* for stop */ -#define DECODE_INSN_U14(insn) UNSIGNED_EXTRACT(insn,14,0) - -/* For ila */ -#define DECODE_INSN_I18(insn) SIGNED_EXTRACT(insn,18,7) -#define DECODE_INSN_U18(insn) UNSIGNED_EXTRACT(insn,18,7) - -/* For rotate and shift and generate control mask */ -#define DECODE_INSN_I7(insn) SIGNED_EXTRACT(insn,7,14) -#define DECODE_INSN_U7(insn) UNSIGNED_EXTRACT(insn,7,14) - -/* For float <-> int conversion */ -#define DECODE_INSN_I8(insn) SIGNED_EXTRACT(insn,8,14) -#define DECODE_INSN_U8(insn) UNSIGNED_EXTRACT(insn,8,14) - -/* For hbr */ -#define DECODE_INSN_I9a(insn) ((SIGNED_EXTRACT(insn,2,23) << 7) | UNSIGNED_EXTRACT(insn,7,0)) -#define DECODE_INSN_I9b(insn) ((SIGNED_EXTRACT(insn,2,14) << 7) | UNSIGNED_EXTRACT(insn,7,0)) -#define DECODE_INSN_U9a(insn) ((UNSIGNED_EXTRACT(insn,2,23) << 7) | UNSIGNED_EXTRACT(insn,7,0)) -#define DECODE_INSN_U9b(insn) ((UNSIGNED_EXTRACT(insn,2,14) << 7) | UNSIGNED_EXTRACT(insn,7,0)) - diff --git a/include/opcode/tahoe.h b/include/opcode/tahoe.h deleted file mode 100644 index 70fcf62..0000000 --- a/include/opcode/tahoe.h +++ /dev/null @@ -1,232 +0,0 @@ -/* - * Ported by the State University of New York at Buffalo by the Distributed - * Computer Systems Lab, Department of Computer Science, 1991. - */ -/* Copyright 2012 Free Software Foundation, Inc. - - This file is part of GDB and BINUTILS. - - GDB and BINUTILS are free software; you can redistribute them and/or - modify them under the terms of the GNU General Public License as - published by the Free Software Foundation; either version 3, or (at - your option) any later version. - - GDB and BINUTILS are distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - General Public License for more details. - - You should have received a copy of the GNU General Public License - along with GDB or BINUTILS; see the file COPYING3. If not, write - to the Free Software Foundation, 51 Franklin Street - Fifth Floor, - Boston, MA 02110-1301, USA. */ - - -#ifndef tahoe_opcodeT -#define tahoe_opcodeT int -#endif /* no tahoe_opcodeT */ - -struct vot_wot /* tahoe opcode table: wot to do with this */ - /* particular opcode */ -{ - char * args; /* how to compile said opcode */ - tahoe_opcodeT code; /* op-code (may be > 8 bits!) */ -}; - -struct vot /* tahoe opcode text */ -{ - char * name; /* opcode name: lowercase string [key] */ - struct vot_wot detail; /* rest of opcode table [datum] */ -}; - -#define vot_how args -#define vot_code code -#define vot_detail detail -#define vot_name name - -static struct vot -votstrs[] = -{ -{ "halt", {"", 0x00 } }, -{ "sinf", {"", 0x05 } }, -{ "ldf", {"rl", 0x06 } }, -{ "ldd", {"rq", 0x07 } }, -{ "addb2", {"rbmb", 0x08 } }, -{ "movb", {"rbwb", 0x09 } }, -{ "addw2", {"rwmw", 0x0a } }, -{ "movw", {"rwww", 0x0b } }, -{ "addl2", {"rlml", 0x0c } }, -{ "movl", {"rlwl", 0x0d } }, -{ "bbs", {"rlvlbw", 0x0e } }, -{ "nop", {"", 0x10 } }, -{ "brb", {"bb", 0x11 } }, -{ "brw", {"bw", 0x13 } }, -{ "cosf", {"", 0x15 } }, -{ "lnf", {"rl", 0x16 } }, -{ "lnd", {"rq", 0x17 } }, -{ "addb3", {"rbrbwb", 0x18 } }, -{ "cmpb", {"rbwb", 0x19 } }, -{ "addw3", {"rwrwww", 0x1a } }, -{ "cmpw", {"rwww", 0x1b } }, -{ "addl3", {"rlrlwl", 0x1c } }, -{ "cmpl", {"rlwl", 0x1d } }, -{ "bbc", {"rlvlbw", 0x1e } }, -{ "rei", {"", 0x20 } }, -{ "bneq", {"bb", 0x21 } }, -{ "bnequ", {"bb", 0x21 } }, -{ "cvtwl", {"rwwl", 0x23 } }, -{ "stf", {"wl", 0x26 } }, -{ "std", {"wq", 0x27 } }, -{ "subb2", {"rbmb", 0x28 } }, -{ "mcomb", {"rbwb", 0x29 } }, -{ "subw2", {"rwmw", 0x2a } }, -{ "mcomw", {"rwww", 0x2b } }, -{ "subl2", {"rlml", 0x2c } }, -{ "mcoml", {"rlwl", 0x2d } }, -{ "emul", {"rlrlrlwq", 0x2e } }, -{ "aoblss", {"rlmlbw", 0x2f } }, -{ "bpt", {"", 0x30 } }, -{ "beql", {"bb", 0x31 } }, -{ "beqlu", {"bb", 0x31 } }, -{ "cvtwb", {"rwwb", 0x33 } }, -{ "logf", {"", 0x35 } }, -{ "cmpf", {"rl", 0x36 } }, -{ "cmpd", {"rq", 0x37 } }, -{ "subb3", {"rbrbwb", 0x38 } }, -{ "bitb", {"rbrb", 0x39 } }, -{ "subw3", {"rwrwww", 0x3a } }, -{ "bitw", {"rwrw", 0x3b } }, -{ "subl3", {"rlrlwl", 0x3c } }, -{ "bitl", {"rlrl", 0x3d } }, -{ "ediv", {"rlrqwlwl", 0x3e } }, -{ "aobleq", {"rlmlbw", 0x3f } }, -{ "ret", {"", 0x40 } }, -{ "bgtr", {"bb", 0x41 } }, -{ "sqrtf", {"", 0x45 } }, -{ "cmpf2", {"rl", 0x46 } }, -{ "cmpd2", {"rqrq", 0x47 } }, -{ "shll", {"rbrlwl", 0x48 } }, -{ "clrb", {"wb", 0x49 } }, -{ "shlq", {"rbrqwq", 0x4a } }, -{ "clrw", {"ww", 0x4b } }, -{ "mull2", {"rlml", 0x4c } }, -{ "clrl", {"wl", 0x4d } }, -{ "shal", {"rbrlwl", 0x4e } }, -{ "bleq", {"bb", 0x51 } }, -{ "expf", {"", 0x55 } }, -{ "tstf", {"", 0x56 } }, -{ "tstd", {"", 0x57 } }, -{ "shrl", {"rbrlwl", 0x58 } }, -{ "tstb", {"rb", 0x59 } }, -{ "shrq", {"rbrqwq", 0x5a } }, -{ "tstw", {"rw", 0x5b } }, -{ "mull3", {"rlrlwl", 0x5c } }, -{ "tstl", {"rl", 0x5d } }, -{ "shar", {"rbrlwl", 0x5e } }, -{ "bbssi", {"rlmlbw", 0x5f } }, -{ "ldpctx", {"", 0x60 } }, -{ "pushd", {"", 0x67 } }, -{ "incb", {"mb", 0x69 } }, -{ "incw", {"mw", 0x6b } }, -{ "divl2", {"rlml", 0x6c } }, -{ "incl", {"ml", 0x6d } }, -{ "cvtlb", {"rlwb", 0x6f } }, -{ "svpctx", {"", 0x70 } }, -{ "jmp", {"ab", 0x71 } }, -{ "cvlf", {"rl", 0x76 } }, -{ "cvld", {"rl", 0x77 } }, -{ "decb", {"mb", 0x79 } }, -{ "decw", {"mw", 0x7b } }, -{ "divl3", {"rlrlwl", 0x7c } }, -{ "decl", {"ml", 0x7d } }, -{ "cvtlw", {"rlww", 0x7f } }, -{ "bgeq", {"bb", 0x81 } }, -{ "movs2", {"abab", 0x82 } }, -{ "cvfl", {"wl", 0x86 } }, -{ "cvdl", {"wl", 0x87 } }, -{ "orb2", {"rbmb", 0x88 } }, -{ "cvtbl", {"rbwl", 0x89 } }, -{ "orw2", {"rwmw", 0x8a } }, -{ "bispsw", {"rw", 0x8b } }, -{ "orl2", {"rlml", 0x8c } }, -{ "adwc", {"rlml", 0x8d } }, -{ "adda", {"rlml", 0x8e } }, -{ "blss", {"bb", 0x91 } }, -{ "cmps2", {"abab", 0x92 } }, -{ "ldfd", {"rl", 0x97 } }, -{ "orb3", {"rbrbwb", 0x98 } }, -{ "cvtbw", {"rbww", 0x99 } }, -{ "orw3", {"rwrwww", 0x9a } }, -{ "bicpsw", {"rw", 0x9b } }, -{ "orl3", {"rlrlwl", 0x9c } }, -{ "sbwc", {"rlml", 0x9d } }, -{ "suba", {"rlml", 0x9e } }, -{ "bgtru", {"bb", 0xa1 } }, -{ "cvdf", {"", 0xa6 } }, -{ "andb2", {"rbmb", 0xa8 } }, -{ "movzbl", {"rbwl", 0xa9 } }, -{ "andw2", {"rwmw", 0xaa } }, -{ "loadr", {"rwal", 0xab } }, -{ "andl2", {"rlml", 0xac } }, -{ "mtpr", {"rlrl", 0xad } }, -{ "ffs", {"rlwl", 0xae } }, -{ "blequ", {"bb", 0xb1 } }, -{ "negf", {"", 0xb6 } }, -{ "negd", {"", 0xb7 } }, -{ "andb3", {"rbrbwb", 0xb8 } }, -{ "movzbw", {"rbww", 0xb9 } }, -{ "andw3", {"rwrwww", 0xba } }, -{ "storer", {"rwal", 0xbb } }, -{ "andl3", {"rlrlwl", 0xbc } }, -{ "mfpr", {"rlwl", 0xbd } }, -{ "ffc", {"rlwl", 0xbe } }, -{ "calls", {"rbab", 0xbf } }, -{ "prober", {"rbabrl", 0xc0 } }, -{ "bvc", {"bb", 0xc1 } }, -{ "movs3", {"ababrw", 0xc2 } }, -{ "movzwl", {"rwwl", 0xc3 } }, -{ "addf", {"rl", 0xc6 } }, -{ "addd", {"rq", 0xc7 } }, -{ "xorb2", {"rbmb", 0xc8 } }, -{ "movob", {"rbwb", 0xc9 } }, -{ "xorw2", {"rwmw", 0xca } }, -{ "movow", {"rwww", 0xcb } }, -{ "xorl2", {"rlml", 0xcc } }, -{ "movpsl", {"wl", 0xcd } }, -{ "kcall", {"rw", 0xcf } }, -{ "probew", {"rbabrl", 0xd0 } }, -{ "bvs", {"bb", 0xd1 } }, -{ "cmps3", {"ababrw", 0xd2 } }, -{ "subf", {"rq", 0xd6 } }, -{ "subd", {"rq", 0xd7 } }, -{ "xorb3", {"rbrbwb", 0xd8 } }, -{ "pushb", {"rb", 0xd9 } }, -{ "xorw3", {"rwrwww", 0xda } }, -{ "pushw", {"rw", 0xdb } }, -{ "xorl3", {"rlrlwl", 0xdc } }, -{ "pushl", {"rl", 0xdd } }, -{ "insque", {"abab", 0xe0 } }, -{ "bcs", {"bb", 0xe1 } }, -{ "bgequ", {"bb", 0xe1 } }, -{ "mulf", {"rq", 0xe6 } }, -{ "muld", {"rq", 0xe7 } }, -{ "mnegb", {"rbwb", 0xe8 } }, -{ "movab", {"abwl", 0xe9 } }, -{ "mnegw", {"rwww", 0xea } }, -{ "movaw", {"awwl", 0xeb } }, -{ "mnegl", {"rlwl", 0xec } }, -{ "moval", {"alwl", 0xed } }, -{ "remque", {"ab", 0xf0 } }, -{ "bcc", {"bb", 0xf1 } }, -{ "blssu", {"bb", 0xf1 } }, -{ "divf", {"rq", 0xf6 } }, -{ "divd", {"rq", 0xf7 } }, -{ "movblk", {"alalrw", 0xf8 } }, -{ "pushab", {"ab", 0xf9 } }, -{ "pushaw", {"aw", 0xfb } }, -{ "casel", {"rlrlrl", 0xfc } }, -{ "pushal", {"al", 0xfd } }, -{ "callf", {"rbab", 0xfe } }, -{ "" , "" } /* empty is end sentinel */ - -}; diff --git a/include/opcode/tic30.h b/include/opcode/tic30.h deleted file mode 100644 index 3f4d307..0000000 --- a/include/opcode/tic30.h +++ /dev/null @@ -1,691 +0,0 @@ -/* tic30.h -- Header file for TI TMS320C30 opcode table - Copyright 1998, 2005, 2009, 2010 Free Software Foundation, Inc. - Contributed by Steven Haworth (steve@pm.cse.rmit.edu.au) - - This file is part of GDB, GAS, and the GNU binutils. - - GDB, GAS, and the GNU binutils are free software; you can redistribute - them and/or modify them under the terms of the GNU General Public - License as published by the Free Software Foundation; either version 3, - or (at your option) any later version. - - GDB, GAS, and the GNU binutils are distributed in the hope that they - will be useful, but WITHOUT ANY WARRANTY; without even the implied - warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See - the GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this file; see the file COPYING3. If not, write to the Free - Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA - 02110-1301, USA. */ - -/* FIXME: The opcode table should be in opcodes/tic30-opc.c, not in a - header file. */ - -#ifndef _TMS320_H_ -#define _TMS320_H_ - -struct _register -{ - char *name; - unsigned char opcode; - unsigned char regtype; -}; - -typedef struct _register reg; - -#define REG_Rn 0x01 -#define REG_ARn 0x02 -#define REG_DP 0x03 -#define REG_OTHER 0x04 - -static const reg tic30_regtab[] = { - { "r0", 0x00, REG_Rn }, - { "r1", 0x01, REG_Rn }, - { "r2", 0x02, REG_Rn }, - { "r3", 0x03, REG_Rn }, - { "r4", 0x04, REG_Rn }, - { "r5", 0x05, REG_Rn }, - { "r6", 0x06, REG_Rn }, - { "r7", 0x07, REG_Rn }, - { "ar0",0x08, REG_ARn }, - { "ar1",0x09, REG_ARn }, - { "ar2",0x0A, REG_ARn }, - { "ar3",0x0B, REG_ARn }, - { "ar4",0x0C, REG_ARn }, - { "ar5",0x0D, REG_ARn }, - { "ar6",0x0E, REG_ARn }, - { "ar7",0x0F, REG_ARn }, - { "dp", 0x10, REG_DP }, - { "ir0",0x11, REG_OTHER }, - { "ir1",0x12, REG_OTHER }, - { "bk", 0x13, REG_OTHER }, - { "sp", 0x14, REG_OTHER }, - { "st", 0x15, REG_OTHER }, - { "ie", 0x16, REG_OTHER }, - { "if", 0x17, REG_OTHER }, - { "iof",0x18, REG_OTHER }, - { "rs", 0x19, REG_OTHER }, - { "re", 0x1A, REG_OTHER }, - { "rc", 0x1B, REG_OTHER }, - { "R0", 0x00, REG_Rn }, - { "R1", 0x01, REG_Rn }, - { "R2", 0x02, REG_Rn }, - { "R3", 0x03, REG_Rn }, - { "R4", 0x04, REG_Rn }, - { "R5", 0x05, REG_Rn }, - { "R6", 0x06, REG_Rn }, - { "R7", 0x07, REG_Rn }, - { "AR0",0x08, REG_ARn }, - { "AR1",0x09, REG_ARn }, - { "AR2",0x0A, REG_ARn }, - { "AR3",0x0B, REG_ARn }, - { "AR4",0x0C, REG_ARn }, - { "AR5",0x0D, REG_ARn }, - { "AR6",0x0E, REG_ARn }, - { "AR7",0x0F, REG_ARn }, - { "DP", 0x10, REG_DP }, - { "IR0",0x11, REG_OTHER }, - { "IR1",0x12, REG_OTHER }, - { "BK", 0x13, REG_OTHER }, - { "SP", 0x14, REG_OTHER }, - { "ST", 0x15, REG_OTHER }, - { "IE", 0x16, REG_OTHER }, - { "IF", 0x17, REG_OTHER }, - { "IOF",0x18, REG_OTHER }, - { "RS", 0x19, REG_OTHER }, - { "RE", 0x1A, REG_OTHER }, - { "RC", 0x1B, REG_OTHER }, - { "", 0, 0 } -}; - -static const reg *const tic30_regtab_end - = tic30_regtab + sizeof(tic30_regtab)/sizeof(tic30_regtab[0]); - -/* Indirect Addressing Modes Modification Fields */ -/* Indirect Addressing with Displacement */ -#define PreDisp_Add 0x00 -#define PreDisp_Sub 0x01 -#define PreDisp_Add_Mod 0x02 -#define PreDisp_Sub_Mod 0x03 -#define PostDisp_Add_Mod 0x04 -#define PostDisp_Sub_Mod 0x05 -#define PostDisp_Add_Circ 0x06 -#define PostDisp_Sub_Circ 0x07 -/* Indirect Addressing with Index Register IR0 */ -#define PreIR0_Add 0x08 -#define PreIR0_Sub 0x09 -#define PreIR0_Add_Mod 0x0A -#define PreIR0_Sub_Mod 0x0B -#define PostIR0_Add_Mod 0x0C -#define PostIR0_Sub_Mod 0x0D -#define PostIR0_Add_Circ 0x0E -#define PostIR0_Sub_Circ 0x0F -/* Indirect Addressing with Index Register IR1 */ -#define PreIR1_Add 0x10 -#define PreIR1_Sub 0x11 -#define PreIR1_Add_Mod 0x12 -#define PreIR1_Sub_Mod 0x13 -#define PostIR1_Add_Mod 0x14 -#define PostIR1_Sub_Mod 0x15 -#define PostIR1_Add_Circ 0x16 -#define PostIR1_Sub_Circ 0x17 -/* Indirect Addressing (Special Cases) */ -#define IndirectOnly 0x18 -#define PostIR0_Add_BitRev 0x19 - -typedef struct { - char *syntax; - unsigned char modfield; - unsigned char displacement; -} ind_addr_type; - -#define IMPLIED_DISP 0x01 -#define DISP_REQUIRED 0x02 -#define NO_DISP 0x03 - -static const ind_addr_type tic30_indaddr_tab[] = { - { "*+ar", PreDisp_Add, IMPLIED_DISP }, - { "*-ar", PreDisp_Sub, IMPLIED_DISP }, - { "*++ar", PreDisp_Add_Mod, IMPLIED_DISP }, - { "*--ar", PreDisp_Sub_Mod, IMPLIED_DISP }, - { "*ar++", PostDisp_Add_Mod, IMPLIED_DISP }, - { "*ar--", PostDisp_Sub_Mod, IMPLIED_DISP }, - { "*ar++%", PostDisp_Add_Circ, IMPLIED_DISP }, - { "*ar--%", PostDisp_Sub_Circ, IMPLIED_DISP }, - { "*+ar()", PreDisp_Add, DISP_REQUIRED }, - { "*-ar()", PreDisp_Sub, DISP_REQUIRED }, - { "*++ar()", PreDisp_Add_Mod, DISP_REQUIRED }, - { "*--ar()", PreDisp_Sub_Mod, DISP_REQUIRED }, - { "*ar++()", PostDisp_Add_Mod, DISP_REQUIRED }, - { "*ar--()", PostDisp_Sub_Mod, DISP_REQUIRED }, - { "*ar++()%", PostDisp_Add_Circ, DISP_REQUIRED }, - { "*ar--()%", PostDisp_Sub_Circ, DISP_REQUIRED }, - { "*+ar(ir0)", PreIR0_Add, NO_DISP }, - { "*-ar(ir0)", PreIR0_Sub, NO_DISP }, - { "*++ar(ir0)", PreIR0_Add_Mod, NO_DISP }, - { "*--ar(ir0)", PreIR0_Sub_Mod, NO_DISP }, - { "*ar++(ir0)", PostIR0_Add_Mod, NO_DISP }, - { "*ar--(ir0)", PostIR0_Sub_Mod, NO_DISP }, - { "*ar++(ir0)%",PostIR0_Add_Circ, NO_DISP }, - { "*ar--(ir0)%",PostIR0_Sub_Circ, NO_DISP }, - { "*+ar(ir1)", PreIR1_Add, NO_DISP }, - { "*-ar(ir1)", PreIR1_Sub, NO_DISP }, - { "*++ar(ir1)", PreIR1_Add_Mod, NO_DISP }, - { "*--ar(ir1)", PreIR1_Sub_Mod, NO_DISP }, - { "*ar++(ir1)", PostIR1_Add_Mod, NO_DISP }, - { "*ar--(ir1)", PostIR1_Sub_Mod, NO_DISP }, - { "*ar++(ir1)%",PostIR1_Add_Circ, NO_DISP }, - { "*ar--(ir1)%",PostIR1_Sub_Circ, NO_DISP }, - { "*ar", IndirectOnly, NO_DISP }, - { "*ar++(ir0)b",PostIR0_Add_BitRev, NO_DISP }, - { "", 0,0 } -}; - -static const ind_addr_type *const tic30_indaddrtab_end - = tic30_indaddr_tab + sizeof(tic30_indaddr_tab)/sizeof(tic30_indaddr_tab[0]); - -/* Possible operand types */ -/* Register types */ -#define Rn 0x0001 -#define ARn 0x0002 -#define DPReg 0x0004 -#define OtherReg 0x0008 -/* Addressing mode types */ -#define Direct 0x0010 -#define Indirect 0x0020 -#define Imm16 0x0040 -#define Disp 0x0080 -#define Imm24 0x0100 -#define Abs24 0x0200 -/* 3 operand addressing mode types */ -#define op3T1 0x0400 -#define op3T2 0x0800 -/* Interrupt vector */ -#define IVector 0x1000 -/* Not required */ -#define NotReq 0x2000 - -#define GAddr1 Rn | Direct | Indirect | Imm16 -#define GAddr2 GAddr1 | AllReg -#define TAddr1 op3T1 | Rn | Indirect -#define TAddr2 op3T2 | Rn | Indirect -#define Reg Rn | ARn -#define AllReg Reg | DPReg | OtherReg - -typedef struct _template -{ - char *name; - unsigned int operands; /* how many operands */ - unsigned int base_opcode; /* base_opcode is the fundamental opcode byte */ - /* the bits in opcode_modifier are used to generate the final opcode from - the base_opcode. These bits also are used to detect alternate forms of - the same instruction */ - unsigned int opcode_modifier; - - /* opcode_modifier bits: */ -#define AddressMode 0x00600000 -#define PCRel 0x02000000 -#define StackOp 0x001F0000 -#define Rotate StackOp - - /* operand_types[i] describes the type of operand i. This is made - by OR'ing together all of the possible type masks. (e.g. - 'operand_types[i] = Reg|Imm' specifies that operand i can be - either a register or an immediate operand */ - unsigned int operand_types[3]; - /* This defines the number type of an immediate argument to an instruction. */ - int imm_arg_type; -#define Imm_None 0 -#define Imm_Float 1 -#define Imm_SInt 2 -#define Imm_UInt 3 -} -insn_template; - -static const insn_template tic30_optab[] = { - { "absf" ,2,0x00000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "absi" ,2,0x00800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "addc" ,2,0x01000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "addc3" ,3,0x20000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, - { "addf" ,2,0x01800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "addf3" ,3,0x20800000,AddressMode, { TAddr1, TAddr2, Rn }, Imm_None }, - { "addi" ,2,0x02000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "addi3" ,3,0x21000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, - { "and" ,2,0x02800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt }, - { "and3" ,3,0x21800000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, - { "andn" ,2,0x03000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt }, - { "andn3" ,3,0x22000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, - { "ash" ,2,0x03800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ash3" ,3,0x22800000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, - { "b" ,1,0x68000000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bu" ,1,0x68000000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "blo" ,1,0x68010000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bls" ,1,0x68020000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bhi" ,1,0x68030000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bhs" ,1,0x68040000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "beq" ,1,0x68050000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bne" ,1,0x68060000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "blt" ,1,0x68070000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "ble" ,1,0x68080000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bgt" ,1,0x68090000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bge" ,1,0x680A0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bz" ,1,0x68050000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bnz" ,1,0x68060000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bp" ,1,0x68090000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bn" ,1,0x68070000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bnn" ,1,0x680A0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bnv" ,1,0x680C0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bv" ,1,0x680D0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bnuf" ,1,0x680E0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "buf" ,1,0x680F0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bnc" ,1,0x68040000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bc" ,1,0x68010000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bnlv" ,1,0x68100000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "blv" ,1,0x68110000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bnluf" ,1,0x68120000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bluf" ,1,0x68130000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bzuf" ,1,0x68140000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bd" ,1,0x68200000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bud" ,1,0x68200000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "blod" ,1,0x68210000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "blsd" ,1,0x68220000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bhid" ,1,0x68230000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bhsd" ,1,0x68240000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "beqd" ,1,0x68250000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bned" ,1,0x68260000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bltd" ,1,0x68270000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bled" ,1,0x68280000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bgtd" ,1,0x68290000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bged" ,1,0x682A0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bzd" ,1,0x68250000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bnzd" ,1,0x68260000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bpd" ,1,0x68290000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bnd" ,1,0x68270000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bnnd" ,1,0x682A0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bnvd" ,1,0x682C0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bvd" ,1,0x682D0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bnufd" ,1,0x682E0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bufd" ,1,0x682F0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bncd" ,1,0x68240000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bcd" ,1,0x68210000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bnlvd" ,1,0x68300000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "blvd" ,1,0x68310000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bnlufd" ,1,0x68320000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "blufd" ,1,0x68330000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bzufd" ,1,0x68340000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "br" ,1,0x60000000,0, { Imm24, 0, 0 }, Imm_UInt }, - { "brd" ,1,0x61000000,0, { Imm24, 0, 0 }, Imm_UInt }, - { "call" ,1,0x62000000,0, { Imm24, 0, 0 }, Imm_UInt }, - { "callu" ,1,0x70000000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "calllo" ,1,0x70010000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "callls" ,1,0x70020000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "callhi" ,1,0x70030000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "callhs" ,1,0x70040000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "calleq" ,1,0x70050000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "callne" ,1,0x70060000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "calllt" ,1,0x70070000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "callle" ,1,0x70080000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "callgt" ,1,0x70090000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "callge" ,1,0x700A0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "callz" ,1,0x70050000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "callnz" ,1,0x70060000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "callp" ,1,0x70090000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "calln" ,1,0x70070000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "callnn" ,1,0x700A0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "callnv" ,1,0x700C0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "callv" ,1,0x700D0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "callnuf",1,0x700E0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "calluf" ,1,0x700F0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "callnc" ,1,0x70040000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "callc" ,1,0x70010000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "callnlv",1,0x70100000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "calllv" ,1,0x70110000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "callnluf",1,0x70120000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "callluf",1,0x70130000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "callzuf",1,0x70140000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "cmpf" ,2,0x04000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "cmpf3" ,2,0x23000000,AddressMode, { TAddr1, TAddr2, 0 }, Imm_None }, - { "cmpi" ,2,0x04800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "cmpi3" ,2,0x23800000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, 0 }, Imm_None }, - { "db" ,2,0x6C000000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbu" ,2,0x6C000000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dblo" ,2,0x6C010000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbls" ,2,0x6C020000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbhi" ,2,0x6C030000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbhs" ,2,0x6C040000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbeq" ,2,0x6C050000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbne" ,2,0x6C060000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dblt" ,2,0x6C070000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dble" ,2,0x6C080000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbgt" ,2,0x6C090000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbge" ,2,0x6C0A0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbz" ,2,0x6C050000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbnz" ,2,0x6C060000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbp" ,2,0x6C090000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbn" ,2,0x6C070000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbnn" ,2,0x6C0A0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbnv" ,2,0x6C0C0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbv" ,2,0x6C0D0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbnuf" ,2,0x6C0E0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbuf" ,2,0x6C0F0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbnc" ,2,0x6C040000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbc" ,2,0x6C010000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbnlv" ,2,0x6C100000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dblv" ,2,0x6C110000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbnluf" ,2,0x6C120000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbluf" ,2,0x6C130000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbzuf" ,2,0x6C140000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbd" ,2,0x6C200000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbud" ,2,0x6C200000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dblod" ,2,0x6C210000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dblsd" ,2,0x6C220000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbhid" ,2,0x6C230000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbhsd" ,2,0x6C240000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbeqd" ,2,0x6C250000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbned" ,2,0x6C260000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbltd" ,2,0x6C270000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbled" ,2,0x6C280000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbgtd" ,2,0x6C290000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbged" ,2,0x6C2A0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbzd" ,2,0x6C250000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbnzd" ,2,0x6C260000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbpd" ,2,0x6C290000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbnd" ,2,0x6C270000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbnnd" ,2,0x6C2A0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbnvd" ,2,0x6C2C0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbvd" ,2,0x6C2D0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbnufd" ,2,0x6C2E0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbufd" ,2,0x6C2F0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbncd" ,2,0x6C240000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbcd" ,2,0x6C210000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbnlvd" ,2,0x6C300000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dblvd" ,2,0x6C310000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbnlufd",2,0x6C320000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dblufd" ,2,0x6C330000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbzufd" ,2,0x6C340000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "fix" ,2,0x05000000,AddressMode, { GAddr1, AllReg, 0 }, Imm_Float }, - { "float" ,2,0x05800000,AddressMode, { GAddr2, Rn, 0 }, Imm_SInt }, - { "iack" ,1,0x1B000000,AddressMode, { Direct|Indirect, 0, 0 }, Imm_None }, - { "idle" ,0,0x06000000,0, { 0, 0, 0 }, Imm_None }, - { "idle2" ,0,0x06000001,0, { 0, 0, 0 }, Imm_None }, /* LC31 Only */ - { "lde" ,2,0x06800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldf" ,2,0x07000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfu" ,2,0x40000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldflo" ,2,0x40800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfls" ,2,0x41000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfhi" ,2,0x41800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfhs" ,2,0x42000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfeq" ,2,0x42800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfne" ,2,0x43000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldflt" ,2,0x43800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfle" ,2,0x44000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfgt" ,2,0x44800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfge" ,2,0x45000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfz" ,2,0x42800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfnz" ,2,0x43000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfp" ,2,0x44800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfn" ,2,0x43800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfnn" ,2,0x45000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfnv" ,2,0x46000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfv" ,2,0x46800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfnuf" ,2,0x47000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfuf" ,2,0x47800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfnc" ,2,0x42000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfc" ,2,0x40800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfnlv" ,2,0x48000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldflv" ,2,0x48800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfnluf",2,0x49000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfluf" ,2,0x49800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfzuf" ,2,0x4A000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfi" ,2,0x07800000,AddressMode, { Direct|Indirect, Rn, 0 }, Imm_None }, - { "ldi" ,2,0x08000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldiu" ,2,0x50000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldilo" ,2,0x50800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldils" ,2,0x51000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldihi" ,2,0x51800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldihs" ,2,0x52000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldieq" ,2,0x52800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldine" ,2,0x53000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldilt" ,2,0x53800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldile" ,2,0x54000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldigt" ,2,0x54800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldige" ,2,0x55000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldiz" ,2,0x52800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldinz" ,2,0x53000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldip" ,2,0x54800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldin" ,2,0x53800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldinn" ,2,0x55000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldinv" ,2,0x56000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldiv" ,2,0x56800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldinuf" ,2,0x57000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldiuf" ,2,0x57800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldinc" ,2,0x52000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldic" ,2,0x50800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldinlv" ,2,0x58000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldilv" ,2,0x58800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldinluf",2,0x59000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldiluf" ,2,0x59800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldizuf" ,2,0x5A000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldii" ,2,0x08800000,AddressMode, { Direct|Indirect, AllReg, 0 }, Imm_None }, - { "ldm" ,2,0x09000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldp" ,2,0x08700000,0, { Abs24|Direct, DPReg|NotReq, 0 }, Imm_UInt }, - { "lopower",0,0x10800001,0, { 0, 0, 0 }, Imm_None }, /* LC31 Only */ - { "lsh" ,2,0x09800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt }, - { "lsh3" ,3,0x24000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, - { "maxspeed",0,0x10800000,0, { 0, 0, 0 }, Imm_None }, /* LC31 Only */ - { "mpyf" ,2,0x0A000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "mpyf3" ,3,0x24800000,AddressMode, { TAddr1, TAddr2, Rn }, Imm_None }, - { "mpyi" ,2,0x0A800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "mpyi3" ,3,0x25000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, - { "negb" ,2,0x0B000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "negf" ,2,0x0B800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "negi" ,2,0x0C000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "nop" ,1,0x0C800000,AddressMode, { AllReg|Indirect|NotReq, 0, 0 }, Imm_None }, - { "norm" ,2,0x0D000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, /*Check another source*/ - { "not" ,2,0x0D800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt }, - { "or" ,2,0x10000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt }, - { "or3" ,3,0x25800000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, - { "pop" ,1,0x0E200000,StackOp, { AllReg, 0, 0 }, Imm_None }, - { "popf" ,1,0x0EA00000,StackOp, { Rn, 0, 0 }, Imm_None }, - { "push" ,1,0x0F200000,StackOp, { AllReg, 0, 0 }, Imm_None }, - { "pushf" ,1,0x0FA00000,StackOp, { Rn, 0, 0 }, Imm_None }, - { "reti" ,0,0x78000000,0, { 0, 0, 0 }, Imm_None }, - { "retiu" ,0,0x78000000,0, { 0, 0, 0 }, Imm_None }, - { "retilo" ,0,0x78010000,0, { 0, 0, 0 }, Imm_None }, - { "retils" ,0,0x78020000,0, { 0, 0, 0 }, Imm_None }, - { "retihi" ,0,0x78030000,0, { 0, 0, 0 }, Imm_None }, - { "retihs" ,0,0x78040000,0, { 0, 0, 0 }, Imm_None }, - { "retieq" ,0,0x78050000,0, { 0, 0, 0 }, Imm_None }, - { "retine" ,0,0x78060000,0, { 0, 0, 0 }, Imm_None }, - { "retilt" ,0,0x78070000,0, { 0, 0, 0 }, Imm_None }, - { "retile" ,0,0x78080000,0, { 0, 0, 0 }, Imm_None }, - { "retigt" ,0,0x78090000,0, { 0, 0, 0 }, Imm_None }, - { "retige" ,0,0x780A0000,0, { 0, 0, 0 }, Imm_None }, - { "retiz" ,0,0x78050000,0, { 0, 0, 0 }, Imm_None }, - { "retinz" ,0,0x78060000,0, { 0, 0, 0 }, Imm_None }, - { "retip" ,0,0x78090000,0, { 0, 0, 0 }, Imm_None }, - { "retin" ,0,0x78070000,0, { 0, 0, 0 }, Imm_None }, - { "retinn" ,0,0x780A0000,0, { 0, 0, 0 }, Imm_None }, - { "retinv" ,0,0x780C0000,0, { 0, 0, 0 }, Imm_None }, - { "retiv" ,0,0x780D0000,0, { 0, 0, 0 }, Imm_None }, - { "retinuf",0,0x780E0000,0, { 0, 0, 0 }, Imm_None }, - { "retiuf" ,0,0x780F0000,0, { 0, 0, 0 }, Imm_None }, - { "retinc" ,0,0x78040000,0, { 0, 0, 0 }, Imm_None }, - { "retic" ,0,0x78010000,0, { 0, 0, 0 }, Imm_None }, - { "retinlv",0,0x78100000,0, { 0, 0, 0 }, Imm_None }, - { "retilv" ,0,0x78110000,0, { 0, 0, 0 }, Imm_None }, - { "retinluf",0,0x78120000,0, { 0, 0, 0 }, Imm_None }, - { "retiluf",0,0x78130000,0, { 0, 0, 0 }, Imm_None }, - { "retizuf",0,0x78140000,0, { 0, 0, 0 }, Imm_None }, - { "rets" ,0,0x78800000,0, { 0, 0, 0 }, Imm_None }, - { "retsu" ,0,0x78800000,0, { 0, 0, 0 }, Imm_None }, - { "retslo" ,0,0x78810000,0, { 0, 0, 0 }, Imm_None }, - { "retsls" ,0,0x78820000,0, { 0, 0, 0 }, Imm_None }, - { "retshi" ,0,0x78830000,0, { 0, 0, 0 }, Imm_None }, - { "retshs" ,0,0x78840000,0, { 0, 0, 0 }, Imm_None }, - { "retseq" ,0,0x78850000,0, { 0, 0, 0 }, Imm_None }, - { "retsne" ,0,0x78860000,0, { 0, 0, 0 }, Imm_None }, - { "retslt" ,0,0x78870000,0, { 0, 0, 0 }, Imm_None }, - { "retsle" ,0,0x78880000,0, { 0, 0, 0 }, Imm_None }, - { "retsgt" ,0,0x78890000,0, { 0, 0, 0 }, Imm_None }, - { "retsge" ,0,0x788A0000,0, { 0, 0, 0 }, Imm_None }, - { "retsz" ,0,0x78850000,0, { 0, 0, 0 }, Imm_None }, - { "retsnz" ,0,0x78860000,0, { 0, 0, 0 }, Imm_None }, - { "retsp" ,0,0x78890000,0, { 0, 0, 0 }, Imm_None }, - { "retsn" ,0,0x78870000,0, { 0, 0, 0 }, Imm_None }, - { "retsnn" ,0,0x788A0000,0, { 0, 0, 0 }, Imm_None }, - { "retsnv" ,0,0x788C0000,0, { 0, 0, 0 }, Imm_None }, - { "retsv" ,0,0x788D0000,0, { 0, 0, 0 }, Imm_None }, - { "retsnuf",0,0x788E0000,0, { 0, 0, 0 }, Imm_None }, - { "retsuf" ,0,0x788F0000,0, { 0, 0, 0 }, Imm_None }, - { "retsnc" ,0,0x78840000,0, { 0, 0, 0 }, Imm_None }, - { "retsc" ,0,0x78810000,0, { 0, 0, 0 }, Imm_None }, - { "retsnlv",0,0x78900000,0, { 0, 0, 0 }, Imm_None }, - { "retslv" ,0,0x78910000,0, { 0, 0, 0 }, Imm_None }, - { "retsnluf",0,0x78920000,0, { 0, 0, 0 }, Imm_None }, - { "retsluf",0,0x78930000,0, { 0, 0, 0 }, Imm_None }, - { "retszuf",0,0x78940000,0, { 0, 0, 0 }, Imm_None }, - { "rnd" ,2,0x11000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "rol" ,1,0x11E00001,Rotate, { AllReg, 0, 0 }, Imm_None }, - { "rolc" ,1,0x12600001,Rotate, { AllReg, 0, 0 }, Imm_None }, - { "ror" ,1,0x12E0FFFF,Rotate, { AllReg, 0, 0 }, Imm_None }, - { "rorc" ,1,0x1360FFFF,Rotate, { AllReg, 0, 0 }, Imm_None }, - { "rptb" ,1,0x64000000,0, { Imm24, 0, 0 }, Imm_UInt }, - { "rpts" ,1,0x139B0000,AddressMode, { GAddr2, 0, 0 }, Imm_UInt }, - { "sigi" ,0,0x16000000,0, { 0, 0, 0 }, Imm_None }, - { "stf" ,2,0x14000000,AddressMode, { Rn, Direct|Indirect, 0 }, Imm_Float }, - { "stfi" ,2,0x14800000,AddressMode, { Rn, Direct|Indirect, 0 }, Imm_Float }, - { "sti" ,2,0x15000000,AddressMode, { AllReg, Direct|Indirect, 0 }, Imm_SInt }, - { "stii" ,2,0x15800000,AddressMode, { AllReg, Direct|Indirect, 0 }, Imm_SInt }, - { "subb" ,2,0x16800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "subb3" ,3,0x26000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, - { "subc" ,2,0x17000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt }, - { "subf" ,2,0x17800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "subf3" ,3,0x26800000,AddressMode, { TAddr1, TAddr2, Rn }, Imm_None }, - { "subi" ,2,0x18000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "subi3" ,3,0x27000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, - { "subrb" ,2,0x18800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "subrf" ,2,0x19000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "subri" ,2,0x19800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "swi" ,0,0x66000000,0, { 0, 0, 0 }, Imm_None }, - { "trap" ,1,0x74800020,0, { IVector, 0, 0 }, Imm_None }, - { "trapu" ,1,0x74800020,0, { IVector, 0, 0 }, Imm_None }, - { "traplo" ,1,0x74810020,0, { IVector, 0, 0 }, Imm_None }, - { "trapls" ,1,0x74820020,0, { IVector, 0, 0 }, Imm_None }, - { "traphi" ,1,0x74830020,0, { IVector, 0, 0 }, Imm_None }, - { "traphs" ,1,0x74840020,0, { IVector, 0, 0 }, Imm_None }, - { "trapeq" ,1,0x74850020,0, { IVector, 0, 0 }, Imm_None }, - { "trapne" ,1,0x74860020,0, { IVector, 0, 0 }, Imm_None }, - { "traplt" ,1,0x74870020,0, { IVector, 0, 0 }, Imm_None }, - { "traple" ,1,0x74880020,0, { IVector, 0, 0 }, Imm_None }, - { "trapgt" ,1,0x74890020,0, { IVector, 0, 0 }, Imm_None }, - { "trapge" ,1,0x748A0020,0, { IVector, 0, 0 }, Imm_None }, - { "trapz" ,1,0x74850020,0, { IVector, 0, 0 }, Imm_None }, - { "trapnz" ,1,0x74860020,0, { IVector, 0, 0 }, Imm_None }, - { "trapp" ,1,0x74890020,0, { IVector, 0, 0 }, Imm_None }, - { "trapn" ,1,0x74870020,0, { IVector, 0, 0 }, Imm_None }, - { "trapnn" ,1,0x748A0020,0, { IVector, 0, 0 }, Imm_None }, - { "trapnv" ,1,0x748C0020,0, { IVector, 0, 0 }, Imm_None }, - { "trapv" ,1,0x748D0020,0, { IVector, 0, 0 }, Imm_None }, - { "trapnuf",1,0x748E0020,0, { IVector, 0, 0 }, Imm_None }, - { "trapuf" ,1,0x748F0020,0, { IVector, 0, 0 }, Imm_None }, - { "trapnc" ,1,0x74840020,0, { IVector, 0, 0 }, Imm_None }, - { "trapc" ,1,0x74810020,0, { IVector, 0, 0 }, Imm_None }, - { "trapnlv",1,0x74900020,0, { IVector, 0, 0 }, Imm_None }, - { "traplv" ,1,0x74910020,0, { IVector, 0, 0 }, Imm_None }, - { "trapnluf",1,0x74920020,0, { IVector, 0, 0 }, Imm_None }, - { "trapluf",1,0x74930020,0, { IVector, 0, 0 }, Imm_None }, - { "trapzuf",1,0x74940020,0, { IVector, 0, 0 }, Imm_None }, - { "tstb" ,2,0x1A000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt }, - { "tstb3" ,2,0x27800000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, 0 }, Imm_None }, - { "xor" ,2,0x1A800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt }, - { "xor3" ,3,0x28000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, - { "" ,0,0x00000000,0, { 0, 0, 0 }, 0 } -}; - -static const insn_template *const tic30_optab_end = - tic30_optab + sizeof(tic30_optab)/sizeof(tic30_optab[0]); - -typedef struct { - char *name; - unsigned int operands_1; - unsigned int operands_2; - unsigned int base_opcode; - unsigned int operand_types[2][3]; - /* Which operand fits into which part of the final opcode word. */ - int oporder; -} partemplate; - -/* oporder defines - not very descriptive. */ -#define OO_4op1 0 -#define OO_4op2 1 -#define OO_4op3 2 -#define OO_5op1 3 -#define OO_5op2 4 -#define OO_PField 5 - -static const partemplate tic30_paroptab[] = { - { "q_absf_stf", 2,2,0xC8000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } }, - OO_4op1 }, - { "q_absi_sti", 2,2,0xCA000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } }, - OO_4op1 }, - { "q_addf3_stf", 3,2,0xCC000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } }, - OO_5op1 }, - { "q_addi3_sti", 3,2,0xCE000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } }, - OO_5op1 }, - { "q_and3_sti", 3,2,0xD0000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } }, - OO_5op1 }, - { "q_ash3_sti", 3,2,0xD2000000, { { Rn, Indirect, Rn }, { Rn, Indirect, 0 } }, - OO_5op2 }, - { "q_fix_sti", 2,2,0xD4000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } }, - OO_4op1 }, - { "q_float_stf", 2,2,0xD6000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } }, - OO_4op1 }, - { "q_ldf_ldf", 2,2,0xC4000000, { { Indirect, Rn, 0 }, { Indirect, Rn, 0 } }, - OO_4op2 }, - { "q_ldf_stf", 2,2,0xD8000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } }, - OO_4op1 }, - { "q_ldi_ldi", 2,2,0xC6000000, { { Indirect, Rn, 0 }, { Indirect, Rn, 0 } }, - OO_4op2 }, - { "q_ldi_sti", 2,2,0xDA000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } }, - OO_4op1 }, - { "q_lsh3_sti", 3,2,0xDC000000, { { Rn, Indirect, Rn }, { Rn, Indirect, 0 } }, - OO_5op2 }, - { "q_mpyf3_addf3",3,3,0x80000000, { { Rn | Indirect, Rn | Indirect, Rn }, - { Rn | Indirect, Rn | Indirect, Rn } }, OO_PField }, - { "q_mpyf3_stf", 3,2,0xDE000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } }, - OO_5op1 }, - { "q_mpyf3_subf3",3,3,0x84000000, { { Rn | Indirect, Rn | Indirect, Rn }, - { Rn | Indirect, Rn | Indirect, Rn } }, OO_PField }, - { "q_mpyi3_addi3",3,3,0x88000000, { { Rn | Indirect, Rn | Indirect, Rn }, - { Rn | Indirect, Rn | Indirect, Rn } }, OO_PField }, - { "q_mpyi3_sti", 3,2,0xE0000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } }, - OO_5op1 }, - { "q_mpyi3_subi3",3,3,0x8C000000, { { Rn | Indirect, Rn | Indirect, Rn }, - { Rn | Indirect, Rn | Indirect, Rn } }, OO_PField }, - { "q_negf_stf", 2,2,0xE2000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } }, - OO_4op1 }, - { "q_negi_sti", 2,2,0xE4000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } }, - OO_4op1 }, - { "q_not_sti", 2,2,0xE6000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } }, - OO_4op1 }, - { "q_or3_sti", 3,2,0xE8000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } }, - OO_5op1 }, - { "q_stf_stf", 2,2,0xC0000000, { { Rn, Indirect, 0 }, { Rn, Indirect, 0 } }, - OO_4op3 }, - { "q_sti_sti", 2,2,0xC2000000, { { Rn, Indirect, 0 }, { Rn, Indirect, 0 } }, - OO_4op3 }, - { "q_subf3_stf", 3,2,0xEA000000, { { Rn, Indirect, Rn }, { Rn, Indirect, 0 } }, - OO_5op2 }, - { "q_subi3_sti", 3,2,0xEC000000, { { Rn, Indirect, Rn }, { Rn, Indirect, 0 } }, - OO_5op2 }, - { "q_xor3_sti", 3,2,0xEE000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } }, - OO_5op1 }, - { "", 0,0,0x00000000, { { 0, 0, 0 }, { 0, 0, 0 } }, 0 } -}; - -static const partemplate *const tic30_paroptab_end = - tic30_paroptab + sizeof(tic30_paroptab)/sizeof(tic30_paroptab[0]); - -#endif diff --git a/include/opcode/tic4x.h b/include/opcode/tic4x.h deleted file mode 100644 index 6f16fcb..0000000 --- a/include/opcode/tic4x.h +++ /dev/null @@ -1,1079 +0,0 @@ -/* Table of opcodes for the Texas Instruments TMS320C[34]X family. - - Copyright (C) 2002, 2003, 2010 Free Software Foundation. - - Contributed by Michael P. Hayes (m.hayes@elec.canterbury.ac.nz) - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, - MA 02110-1301, USA. */ - -#define IS_CPU_TIC3X(v) ((v) == 30 || (v) == 31 || (v) == 32 || (v) == 33) -#define IS_CPU_TIC4X(v) ((v) == 0 || (v) == 40 || (v) == 44) - -/* Define some bitfield extraction/insertion macros. */ -#define EXTR(inst, m, l) ((inst) << (31 - (m)) >> (31 - ((m) - (l)))) -#define EXTRU(inst, m, l) EXTR ((unsigned long)(inst), (m), (l)) -#define EXTRS(inst, m, l) EXTR ((long)(inst), (m), (l)) -#define INSERTU(inst, val, m, l) (inst |= ((val) << (l))) -#define INSERTS(inst, val, m, l) INSERTU (inst, ((val) & ((1 << ((m) - (l) + 1)) - 1)), m, l) - -/* Define register numbers. */ -typedef enum - { - REG_R0, REG_R1, REG_R2, REG_R3, - REG_R4, REG_R5, REG_R6, REG_R7, - REG_AR0, REG_AR1, REG_AR2, REG_AR3, - REG_AR4, REG_AR5, REG_AR6, REG_AR7, - REG_DP, REG_IR0, REG_IR1, REG_BK, - REG_SP, REG_ST, REG_DIE, REG_IIE, - REG_IIF, REG_RS, REG_RE, REG_RC, - REG_R8, REG_R9, REG_R10, REG_R11, - REG_IVTP, REG_TVTP - } -c4x_reg_t; - -/* Note that the actual register numbers for IVTP is 0 and TVTP is 1. */ - -#define REG_IE REG_DIE /* C3x only */ -#define REG_IF REG_IIE /* C3x only */ -#define REG_IOF REG_IIF /* C3x only */ - -#define TIC3X_REG_MAX REG_RC -#define TIC4X_REG_MAX REG_TVTP - -/* Register table size including C4x expansion regs. */ -#define REG_TABLE_SIZE (TIC4X_REG_MAX + 1) - -struct tic4x_register -{ - char * name; - unsigned long regno; -}; - -typedef struct tic4x_register tic4x_register_t; - -/* We could store register synonyms here. */ -static const tic4x_register_t tic3x_registers[] = -{ - {"f0", REG_R0}, - {"r0", REG_R0}, - {"f1", REG_R1}, - {"r1", REG_R1}, - {"f2", REG_R2}, - {"r2", REG_R2}, - {"f3", REG_R3}, - {"r3", REG_R3}, - {"f4", REG_R4}, - {"r4", REG_R4}, - {"f5", REG_R5}, - {"r5", REG_R5}, - {"f6", REG_R6}, - {"r6", REG_R6}, - {"f7", REG_R7}, - {"r7", REG_R7}, - {"ar0", REG_AR0}, - {"ar1", REG_AR1}, - {"ar2", REG_AR2}, - {"ar3", REG_AR3}, - {"ar4", REG_AR4}, - {"ar5", REG_AR5}, - {"ar6", REG_AR6}, - {"ar7", REG_AR7}, - {"dp", REG_DP}, - {"ir0", REG_IR0}, - {"ir1", REG_IR1}, - {"bk", REG_BK}, - {"sp", REG_SP}, - {"st", REG_ST}, - {"ie", REG_IE}, - {"if", REG_IF}, - {"iof", REG_IOF}, - {"rs", REG_RS}, - {"re", REG_RE}, - {"rc", REG_RC}, - {"", 0} -}; - -const unsigned int tic3x_num_registers = (((sizeof tic3x_registers) / (sizeof tic3x_registers[0])) - 1); - -/* Define C4x registers in addition to C3x registers. */ -static const tic4x_register_t tic4x_registers[] = -{ - {"die", REG_DIE}, /* Clobbers C3x REG_IE */ - {"iie", REG_IIE}, /* Clobbers C3x REG_IF */ - {"iif", REG_IIF}, /* Clobbers C3x REG_IOF */ - {"f8", REG_R8}, - {"r8", REG_R8}, - {"f9", REG_R9}, - {"r9", REG_R9}, - {"f10", REG_R10}, - {"r10", REG_R10}, - {"f11", REG_R11}, - {"r11", REG_R11}, - {"ivtp", REG_IVTP}, - {"tvtp", REG_TVTP}, - {"", 0} -}; - -const unsigned int tic4x_num_registers = (((sizeof tic4x_registers) / (sizeof tic4x_registers[0])) - 1); - -struct tic4x_cond -{ - char * name; - unsigned long cond; -}; - -typedef struct tic4x_cond tic4x_cond_t; - -/* Define conditional branch/load suffixes. Put desired form for - disassembler last. */ -static const tic4x_cond_t tic4x_conds[] = -{ - { "u", 0x00 }, - { "c", 0x01 }, { "lo", 0x01 }, - { "ls", 0x02 }, - { "hi", 0x03 }, - { "nc", 0x04 }, { "hs", 0x04 }, - { "z", 0x05 }, { "eq", 0x05 }, - { "nz", 0x06 }, { "ne", 0x06 }, - { "n", 0x07 }, { "l", 0x07 }, { "lt", 0x07 }, - { "le", 0x08 }, - { "p", 0x09 }, { "gt", 0x09 }, - { "nn", 0x0a }, { "ge", 0x0a }, - { "nv", 0x0c }, - { "v", 0x0d }, - { "nuf", 0x0e }, - { "uf", 0x0f }, - { "nlv", 0x10 }, - { "lv", 0x11 }, - { "nluf", 0x12 }, - { "luf", 0x13 }, - { "zuf", 0x14 }, - /* Dummy entry, not included in num_conds. This - lets code examine entry i+1 without checking - if we've run off the end of the table. */ - { "", 0x0} -}; - -const unsigned int tic4x_num_conds = (((sizeof tic4x_conds) / (sizeof tic4x_conds[0])) - 1); - -struct tic4x_indirect -{ - char * name; - unsigned long modn; -}; - -typedef struct tic4x_indirect tic4x_indirect_t; - -/* Define indirect addressing modes where: - d displacement (signed) - y ir0 - z ir1 */ - -static const tic4x_indirect_t tic4x_indirects[] = -{ - { "*+a(d)", 0x00 }, - { "*-a(d)", 0x01 }, - { "*++a(d)", 0x02 }, - { "*--a(d)", 0x03 }, - { "*a++(d)", 0x04 }, - { "*a--(d)", 0x05 }, - { "*a++(d)%", 0x06 }, - { "*a--(d)%", 0x07 }, - { "*+a(y)", 0x08 }, - { "*-a(y)", 0x09 }, - { "*++a(y)", 0x0a }, - { "*--a(y)", 0x0b }, - { "*a++(y)", 0x0c }, - { "*a--(y)", 0x0d }, - { "*a++(y)%", 0x0e }, - { "*a--(y)%", 0x0f }, - { "*+a(z)", 0x10 }, - { "*-a(z)", 0x11 }, - { "*++a(z)", 0x12 }, - { "*--a(z)", 0x13 }, - { "*a++(z)", 0x14 }, - { "*a--(z)", 0x15 }, - { "*a++(z)%", 0x16 }, - { "*a--(z)%", 0x17 }, - { "*a", 0x18 }, - { "*a++(y)b", 0x19 }, - /* Dummy entry, not included in num_indirects. This - lets code examine entry i+1 without checking - if we've run off the end of the table. */ - { "", 0x0} -}; - -#define TIC3X_MODN_MAX 0x19 - -const unsigned int tic4x_num_indirects = (((sizeof tic4x_indirects) / (sizeof tic4x_indirects[0])) - 1); - -/* Instruction template. */ -struct tic4x_inst -{ - char * name; - unsigned long opcode; - unsigned long opmask; - char * args; - unsigned long oplevel; -}; - -typedef struct tic4x_inst tic4x_inst_t; - -/* Opcode infix - B condition 16--20 U,C,Z,LO,HI, etc. - C condition 23--27 U,C,Z,LO,HI, etc. - - Arguments - , required arg follows - ; optional arg follows - - Argument types bits [classes] - example - ----------------------------------------------------------- - * indirect (all) 0--15 [A,AB,AU,AF,A2,A3,A6,A7,AY,B,BA,BB,BI,B6,B7] - *+AR0(5), *++AR0(IR0) - # direct (for LDP) 0--15 [Z] - @start, start - @ direct 0--15 [A,AB,AU,AF,A3,A6,A7,AY,B,BA,BB,BI,B6,B7] - @start, start - A address register 22--24 [D] - AR0, AR7 - B unsigned integer 0--23 [I,I2] - @start, start (absolute on C3x, relative on C4x) - C indirect (disp - C4x) 0--7 [S,SC,S2,T,TC,T2,T2C] - *+AR0(5) - E register (all) 0--7 [T,TC,T2,T2C] - R0, R7, R11, AR0, DP - e register (0-11) 0--7 [S,SC,S2] - R0, R7, R11 - F short float immediate 0--15 [AF,B,BA,BB] - 3.5, 0e-3.5e-1 - G register (all) 8--15 [T,TC,T2,T2C] - R0, R7, R11, AR0, DP - g register (0-11) 0--7 [S,SC,S2] - R0, R7, R11 - H register (0-7) 18--16 [LS,M,P,Q] - R0, R7 - I indirect (no disp) 0--7 [S,SC,S2,T,TC,T2,T2C] - *+AR0(1), *+AR0(IR0) - i indirect (enhanced) 0--7 [LL,LS,M,P,Q,QC] - *+AR0(1), R5 - J indirect (no disp) 8--15 [LL,LS,P,Q,QC,S,SC,S2,T,TC,T2,T2C] - *+AR0(1), *+AR0(IR0) - j indirect (enhanced) 8--15 [M] - *+AR0(1), R5 - K register 19--21 [LL,M,Q,QC] - R0, R7 - L register 22--24 [LL,LS,P,Q,QC] - R0, R7 - M register (R2,R3) 22--22 [M] R2, R3 - N register (R0,R1) 23--23 [M] R0, R1 - O indirect(disp - C4x) 8--15 [S,SC,S2,T,TC,T2] - *+AR0(5) - P displacement (PC Rel) 0--15 [D,J,JS] - @start, start - Q register (all) 0--15 [A,AB,AU,A2,A3,AY,BA,BI,D,I2,J,JS] - R0, AR0, DP, SP - q register (0-11) 0--15 [AF,B,BB] - R0, R7, R11 - R register (all) 16--20 [A,AB,AU,AF,A6,A7,R,T,TC] - R0, AR0, DP, SP - r register (0-11) 16--20 [B,BA,BB,BI,B6,B7,RF,S,SC] - R0, R1, R11 - S short int immediate 0--15 [A,AB,AY,BI] - -5, 5 - T integer (C4x) 16--20 [Z] - -5, 12 - U unsigned integer 0--15 [AU,A3] - 0, 65535 - V vector (C4x: 0--8) 0--4 [Z] - 25, 7 - W short int (C4x) 0--7 [T,TC,T2,T2C] - -3, 5 - X expansion reg (C4x) 0--4 [Z] - IVTP, TVTP - Y address reg (C4x) 16--20 [Z] - AR0, DP, SP, IR0 - Z expansion reg (C4x) 16--20 [Z] - IVTP, TVTP -*/ - -#define TIC4X_OPERANDS_MAX 7 /* Max number of operands for an inst. */ -#define TIC4X_NAME_MAX 16 /* Max number of chars in parallel name. */ - -/* Define the instruction level */ -#define OP_C3X 0x1 /* C30 support - supported by all */ -#define OP_C4X 0x2 /* C40 support - C40, C44 */ -#define OP_ENH 0x4 /* Class LL,LS,M,P,Q,QC enhancements. Argument type - I and J is enhanced in these classes - C31>=6.0, - C32>=2.0, C33 */ -#define OP_LPWR 0x8 /* Low power support (LOPOWER, MAXSPEED) - C30>=7.0, - LC31, C31>=5.0, C32 */ -#define OP_IDLE2 0x10 /* Idle2 support (IDLE2) - C30>=7.0, LC31, C31>=5.0, - C32, C33, C40>=5.0, C44 */ - -/* The following class definition is a classification scheme for - putting instructions with similar type of arguments together. It - simplifies the op-code definitions significantly, as we then only - need to use the class macroes for 95% of the DSP's opcodes. -*/ - -/* A: General 2-operand integer operations - Syntax: <i> src, dst - src = Register (Q), Direct (@), Indirect (*), Signed immediate (S) - dst = Register (R) - Instr: 15/8 - ABSI, ADDC, ADDI, ASH, CMPI, LDI, LSH, MPYI, NEGB, NEGI, - SUBB, SUBC, SUBI, SUBRB, SUBRI, C4x: LBn, LHn, LWLn, LWRn, - MBn, MHn, MPYSHI, MPYUHI -*/ -#define A_CLASS_INSN(name, opcode, level) \ - { name, opcode|0x00000000, 0xffe00000, "Q;R", level }, \ - { name, opcode|0x00200000, 0xffe00000, "@,R", level }, \ - { name, opcode|0x00400000, 0xffe00000, "*,R", level }, \ - { name, opcode|0x00600000, 0xffe00000, "S,R", level } - -/* AB: General 2-operand integer operation with condition - Syntax: <i>c src, dst - c = Condition - src = Register (Q), Direct (@), Indirect (*), Signed immediate (S) - dst = Register (R) - Instr: 1/0 - LDIc -*/ -#define AB_CLASS_INSN(name, opcode, level) \ - { name, opcode|0x40000000, 0xf0600000, "Q;R", level }, \ - { name, opcode|0x40200000, 0xf0600000, "@,R", level }, \ - { name, opcode|0x40400000, 0xf0600000, "*,R", level }, \ - { name, opcode|0x40600000, 0xf0600000, "S,R", level } - -/* AU: General 2-operand unsigned integer operation - Syntax: <i> src, dst - src = Register (Q), Direct (@), Indirect (*), Unsigned immediate (U) - dst = Register (R) - Instr: 6/2 - AND, ANDN, NOT, OR, TSTB, XOR, C4x: LBUn, LHUn -*/ -#define AU_CLASS_INSN(name, opcode, level) \ - { name, opcode|0x00000000, 0xffe00000, "Q;R", level }, \ - { name, opcode|0x00200000, 0xffe00000, "@,R", level }, \ - { name, opcode|0x00400000, 0xffe00000, "*,R", level }, \ - { name, opcode|0x00600000, 0xffe00000, "U,R", level } - -/* AF: General 2-operand float to integer operation - Syntax: <i> src, dst - src = Register 0-11 (q), Direct (@), Indirect (*), Float immediate (F) - dst = Register (R) - Instr: 1/0 - FIX -*/ -#define AF_CLASS_INSN(name, opcode, level) \ - { name, opcode|0x00000000, 0xffe00000, "q;R", level }, \ - { name, opcode|0x00200000, 0xffe00000, "@,R", level }, \ - { name, opcode|0x00400000, 0xffe00000, "*,R", level }, \ - { name, opcode|0x00600000, 0xffe00000, "F,R", level } - -/* A2: Limited 1-operand (integer) operation - Syntax: <i> src - src = Register (Q), Indirect (*), None - Instr: 1/0 - NOP -*/ -#define A2_CLASS_INSN(name, opcode, level) \ - { name, opcode|0x00000000, 0xffe00000, "Q", level }, \ - { name, opcode|0x00400000, 0xffe00000, "*", level }, \ - { name, opcode|0x00000000, 0xffe00000, "" , level } - -/* A3: General 1-operand unsigned integer operation - Syntax: <i> src - src = Register (Q), Direct (@), Indirect (*), Unsigned immediate (U) - Instr: 1/0 - RPTS -*/ -#define A3_CLASS_INSN(name, opcode, level) \ - { name, opcode|0x00000000, 0xffff0000, "Q", level }, \ - { name, opcode|0x00200000, 0xffff0000, "@", level }, \ - { name, opcode|0x00400000, 0xffff0000, "*", level }, \ - { name, opcode|0x00600000, 0xffff0000, "U", level } - -/* A6: Limited 2-operand integer operation - Syntax: <i> src, dst - src = Direct (@), Indirect (*) - dst = Register (R) - Instr: 1/1 - LDII, C4x: SIGI -*/ -#define A6_CLASS_INSN(name, opcode, level) \ - { name, opcode|0x00200000, 0xffe00000, "@,R", level }, \ - { name, opcode|0x00400000, 0xffe00000, "*,R", level } - -/* A7: Limited 2-operand integer store operation - Syntax: <i> src, dst - src = Register (R) - dst = Direct (@), Indirect (*) - Instr: 2/0 - STI, STII -*/ -#define A7_CLASS_INSN(name, opcode, level) \ - { name, opcode|0x00200000, 0xffe00000, "R,@", level }, \ - { name, opcode|0x00400000, 0xffe00000, "R,*", level } - -/* AY: General 2-operand signed address load operation - Syntax: <i> src, dst - src = Register (Q), Direct (@), Indirect (*), Signed immediate (S) - dst = Address register - ARx, IRx, DP, BK, SP (Y) - Instr: 0/1 - C4x: LDA - Note: Q and Y should *never* be the same register -*/ -#define AY_CLASS_INSN(name, opcode, level) \ - { name, opcode|0x00000000, 0xffe00000, "Q,Y", level }, \ - { name, opcode|0x00200000, 0xffe00000, "@,Y", level }, \ - { name, opcode|0x00400000, 0xffe00000, "*,Y", level }, \ - { name, opcode|0x00600000, 0xffe00000, "S,Y", level } - -/* B: General 2-operand float operation - Syntax: <i> src, dst - src = Register 0-11 (q), Direct (@), Indirect (*), Float immediate (F) - dst = Register 0-11 (r) - Instr: 12/2 - ABSF, ADDF, CMPF, LDE, LDF, LDM, MPYF, NEGF, NORM, RND, - SUBF, SUBRF, C4x: RSQRF, TOIEEE -*/ -#define B_CLASS_INSN(name, opcode, level) \ - { name, opcode|0x00000000, 0xffe00000, "q;r", level }, \ - { name, opcode|0x00200000, 0xffe00000, "@,r", level }, \ - { name, opcode|0x00400000, 0xffe00000, "*,r", level }, \ - { name, opcode|0x00600000, 0xffe00000, "F,r", level } - -/* BA: General 2-operand integer to float operation - Syntax: <i> src, dst - src = Register (Q), Direct (@), Indirect (*), Float immediate (F) - dst = Register 0-11 (r) - Instr: 0/1 - C4x: CRCPF -*/ -#define BA_CLASS_INSN(name, opcode, level) \ - { name, opcode|0x00000000, 0xffe00000, "Q;r", level }, \ - { name, opcode|0x00200000, 0xffe00000, "@,r", level }, \ - { name, opcode|0x00400000, 0xffe00000, "*,r", level }, \ - { name, opcode|0x00600000, 0xffe00000, "F,r", level } - -/* BB: General 2-operand conditional float operation - Syntax: <i>c src, dst - c = Condition - src = Register 0-11 (q), Direct (@), Indirect (*), Float immediate (F) - dst = Register 0-11 (r) - Instr: 1/0 - LDFc -*/ -#define BB_CLASS_INSN(name, opcode, level) \ - { name, opcode|0x40000000, 0xf0600000, "q;r", level }, \ - { name, opcode|0x40200000, 0xf0600000, "@,r", level }, \ - { name, opcode|0x40400000, 0xf0600000, "*,r", level }, \ - { name, opcode|0x40600000, 0xf0600000, "F,r", level } - -/* BI: General 2-operand integer to float operation (yet different to BA) - Syntax: <i> src, dst - src = Register (Q), Direct (@), Indirect (*), Signed immediate (S) - dst = Register 0-11 (r) - Instr: 1/0 - FLOAT -*/ -#define BI_CLASS_INSN(name, opcode, level) \ - { name, opcode|0x00000000, 0xffe00000, "Q;r", level }, \ - { name, opcode|0x00200000, 0xffe00000, "@,r", level }, \ - { name, opcode|0x00400000, 0xffe00000, "*,r", level }, \ - { name, opcode|0x00600000, 0xffe00000, "S,r", level } - -/* B6: Limited 2-operand float operation - Syntax: <i> src, dst - src = Direct (@), Indirect (*) - dst = Register 0-11 (r) - Instr: 1/1 - LDFI, C4x: FRIEEE -*/ -#define B6_CLASS_INSN(name, opcode, level) \ - { name, opcode|0x00200000, 0xffe00000, "@,r", level }, \ - { name, opcode|0x00400000, 0xffe00000, "*,r", level } - -/* B7: Limited 2-operand float store operation - Syntax: <i> src, dst - src = Register 0-11 (r) - dst = Direct (@), Indirect (*) - Instr: 2/0 - STF, STFI -*/ -#define B7_CLASS_INSN(name, opcode, level) \ - { name, opcode|0x00200000, 0xffe00000, "r,@", level }, \ - { name, opcode|0x00400000, 0xffe00000, "r,*", level } - -/* D: Decrement and brach operations - Syntax: <i>c ARn, dst - c = condition - ARn = AR register 0-7 (A) - dst = Register (Q), PC-relative (P) - Instr: 2/0 - DBc, DBcD - Alias: <name1> <name2> -*/ -#define D_CLASS_INSN(name1, name2, opcode, level) \ - { name1, opcode|0x00000000, 0xfe200000, "A,Q", level }, \ - { name1, opcode|0x02000000, 0xfe200000, "A,P", level }, \ - { name2, opcode|0x00000000, 0xfe200000, "A,Q", level }, \ - { name2, opcode|0x02000000, 0xfe200000, "A,P", level } - -/* I: General branch operations - Syntax: <i> dst - dst = Address (B) - Instr: 3/1 - BR, BRD, CALL, C4x: LAJ -*/ - -/* I2: General branch operations (C4x addition) - Syntax: <i> dst - dst = Address (B), C4x: Register (Q) - Instr: 2/0 - RPTB, RPTBD -*/ - -/* J: General conditional branch operations - Syntax: <i>c dst - c = Condition - dst = Register (Q), PC-relative (P) - Instr: 2/3 - Bc, BcD, C4x: BcAF, BcAT, LAJc - Alias: <name1> <name2> -*/ -#define J_CLASS_INSN(name1, name2, opcode, level) \ - { name1, opcode|0x00000000, 0xffe00000, "Q", level }, \ - { name1, opcode|0x02000000, 0xffe00000, "P", level }, \ - { name2, opcode|0x00000000, 0xffe00000, "Q", level }, \ - { name2, opcode|0x02000000, 0xffe00000, "P", level } - -/* JS: General conditional branch operations - Syntax: <i>c dst - c = Condition - dst = Register (Q), PC-relative (P) - Instr: 1/1 - CALLc, C4X: LAJc -*/ - -/* LL: Load-load parallell operation - Syntax: <i> src2, dst2 || <i> src1, dst1 - src1 = Indirect 0,1,IR0,IR1 (J) - dst1 = Register 0-7 (K) - src2 = Indirect 0,1,IR0,IR1, ENH: Register (i) - dst2 = Register 0-7 (L) - Instr: 2/0 - LDF||LDF, LDI||LDI - Alias: i||i, i1||i2, i2||i1 -*/ -#define LL_CLASS_INSN(name, opcode, level) \ - { name "_" name , opcode, 0xfe000000, "i;L|J,K", level }, \ - { name "2_" name "1", opcode, 0xfe000000, "i;L|J,K", level }, \ - { name "1_" name "2", opcode, 0xfe000000, "J,K|i;L", level } - -/* LS: Store-store parallell operation - Syntax: <i> src2, dst2 || <i> src1, dst1 - src1 = Register 0-7 (H) - dst1 = Indirect 0,1,IR0,IR1 (J) - src2 = Register 0-7 (L) - dst2 = Indirect 0,1,IR0,IR1, ENH: register (i) - Instr: 2/0 - STF||STF, STI||STI - Alias: i||i, i1||i2, i2||i1. -*/ -#define LS_CLASS_INSN(name, opcode, level) \ - { name "_" name , opcode, 0xfe000000, "L;i|H,J", level }, \ - { name "2_" name "1", opcode, 0xfe000000, "L;i|H,J", level }, \ - { name "1_" name "2", opcode, 0xfe000000, "H,J|L;i", level } - -/* M: General multiply and add/sub operations - Syntax: <ia> src3,src4,dst1 || <ib> src2,src1,dst2 [00] - Manual - <ia> src3,src1,dst1 || <ib> src2,src4,dst2 [01] - Manual - <ia> src1,src3,dst1 || <ib> src2,src4,dst2 [01] - <ia> src1,src2,dst1 || <ib> src4,src3,dst2 [02] - Manual - <ia> src3,src1,dst1 || <ib> src4,src2,dst2 [03] - Manual - <ia> src1,src3,dst1 || <ib> src4,src2,dst2 [03] - src1 = Register 0-7 (K) - src2 = Register 0-7 (H) - src3 = Indirect 0,1,IR0,IR1, ENH: register (j) - src4 = Indirect 0,1,IR0,IR1, ENH: register (i) - dst1 = Register 0-1 (N) - dst2 = Register 2-3 (M) - Instr: 4/0 - MPYF3||ADDF3, MPYF3||SUBF3, MPYI3||ADDI3, MPYI3||SUBI3 - Alias: a||b, a3||n, a||b3, a3||b3, b||a, b3||a, b||a3, b3||a3 -*/ -#define M_CLASS_INSN(namea, nameb, opcode, level) \ - { namea "_" nameb, opcode|0x00000000, 0xff000000, "i;j;N|H;K;M", level }, \ - { namea "_" nameb, opcode|0x01000000, 0xff000000, "j;K;N|H;i;M", level }, \ - { namea "_" nameb, opcode|0x01000000, 0xff000000, "K;j;N|H;i;M", level }, \ - { namea "_" nameb, opcode|0x02000000, 0xff000000, "H;K;N|i;j;M", level }, \ - { namea "_" nameb, opcode|0x03000000, 0xff000000, "j;K;N|i;H;M", level }, \ - { namea "_" nameb, opcode|0x03000000, 0xff000000, "K;j;N|i;H;M", level }, \ - { namea "3_" nameb, opcode|0x00000000, 0xff000000, "i;j;N|H;K;M", level }, \ - { namea "3_" nameb, opcode|0x01000000, 0xff000000, "j;K;N|H;i;M", level }, \ - { namea "3_" nameb, opcode|0x01000000, 0xff000000, "K;j;N|H;i;M", level }, \ - { namea "3_" nameb, opcode|0x02000000, 0xff000000, "H;K;N|i;j;M", level }, \ - { namea "3_" nameb, opcode|0x03000000, 0xff000000, "j;K;N|i;H;M", level }, \ - { namea "3_" nameb, opcode|0x03000000, 0xff000000, "K;j;N|i;H;M", level }, \ - { namea "_" nameb "3", opcode|0x00000000, 0xff000000, "i;j;N|H;K;M", level }, \ - { namea "_" nameb "3", opcode|0x01000000, 0xff000000, "j;K;N|H;i;M", level }, \ - { namea "_" nameb "3", opcode|0x01000000, 0xff000000, "K;j;N|H;i;M", level }, \ - { namea "_" nameb "3", opcode|0x02000000, 0xff000000, "H;K;N|i;j;M", level }, \ - { namea "_" nameb "3", opcode|0x03000000, 0xff000000, "j;K;N|i;H;M", level }, \ - { namea "_" nameb "3", opcode|0x03000000, 0xff000000, "K;j;N|i;H;M", level }, \ - { namea "3_" nameb "3", opcode|0x00000000, 0xff000000, "i;j;N|H;K;M", level }, \ - { namea "3_" nameb "3", opcode|0x01000000, 0xff000000, "j;K;N|H;i;M", level }, \ - { namea "3_" nameb "3", opcode|0x01000000, 0xff000000, "K;j;N|H;i;M", level }, \ - { namea "3_" nameb "3", opcode|0x02000000, 0xff000000, "H;K;N|i;j;M", level }, \ - { namea "3_" nameb "3", opcode|0x03000000, 0xff000000, "j;K;N|i;H;M", level }, \ - { namea "3_" nameb "3", opcode|0x03000000, 0xff000000, "K;j;N|i;H;M", level }, \ - { nameb "_" namea, opcode|0x00000000, 0xff000000, "H;K;M|i;j;N", level }, \ - { nameb "_" namea, opcode|0x01000000, 0xff000000, "H;i;M|j;K;N", level }, \ - { nameb "_" namea, opcode|0x01000000, 0xff000000, "H;i;M|K;j;N", level }, \ - { nameb "_" namea, opcode|0x02000000, 0xff000000, "i;j;M|H;K;N", level }, \ - { nameb "_" namea, opcode|0x03000000, 0xff000000, "i;H;M|j;K;N", level }, \ - { nameb "_" namea, opcode|0x03000000, 0xff000000, "i;H;M|K;j;N", level }, \ - { nameb "3_" namea, opcode|0x00000000, 0xff000000, "H;K;M|i;j;N", level }, \ - { nameb "3_" namea, opcode|0x01000000, 0xff000000, "H;i;M|j;K;N", level }, \ - { nameb "3_" namea, opcode|0x01000000, 0xff000000, "H;i;M|K;j;N", level }, \ - { nameb "3_" namea, opcode|0x02000000, 0xff000000, "i;j;M|H;K;N", level }, \ - { nameb "3_" namea, opcode|0x03000000, 0xff000000, "i;H;M|j;K;N", level }, \ - { nameb "3_" namea, opcode|0x03000000, 0xff000000, "i;H;M|K;j;N", level }, \ - { nameb "_" namea "3", opcode|0x00000000, 0xff000000, "H;K;M|i;j;N", level }, \ - { nameb "_" namea "3", opcode|0x01000000, 0xff000000, "H;i;M|j;K;N", level }, \ - { nameb "_" namea "3", opcode|0x01000000, 0xff000000, "H;i;M|K;j;N", level }, \ - { nameb "_" namea "3", opcode|0x02000000, 0xff000000, "i;j;M|H;K;N", level }, \ - { nameb "_" namea "3", opcode|0x03000000, 0xff000000, "i;H;M|j;K;N", level }, \ - { nameb "_" namea "3", opcode|0x03000000, 0xff000000, "i;H;M|K;j;N", level }, \ - { nameb "3_" namea "3", opcode|0x00000000, 0xff000000, "H;K;M|i;j;N", level }, \ - { nameb "3_" namea "3", opcode|0x01000000, 0xff000000, "H;i;M|j;K;N", level }, \ - { nameb "3_" namea "3", opcode|0x01000000, 0xff000000, "H;i;M|K;j;N", level }, \ - { nameb "3_" namea "3", opcode|0x02000000, 0xff000000, "i;j;M|H;K;N", level }, \ - { nameb "3_" namea "3", opcode|0x03000000, 0xff000000, "i;H;M|j;K;N", level }, \ - { nameb "3_" namea "3", opcode|0x03000000, 0xff000000, "i;H;M|K;j;N", level } - -/* P: General 2-operand operation with parallell store - Syntax: <ia> src2, dst1 || <ib> src3, dst2 - src2 = Indirect 0,1,IR0,IR1, ENH: register (i) - dst1 = Register 0-7 (L) - src3 = Register 0-7 (H) - dst2 = Indirect 0,1,IR0,IR1 (J) - Instr: 9/2 - ABSF||STF, ABSI||STI, FIX||STI, FLOAT||STF, LDF||STF, - LDI||STI, NEGF||STF, NEGI||STI, NOT||STI, C4x: FRIEEE||STF, - TOIEEE||STF - Alias: a||b, b||a -*/ -#define P_CLASS_INSN(namea, nameb, opcode, level) \ - { namea "_" nameb, opcode, 0xfe000000, "i;L|H,J", level }, \ - { nameb "_" namea, opcode, 0xfe000000, "H,J|i;L", level } - -/* Q: General 3-operand operation with parallell store - Syntax: <ia> src1, src2, dst1 || <ib> src3, dst2 - src1 = Register 0-7 (K) - src2 = Indirect 0,1,IR0,IR1, ENH: register (i) - dst1 = Register 0-7 (L) - src3 = Register 0-7 (H) - dst2 = Indirect 0,1,IR0,IR1 (J) - Instr: 4/0 - ASH3||STI, LSH3||STI, SUBF3||STF, SUBI3||STI - Alias: a||b, b||a, a3||b, b||a3 -*/ -#define Q_CLASS_INSN(namea, nameb, opcode, level) \ - { namea "_" nameb , opcode, 0xfe000000, "K,i;L|H,J", level }, \ - { nameb "_" namea , opcode, 0xfe000000, "H,J|K,i;L", level }, \ - { namea "3_" nameb , opcode, 0xfe000000, "K,i;L|H,J", level }, \ - { nameb "_" namea "3", opcode, 0xfe000000, "H,J|K,i;L", level } - -/* QC: General commutative 3-operand operation with parallell store - Syntax: <ia> src2, src1, dst1 || <ib> src3, dst2 - <ia> src1, src2, dst1 || <ib> src3, dst2 - Manual - src1 = Register 0-7 (K) - src2 = Indirect 0,1,IR0,IR1, ENH: register (i) - dst1 = Register 0-7 (L) - src3 = Register 0-7 (H) - dst2 = Indirect 0,1,IR0,IR1 (J) - Instr: 7/0 - ADDF3||STF, ADDI3||STI, AND3||STI, MPYF3||STF, MPYI3||STI, - OR3||STI, XOR3||STI - Alias: a||b, b||a, a3||b, b||a3 -*/ -#define QC_CLASS_INSN(namea, nameb, opcode, level) \ - { namea "_" nameb , opcode, 0xfe000000, "i;K;L|H,J", level }, \ - { namea "_" nameb , opcode, 0xfe000000, "K;i;L|H,J", level }, \ - { nameb "_" namea , opcode, 0xfe000000, "H,J|i;K;L", level }, \ - { nameb "_" namea , opcode, 0xfe000000, "H,J|K;i;L", level }, \ - { namea "3_" nameb , opcode, 0xfe000000, "i;K;L|H,J", level }, \ - { namea "3_" nameb , opcode, 0xfe000000, "K;i;L|H,J", level }, \ - { nameb "_" namea "3", opcode, 0xfe000000, "H,J|i;K;L", level }, \ - { nameb "_" namea "3", opcode, 0xfe000000, "H,J|K;i;L", level } - -/* R: General register integer operation - Syntax: <i> dst - dst = Register (R) - Instr: 6/0 - POP, PUSH, ROL, ROLC, ROR, RORC -*/ -#define R_CLASS_INSN(name, opcode, level) \ - { name, opcode, 0xffe0ffff, "R", level } - -/* RF: General register float operation - Syntax: <i> dst - dst = Register 0-11 (r) - Instr: 2/0 - POPF, PUSHF -*/ -#define RF_CLASS_INSN(name, opcode, level) \ - { name, opcode, 0xffe0ffff, "r", level } - -/* S: General 3-operand float operation - Syntax: <i> src2, src1, dst - src2 = Register 0-11 (e), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C) - src1 = Register 0-11 (g), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (O) - dst = Register 0-11 (r) - Instr: 1/0 - SUBF3 - Alias: i, i3 -*/ -#define S_CLASS_INSN(name, opcode, level) \ - { name, opcode|0x20000000, 0xffe00000, "e,g;r", level }, \ - { name, opcode|0x20200000, 0xffe00000, "e,J,r", level }, \ - { name, opcode|0x20400000, 0xffe00000, "I,g;r", level }, \ - { name, opcode|0x20600000, 0xffe00000, "I,J,r", level }, \ - { name, opcode|0x30200000, 0xffe00000, "C,g;r", OP_C4X }, \ - { name, opcode|0x30600000, 0xffe00000, "C,O,r", OP_C4X }, \ - { name "3", opcode|0x20000000, 0xffe00000, "e,g;r", level }, \ - { name "3", opcode|0x20200000, 0xffe00000, "e,J,r", level }, \ - { name "3", opcode|0x20400000, 0xffe00000, "I,g;r", level }, \ - { name "3", opcode|0x20600000, 0xffe00000, "I,J,r", level }, \ - { name "3", opcode|0x30200000, 0xffe00000, "C,g;r", OP_C4X }, \ - { name "3", opcode|0x30600000, 0xffe00000, "C,O,r", OP_C4X } - -/* SC: General commutative 3-operand float operation - Syntax: <i> src2, src1, dst - Manual - <i> src1, src2, dst - src2 = Register 0-11 (e), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C) - src1 = Register 0-11 (g), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (O) - dst = Register 0-11 (r) - Instr: 2/0 - ADDF3, MPYF3 - Alias: i, i3 -*/ -#define SC_CLASS_INSN(name, opcode, level) \ - { name, opcode|0x20000000, 0xffe00000, "e,g;r", level }, \ - { name, opcode|0x20200000, 0xffe00000, "e,J,r", level }, \ - { name, opcode|0x20400000, 0xffe00000, "I,g;r", level }, \ - { name, opcode|0x20600000, 0xffe00000, "I,J,r", level }, \ - { name, opcode|0x30200000, 0xffe00000, "C,g;r", OP_C4X }, \ - { name, opcode|0x30200000, 0xffe00000, "g,C,r", OP_C4X }, \ - { name, opcode|0x30600000, 0xffe00000, "C,O,r", OP_C4X }, \ - { name "3", opcode|0x20000000, 0xffe00000, "e,g;r", level }, \ - { name "3", opcode|0x20200000, 0xffe00000, "e,J,r", level }, \ - { name "3", opcode|0x20400000, 0xffe00000, "I,g;r", level }, \ - { name "3", opcode|0x20600000, 0xffe00000, "I,J,r", level }, \ - { name "3", opcode|0x30200000, 0xffe00000, "g,C,r", OP_C4X }, \ - { name "3", opcode|0x30200000, 0xffe00000, "C,g;r", OP_C4X }, \ - { name "3", opcode|0x30600000, 0xffe00000, "C,O,r", OP_C4X } - -/* S2: General 3-operand float operation with 2 args - Syntax: <i> src2, src1 - src2 = Register 0-11 (e), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C) - src1 = Register 0-11 (g), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (O) - Instr: 1/0 - CMPF3 - Alias: i, i3 -*/ -#define S2_CLASS_INSN(name, opcode, level) \ - { name, opcode|0x20000000, 0xffe00000, "e,g", level }, \ - { name, opcode|0x20200000, 0xffe00000, "e,J", level }, \ - { name, opcode|0x20400000, 0xffe00000, "I,g", level }, \ - { name, opcode|0x20600000, 0xffe00000, "I,J", level }, \ - { name, opcode|0x30200000, 0xffe00000, "C,g", OP_C4X }, \ - { name, opcode|0x30600000, 0xffe00000, "C,O", OP_C4X }, \ - { name "3", opcode|0x20000000, 0xffe00000, "e,g", level }, \ - { name "3", opcode|0x20200000, 0xffe00000, "e,J", level }, \ - { name "3", opcode|0x20400000, 0xffe00000, "I,g", level }, \ - { name "3", opcode|0x20600000, 0xffe00000, "I,J", level }, \ - { name "3", opcode|0x30200000, 0xffe00000, "C,g", OP_C4X }, \ - { name "3", opcode|0x30600000, 0xffe00000, "C,O", OP_C4X } - -/* T: General 3-operand integer operand - Syntax: <i> src2, src1, dst - src2 = Register (E), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C), Immediate (W) - src1 = Register (G), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (O) - dst = Register (R) - Instr: 5/0 - ANDN3, ASH3, LSH3, SUBB3, SUBI3 - Alias: i, i3 -*/ -#define T_CLASS_INSN(name, opcode, level) \ - { name, opcode|0x20000000, 0xffe00000, "E,G;R", level }, \ - { name, opcode|0x20200000, 0xffe00000, "E,J,R", level }, \ - { name, opcode|0x20400000, 0xffe00000, "I,G;R", level }, \ - { name, opcode|0x20600000, 0xffe00000, "I,J,R", level }, \ - { name, opcode|0x30000000, 0xffe00000, "W,G;R", OP_C4X }, \ - { name, opcode|0x30200000, 0xffe00000, "C,G;R", OP_C4X }, \ - { name, opcode|0x30400000, 0xffe00000, "W,O,R", OP_C4X }, \ - { name, opcode|0x30600000, 0xffe00000, "C,O,R", OP_C4X }, \ - { name "3", opcode|0x20000000, 0xffe00000, "E,G;R", level }, \ - { name "3", opcode|0x20200000, 0xffe00000, "E,J,R", level }, \ - { name "3", opcode|0x20400000, 0xffe00000, "I,G;R", level }, \ - { name "3", opcode|0x20600000, 0xffe00000, "I,J,R", level }, \ - { name "3", opcode|0x30000000, 0xffe00000, "W,G;R", OP_C4X }, \ - { name "3", opcode|0x30200000, 0xffe00000, "C,G;R", OP_C4X }, \ - { name "3", opcode|0x30400000, 0xffe00000, "W,O,R", OP_C4X }, \ - { name "3", opcode|0x30600000, 0xffe00000, "C,O,R", OP_C4X } - -/* TC: General commutative 3-operand integer operation - Syntax: <i> src2, src1, dst - <i> src1, src2, dst - src2 = Register (E), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C), Immediate (W) - src1 = Register (G), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (O) - dst = Register (R) - Instr: 6/2 - ADDC3, ADDI3, AND3, MPYI3, OR3, XOR3, C4x: MPYSHI, MPYUHI - Alias: i, i3 -*/ -#define TC_CLASS_INSN(name, opcode, level) \ - { name, opcode|0x20000000, 0xffe00000, "E,G;R", level }, \ - { name, opcode|0x20200000, 0xffe00000, "E,J,R", level }, \ - { name, opcode|0x20400000, 0xffe00000, "I,G;R", level }, \ - { name, opcode|0x20600000, 0xffe00000, "I,J,R", level }, \ - { name, opcode|0x30000000, 0xffe00000, "W,G;R", OP_C4X }, \ - { name, opcode|0x30000000, 0xffe00000, "G,W,R", OP_C4X }, \ - { name, opcode|0x30200000, 0xffe00000, "C,G;R", OP_C4X }, \ - { name, opcode|0x30200000, 0xffe00000, "G,C,R", OP_C4X }, \ - { name, opcode|0x30400000, 0xffe00000, "W,O,R", OP_C4X }, \ - { name, opcode|0x30400000, 0xffe00000, "O,W,R", OP_C4X }, \ - { name, opcode|0x30600000, 0xffe00000, "C,O,R", OP_C4X }, \ - { name "3", opcode|0x20000000, 0xffe00000, "E,G;R", level }, \ - { name "3", opcode|0x20200000, 0xffe00000, "E,J,R", level }, \ - { name "3", opcode|0x20400000, 0xffe00000, "I,G;R", level }, \ - { name "3", opcode|0x20600000, 0xffe00000, "I,J,R", level }, \ - { name "3", opcode|0x30000000, 0xffe00000, "W,G;R", OP_C4X }, \ - { name "3", opcode|0x30000000, 0xffe00000, "G,W,R", OP_C4X }, \ - { name "3", opcode|0x30200000, 0xffe00000, "C,G;R", OP_C4X }, \ - { name "3", opcode|0x30200000, 0xffe00000, "G,C,R", OP_C4X }, \ - { name "3", opcode|0x30400000, 0xffe00000, "W,O,R", OP_C4X }, \ - { name "3", opcode|0x30400000, 0xffe00000, "O,W,R", OP_C4X }, \ - { name "3", opcode|0x30600000, 0xffe00000, "C,O,R", OP_C4X } - -/* T2: General 3-operand integer operation with 2 args - Syntax: <i> src2, src1 - src2 = Register (E), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C), Immediate (W) - src1 = Register (G), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (O) - Instr: 1/0 - CMPI3 - Alias: i, i3 -*/ -#define T2_CLASS_INSN(name, opcode, level) \ - { name, opcode|0x20000000, 0xffe00000, "E,G", level }, \ - { name, opcode|0x20200000, 0xffe00000, "E,J", level }, \ - { name, opcode|0x20400000, 0xffe00000, "I,G", level }, \ - { name, opcode|0x20600000, 0xffe00000, "I,J", level }, \ - { name, opcode|0x30000000, 0xffe00000, "W,G", OP_C4X }, \ - { name, opcode|0x30200000, 0xffe00000, "C,G", OP_C4X }, \ - { name, opcode|0x30400000, 0xffe00000, "W,O", OP_C4X }, \ - { name, opcode|0x30600000, 0xffe00000, "C,O", OP_C4X }, \ - { name "3", opcode|0x20000000, 0xffe00000, "E,G", level }, \ - { name "3", opcode|0x20200000, 0xffe00000, "E,J", level }, \ - { name "3", opcode|0x20400000, 0xffe00000, "I,G", level }, \ - { name "3", opcode|0x20600000, 0xffe00000, "I,J", level }, \ - { name "3", opcode|0x30000000, 0xffe00000, "W,G", OP_C4X }, \ - { name "3", opcode|0x30200000, 0xffe00000, "C,G", OP_C4X }, \ - { name "3", opcode|0x30400000, 0xffe00000, "W,O", OP_C4X }, \ - { name "3", opcode|0x30600000, 0xffe00000, "C,O", OP_C4X } - -/* T2C: General commutative 3-operand integer operation with 2 args - Syntax: <i> src2, src1 - Manual - <i> src1, src2 - src2 = Register (E), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C), Immediate (W) - src1 = Register (G), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (0) - Instr: 1/0 - TSTB3 - Alias: i, i3 -*/ -#define T2C_CLASS_INSN(name, opcode, level) \ - { name, opcode|0x20000000, 0xffe00000, "E,G", level }, \ - { name, opcode|0x20200000, 0xffe00000, "E,J", level }, \ - { name, opcode|0x20400000, 0xffe00000, "I,G", level }, \ - { name, opcode|0x20600000, 0xffe00000, "I,J", level }, \ - { name, opcode|0x30000000, 0xffe00000, "W,G", OP_C4X }, \ - { name, opcode|0x30000000, 0xffe00000, "G,W", OP_C4X }, \ - { name, opcode|0x30200000, 0xffe00000, "C,G", OP_C4X }, \ - { name, opcode|0x30200000, 0xffe00000, "G,C", OP_C4X }, \ - { name, opcode|0x30400000, 0xffe00000, "W,O", OP_C4X }, \ - { name, opcode|0x30400000, 0xffe00000, "O,W", OP_C4X }, \ - { name, opcode|0x30600000, 0xffe00000, "C,O", OP_C4X }, \ - { name "3", opcode|0x20000000, 0xffe00000, "E,G", level }, \ - { name "3", opcode|0x20200000, 0xffe00000, "E,J", level }, \ - { name "3", opcode|0x20400000, 0xffe00000, "I,G", level }, \ - { name "3", opcode|0x20600000, 0xffe00000, "I,J", level }, \ - { name "3", opcode|0x30000000, 0xffe00000, "W,G", OP_C4X }, \ - { name "3", opcode|0x30000000, 0xffe00000, "G,W", OP_C4X }, \ - { name "3", opcode|0x30200000, 0xffe00000, "C,G", OP_C4X }, \ - { name "3", opcode|0x30200000, 0xffe00000, "G,C", OP_C4X }, \ - { name "3", opcode|0x30400000, 0xffe00000, "W,O", OP_C4X }, \ - { name "3", opcode|0x30400000, 0xffe00000, "O,W", OP_C4X }, \ - { name "3", opcode|0x30600000, 0xffe00000, "C,O", OP_C4X } - -/* Z: Misc operations with or without arguments - Syntax: <i> <arg1>,... - Instr: 16 - RETIc, RETSc, SIGI(c3X), SWI, IDLE, IDLE2, RETIcD, - TRAPc, LATc, LDEP, LDEHI, LDEPE, LDPK, STIK, LDP, IACK -*/ - - -/* Define tic4x opcodes for assembler and disassembler. */ -static const tic4x_inst_t tic4x_insts[] = -{ - /* Put synonyms after the desired forms in table so that they get - overwritten in the lookup table. The disassembler will thus - print the `proper' mnemonics. Note that the disassembler - only decodes the 11 MSBs, so instructions like ldp @0x500 will - be printed as ldiu 5, dp. Note that with parallel instructions, - the second part is executed before the first part, unless - the sti1||sti2 form is used. We also allow sti2||sti1 - which is equivalent to the default sti||sti form. - */ - B_CLASS_INSN( "absf", 0x00000000, OP_C3X ), - P_CLASS_INSN( "absf", "stf", 0xc8000000, OP_C3X ), - A_CLASS_INSN( "absi", 0x00800000, OP_C3X ), - P_CLASS_INSN( "absi", "sti", 0xca000000, OP_C3X ), - A_CLASS_INSN( "addc", 0x01000000, OP_C3X ), - TC_CLASS_INSN( "addc", 0x00000000, OP_C3X ), - B_CLASS_INSN( "addf", 0x01800000, OP_C3X ), - SC_CLASS_INSN( "addf", 0x00800000, OP_C3X ), - QC_CLASS_INSN( "addf", "stf", 0xcc000000, OP_C3X ), - A_CLASS_INSN( "addi", 0x02000000, OP_C3X ), - TC_CLASS_INSN( "addi", 0x01000000, OP_C3X ), - QC_CLASS_INSN( "addi", "sti", 0xce000000, OP_C3X ), - AU_CLASS_INSN( "and", 0x02800000, OP_C3X ), - TC_CLASS_INSN( "and", 0x01800000, OP_C3X ), - QC_CLASS_INSN( "and", "sti", 0xd0000000, OP_C3X ), - AU_CLASS_INSN( "andn", 0x03000000, OP_C3X ), - T_CLASS_INSN( "andn", 0x02000000, OP_C3X ), - A_CLASS_INSN( "ash", 0x03800000, OP_C3X ), - T_CLASS_INSN( "ash", 0x02800000, OP_C3X ), - Q_CLASS_INSN( "ash", "sti", 0xd2000000, OP_C3X ), - J_CLASS_INSN( "bB", "b", 0x68000000, OP_C3X ), - J_CLASS_INSN( "bBd", "bd", 0x68200000, OP_C3X ), - J_CLASS_INSN( "bBaf", "baf", 0x68a00000, OP_C4X ), - J_CLASS_INSN( "bBat", "bat", 0x68600000, OP_C4X ), - { "br", 0x60000000, 0xff000000, "B" , OP_C3X }, /* I_CLASS */ - { "brd", 0x61000000, 0xff000000, "B" , OP_C3X }, /* I_CLASS */ - { "call", 0x62000000, 0xff000000, "B" , OP_C3X }, /* I_CLASS */ - { "callB", 0x70000000, 0xffe00000, "Q" , OP_C3X }, /* JS_CLASS */ - { "callB", 0x72000000, 0xffe00000, "P" , OP_C3X }, /* JS_CLASS */ - B_CLASS_INSN( "cmpf", 0x04000000, OP_C3X ), - S2_CLASS_INSN( "cmpf", 0x03000000, OP_C3X ), - A_CLASS_INSN( "cmpi", 0x04800000, OP_C3X ), - T2_CLASS_INSN( "cmpi", 0x03800000, OP_C3X ), - D_CLASS_INSN( "dbB", "db", 0x6c000000, OP_C3X ), - D_CLASS_INSN( "dbBd", "dbd", 0x6c200000, OP_C3X ), - AF_CLASS_INSN( "fix", 0x05000000, OP_C3X ), - P_CLASS_INSN( "fix", "sti", 0xd4000000, OP_C3X ), - BI_CLASS_INSN( "float", 0x05800000, OP_C3X ), - P_CLASS_INSN( "float", "stf", 0xd6000000, OP_C3X ), - B6_CLASS_INSN( "frieee", 0x1c000000, OP_C4X ), - P_CLASS_INSN( "frieee","stf", 0xf2000000, OP_C4X ), - { "iack", 0x1b200000, 0xffe00000, "@" , OP_C3X }, /* Z_CLASS */ - { "iack", 0x1b400000, 0xffe00000, "*" , OP_C3X }, /* Z_CLASS */ - { "idle", 0x06000000, 0xffffffff, "" , OP_C3X }, /* Z_CLASS */ - { "idlez", 0x06000000, 0xffffffff, "" , OP_C3X }, /* Z_CLASS */ - { "idle2", 0x06000001, 0xffffffff, "" , OP_IDLE2 }, /* Z_CLASS */ - { "laj", 0x63000000, 0xff000000, "B" , OP_C4X }, /* I_CLASS */ - { "lajB", 0x70200000, 0xffe00000, "Q" , OP_C4X }, /* JS_CLASS */ - { "lajB", 0x72200000, 0xffe00000, "P" , OP_C4X }, /* JS_CLASS */ - { "latB", 0x74800000, 0xffe00000, "V" , OP_C4X }, /* Z_CLASS */ - A_CLASS_INSN( "lb0", 0xb0000000, OP_C4X ), - A_CLASS_INSN( "lb1", 0xb0800000, OP_C4X ), - A_CLASS_INSN( "lb2", 0xb1000000, OP_C4X ), - A_CLASS_INSN( "lb3", 0xb1800000, OP_C4X ), - AU_CLASS_INSN( "lbu0", 0xb2000000, OP_C4X ), - AU_CLASS_INSN( "lbu1", 0xb2800000, OP_C4X ), - AU_CLASS_INSN( "lbu2", 0xb3000000, OP_C4X ), - AU_CLASS_INSN( "lbu3", 0xb3800000, OP_C4X ), - AY_CLASS_INSN( "lda", 0x1e800000, OP_C4X ), - B_CLASS_INSN( "lde", 0x06800000, OP_C3X ), - { "ldep", 0x76000000, 0xffe00000, "X,R" , OP_C4X }, /* Z_CLASS */ - B_CLASS_INSN( "ldf", 0x07000000, OP_C3X ), - LL_CLASS_INSN( "ldf", 0xc4000000, OP_C3X ), - P_CLASS_INSN( "ldf", "stf", 0xd8000000, OP_C3X ), - BB_CLASS_INSN( "ldfC", 0x00000000, OP_C3X ), - B6_CLASS_INSN( "ldfi", 0x07800000, OP_C3X ), - { "ldhi", 0x1fe00000, 0xffe00000, "U,R" , OP_C4X }, /* Z_CLASS */ - { "ldhi", 0x1fe00000, 0xffe00000, "#,R" , OP_C4X }, /* Z_CLASS */ - A_CLASS_INSN( "ldi", 0x08000000, OP_C3X ), - LL_CLASS_INSN( "ldi", 0xc6000000, OP_C3X ), - P_CLASS_INSN( "ldi", "sti", 0xda000000, OP_C3X ), - AB_CLASS_INSN( "ldiC", 0x10000000, OP_C3X ), - A6_CLASS_INSN( "ldii", 0x08800000, OP_C3X ), - { "ldp", 0x50700000, 0xffff0000, "#" , OP_C3X }, /* Z_CLASS - synonym for ldiu #,dp */ - B_CLASS_INSN( "ldm", 0x09000000, OP_C3X ), - { "ldpe", 0x76800000, 0xffe00000, "Q,Z" , OP_C4X }, /* Z_CLASS */ - { "ldpk", 0x1F700000, 0xffff0000, "#" , OP_C4X }, /* Z_CLASS */ - A_CLASS_INSN( "lh0", 0xba000000, OP_C4X ), - A_CLASS_INSN( "lh1", 0xba800000, OP_C4X ), - AU_CLASS_INSN( "lhu0", 0xbb000000, OP_C4X ), - AU_CLASS_INSN( "lhu1", 0xbb800000, OP_C4X ), - { "lopower", 0x10800001,0xffffffff, "" , OP_LPWR }, /* Z_CLASS */ - A_CLASS_INSN( "lsh", 0x09800000, OP_C3X ), - T_CLASS_INSN( "lsh", 0x04000000, OP_C3X ), - Q_CLASS_INSN( "lsh", "sti", 0xdc000000, OP_C3X ), - A_CLASS_INSN( "lwl0", 0xb4000000, OP_C4X ), - A_CLASS_INSN( "lwl1", 0xb4800000, OP_C4X ), - A_CLASS_INSN( "lwl2", 0xb5000000, OP_C4X ), - A_CLASS_INSN( "lwl3", 0xb5800000, OP_C4X ), - A_CLASS_INSN( "lwr0", 0xb6000000, OP_C4X ), - A_CLASS_INSN( "lwr1", 0xb6800000, OP_C4X ), - A_CLASS_INSN( "lwr2", 0xb7000000, OP_C4X ), - A_CLASS_INSN( "lwr3", 0xb7800000, OP_C4X ), - { "maxspeed",0x10800000,0xffffffff, "" , OP_LPWR }, /* Z_CLASS */ - A_CLASS_INSN( "mb0", 0xb8000000, OP_C4X ), - A_CLASS_INSN( "mb1", 0xb8800000, OP_C4X ), - A_CLASS_INSN( "mb2", 0xb9000000, OP_C4X ), - A_CLASS_INSN( "mb3", 0xb9800000, OP_C4X ), - A_CLASS_INSN( "mh0", 0xbc000000, OP_C4X ), - A_CLASS_INSN( "mh1", 0xbc800000, OP_C4X ), - A_CLASS_INSN( "mh2", 0xbd000000, OP_C4X ), - A_CLASS_INSN( "mh3", 0xbd800000, OP_C4X ), - B_CLASS_INSN( "mpyf", 0x0a000000, OP_C3X ), - SC_CLASS_INSN( "mpyf", 0x04800000, OP_C3X ), - M_CLASS_INSN( "mpyf", "addf", 0x80000000, OP_C3X ), - QC_CLASS_INSN( "mpyf", "stf", 0xde000000, OP_C3X ), - M_CLASS_INSN( "mpyf", "subf", 0x84000000, OP_C3X ), - A_CLASS_INSN( "mpyi", 0x0a800000, OP_C3X ), - TC_CLASS_INSN( "mpyi", 0x05000000, OP_C3X ), - M_CLASS_INSN( "mpyi", "addi", 0x88000000, OP_C3X ), - QC_CLASS_INSN( "mpyi", "sti", 0xe0000000, OP_C3X ), - M_CLASS_INSN( "mpyi", "subi", 0x8c000000, OP_C3X ), - A_CLASS_INSN( "mpyshi", 0x1d800000, OP_C4X ), - TC_CLASS_INSN( "mpyshi", 0x28800000, OP_C4X ), - A_CLASS_INSN( "mpyuhi", 0x1e000000, OP_C4X ), - TC_CLASS_INSN( "mpyuhi", 0x29000000, OP_C4X ), - A_CLASS_INSN( "negb", 0x0b000000, OP_C3X ), - B_CLASS_INSN( "negf", 0x0b800000, OP_C3X ), - P_CLASS_INSN( "negf", "stf", 0xe2000000, OP_C3X ), - A_CLASS_INSN( "negi", 0x0c000000, OP_C3X ), - P_CLASS_INSN( "negi", "sti", 0xe4000000, OP_C3X ), - A2_CLASS_INSN( "nop", 0x0c800000, OP_C3X ), - B_CLASS_INSN( "norm", 0x0d000000, OP_C3X ), - AU_CLASS_INSN( "not", 0x0d800000, OP_C3X ), - P_CLASS_INSN( "not", "sti", 0xe6000000, OP_C3X ), - AU_CLASS_INSN( "or", 0x10000000, OP_C3X ), - TC_CLASS_INSN( "or", 0x05800000, OP_C3X ), - QC_CLASS_INSN( "or", "sti", 0xe8000000, OP_C3X ), - R_CLASS_INSN( "pop", 0x0e200000, OP_C3X ), - RF_CLASS_INSN( "popf", 0x0ea00000, OP_C3X ), - R_CLASS_INSN( "push", 0x0f200000, OP_C3X ), - RF_CLASS_INSN( "pushf", 0x0fa00000, OP_C3X ), - BA_CLASS_INSN( "rcpf", 0x1d000000, OP_C4X ), - { "retiB", 0x78000000, 0xffe00000, "" , OP_C3X }, /* Z_CLASS */ - { "reti", 0x78000000, 0xffe00000, "" , OP_C3X }, /* Z_CLASS - Alias for retiu */ - { "retiBd", 0x78200000, 0xffe00000, "" , OP_C4X }, /* Z_CLASS */ - { "retid", 0x78200000, 0xffe00000, "" , OP_C4X }, /* Z_CLASS - Alias for retiud */ - { "retsB", 0x78800000, 0xffe00000, "" , OP_C3X }, /* Z_CLASS */ - { "rets", 0x78800000, 0xffe00000, "" , OP_C3X }, /* Z_CLASS - Alias for retsu */ - B_CLASS_INSN( "rnd", 0x11000000, OP_C3X ), - R_CLASS_INSN( "rol", 0x11e00001, OP_C3X ), - R_CLASS_INSN( "rolc", 0x12600001, OP_C3X ), - R_CLASS_INSN( "ror", 0x12e0ffff, OP_C3X ), - R_CLASS_INSN( "rorc", 0x1360ffff, OP_C3X ), - { "rptb", 0x64000000, 0xff000000, "B" , OP_C3X }, /* I2_CLASS */ - { "rptb", 0x79000000, 0xff000000, "Q" , OP_C4X }, /* I2_CLASS */ - { "rptbd", 0x65000000, 0xff000000, "B" , OP_C4X }, /* I2_CLASS */ - { "rptbd", 0x79800000, 0xff000000, "Q" , OP_C4X }, /* I2_CLASS */ - A3_CLASS_INSN( "rpts", 0x139b0000, OP_C3X ), - B_CLASS_INSN( "rsqrf", 0x1c800000, OP_C4X ), - { "sigi", 0x16000000, 0xffe00000, "" , OP_C3X }, /* Z_CLASS */ - A6_CLASS_INSN( "sigi", 0x16000000, OP_C4X ), - B7_CLASS_INSN( "stf", 0x14000000, OP_C3X ), - LS_CLASS_INSN( "stf", 0xc0000000, OP_C3X ), - B7_CLASS_INSN( "stfi", 0x14800000, OP_C3X ), - A7_CLASS_INSN( "sti", 0x15000000, OP_C3X ), - { "sti", 0x15000000, 0xffe00000, "T,@" , OP_C4X }, /* Class A7 - Alias for stik */ - { "sti", 0x15600000, 0xffe00000, "T,*" , OP_C4X }, /* Class A7 */ - LS_CLASS_INSN( "sti", 0xc2000000, OP_C3X ), - A7_CLASS_INSN( "stii", 0x15800000, OP_C3X ), - { "stik", 0x15000000, 0xffe00000, "T,@" , OP_C4X }, /* Z_CLASS */ - { "stik", 0x15600000, 0xffe00000, "T,*" , OP_C4X }, /* Z_CLASS */ - A_CLASS_INSN( "subb", 0x16800000, OP_C3X ), - T_CLASS_INSN( "subb", 0x06000000, OP_C3X ), - A_CLASS_INSN( "subc", 0x17000000, OP_C3X ), - B_CLASS_INSN( "subf", 0x17800000, OP_C3X ), - S_CLASS_INSN( "subf", 0x06800000, OP_C3X ), - Q_CLASS_INSN( "subf", "stf", 0xea000000, OP_C3X ), - A_CLASS_INSN( "subi", 0x18000000, OP_C3X ), - T_CLASS_INSN( "subi", 0x07000000, OP_C3X ), - Q_CLASS_INSN( "subi", "sti", 0xec000000, OP_C3X ), - A_CLASS_INSN( "subrb", 0x18800000, OP_C3X ), - B_CLASS_INSN( "subrf", 0x19000000, OP_C3X ), - A_CLASS_INSN( "subri", 0x19800000, OP_C3X ), - { "swi", 0x66000000, 0xffffffff, "" , OP_C3X }, /* Z_CLASS */ - B_CLASS_INSN( "toieee", 0x1b800000, OP_C4X ), - P_CLASS_INSN( "toieee","stf", 0xf0000000, OP_C4X ), - { "trapB", 0x74000000, 0xffe00000, "V" , OP_C3X }, /* Z_CLASS */ - { "trap", 0x74000000, 0xffe00000, "V" , OP_C3X }, /* Z_CLASS - Alias for trapu */ - AU_CLASS_INSN( "tstb", 0x1a000000, OP_C3X ), - T2C_CLASS_INSN("tstb", 0x07800000, OP_C3X ), - AU_CLASS_INSN( "xor", 0x1a800000, OP_C3X ), - TC_CLASS_INSN( "xor", 0x08000000, OP_C3X ), - QC_CLASS_INSN( "xor", "sti", 0xee000000, OP_C3X ), - - /* Dummy entry, not included in tic4x_num_insts. This - lets code examine entry i + 1 without checking - if we've run off the end of the table. */ - { "", 0x0, 0x00, "", 0 } -}; - -const unsigned int tic4x_num_insts = (((sizeof tic4x_insts) / (sizeof tic4x_insts[0])) - 1); diff --git a/include/opcode/tic54x.h b/include/opcode/tic54x.h deleted file mode 100644 index f468714..0000000 --- a/include/opcode/tic54x.h +++ /dev/null @@ -1,163 +0,0 @@ -/* tic54x.h -- Header file for TI TMS320C54X opcode table - Copyright 1999, 2000, 2001, 2005, 2009, 2010 Free Software Foundation, Inc. - Written by Timothy Wall (twall@cygnus.com) - - This file is part of GDB, GAS, and the GNU binutils. - - GDB, GAS, and the GNU binutils are free software; you can redistribute - them and/or modify them under the terms of the GNU General Public - License as published by the Free Software Foundation; either version 3, - or (at your option) any later version. - - GDB, GAS, and the GNU binutils are distributed in the hope that they - will be useful, but WITHOUT ANY WARRANTY; without even the implied - warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See - the GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this file; see the file COPYING3. If not, write to the Free - Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA - 02110-1301, USA. */ - -#ifndef _opcode_tic54x_h_ -#define _opcode_tic54x_h_ - -typedef struct _symbol -{ - const char *name; - unsigned short value; -} symbol; - -enum optype { - OPT = 0x8000, - OP_None = 0x0, - - OP_Xmem, /* AR3 or AR4, indirect */ - OP_Ymem, /* AR3 or AR4, indirect */ - OP_pmad, /* PROG mem, direct */ - OP_dmad, /* DATA mem, direct */ - OP_Smem, - OP_Lmem, /* 32-bit single-addressed (direct/indirect) */ - OP_MMR, - OP_PA, - OP_Sind, - OP_xpmad, - OP_xpmad_ms7, - OP_MMRX, - OP_MMRY, - - OP_SRC1, /* src accumulator in bit 8 */ - OP_SRC, /* src accumulator in bit 9 */ - OP_RND, /* rounded result dst accumulator, opposite of bit 8 */ - OP_DST, /* dst accumulator in bit 8 */ - OP_ARX, /* arX in bits 0-3 */ - OP_SHIFT, /* -16 to 15 (SHIFT), bits 0-4 */ - OP_SHFT, /* 0 to 15 (SHIFT1 in summary), bits 0-3 */ - OP_B, /* ACC B only */ - OP_A, /* ACC A only */ - - OP_lk, /* 16-bit immediate, '#' optional */ - OP_TS, - OP_k8, /* -128 <= k <= 128 */ - OP_16, /* literal "16" */ - OP_BITC, /* 0 to 16 */ - OP_CC, /* condition code */ - OP_CC2, /* 4-bit condition code */ - OP_CC3, /* 2-bit condition code */ - OP_123, /* 1, 2, or 3 */ - OP_031, /* 0-31, numeric */ - OP_k5, /* 0 to 31 */ - OP_k8u, /* 0 to 255 */ - OP_ASM, /* "ASM" */ - OP_T, /* "T" */ - OP_DP, /* "DP" */ - OP_ARP, /* "ARP" */ - OP_k3, /* 0-7 */ - OP_lku, /* 0 to 65535 */ - OP_N, /* 0/1 or ST0/ST1 */ - OP_SBIT, /* status bit or 0-15 */ - OP_12, /* one or two */ - OP_k9, /* 9 bits of data page (DP) address */ - OP_TRN, /* "TRN" */ - -}; - -typedef struct _template -{ - /* The opcode mnemonic */ - const char *name; - unsigned int words; /* insn size in words */ - int minops, maxops; /* min/max operand count */ - /* The significant bits in the opcode. Other bits are zero. - Instructions with more than 16 bits of opcode store the rest in the upper - 16 bits. - */ - unsigned short opcode; -#define INDIRECT(OP) ((OP)&0x80) -#define MOD(OP) (((OP)>>3)&0xF) -#define ARF(OP) ((OP)&0x7) -#define IS_LKADDR(OP) (INDIRECT(OP) && MOD(OP)>=12) -#define SRC(OP) ((OP)&0x200) -#define DST(OP) ((OP)&0x100) -#define SRC1(OP) ((OP)&0x100) -#define SHIFT(OP) (((OP)&0x10)?(((OP)&0x1F)-32):((OP)&0x1F)) -#define SHFT(OP) ((OP)&0xF) -#define ARX(OP) ((OP)&0x7) -#define XMEM(OP) (((OP)&0x00F0)>>4) -#define YMEM(OP) ((OP)&0x000F) -#define XMOD(C) (((C)&0xC)>>2) -#define XARX(C) (((C)&0x3)+2) -#define CC3(OP) (((OP)>>8)&0x3) -#define SBIT(OP) ((OP)&0xF) -#define MMR(OP) ((OP)&0x7F) -#define MMRX(OP) ((((OP)>>4)&0xF)+16) -#define MMRY(OP) (((OP)&0xF)+16) - -#define OPTYPE(X) ((X)&~OPT) - - /* Ones in this mask indicate which bits must match the opcode field. - Zeroes indicate don't care bits (operands and/or opcode options) */ - unsigned short mask; - - /* An array of operand codes (at most 4 operands) */ -#define MAX_OPERANDS 4 - enum optype operand_types[MAX_OPERANDS]; - - /* Special purpose flags (e.g. branch type, parallel, delay, etc) - */ - unsigned short flags; -#define B_NEXT 0 /* normal execution, next insn is next address */ -#define B_BRANCH 1 /* next insn is in opcode */ -#define B_RET 2 /* next insn is on stack */ -#define B_BACC 3 /* next insn is in acc */ -#define B_REPEAT 4 /* next insn repeats */ -#define FL_BMASK 0x07 - -#define FL_DELAY 0x10 /* instruction uses delay slots */ -#define FL_EXT 0x20 /* instruction takes two words */ -#define FL_FAR 0x40 /* far mode addressing */ -#define FL_LP 0x80 /* LP-only instruction */ -#define FL_NR 0x100 /* no repeat allowed */ -#define FL_SMR 0x200 /* Smem read (for flagging write-only *+ARx */ - -#define FL_PAR 0x400 /* Parallel instruction. */ - - unsigned short opcode2, mask2; /* some insns have an extended opcode */ - - const char* parname; - enum optype paroperand_types[MAX_OPERANDS]; - -} insn_template; - -extern const insn_template tic54x_unknown_opcode; -extern const insn_template tic54x_optab[]; -extern const insn_template tic54x_paroptab[]; -extern const symbol mmregs[], regs[]; -extern const symbol condition_codes[], cc2_codes[], status_bits[]; -extern const symbol cc3_codes[]; -extern const char *misc_symbols[]; -struct disassemble_info; -extern const insn_template* tic54x_get_insn (struct disassemble_info *, - bfd_vma, unsigned short, int *); - -#endif /* _opcode_tic54x_h_ */ diff --git a/include/opcode/tic6x-control-registers.h b/include/opcode/tic6x-control-registers.h deleted file mode 100644 index b438777..0000000 --- a/include/opcode/tic6x-control-registers.h +++ /dev/null @@ -1,56 +0,0 @@ -/* TI C6X control register information. - Copyright 2010 - Free Software Foundation, Inc. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, - MA 02110-1301, USA. */ - -/* Define the CTRL macro before including this file; it takes as - arguments the fields from tic6x_ctrl (defined in tic6x.h). The - control register name is given as an identifier; the isa_variants - field without the leading TIC6X_INSN_; the rw field without the - leading tic6x_rw_. */ - -CTRL(amr, C62X, read_write, 0x0, 0x10) -CTRL(csr, C62X, read_write, 0x1, 0x10) -CTRL(dnum, C64XP, read, 0x11, 0x1f) -CTRL(ecr, C64XP, write, 0x1d, 0x1f) -CTRL(efr, C64XP, read, 0x1d, 0x1f) -CTRL(fadcr, C67X, read_write, 0x12, 0x1f) -CTRL(faucr, C67X, read_write, 0x13, 0x1f) -CTRL(fmcr, C67X, read_write, 0x14, 0x1f) -CTRL(gfpgfr, C64X, read_write, 0x18, 0x1f) -CTRL(gplya, C64XP, read_write, 0x16, 0x1f) -CTRL(gplyb, C64XP, read_write, 0x17, 0x1f) -CTRL(icr, C62X, write, 0x3, 0x10) -CTRL(ier, C62X, read_write, 0x4, 0x10) -CTRL(ierr, C64XP, read_write, 0x1f, 0x1f) -CTRL(ifr, C62X, read, 0x2, 0x1d) -CTRL(ilc, C64XP, read_write, 0xd, 0x1f) -CTRL(irp, C62X, read_write, 0x6, 0x10) -CTRL(isr, C62X, write, 0x2, 0x10) -CTRL(istp, C62X, read_write, 0x5, 0x10) -CTRL(itsr, C64XP, read_write, 0x1b, 0x1f) -CTRL(nrp, C62X, read_write, 0x7, 0x10) -CTRL(ntsr, C64XP, read_write, 0x1c, 0x1f) -CTRL(pce1, C62X, read, 0x10, 0xf) -CTRL(rep, C64XP, read_write, 0xf, 0x1f) -CTRL(rilc, C64XP, read_write, 0xe, 0x1f) -CTRL(ssr, C64XP, read_write, 0x15, 0x1f) -CTRL(tsch, C64XP, read, 0xb, 0x1f) -/* Contrary to Table 3-26 in SPRUFE8, this register is read-write, as - documented in section 2.9.13. */ -CTRL(tscl, C64XP, read_write, 0xa, 0x1f) -CTRL(tsr, C64XP, read_write, 0x1a, 0x1f) diff --git a/include/opcode/tic6x-insn-formats.h b/include/opcode/tic6x-insn-formats.h deleted file mode 100644 index 80bc9fa..0000000 --- a/include/opcode/tic6x-insn-formats.h +++ /dev/null @@ -1,616 +0,0 @@ -/* TI C6X instruction format information. - Copyright 2010-2013 Free Software Foundation, Inc. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, - MA 02110-1301, USA. */ - -/* Define the FMT macro before including this file; it takes a name - and the fields from tic6x_insn_format (defined in tic6x.h). */ - -/* Expansion fields values for 16 bits insn. */ -#define SAT(a) (((a) & 1) << TIC6X_COMPACT_SAT_POS) -#define BR(a) (((a) & 1) << TIC6X_COMPACT_BR_POS) -#define DSZ(a) (((a) & 7) << TIC6X_COMPACT_DSZ_POS) -/* Composite fields for 16 bits insn. */ -#define BFLD(low_pos, width, pos) { (low_pos), (width), (pos) } -#define BFLD1(a) 1, { a } -#define BFLD2(a, b) 2, { a, b } -#define BFLD3(a, b, c) 3, { a, b, c } -#define BFLD4(a, b, c, d) 4, { a, b, c, d } -#define COMPFLD(name, bitfields) { CONCAT2(tic6x_field_,name), bitfields } -/**/ -#define FLD(name, pos, width) { CONCAT2(tic6x_field_,name), BFLD1(BFLD(pos, width, 0)) } -#define CFLDS FLD(p, 0, 1), FLD(creg, 29, 3), FLD(z, 28, 1) -#define CFLDS2(a, b) 5, { CFLDS, a, b } -#define CFLDS3(a, b, c) 6, { CFLDS, a, b, c } -#define CFLDS4(a, b, c, d) 7, { CFLDS, a, b, c, d } -#define CFLDS5(a, b, c, d, e) 8, { CFLDS, a, b, c, d, e } -#define CFLDS6(a, b, c, d, e, f) 9, { CFLDS, a, b, c, d, e, f } -#define CFLDS7(a, b, c, d, e, f, g) 10, { CFLDS, a, b, c, d, e, f, g } -#define CFLDS8(a, b, c, d, e, f, g, h) 11, { CFLDS, a, b, c, d, e, f, g, h } -#define NFLDS FLD(p, 0, 1) -#define NFLDS1(a) 2, { NFLDS, a } -#define NFLDS2(a, b) 3, { NFLDS, a, b } -#define NFLDS3(a, b, c) 4, { NFLDS, a, b, c } -#define NFLDS5(a, b, c, d, e) 6, { NFLDS, a, b, c, d, e } -#define NFLDS6(a, b, c, d, e, f) 7, { NFLDS, a, b, c, d, e, f } -#define NFLDS7(a, b, c, d, e, f, g) 8, { NFLDS, a, b, c, d, e, f, g } -/* 16 bits insn */ -#define FLDS1(a) 1, { a } -#define FLDS2(a, b) 2, { a, b } -#define FLDS3(a, b, c) 3, { a, b, c } -#define FLDS4(a, b, c, d) 4, { a, b, c, d } -#define FLDS5(a, b, c, d, e) 5, { a, b, c, d, e } -#define SFLDS FLD(s, 0, 1) -#define SFLDS1(a) 2, { SFLDS, a } -#define SFLDS2(a, b) 3, { SFLDS, a, b } -#define SFLDS3(a, b, c) 4, { SFLDS, a, b, c } -#define SFLDS4(a, b, c, d) 5, { SFLDS, a, b, c, d } -#define SFLDS5(a, b, c, d, e) 6, { SFLDS, a, b, c, d, e } -#define SFLDS6(a, b, c, d, e, f) 7, { SFLDS, a, b, c, d, e, f } -#define SFLDS7(a, b, c, d, e, f, g) 8, { SFLDS, a, b, c, d, e, f, g } -/**/ - -/* These are in the order from SPRUFE8, appendices C-H. */ - -/* Appendix C 32-bit formats. */ - -FMT(d_1_or_2_src, 32, 0x40, 0x7c, - CFLDS5(FLD(s, 1, 1), FLD(op, 7, 6), FLD(src1, 13, 5), FLD(src2, 18, 5), - FLD(dst, 23, 5))) -FMT(d_ext_1_or_2_src, 32, 0x830, 0xc3c, - CFLDS6(FLD(s, 1, 1), FLD(op, 6, 4), FLD(x, 12, 1), FLD(src1, 13, 5), - FLD(src2, 18, 5), FLD(dst, 23, 5))) -FMT(d_load_store, 32, 0x4, 0xc, - CFLDS8(FLD(s, 1, 1), FLD(op, 4, 3), FLD(y, 7, 1), FLD(r, 8, 1), - FLD(mode, 9, 4), FLD(offsetR, 13, 5), FLD(baseR, 18, 5), - FLD(srcdst, 23, 5))) -/* The nonaligned loads and stores have the formats shown in the - individual instruction descriptions; the appendix is incorrect. */ -FMT(d_load_nonaligned, 32, 0x124, 0x17c, - CFLDS7(FLD(s, 1, 1), FLD(y, 7, 1), FLD(mode, 9, 4), FLD(offsetR, 13, 5), - FLD(baseR, 18, 5), FLD(sc, 23, 1), FLD(dst, 24, 4))) -FMT(d_store_nonaligned, 32, 0x174, 0x17c, - CFLDS7(FLD(s, 1, 1), FLD(y, 7, 1), FLD(mode, 9, 4), FLD(offsetR, 13, 5), - FLD(baseR, 18, 5), FLD(sc, 23, 1), FLD(src, 24, 4))) -FMT(d_load_store_long, 32, 0xc, 0xc, - CFLDS5(FLD(s, 1, 1), FLD(op, 4, 3), FLD(y, 7, 1), FLD(offsetR, 8, 15), - FLD(dst, 23, 5))) -FMT(d_adda_long, 32, 0x1000000c, 0xf000000c, - NFLDS5(FLD(s, 1, 1), FLD(op, 4, 3), FLD(y, 7, 1), FLD(offsetR, 8, 15), - FLD(dst, 23, 5))) - -/* Appendix C 16-bit formats will go here. */ - -/* C-8 */ -FMT(d_doff4_dsz_0xx, 16, DSZ(0) | 0x0004, DSZ(0x4) | 0x0406, - SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), FLD(t, 12, 1), - COMPFLD(cst, BFLD2(BFLD(13, 3, 0), BFLD(11, 1, 3))))) -FMT(d_doff4_dsz_100, 16, DSZ(4) | 0x0004, DSZ(0x7) | 0x0406, - SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), FLD(t, 12, 1), - COMPFLD(cst, BFLD2(BFLD(13, 3, 0), BFLD(11, 1, 3))))) -FMT(d_doff4_dsz_000, 16, DSZ(0) | 0x0004, DSZ(0x7) | 0x0406, - SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), FLD(t, 12, 1), - COMPFLD(cst, BFLD2(BFLD(13, 3, 0), BFLD(11, 1, 3))))) -FMT(d_doff4_dsz_x01, 16, DSZ(1) | 0x0004, DSZ(0x3) | 0x0406, - SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), FLD(t, 12, 1), - COMPFLD(cst, BFLD2(BFLD(13, 3, 0), BFLD(11, 1, 3))))) -FMT(d_doff4_dsz_01x, 16, DSZ(2) | 0x0004, DSZ(0x6) | 0x0406, - SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), FLD(t, 12, 1), - COMPFLD(cst, BFLD2(BFLD(13, 3, 0), BFLD(11, 1, 3))))) -FMT(d_doff4_dsz_111, 16, DSZ(7) | 0x0004, DSZ(0x7) | 0x0406, - SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), FLD(t, 12, 1), - COMPFLD(cst, BFLD2(BFLD(13, 3, 0), BFLD(11, 1, 3))))) -FMT(d_doff4_dsz_x11, 16, DSZ(3) | 0x0004, DSZ(0x3) | 0x0406, - SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), FLD(t, 12, 1), - COMPFLD(cst, BFLD2(BFLD(13, 3, 0), BFLD(11, 1, 3))))) -FMT(d_doff4_dsz_010, 16, DSZ(2) | 0x0004, DSZ(0x7) | 0x0406, - SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), FLD(t, 12, 1), - COMPFLD(cst, BFLD2(BFLD(13, 3, 0), BFLD(11, 1, 3))))) -FMT(d_doff4_dsz_110, 16, DSZ(6) | 0x0004, DSZ(0x7) | 0x0406, - SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), FLD(t, 12, 1), - COMPFLD(cst, BFLD2(BFLD(13, 3, 0), BFLD(11, 1, 3))))) - -/* C-9 */ -FMT(d_doff4dw, 16, DSZ(4) | 0x0004, DSZ(0x4) | 0x0406, - SFLDS7(FLD(op, 3, 1), FLD(na, 4, 1), FLD(srcdst, 5, 2), FLD(ptr, 7, 2), FLD(sz, 9, 1), FLD(t, 12, 1), - COMPFLD(cst, BFLD2(BFLD(13, 3, 0), BFLD(11, 1, 3))))) - -/* C-10 */ -FMT(d_dind_dsz_0xx, 16, DSZ(0) | 0x0404, DSZ(0x4) | 0x0c06, - SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), - FLD(t, 12, 1), FLD(src1, 13, 3))) - -FMT(d_dind_dsz_x01, 16, DSZ(1) | 0x0404, DSZ(0x3) | 0x0c06, - SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), - FLD(t, 12, 1), FLD(src1, 13, 3))) - -FMT(d_dind_dsz_x11, 16, DSZ(3) | 0x0404, DSZ(0x3) | 0x0c06, - SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), - FLD(t, 12, 1), FLD(src1, 13, 3))) - -FMT(d_dind_dsz_01x, 16, DSZ(2) | 0x0404, DSZ(0x6) | 0x0c06, - SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), - FLD(t, 12, 1), FLD(src1, 13, 3))) - -FMT(d_dind_dsz_000, 16, DSZ(0) | 0x0404, DSZ(0x7) | 0x0c06, - SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), - FLD(t, 12, 1), FLD(src1, 13, 3))) - -FMT(d_dind_dsz_010, 16, DSZ(2) | 0x0404, DSZ(0x7) | 0x0c06, - SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), - FLD(t, 12, 1), FLD(src1, 13, 3))) - -FMT(d_dind_dsz_100, 16, DSZ(4) | 0x0404, DSZ(0x7) | 0x0c06, - SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), - FLD(t, 12, 1), FLD(src1, 13, 3))) - -FMT(d_dind_dsz_110, 16, DSZ(6) | 0x0404, DSZ(0x7) | 0x0c06, - SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), - FLD(t, 12, 1), FLD(src1, 13, 3))) - -FMT(d_dind_dsz_111, 16, DSZ(7) | 0x0404, DSZ(0x7) | 0x0c06, - SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), - FLD(t, 12, 1), FLD(src1, 13, 3))) - -/* C-11 */ -FMT(d_dinddw, 16, DSZ(4) | 0x0404, DSZ(0x4) | 0x0c06, - SFLDS7(FLD(op, 3, 1), FLD(na, 4, 1), FLD(srcdst, 5, 2), FLD(ptr, 7, 2), - FLD(sz, 9, 1), FLD(t, 12, 1), FLD(src1, 13, 3))) - -/* C-12 */ -FMT(d_dinc_dsz_x01, 16, DSZ(1) | 0x0c04, DSZ(0x3) | 0xcc06, - SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), - FLD(t, 12, 1), FLD(cst, 13, 1))) - -FMT(d_dinc_dsz_0xx, 16, DSZ(0) | 0x0c04, DSZ(0x4) | 0xcc06, - SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), - FLD(t, 12, 1), FLD(cst, 13, 1))) - -FMT(d_dinc_dsz_01x, 16, DSZ(2) | 0x0c04, DSZ(0x6) | 0xcc06, - SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), - FLD(t, 12, 1), FLD(cst, 13, 1))) - -FMT(d_dinc_dsz_x11,16, DSZ(3) | 0x0c04, DSZ(0x3) | 0xcc06, - SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), - FLD(t, 12, 1), FLD(cst, 13, 1))) - -FMT(d_dinc_dsz_000, 16, DSZ(0) | 0x0c04, DSZ(0x7) | 0xcc06, - SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), - FLD(t, 12, 1), FLD(cst, 13, 1))) - -FMT(d_dinc_dsz_010, 16, DSZ(2) | 0x0c04, DSZ(0x7) | 0xcc06, - SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), - FLD(t, 12, 1), FLD(cst, 13, 1))) - -FMT(d_dinc_dsz_100, 16, DSZ(4) | 0x0c04, DSZ(0x7) | 0xcc06, - SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), - FLD(t, 12, 1), FLD(cst, 13, 1))) - -FMT(d_dinc_dsz_110, 16, DSZ(6) | 0x0c04, DSZ(0x7) | 0xcc06, - SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), - FLD(t, 12, 1), FLD(cst, 13, 1))) - -FMT(d_dinc_dsz_111, 16, DSZ(7) | 0x0c04, DSZ(0x7) | 0xcc06, - SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), - FLD(t, 12, 1), FLD(cst, 13, 1))) - -/* C-13*/ -FMT(d_dincdw, 16, DSZ(4) | 0x0c04, DSZ(0x4) | 0xcc06, - SFLDS7(FLD(op, 3, 1), FLD(na, 4, 1), FLD(srcdst, 5, 2), FLD(ptr, 7, 2), - FLD(sz, 9, 1), FLD(t, 12, 1), FLD(cst, 13, 1))) - -/* C-14 */ -FMT(d_ddec_dsz_01x, 16, DSZ(2) | 0x4c04, DSZ(0x6) | 0xcc06, - SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), - FLD(t, 12, 1), FLD(cst, 13, 1))) - -FMT(d_ddec_dsz_0xx, 16, DSZ(0) | 0x4c04, DSZ(0x4) | 0xcc06, - SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), - FLD(t, 12, 1), FLD(cst, 13, 1))) - -FMT(d_ddec_dsz_x01, 16, DSZ(1) | 0x4c04, DSZ(0x3) | 0xcc06, - SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), - FLD(t, 12, 1), FLD(cst, 13, 1))) - -FMT(d_ddec_dsz_x11, 16, DSZ(3) | 0x4c04, DSZ(0x3) | 0xcc06, - SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), - FLD(t, 12, 1), FLD(cst, 13, 1))) - -FMT(d_ddec_dsz_000, 16, DSZ(0) | 0x4c04, DSZ(0x7) | 0xcc06, - SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), - FLD(t, 12, 1), FLD(cst, 13, 1))) - -FMT(d_ddec_dsz_010, 16, DSZ(2) | 0x4c04, DSZ(0x7) | 0xcc06, - SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), - FLD(t, 12, 1), FLD(cst, 13, 1))) - -FMT(d_ddec_dsz_100, 16, DSZ(4) | 0x4c04, DSZ(0x7) | 0xcc06, - SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), - FLD(t, 12, 1), FLD(cst, 13, 1))) - -FMT(d_ddec_dsz_110, 16, DSZ(6) | 0x4c04, DSZ(0x7) | 0xcc06, - SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), - FLD(t, 12, 1), FLD(cst, 13, 1))) - -FMT(d_ddec_dsz_111, 16, DSZ(7) | 0x4c04, DSZ(0x7) | 0xcc06, - SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), - FLD(t, 12, 1), FLD(cst, 13, 1))) - -/* C-15 */ -FMT(d_ddecdw, 16, DSZ(4) | 0x4c04, DSZ(0x4) | 0xcc06, - SFLDS7(FLD(op, 3, 1), FLD(na, 4, 1), FLD(srcdst, 5, 2), FLD(ptr, 7, 2), - FLD(sz, 9, 1), FLD(t, 12, 1), FLD(cst, 13, 1))) - -/* C-16 */ -FMT(d_dstk, 16, 0x8c04, 0x8c06, - SFLDS4(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(t, 12, 1), - COMPFLD(cst, BFLD2(BFLD(7, 3, 2), BFLD(13, 2, 0))))) - -/* C-17 */ -FMT(d_dx2op, 16, 0x0036, 0x047e, - SFLDS4(FLD(src2, 7, 3), FLD(op, 11, 1), FLD(x, 12, 1), FLD(srcdst, 13, 3))) - -/* C-18 */ -FMT(d_dx5, 16, 0x0436, 0x047e, - SFLDS2(FLD(dst, 7, 3), - COMPFLD(cst, BFLD2(BFLD(11, 2, 3), BFLD(13, 3, 0))))) - -/* C-19 */ -FMT(d_dx5p, 16, 0x0c76, 0x1c7e, - SFLDS2(FLD(op, 7, 1), - COMPFLD(cst, BFLD2(BFLD(8, 2, 3), BFLD(13, 3, 0))))) - -/* C-20 */ -FMT(d_dx1, 16, 0x1876, 0x1c7e, - SFLDS2(FLD(srcdst, 7, 3), FLD(op, 13, 3))) - -/* C-21 */ -FMT(d_dpp, 16, 0x0077, 0x087f, - SFLDS5(FLD(srcdst, 7, 4), FLD(t, 12, 1), FLD(cst, 13, 1), FLD(op, 14, 1), - FLD(dw, 15, 1))) - -/* Appendix D 32-bit formats. */ - -FMT(l_1_or_2_src, 32, 0x18, 0x1c, - CFLDS6(FLD(s, 1, 1), FLD(op, 5, 7), FLD(x, 12, 1), FLD(src1, 13, 5), - FLD(src2, 18, 5), FLD(dst, 23, 5))) -FMT(l_1_or_2_src_noncond, 32, 0x10000018, 0xf000001c, - NFLDS6(FLD(s, 1, 1), FLD(op, 5, 7), FLD(x, 12, 1), FLD(src1, 13, 5), - FLD(src2, 18, 5), FLD(dst, 23, 5))) -FMT(l_unary, 32, 0x358, 0xffc, - CFLDS5(FLD(s, 1, 1), FLD(x, 12, 1), FLD(op, 13, 5), FLD(src2, 18, 5), - FLD(dst, 23, 5))) - -/* Appendix D 16-bit formats will go here. */ - -/* D-4 */ -FMT(l_l3_sat_0, 16, SAT(0) | 0x0000, SAT(1) | 0x040e, - SFLDS5(FLD(dst, 4, 3), FLD(src2, 7, 3), FLD(op, 11, 1), FLD(x, 12, 1), - FLD(src1, 13, 3))) - -FMT(l_l3_sat_1, 16, SAT(1) | 0x0000, SAT(1) | 0x040e, - SFLDS5(FLD(dst, 4, 3), FLD(src2, 7, 3), FLD(op, 11, 1), FLD(x, 12, 1), - FLD(src1, 13, 3))) - -/* D-5 - combine cst3 and n fields into a single field cst */ -FMT(l_l3i, 16, 0x0400, 0x040e, - SFLDS5(FLD(dst, 4, 3), FLD(src2, 7, 3), FLD(sn, 11, 1), FLD(x, 12, 1), - COMPFLD(cst, BFLD2(BFLD(13, 3, 0), BFLD(11, 1, 3))))) - -/* D-6 Mtbd ? */ - -/* D-7 */ -FMT(l_l2c, 16, 0x0408, 0x040e, - SFLDS5(FLD(dst, 4, 1), FLD(src2, 7, 3), FLD(x, 12, 1), FLD(src1, 13, 3), - COMPFLD(op, BFLD2(BFLD(5, 2, 0), BFLD(11, 1, 2))))) - -/* D-8 */ -FMT(l_lx5, 16, 0x0426, 0x047e, - SFLDS2(FLD(dst, 7, 3), - COMPFLD(cst, BFLD2(BFLD(11, 2, 3), BFLD(13, 3, 0))))) - -/* D-9 */ -FMT(l_lx3c, 16, 0x0026, 0x147e, - SFLDS3(FLD(src2, 7, 3), FLD(dst, 11, 1), FLD(cst, 13, 3))) - -/* D-10 */ -FMT(l_lx1c, 16, 0x1026, 0x147e, - SFLDS4(FLD(src2, 7, 3), FLD(dst, 11, 1), FLD(cst, 13, 1), FLD(op, 14, 2))) - -/* D-11 */ -FMT(l_lx1, 16, 0x1866, 0x1c7e, - SFLDS2(FLD(srcdst, 7, 3), FLD(op, 13, 3))) - -/* Appendix E 32-bit formats. */ - -FMT(m_compound, 32, 0x30, 0x83c, - CFLDS6(FLD(s, 1, 1), FLD(op, 6, 5), FLD(x, 12, 1), FLD(src1, 13, 5), - FLD(src2, 18, 5), FLD(dst, 23, 5))) -FMT(m_1_or_2_src, 32, 0x10000030, 0xf000083c, - NFLDS6(FLD(s, 1, 1), FLD(op, 6, 5), FLD(x, 12, 1), FLD(src1, 13, 5), - FLD(src2, 18, 5), FLD(dst, 23, 5))) -/* Contrary to SPRUFE8, this does have predicate fields. */ -FMT(m_unary, 32, 0xf0, 0xffc, - CFLDS5(FLD(s, 1, 1), FLD(x, 12, 1), FLD(op, 13, 5), FLD(src2, 18, 5), - FLD(dst, 23, 5))) - -/* M-unit formats missing from Appendix E. */ -FMT(m_mpy, 32, 0x0, 0x7c, - CFLDS6(FLD(s, 1, 1), FLD(op, 7, 5), FLD(x, 12, 1), FLD(src1, 13, 5), - FLD(src2, 18, 5), FLD(dst, 23, 5))) - -/* Appendix E 16-bit formats will go here. */ -FMT(m_m3_sat_0, 16, SAT(0) | 0x001e, SAT(1) | 0x001e, - SFLDS5(FLD(op, 5, 2), FLD(src2, 7, 3), FLD(dst, 10, 2), - FLD(x, 12, 1), FLD(src1, 13, 3))) -FMT(m_m3_sat_1, 16, SAT(1) | 0x001e, SAT(1) | 0x001e, - SFLDS5(FLD(op, 5, 2), FLD(src2, 7, 3), FLD(dst, 10, 2), - FLD(x, 12, 1), FLD(src1, 13, 3))) - -/* Appendix F 32-bit formats. */ - -FMT(s_1_or_2_src, 32, 0x20, 0x3c, - CFLDS6(FLD(s, 1, 1), FLD(op, 6, 6), FLD(x, 12, 1), FLD(src1, 13, 5), - FLD(src2, 18, 5), FLD(dst, 23 ,5))) -FMT(s_ext_1_or_2_src, 32, 0xc30, 0xc3c, - CFLDS6(FLD(s, 1, 1), FLD(op, 6, 4), FLD(x, 12, 1), FLD(src1, 13, 5), - FLD(src2, 18, 5), FLD(dst, 23, 5))) -FMT(s_ext_1_or_2_src_noncond, 32, 0xc30, 0xe0000c3c, - NFLDS7(FLD(s, 1, 1), FLD(op, 6, 4), FLD(x, 12, 1), FLD(src1, 13, 5), - FLD(src2, 18, 5), FLD(dst, 23, 5), FLD(z, 28, 1))) -FMT(s_unary, 32, 0xf20, 0xffc, - CFLDS5(FLD(s, 1, 1), FLD(x, 12, 1), FLD(op, 13, 5), FLD(src2, 18, 5), - FLD(dst, 23, 5))) -FMT(s_ext_branch_cond_imm, 32, 0x10, 0x7c, - CFLDS2(FLD(s, 1, 1), FLD(cst, 7, 21))) -FMT(s_call_imm_nop, 32, 0x10, 0xe000007c, - NFLDS3(FLD(s, 1, 1), FLD(cst, 7, 21), FLD(z, 28, 1))) -FMT(s_branch_nop_cst, 32, 0x120, 0x1ffc, - CFLDS3(FLD(s, 1, 1), FLD(src1, 13, 3), FLD(src2, 16, 12))) -FMT(s_branch_nop_reg, 32, 0x800360, 0xf830ffc, - CFLDS4(FLD(s, 1, 1), FLD(x, 12, 1), FLD(src1, 13, 3), FLD(src2, 18, 5))) -FMT(s_branch, 32, 0x360, 0xf83effc, - CFLDS3(FLD(s, 1, 1), FLD(x, 12, 1), FLD(src2, 18, 5))) -FMT(s_mvk, 32, 0x28, 0x3c, - CFLDS4(FLD(s, 1, 1), FLD(h, 6, 1), FLD(cst, 7, 16), FLD(dst, 23, 5))) -FMT(s_field, 32, 0x8, 0x3c, - CFLDS6(FLD(s, 1, 1), FLD(op, 6, 2), FLD(cstb, 8, 5), FLD(csta, 13, 5), - FLD(src2, 18, 5), FLD(dst, 23, 5))) - -/* S-unit formats missing from Appendix F. */ -FMT(s_addk, 32, 0x50, 0x7c, - CFLDS3(FLD(s, 1, 1), FLD(cst, 7, 16), FLD(dst, 23, 5))) -FMT(s_addkpc, 32, 0x160, 0x1ffc, - CFLDS4(FLD(s, 1, 1), FLD(src2, 13, 3), FLD(src1, 16, 7), FLD(dst, 23, 5))) -FMT(s_b_irp, 32, 0x1800e0, 0x7feffc, - CFLDS3(FLD(s, 1, 1), FLD(x, 12, 1), FLD(dst, 23, 5))) -FMT(s_b_nrp, 32, 0x1c00e0, 0x7feffc, - CFLDS3(FLD(s, 1, 1), FLD(x, 12, 1), FLD(dst, 23, 5))) -FMT(s_bdec, 32, 0x1020, 0x1ffc, - CFLDS3(FLD(s, 1, 1), FLD(src, 13, 10), FLD(dst, 23, 5))) -FMT(s_bpos, 32, 0x20, 0x1ffc, - CFLDS3(FLD(s, 1, 1), FLD(src, 13, 10), FLD(dst, 23, 5))) - -/* Appendix F 16-bit formats will go here. */ - -/* F-17 Sbs7 Instruction Format */ -FMT(s_sbs7, 16, BR(1) | 0x000a, BR(1) | 0x003e, - SFLDS2(FLD(cst, 6, 7), FLD(n, 13, 3))) - -/* F-18 Sbu8 Instruction Format */ -FMT(s_sbu8, 16, BR(1) | 0xc00a, BR(1) | 0xc03e, - SFLDS1(FLD(cst, 6, 8))) - -/* F-19 Scs10 Instruction Format */ -FMT(s_scs10, 16, BR(1) | 0x001a, BR(1) | 0x003e, - SFLDS1(FLD(cst, 6, 10))) - -/* F-20 Sbs7c Instruction Format */ -FMT(s_sbs7c, 16, BR(1) | 0x002a, BR(1) | 0x002e, - SFLDS3(FLD(z, 4, 1), FLD(cst, 6, 7), FLD(n, 13, 3))) - -/* F-21 Sbu8c Instruction Format */ -FMT(s_sbu8c, 16, BR(1) | 0xc02a, BR(1) | 0xc02e, - SFLDS2(FLD(z, 4, 1), FLD(cst, 6, 8))) - -/* F-22 S3 Instruction Format */ -FMT(s_s3, 16, BR(0) | 0x000a, BR(1) | 0x040e, - SFLDS5(FLD(dst, 4, 3), FLD(src2, 7, 3), FLD(op, 11, 1), FLD(x, 12, 1), - FLD(src1, 13, 3))) - -FMT(s_s3_sat_x, 16, BR(0) | SAT(0) | 0x000a, BR(1) | SAT(0) | 0x040e, - SFLDS5(FLD(dst, 4, 3), FLD(src2, 7, 3), FLD(op, 11, 1), FLD(x, 12, 1), - FLD(src1, 13, 3))) - -FMT(s_s3_sat_0, 16, BR(0) | SAT(0) | 0x000a, BR(1) | SAT(1) | 0x040e, - SFLDS5(FLD(dst, 4, 3), FLD(src2, 7, 3), FLD(op, 11, 1), FLD(x, 12, 1), - FLD(src1, 13, 3))) - -FMT(s_s3_sat_1, 16, BR(0) | SAT(1) | 0x000a, BR(1) | SAT(1) | 0x040e, - SFLDS5(FLD(dst, 4, 3), FLD(src2, 7, 3), FLD(op, 11, 1), FLD(x, 12, 1), - FLD(src1, 13, 3))) - -/* F-23 S3i Instruction Format */ -FMT(s_s3i, 16, BR(0) | 0x040a, BR(1) | 0x040e, - SFLDS5(FLD(dst, 4, 3), FLD(src2, 7, 3), FLD(op, 11, 1), FLD(x, 12, 1), - FLD(cst, 13, 3))) - -/* F-24 Smvk8 Instruction Format */ -FMT(s_smvk8, 16, 0x0012, 0x001e, - SFLDS2(FLD(dst, 7, 3), - COMPFLD(cst, BFLD4(BFLD(10, 1, 7), BFLD(5, 2, 5), BFLD(11, 2, 3), BFLD(13, 3, 0))))) - -/* F-25 Ssh5 Instruction Format */ -FMT(s_ssh5_sat_x, 16, SAT(0) | 0x0402, SAT(0) | 0x041e, - SFLDS3(FLD(op, 5, 2), FLD(srcdst, 7, 3), - COMPFLD(cst, BFLD2(BFLD(11, 2, 3), BFLD(13, 3, 0))))) -FMT(s_ssh5_sat_0, 16, SAT(0) | 0x0402, SAT(1) | 0x041e, - SFLDS3(FLD(op, 5, 2), FLD(srcdst, 7, 3), - COMPFLD(cst, BFLD2(BFLD(11, 2, 3), BFLD(13, 3, 0))))) -FMT(s_ssh5_sat_1, 16, SAT(1) | 0x0402, SAT(1) | 0x041e, - SFLDS3(FLD(op, 5, 2), FLD(srcdst, 7, 3), - COMPFLD(cst, BFLD2(BFLD(11, 2, 3), BFLD(13, 3, 0))))) - -/* F-26 S2sh Instruction Format */ -FMT(s_s2sh, 16, 0x0462, 0x047e, - SFLDS3(FLD(srcdst, 7, 3), FLD(op, 11, 2), FLD(src1, 13, 3))) - -/* F-27 Sc5 Instruction Format */ -FMT(s_sc5, 16, 0x0002, 0x041e, - SFLDS3(FLD(op, 5, 2), FLD(srcdst, 7, 3), - COMPFLD(cst, BFLD2(BFLD(11, 2, 3), BFLD(13, 3, 0))))) - -/* F-28 S2ext Instruction Format */ -FMT(s_s2ext, 16, 0x0062, 0x047e, - SFLDS3(FLD(src, 7, 3), FLD(op, 11, 2), FLD(dst, 13, 3))) - -/* F-29 Sx2op Instruction Format */ -FMT(s_sx2op, 16, 0x002e, 0x047e, - SFLDS4(FLD(src2, 7, 3), FLD(op, 11, 1), FLD(x, 12, 1), - FLD(srcdst, 13, 3))) - -/* F-30 Sx5 Instruction Format */ -FMT(s_sx5, 16, 0x042e, 0x047e, - SFLDS2(FLD(dst, 7, 3), - COMPFLD(cst, BFLD2(BFLD(11, 2, 3), BFLD(13, 3, 0))))) - -/* F-31 Sx1 Instruction Format */ -FMT(s_sx1, 16, 0x186e, 0x1c7e, - SFLDS2(FLD(srcdst, 7, 3), FLD(op, 13, 3))) - -/* F-32 Sx1b Instruction Format */ -FMT(s_sx1b, 16, 0x006e, 0x187e, - SFLDS2(FLD(src2, 7, 4), FLD(n, 13, 3))) - -/* Appendix G 16-bit formats will go here. */ -FMT(lsdmvto, 16, 0x0006, 0x0066, - SFLDS4(FLD(unit, 3, 2), - FLD(x, 12, 1), FLD(dst, 13, 3), - COMPFLD(src2, BFLD2(BFLD(10, 2, 3), BFLD(7, 3, 0))))) - -FMT(lsdmvfr, 16, 0x0046, 0x0066, - SFLDS4(FLD(unit, 3, 2), FLD(src2, 7, 3), FLD(x, 12, 1), - COMPFLD(dst, BFLD2(BFLD(10, 2, 3), BFLD(13, 3, 0))))) - -/* G-3 */ -FMT(lsdx1c, 16, 0x0866, 0x1c66, - SFLDS4(FLD(unit, 3, 2), FLD(dst, 7, 3), FLD(cst, 13, 1), - FLD(cc, 14, 2))) - -/* G-4 */ -FMT(lsdx1, 16, 0x1866, 0x1c66, - SFLDS3(FLD(unit, 3, 2), FLD(srcdst, 7, 3), FLD(op, 13, 3))) - -/* Appendix H 32-bit formats. */ - -FMT(nfu_loop_buffer, 32, 0x00020000, 0x00021ffc, - CFLDS4(FLD(s, 1, 1), FLD(op, 13, 4), FLD(csta, 18, 5), FLD(cstb, 23, 5))) -/* Corrected relative to Appendix H. */ -FMT(nfu_nop_idle, 32, 0x00000000, 0xfffe1ffc, - NFLDS2(FLD(s, 1, 1), FLD(op, 13, 4))) - -/* No-unit formats missing from Appendix H (given the NOP and IDLE - correction). */ -FMT(nfu_dint, 32, 0x10004000, 0xfffffffc, - NFLDS1(FLD(s, 1, 1))) -FMT(nfu_rint, 32, 0x10006000, 0xfffffffc, - NFLDS1(FLD(s, 1, 1))) -FMT(nfu_swe, 32, 0x10000000, 0xfffffffc, - NFLDS1(FLD(s, 1, 1))) -FMT(nfu_swenr, 32, 0x10002000, 0xfffffffc, - NFLDS1(FLD(s, 1, 1))) -/* Although formally covered by the loop buffer format, the fields in - that format are not useful for all such instructions and not all - instructions can be predicated. */ -FMT(nfu_spkernel, 32, 0x00034000, 0xf03ffffc, - NFLDS2(FLD(s, 1, 1), FLD(fstgfcyc, 22, 6))) -FMT(nfu_spkernelr, 32, 0x00036000, 0xfffffffc, - NFLDS1(FLD(s, 1, 1))) -FMT(nfu_spmask, 32, 0x00020000, 0xfc021ffc, - NFLDS3(FLD(s, 1, 1), FLD(op, 13, 4), FLD(mask, 18, 8))) - -/* Appendix H 16-bit formats will go here. */ - -/* H-5 */ -FMT(nfu_uspl, 16, 0x0c66, 0xbc7e, - FLDS2(FLD(op, 0, 1), COMPFLD(ii, BFLD2(BFLD(7, 3, 0), BFLD(14, 1, 3))))) - -/* H-6 */ -/* make up some fields to pretend to have s and z fields s for this format - so as to fit in other predicated compact instruction to avoid special- - casing this instruction in tic6x-dis.c - use op field as a predicate adress register selector (s field) - use the first zeroed bit as a z value as this insn only supports [a0] - and [b0] predicate forms. -*/ -FMT(nfu_uspldr, 16, 0x8c66, 0xbc7e, - FLDS4(FLD(op, 0, 1), FLD(s, 0, 1), FLD(z, 3, 1), - COMPFLD(ii, BFLD2(BFLD(7, 3, 0), BFLD(14, 1, 3))))) - -/* H-7 */ -FMT(nfu_uspk, 16, 0x1c66, 0x3c7e, - FLDS1(COMPFLD(fstgfcyc, BFLD3(BFLD(0, 1, 0), BFLD(7, 3, 1), BFLD(14, 2, 4))))) - -/* H-8a */ -FMT(nfu_uspma, 16, 0x2c66, 0x3c7e, - FLDS1(COMPFLD(mask, BFLD3(BFLD(0, 1, 0), BFLD(7, 3, 1), BFLD(14, 2, 4))))) - -/* H-8b */ -FMT(nfu_uspmb, 16, 0x3c66, 0x3c7e, - FLDS1(COMPFLD(mask, BFLD3(BFLD(0, 1, 0), BFLD(7, 3, 1), BFLD(14, 2, 4))))) - -/* H-9 */ -FMT(nfu_unop, 16, 0x0c6e, 0x1fff, - FLDS1(FLD(n, 13, 3))) - -#undef FLD -#undef CFLDS -#undef CFLDS2 -#undef CFLDS3 -#undef CFLDS4 -#undef CFLDS5 -#undef CFLDS6 -#undef CFLDS7 -#undef CFLDS8 -#undef NFLDS -#undef NFLDS1 -#undef NFLDS2 -#undef NFLDS3 -#undef NFLDS5 -#undef NFLDS6 -#undef NFLDS7 -#undef SFLDS -#undef SFLDS1 -#undef SFLDS2 -#undef SFLDS3 -#undef SFLDS4 -#undef SFLDS5 -#undef SFLDS6 -#undef SFLDS7 -#undef BFLD -#undef BFLD1 -#undef BFLD2 -#undef BFLD3 -#undef BFLD4 -#undef FLDS1 -#undef FLDS2 -#undef FLDS3 -#undef FLDS4 -#undef FLDS5 -#undef COMPFLD -#undef DSZ -#undef BR -#undef SAT diff --git a/include/opcode/tic6x-opcode-table.h b/include/opcode/tic6x-opcode-table.h deleted file mode 100644 index d876c56..0000000 --- a/include/opcode/tic6x-opcode-table.h +++ /dev/null @@ -1,3677 +0,0 @@ -/* TI C6X opcode table. - Copyright 2010-2013 Free Software Foundation, Inc. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, - MA 02110-1301, USA. */ - -/* Define the INSN macro before including this file; it takes as - arguments the fields from tic6x_opcode (defined in tic6x.h). The - name is given as an identifier; the subsequent four operands should - have "tic6x_func_unit_", "tic6x_insn_format_", "tic6x_pipeline_" - and "TIC6X_INSN_", respectively, prepended to them by the macro - definition. Also define INSNE, which has a second argument that - goes after tic6x_opcode_NAME_ to form the enumeration value for - this instruction, where the value otherwise formed from the name, - functional unit and format is ambiguous, but otherwise has the same - arguments as INSN. */ - -#define TIC6X_INSN_C64X_AND_C67X TIC6X_INSN_C64X|TIC6X_INSN_C67X -#define tic6x_insn_format_nfu_s_branch_nop_cst \ - tic6x_insn_format_s_branch_nop_cst -#define tic6x_insn_format_s_l_1_or_2_src tic6x_insn_format_l_1_or_2_src -#define RAN(id, min, max) { CONCAT2(tic6x_field_,id), (min), (max) } -#define FIX(id, val) RAN(id, val, val) -#define FIX0() 0, { { 0, 0, 0 } } -#define FIX1(a) 1, { a } -#define FIX2(a, b) 2, { a, b } -#define FIX3(a, b, c) 3, { a, b, c } -#define FIX4(a, b, c, d) 4, { a, b, c, d } -#define OP0() 0, { { 0, 0, FALSE, 0, 0, 0, 0 } } -#define OP1(a) 1, { a } -#define OP2(a, b) 2, { a, b } -#define OP3(a, b, c) 3, { a, b, c } -#define OP4(a, b, c, d) 4, { a, b, c, d } -#define OACST { tic6x_operand_asm_const, 0, tic6x_rw_none, 0, 0, 0, 0 } -#define OLCST { tic6x_operand_link_const, 0, tic6x_rw_none, 0, 0, 0, 0 } -#define OHWCSTM1 { tic6x_operand_hw_const_minus_1, 0, tic6x_rw_none, 0, 0, 0, 0 } -#define OHWCST0 { tic6x_operand_hw_const_0, 0, tic6x_rw_none, 0, 0, 0, 0 } -#define OHWCST1 { tic6x_operand_hw_const_1, 0, tic6x_rw_none, 0, 0, 0, 0 } -#define OHWCST5 { tic6x_operand_hw_const_5, 0, tic6x_rw_none, 0, 0, 0, 0 } -#define OHWCST16 { tic6x_operand_hw_const_16, 0, tic6x_rw_none, 0, 0, 0, 0 } -#define OHWCST24 { tic6x_operand_hw_const_24, 0, tic6x_rw_none, 0, 0, 0, 0 } -#define OHWCST31 { tic6x_operand_hw_const_31, 0, tic6x_rw_none, 0, 0, 0, 0 } -#define OFULIST { tic6x_operand_func_unit, 0, tic6x_rw_none, 0, 0, 0, 0 } -#define ORIRP1 { tic6x_operand_irp, 4, tic6x_rw_read, 1, 1, 0, 0 } -#define ORNRP1 { tic6x_operand_nrp, 4, tic6x_rw_read, 1, 1, 0, 0 } -#define OWREG1 { tic6x_operand_reg, 4, tic6x_rw_write, 1, 1, 0, 0 } -#define OWREG1Z { tic6x_operand_zreg, 4, tic6x_rw_write, 1, 1, 0, 0 } -#define OWREG1NORS { tic6x_operand_reg_nors, 4, tic6x_rw_write, 1, 1, 0, 0 } -#define ORREG1B { tic6x_operand_reg_bside, 4, tic6x_rw_write, 1, 1, 0, 0 } -#define ORREG1BNORS { tic6x_operand_reg_bside_nors, 4, tic6x_rw_write, 1, 1, 0, 0 } -#define OWRETREG1 { tic6x_operand_retreg, 4, tic6x_rw_write, 1, 1, 0, 0 } -#define ORREG1 { tic6x_operand_reg, 4, tic6x_rw_read, 1, 1, 0, 0 } -#define ORDREG1 { tic6x_operand_dreg, 4, tic6x_rw_read, 1, 1, 0, 0 } -#define ORTREG1 { tic6x_operand_treg, 4, tic6x_rw_read, 1, 1, 0, 0 } -#define ORWREG1 { tic6x_operand_reg, 4, tic6x_rw_read_write, 1, 1, 0, 0 } -#define ORB15REG1 { tic6x_operand_b15reg, 4, tic6x_rw_read, 1, 1, 0, 0 } -#define OWB15REG1 { tic6x_operand_b15reg, 4, tic6x_rw_write, 1, 1, 0, 0 } -#define ORAREG1 { tic6x_operand_areg, 4, tic6x_rw_read, 1, 1, 0, 0 } -#define ORXREG1 { tic6x_operand_xreg, 4, tic6x_rw_read, 1, 1, 0, 0 } -#define ORREG12 { tic6x_operand_reg, 4, tic6x_rw_read, 1, 2, 0, 0 } -#define ORREG14 { tic6x_operand_reg, 4, tic6x_rw_read, 1, 4, 0, 0 } -#define ORXREG14 { tic6x_operand_xreg, 4, tic6x_rw_read, 1, 4, 0, 0 } -#define OWREG2 { tic6x_operand_reg, 4, tic6x_rw_write, 2, 2, 0, 0 } -#define OWREG4 { tic6x_operand_reg, 4, tic6x_rw_write, 4, 4, 0, 0 } -#define OWREG9 { tic6x_operand_reg, 4, tic6x_rw_write, 9, 9, 0, 0 } -#define OWDREG5 { tic6x_operand_dreg, 4, tic6x_rw_write, 5, 5, 0, 0 } -#define OWTREG5 { tic6x_operand_treg, 4, tic6x_rw_write, 5, 5, 0, 0 } -#define OWREGL1 { tic6x_operand_regpair, 5, tic6x_rw_write, 1, 1, 1, 1 } -#define ORREGL1 { tic6x_operand_regpair, 5, tic6x_rw_read, 1, 1, 1, 1 } -#define OWREGD1 { tic6x_operand_regpair, 8, tic6x_rw_write, 1, 1, 1, 1 } -#define OWREGD12 { tic6x_operand_regpair, 8, tic6x_rw_write, 1, 1, 2, 2 } -#define OWREGD4 { tic6x_operand_regpair, 8, tic6x_rw_write, 4, 4, 4, 4 } -#define ORREGD1 { tic6x_operand_regpair, 8, tic6x_rw_read, 1, 1, 1, 1 } -#define OWREGD45 { tic6x_operand_regpair, 8, tic6x_rw_write, 4, 4, 5, 5 } -#define OWREGD67 { tic6x_operand_regpair, 8, tic6x_rw_write, 6, 6, 7, 7 } -#define ORDREGD1 { tic6x_operand_dregpair, 8, tic6x_rw_read, 1, 1, 1, 1 } -#define ORTREGD1 { tic6x_operand_tregpair, 8, tic6x_rw_read, 1, 1, 1, 1 } -#define OWDREGD5 { tic6x_operand_dregpair, 8, tic6x_rw_write, 5, 5, 5, 5 } -#define OWTREGD5 { tic6x_operand_tregpair, 8, tic6x_rw_write, 5, 5, 5, 5 } -#define ORREGD12 { tic6x_operand_regpair, 8, tic6x_rw_read, 1, 1, 2, 2 } -#define ORXREGD12 { tic6x_operand_xregpair, 8, tic6x_rw_read, 1, 1, 2, 2 } -#define ORREGD1234 { tic6x_operand_regpair, 8, tic6x_rw_read, 1, 2, 3, 4 } -#define ORXREGD1324 { tic6x_operand_xregpair, 8, tic6x_rw_read, 1, 3, 2, 4 } -#define OWREGD910 { tic6x_operand_regpair, 8, tic6x_rw_write, 9, 9, 10, 10 } -#define ORCREG1 { tic6x_operand_ctrl, 4, tic6x_rw_read, 1, 1, 0, 0 } -#define OWCREG1 { tic6x_operand_ctrl, 4, tic6x_rw_write, 1, 1, 0, 0 } -#define OWILC1 { tic6x_operand_ilc, 4, tic6x_rw_write, 1, 1, 0, 0 } -#define ORMEMDW { tic6x_operand_mem_deref, 4, tic6x_rw_read, 3, 3, 0, 0 } -#define OWMEMDW { tic6x_operand_mem_deref, 4, tic6x_rw_write, 3, 3, 0, 0 } -#define ORMEMSB { tic6x_operand_mem_short, 1, tic6x_rw_read, 3, 3, 0, 0 } -#define OWMEMSB { tic6x_operand_mem_short, 1, tic6x_rw_write, 3, 3, 0, 0 } -#define ORMEMLB { tic6x_operand_mem_long, 1, tic6x_rw_read, 3, 3, 0, 0 } -#define OWMEMLB { tic6x_operand_mem_long, 1, tic6x_rw_write, 3, 3, 0, 0 } -#define ORMEMSH { tic6x_operand_mem_short, 2, tic6x_rw_read, 3, 3, 0, 0 } -#define OWMEMSH { tic6x_operand_mem_short, 2, tic6x_rw_write, 3, 3, 0, 0 } -#define ORMEMLH { tic6x_operand_mem_long, 2, tic6x_rw_read, 3, 3, 0, 0 } -#define OWMEMLH { tic6x_operand_mem_long, 2, tic6x_rw_write, 3, 3, 0, 0 } -#define ORMEMSW { tic6x_operand_mem_short, 4, tic6x_rw_read, 3, 3, 0, 0 } -#define OWMEMSW { tic6x_operand_mem_short, 4, tic6x_rw_write, 3, 3, 0, 0 } -#define ORMEMLW { tic6x_operand_mem_long, 4, tic6x_rw_read, 3, 3, 0, 0 } -#define OWMEMLW { tic6x_operand_mem_long, 4, tic6x_rw_write, 3, 3, 0, 0 } -#define ORMEMSD { tic6x_operand_mem_short, 8, tic6x_rw_read, 3, 3, 0, 0 } -#define OWMEMSD { tic6x_operand_mem_short, 8, tic6x_rw_write, 3, 3, 0, 0 } -#define ORMEMND { tic6x_operand_mem_ndw, 8, tic6x_rw_read, 3, 3, 0, 0 } -#define OWMEMND { tic6x_operand_mem_ndw, 8, tic6x_rw_write, 3, 3, 0, 0 } -#define ENC(id, meth, op) { \ - CONCAT2(tic6x_field_,id), \ - CONCAT2(tic6x_coding_,meth), \ - op \ - } -#define ENC0() 0, { { 0, 0, 0 } } -#define ENC1(a) 1, { a } -#define ENC2(a, b) 2, { a, b } -#define ENC3(a, b, c) 3, { a, b, c } -#define ENC4(a, b, c, d) 4, { a, b, c, d } -#define ENC5(a, b, c, d, e) 5, { a, b, c, d, e } -#define ENC6(a, b, c, d, e, f) 6, { a, b, c, d, e, f } -#define ENC7(a, b, c, d, e, f, g) 7, { a, b, c, d, e, f, g } - -INSN(abs, l, unary, 1cycle, C62X, 0, - FIX1(FIX(op, 0)), - OP2(ORXREG1, OWREG1), - ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), - ENC(dst, reg, 1))) -INSN(abs, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS, - FIX3(FIX(op, 0x38), FIX(x, 0), FIX(src1, 0)), - OP2(ORREGL1, OWREGL1), - ENC3(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(dst, reg, 1))) - -INSN(abs2, l, unary, 1cycle, C64X, 0, - FIX1(FIX(op, 0x4)), - OP2(ORXREG1, OWREG1), - ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), - ENC(dst, reg, 1))) - -INSN(absdp, s, 1_or_2_src, 2cycle_dp, C67X, TIC6X_FLAG_NO_CROSS, - FIX2(FIX(op, 0x2c), FIX(x, 0)), - OP2(ORREGD1, OWREGD12), - ENC4(ENC(s, fu, 0), ENC(src2, regpair_msb, 0), ENC(src1, regpair_lsb, 0), - ENC(dst, reg, 1))) - -INSN(abssp, s, unary, 1cycle, C67X, 0, - FIX1(FIX(op, 0)), - OP2(ORXREG1, OWREG1), - ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), - ENC(dst, reg, 1))) - -INSNE(add, l_si_xsi_si, l, 1_or_2_src, 1cycle, C62X, 0, - FIX1(FIX(op, 0x3)), - OP3(ORREG1, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -INSNE(add, l_si_xsi_sl, l, 1_or_2_src, 1cycle, C62X, 0, - FIX1(FIX(op, 0x23)), - OP3(ORREG1, ORXREG1, OWREGL1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -INSNE(add, l_xsi_sl_sl, l, 1_or_2_src, 1cycle, C62X, 0, - FIX1(FIX(op, 0x21)), - OP3(ORXREG1, ORREGL1, OWREGL1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -INSNE(add, l_s5_xsi_si, l, 1_or_2_src, 1cycle, C62X, 0, - FIX1(FIX(op, 0x2)), - OP3(OACST, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -INSNE(add, l_s5_sl_sl, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS, - FIX2(FIX(op, 0x20), FIX(x, 0)), - OP3(OACST, ORREGL1, OWREGL1), - ENC4(ENC(s, fu, 0), ENC(src1, scst, 0), ENC(src2, reg, 1), - ENC(dst, reg, 2))) -INSNE(add, s_si_xsi_si, s, 1_or_2_src, 1cycle, C62X, 0, - FIX1(FIX(op, 0x7)), - OP3(ORREG1, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -INSNE(add, s_s5_xsi_si, s, 1_or_2_src, 1cycle, C62X, 0, - FIX1(FIX(op, 0x6)), - OP3(OACST, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -INSNE(add, d_si_si_si, d, 1_or_2_src, 1cycle, C62X, - TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1), - FIX1(FIX(op, 0x10)), - OP3(ORREG1, ORREG1, OWREG1), - ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, reg, 1), - ENC(dst, reg, 2))) -INSNE(add, d_si_u5_si, d, 1_or_2_src, 1cycle, C62X, - TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1), - FIX1(FIX(op, 0x12)), - OP3(ORREG1, OACST, OWREG1), - ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1), - ENC(dst, reg, 2))) -INSNE(add, d_si_xsi_si, d, ext_1_or_2_src, 1cycle, C64X, TIC6X_FLAG_PREFER(0), - FIX1(FIX(op, 0xa)), - OP3(ORREG1, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -INSNE(add, d_xsi_s5_si, d, ext_1_or_2_src, 1cycle, C64X, TIC6X_FLAG_PREFER(0), - FIX1(FIX(op, 0xb)), - OP3(ORXREG1, OACST, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), - ENC(src1, scst, 1), ENC(dst, reg, 2))) - -/* 16 bits insn */ -INSN(add, l, l3_sat_0, 1cycle, C64XP, 0, - FIX1(FIX(op, 0x0)), - OP3(ORREG1, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -INSN(add, l, l3i, 1cycle, C64XP, 0, - FIX0(), - OP3(OACST, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(cst, scst_l3i, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -INSN(add, l, lx1, 1cycle, C64XP, - TIC6X_FLAG_NO_CROSS, - FIX1(FIX(op, 0x3)), - OP3(OHWCSTM1, ORREG1, OWREG1), - ENC3(ENC(s, fu, 0), ENC(srcdst, reg, 1), ENC(srcdst, reg, 2))) -INSN(add, s, s3_sat_0, 1cycle, C64XP, 0, - FIX1(FIX(op, 0x0)), - OP3(ORREG1, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -INSN(add, s, sx1, 1cycle, C64XP, TIC6X_FLAG_NO_CROSS, - FIX1(FIX(op, 0x3)), - OP3(OHWCSTM1, ORREG1, OWREG1), - ENC3(ENC(s, fu, 0), ENC(srcdst, reg, 1), ENC(srcdst, reg, 2))) -INSN(add, s, sx2op, 1cycle, C64XP, 0, - FIX1(FIX(op, 0x0)), - OP3(ORREG1, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(srcdst, reg, 0), ENC(srcdst, reg, 2), - ENC(src2, reg, 1), ENC(x, xpath, 1))) -INSN(add, d, dx2op, 1cycle, C64XP, 0, - FIX1(FIX(op, 0x0)), - OP3(ORREG1, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 1), ENC(srcdst, reg, 0), - ENC(src2, reg, 1), ENC(srcdst, reg, 2))) -INSNU(add, l, lsdx1, 1cycle, C64XP, TIC6X_FLAG_NO_CROSS, - FIX2(FIX(op, 0x5), FIX(unit, 0x0)), - OP3(ORREG1, OHWCST1, OWREG1), - ENC3(ENC(s, fu, 0), ENC(srcdst, reg, 0), ENC(srcdst, reg, 2))) -INSNU(add, s, lsdx1, 1cycle, C64XP, TIC6X_FLAG_NO_CROSS, - FIX2(FIX(op, 0x5), FIX(unit, 0x1)), - OP3(ORREG1, OHWCST1, OWREG1), - ENC3(ENC(s, fu, 0), ENC(srcdst, reg, 0), ENC(srcdst, reg, 2))) -INSNU(add, d, lsdx1, 1cycle, C64XP, TIC6X_FLAG_NO_CROSS, - FIX2(FIX(op, 0x5), FIX(unit, 0x2)), - OP3(ORREG1, OHWCST1, OWREG1), - ENC3(ENC(s, fu, 0), ENC(srcdst, reg, 0), ENC(srcdst, reg, 2))) -/**/ - -INSNE(addab, d_si_si_si, d, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS, - FIX1(FIX(op, 0x30)), - OP3(ORREG1, ORREG1, OWREG1), - ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, reg, 1), - ENC(dst, reg, 2))) -INSNE(addab, d_si_u5_si, d, 1_or_2_src, 1cycle, C62X, - TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1), - FIX1(FIX(op, 0x32)), - OP3(ORREG1, OACST, OWREG1), - ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1), - ENC(dst, reg, 2))) -INSN(addab, d, adda_long, 1cycle, C64XP, TIC6X_FLAG_PREFER(0), - FIX1(FIX(op, 3)), - OP3(ORAREG1, OLCST, OWREG1), - ENC4(ENC(s, fu, 0), ENC(y, areg, 0), ENC(offsetR, ulcst_dpr_byte, 1), - ENC(dst, reg, 2))) - -INSNE(addad, d_si_si_si, d, 1_or_2_src, 1cycle, C64X_AND_C67X, - TIC6X_FLAG_NO_CROSS, - FIX1(FIX(op, 0x3c)), - OP3(ORREG1, ORREG1, OWREG1), - ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, reg, 1), - ENC(dst, reg, 2))) -INSNE(addad, d_si_u5_si, d, 1_or_2_src, 1cycle, C64X_AND_C67X, - TIC6X_FLAG_NO_CROSS, - FIX1(FIX(op, 0x3d)), - OP3(ORREG1, OACST, OWREG1), - ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1), - ENC(dst, reg, 2))) - -INSNE(addah, d_si_si_si, d, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS, - FIX1(FIX(op, 0x34)), - OP3(ORREG1, ORREG1, OWREG1), - ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, reg, 1), - ENC(dst, reg, 2))) -INSNE(addah, d_si_u5_si, d, 1_or_2_src, 1cycle, C62X, - TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1), - FIX1(FIX(op, 0x36)), - OP3(ORREG1, OACST, OWREG1), - ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1), - ENC(dst, reg, 2))) -INSN(addah, d, adda_long, 1cycle, C64XP, TIC6X_FLAG_PREFER(0), - FIX1(FIX(op, 5)), - OP3(ORAREG1, OLCST, OWREG1), - ENC4(ENC(s, fu, 0), ENC(y, areg, 0), ENC(offsetR, ulcst_dpr_half, 1), - ENC(dst, reg, 2))) - -INSNE(addaw, d_si_si_si, d, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS, - FIX1(FIX(op, 0x38)), - OP3(ORREG1, ORREG1, OWREG1), - ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, reg, 1), - ENC(dst, reg, 2))) -INSNE(addaw, d_si_u5_si, d, 1_or_2_src, 1cycle, C62X, - TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1), - FIX1(FIX(op, 0x3a)), - OP3(ORREG1, OACST, OWREG1), - ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1), - ENC(dst, reg, 2))) -INSN(addaw, d, adda_long, 1cycle, C64XP, TIC6X_FLAG_PREFER(0), - FIX1(FIX(op, 7)), - OP3(ORAREG1, OLCST, OWREG1), - ENC4(ENC(s, fu, 0), ENC(y, areg, 0), ENC(offsetR, ulcst_dpr_word, 1), - ENC(dst, reg, 2))) - -/* 16 bits insn */ -INSN(addaw, d, dx5, 1cycle, C64XP, TIC6X_FLAG_INSN16_BSIDE, - FIX0(), - OP3(ORB15REG1, OACST, OWREG1), - ENC3(ENC(s, fu, 0), ENC(cst, ucst, 1), ENC(dst, reg, 2))) -INSN(addaw, d, dx5p, 1cycle, C64XP, TIC6X_FLAG_INSN16_BSIDE, - FIX1(FIX(op, 0)), - OP3(ORB15REG1, OACST, OWB15REG1), - ENC2(ENC(s, fu, 0), ENC(cst, ucst, 1))) -/**/ - -INSN(adddp, l, 1_or_2_src, addsubdp, C67X, 0, - FIX1(FIX(op, 0x18)), - OP3(ORREGD12, ORXREGD12, OWREGD67), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -INSN(adddp, s, l_1_or_2_src, addsubdp, C67XP, 0, - FIX1(FIX(op, 0x72)), - OP3(ORREGD12, ORXREGD12, OWREGD67), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSN(addk, s, addk, 1cycle, C62X, TIC6X_FLAG_NO_CROSS, - FIX0(), - OP2(OLCST, OWREG1), - ENC3(ENC(s, fu, 0), ENC(cst, scst, 0), ENC(dst, reg, 1))) - -/* 16 bits insn */ -INSN(addk, s, sx5, 1cycle, C64XP, TIC6X_FLAG_NO_CROSS, - FIX0(), - OP2(OACST, OWREG1), - ENC3(ENC(s, fu, 0), ENC(cst, ucst, 0), ENC(dst, reg, 1))) -/**/ - -INSN(addkpc, s, addkpc, 1cycle, C64X, - TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MCNOP|TIC6X_FLAG_SIDE_B_ONLY, - FIX1(FIX(s, 1)), - OP3(OLCST, OWREG1, OACST), - ENC3(ENC(src1, pcrel, 0), ENC(dst, reg, 1), ENC(src2, ucst, 2))) - -INSN(addsp, l, 1_or_2_src, 4cycle, C67X, 0, - FIX1(FIX(op, 0x10)), - OP3(ORREG1, ORXREG1, OWREG4), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -INSN(addsp, s, l_1_or_2_src, 4cycle, C67XP, 0, - FIX1(FIX(op, 0x70)), - OP3(ORREG1, ORXREG1, OWREG4), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSN(addsub, l, 1_or_2_src_noncond, 1cycle, C64XP, 0, - FIX1(FIX(op, 0xc)), - OP3(ORREG1, ORXREG1, OWREGD1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSN(addsub2, l, 1_or_2_src_noncond, 1cycle, C64XP, 0, - FIX1(FIX(op, 0xd)), - OP3(ORREG1, ORXREG1, OWREGD1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSNE(addu, l_ui_xui_ul, l, 1_or_2_src, 1cycle, C62X, 0, - FIX1(FIX(op, 0x2b)), - OP3(ORREG1, ORXREG1, OWREGL1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -INSNE(addu, l_xui_ul_ul, l, 1_or_2_src, 1cycle, C62X, 0, - FIX1(FIX(op, 0x29)), - OP3(ORXREG1, ORREGL1, OWREGL1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSN(add2, s, 1_or_2_src, 1cycle, C62X, 0, - FIX1(FIX(op, 0x1)), - OP3(ORREG1, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -INSN(add2, l, 1_or_2_src, 1cycle, C64X, 0, - FIX1(FIX(op, 0x5)), - OP3(ORREG1, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -INSN(add2, d, ext_1_or_2_src, 1cycle, C64X, 0, - FIX1(FIX(op, 0x4)), - OP3(ORREG1, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSN(add4, l, 1_or_2_src, 1cycle, C64X, 0, - FIX1(FIX(op, 0x65)), - OP3(ORREG1, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSNE(and, l_ui_xui_ui, l, 1_or_2_src, 1cycle, C62X, 0, - FIX1(FIX(op, 0x7b)), - OP3(ORREG1, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -INSNE(and, l_s5_xui_ui, l, 1_or_2_src, 1cycle, C62X, 0, - FIX1(FIX(op, 0x7a)), - OP3(OACST, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -INSNE(and, s_ui_xui_ui, s, 1_or_2_src, 1cycle, C62X, 0, - FIX1(FIX(op, 0x1f)), - OP3(ORREG1, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -INSNE(and, s_s5_xui_ui, s, 1_or_2_src, 1cycle, C62X, 0, - FIX1(FIX(op, 0x1e)), - OP3(OACST, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -INSNE(and, d_ui_xui_ui, d, ext_1_or_2_src, 1cycle, C64X, 0, - FIX1(FIX(op, 0x6)), - OP3(ORREG1, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -INSNE(and, d_s5_xui_ui, d, ext_1_or_2_src, 1cycle, C64X, 0, - FIX1(FIX(op, 0x7)), - OP3(OACST, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -/* 16 bits insn */ -INSN(and, l, l2c, 1cycle, C64XP, 0, - FIX1(FIX(op, 0)), - OP3(ORREG1, ORXREG1, OWREG1NORS), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -/**/ - -INSN(andn, l, 1_or_2_src, 1cycle, C64X, 0, - FIX1(FIX(op, 0x7c)), - OP3(ORREG1, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -INSN(andn, s, ext_1_or_2_src, 1cycle, C64X, 0, - FIX1(FIX(op, 0x6)), - OP3(ORREG1, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -INSN(andn, d, ext_1_or_2_src, 1cycle, C64X, 0, - FIX1(FIX(op, 0x0)), - OP3(ORREG1, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSN(avg2, m, compound, 1616_m, C64X, 0, - FIX1(FIX(op, 0x13)), - OP3(ORREG1, ORXREG1, OWREG2), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSN(avgu4, m, compound, 1616_m, C64X, 0, - FIX1(FIX(op, 0x12)), - OP3(ORREG1, ORXREG1, OWREG2), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSN(b, s, ext_branch_cond_imm, branch, C62X, TIC6X_FLAG_NO_CROSS, - FIX0(), - OP1(OLCST), - ENC2(ENC(s, fu, 0), ENC(cst, pcrel, 0))) -INSN(b, s, branch, branch, C62X, TIC6X_FLAG_SIDE_B_ONLY, - FIX1(FIX(s, 1)), - OP1(ORXREG1), - ENC2(ENC(x, xpath, 0), ENC(src2, reg, 0))) -INSN(b, s, b_irp, branch, C62X, TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY, - FIX3(FIX(s, 1), FIX(x, 0), FIX(dst, 0)), - OP1(ORIRP1), - ENC0()) -INSN(b, s, b_nrp, branch, C62X, TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY, - FIX3(FIX(s, 1), FIX(x, 0), FIX(dst, 0)), - OP1(ORNRP1), - ENC0()) - -INSN(bdec, s, bdec, branch, C64X, TIC6X_FLAG_NO_CROSS, - FIX0(), - OP2(OLCST, ORWREG1), - ENC3(ENC(s, fu, 0), ENC(src, pcrel, 0), ENC(dst, reg, 1))) - -INSN(bitc4, m, unary, 1616_m, C64X, 0, - FIX1(FIX(op, 0x1e)), - OP2(ORXREG1, OWREG2), - ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), - ENC(dst, reg, 1))) - -INSN(bitr, m, unary, 1616_m, C64X, 0, - FIX1(FIX(op, 0x1f)), - OP2(ORXREG1, OWREG2), - ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), - ENC(dst, reg, 1))) - -INSN(bnop, s, branch_nop_cst, branch, C64X, - TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MCNOP, - FIX0(), - OP2(OLCST, OACST), - ENC3(ENC(s, fu, 0), ENC(src2, pcrel_half, 0), ENC(src1, ucst, 1))) -INSN(bnop, nfu, s_branch_nop_cst, branch, C64XP, - TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO|TIC6X_FLAG_MCNOP, - FIX1(FIX(s, 0)), - OP2(OLCST, OACST), - ENC2(ENC(src2, pcrel, 0), ENC(src1, ucst, 1))) -INSN(bnop, s, branch_nop_reg, branch, C64X, - TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_MCNOP, - FIX1(FIX(s, 1)), - OP2(ORXREG1, OACST), - ENC3(ENC(x, xpath, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1))) - -/* 16 bits insn format */ -INSN(bnop, s, sbu8, branch, C64XP, - TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MCNOP, - FIX0(), - OP2(OLCST, OHWCST5), - ENC2(ENC(s, fu, 0), ENC(cst, pcrel_half_unsigned, 0))) -INSN(bnop, s, sbs7, branch, C64XP, - TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MCNOP, - FIX0(), - OP2(OLCST, OACST), - ENC3(ENC(s, fu, 0), ENC(cst, pcrel_half, 0), ENC(n, ucst, 1))) -INSN(bnop, s, sbu8c, branch, C64XP, - TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MCNOP|TIC6X_FLAG_INSN16_SPRED, - FIX0(), - OP2(OLCST, OHWCST5), - ENC2(ENC(s, fu, 0), ENC(cst, pcrel_half_unsigned, 0))) -INSN(bnop, s, sbs7c, branch, C64XP, - TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MCNOP|TIC6X_FLAG_INSN16_SPRED, - FIX0(), - OP2(OLCST, OACST), - ENC3(ENC(s, fu, 0), ENC(cst, pcrel_half, 0), ENC(n, ucst, 1))) -INSN(bnop, s, sx1b, branch, C64XP, - TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MCNOP, - FIX0(), - OP2(ORREG1BNORS, OACST), - ENC3(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(n, ucst, 1))) -/**/ - -INSN(bpos, s, bpos, branch, C64X, TIC6X_FLAG_NO_CROSS, - FIX0(), - OP2(OLCST, ORREG1), - ENC3(ENC(s, fu, 0), ENC(src, pcrel, 0), ENC(dst, reg, 1))) - -INSN(call, s, ext_branch_cond_imm, branch, C62X, - TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO|TIC6X_FLAG_CALL, - FIX0(), - OP1(OLCST), - ENC2(ENC(s, fu, 0), ENC(cst, pcrel, 0))) -INSN(call, s, branch, branch, C62X, - TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_MACRO|TIC6X_FLAG_CALL, - FIX1(FIX(s, 1)), - OP1(ORXREG1), - ENC2(ENC(x, xpath, 0), ENC(src2, reg, 0))) -INSN(call, s, b_irp, branch, C62X, - TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_MACRO|TIC6X_FLAG_CALL, - FIX3(FIX(s, 1), FIX(x, 0), FIX(dst, 0)), - OP1(ORIRP1), - ENC0()) -INSN(call, s, b_nrp, branch, C62X, - TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_MACRO|TIC6X_FLAG_CALL, - FIX3(FIX(s, 1), FIX(x, 0), FIX(dst, 0)), - OP1(ORNRP1), - ENC0()) - -INSN(callnop, s, branch_nop_cst, branch, C64X, - TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO|TIC6X_FLAG_MCNOP|TIC6X_FLAG_CALL, - FIX0(), - OP2(OLCST, OACST), - ENC3(ENC(s, fu, 0), ENC(src2, pcrel, 0), ENC(src1, ucst, 1))) -INSN(callnop, nfu, s_branch_nop_cst, branch, C64XP, - TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO|TIC6X_FLAG_MCNOP|TIC6X_FLAG_CALL, - FIX1(FIX(s, 0)), - OP2(OLCST, OACST), - ENC2(ENC(src2, pcrel, 0), ENC(src1, ucst, 1))) -INSN(callnop, s, branch_nop_reg, branch, C64X, - TIC6X_FLAG_MACRO|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_MCNOP|TIC6X_FLAG_CALL, - FIX1(FIX(s, 1)), - OP2(ORXREG1, OACST), - ENC3(ENC(x, xpath, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1))) - - -INSN(callp, s, call_imm_nop, branch, C64XP, - TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MCNOP, - FIX1(FIX(z, 1)), - OP2(OLCST, OWRETREG1), - ENC2(ENC(s, fu, 0), ENC(cst, pcrel, 0))) - -/* 16 bits insn format */ -INSN(callp, s, scs10, branch, C64XP, - TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MCNOP, - FIX0(), - OP2(OLCST, OWRETREG1), - ENC2(ENC(s, fu, 0), ENC(cst, pcrel, 0))) -/**/ - -INSN(callret, s, ext_branch_cond_imm, branch, C62X, - TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO|TIC6X_FLAG_CALL|TIC6X_FLAG_RETURN, - FIX0(), - OP1(OLCST), - ENC2(ENC(s, fu, 0), ENC(cst, pcrel, 0))) -INSN(callret, s, branch, branch, C62X, - TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_MACRO|TIC6X_FLAG_CALL|TIC6X_FLAG_RETURN, - FIX1(FIX(s, 1)), - OP1(ORXREG1), - ENC2(ENC(x, xpath, 0), ENC(src2, reg, 0))) -INSN(callret, s, b_irp, branch, C62X, - TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_MACRO|TIC6X_FLAG_CALL|TIC6X_FLAG_RETURN, - FIX3(FIX(s, 1), FIX(x, 0), FIX(dst, 0)), - OP1(ORIRP1), - ENC0()) -INSN(callret, s, b_nrp, branch, C62X, - TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_MACRO|TIC6X_FLAG_CALL|TIC6X_FLAG_RETURN, - FIX3(FIX(s, 1), FIX(x, 0), FIX(dst, 0)), - OP1(ORNRP1), - ENC0()) - -INSN(clr, s, field, 1cycle, C62X, TIC6X_FLAG_NO_CROSS, - FIX1(FIX(op, 0x3)), - OP4(ORREG1, OACST, OACST, OWREG1), - ENC5(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(csta, ucst, 1), - ENC(cstb, ucst, 2), ENC(dst, reg, 3))) -INSN(clr, s, 1_or_2_src, 1cycle, C62X, 0, - FIX1(FIX(op, 0x3f)), - OP3(ORXREG1, ORREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), - ENC(src1, reg, 1), ENC(dst, reg, 2))) - -/* 16 bits insn */ -INSN(clr, s, sc5, 1cycle, C64XP, 0, - FIX1(FIX(op, 2)), - OP4(ORREG1, OACST, OACST, OWREG1), - ENC5(ENC(s, fu, 0), ENC(srcdst, reg, 0), ENC(cst, ucst, 1), - ENC(cst, ucst, 2), ENC(srcdst, reg, 3))) -/**/ - -INSNE(cmpeq, l_si_xsi_ui, l, 1_or_2_src, 1cycle, C62X, 0, - FIX1(FIX(op, 0x53)), - OP3(ORREG1, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -INSNE(cmpeq, l_s5_xsi_ui, l, 1_or_2_src, 1cycle, C62X, 0, - FIX1(FIX(op, 0x52)), - OP3(OACST, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -INSNE(cmpeq, l_xsi_sl_ui, l, 1_or_2_src, 1cycle, C62X, 0, - FIX1(FIX(op, 0x51)), - OP3(ORXREG1, ORREGL1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -INSNE(cmpeq, l_s5_sl_ui, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS, - FIX2(FIX(op, 0x50), FIX(x, 0)), - OP3(OACST, ORREGL1, OWREG1), - ENC4(ENC(s, fu, 0), ENC(src1, scst, 0), ENC(src2, reg, 1), - ENC(dst, reg, 2))) - -/* 16 bits insn */ -INSN(cmpeq, l, lx3c, 1cycle, C64XP, TIC6X_FLAG_NO_CROSS, - FIX0(), - OP3(OACST, ORXREG1, OWREG1), - ENC4(ENC(s, fu, 0), ENC(cst, ucst, 0), ENC(src2, reg, 1), - ENC(dst, reg, 2))) - -INSN(cmpeq, l, l2c, 1cycle, C64XP, 0, - FIX1(FIX(op, 3)), - OP3(ORREG1, ORXREG1, OWREG1NORS), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -/**/ - -INSN(cmpeq2, s, 1_or_2_src, 1cycle, C64X, 0, - FIX1(FIX(op, 0x1d)), - OP3(ORREG1, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSN(cmpeq4, s, 1_or_2_src, 1cycle, C64X, 0, - FIX1(FIX(op, 0x1c)), - OP3(ORREG1, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSN(cmpeqdp, s, 1_or_2_src, dpcmp, C67X, 0, - FIX1(FIX(op, 0x28)), - OP3(ORREGD12, ORXREGD12, OWREG2), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSN(cmpeqsp, s, 1_or_2_src, 1cycle, C67X, 0, - FIX1(FIX(op, 0x38)), - OP3(ORREG1, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSNE(cmpgt, l_si_xsi_ui, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_PREFER(1), - FIX1(FIX(op, 0x47)), - OP3(ORREG1, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -INSNE(cmpgt, l_s5_xsi_ui, l, 1_or_2_src, 1cycle, C62X, 0, - FIX1(FIX(op, 0x46)), - OP3(OACST, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -INSNE(cmpgt, l_xsi_sl_ui, l, 1_or_2_src, 1cycle, C62X, 0, - FIX1(FIX(op, 0x45)), - OP3(ORXREG1, ORREGL1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -INSNE(cmpgt, l_s5_sl_ui, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS, - FIX2(FIX(op, 0x44), FIX(x, 0)), - OP3(OACST, ORREGL1, OWREG1), - ENC4(ENC(s, fu, 0), ENC(src1, scst, 0), ENC(src2, reg, 1), - ENC(dst, reg, 2))) -INSNE(cmpgt, l_xsi_si_ui, l, 1_or_2_src, 1cycle, C62X, - TIC6X_FLAG_MACRO|TIC6X_FLAG_PREFER(0), - FIX1(FIX(op, 0x57)), - OP3(ORXREG1, ORREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 1), - ENC(src2, reg, 0), ENC(dst, reg, 2))) -INSNE(cmpgt, l_xsi_s5_ui, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_MACRO, - FIX1(FIX(op, 0x56)), - OP3(ORXREG1, OACST, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 1), - ENC(src2, reg, 0), ENC(dst, reg, 2))) -INSNE(cmpgt, l_sl_xsi_ui, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_MACRO, - FIX1(FIX(op, 0x55)), - OP3(ORREGL1, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 1), - ENC(src2, reg, 0), ENC(dst, reg, 2))) -INSNE(cmpgt, l_sl_s5_ui, l, 1_or_2_src, 1cycle, C62X, - TIC6X_FLAG_MACRO|TIC6X_FLAG_NO_CROSS, - FIX2(FIX(op, 0x54), FIX(x, 0)), - OP3(ORREGL1, OACST, OWREG1), - ENC4(ENC(s, fu, 0), ENC(src1, scst, 1), ENC(src2, reg, 0), - ENC(dst, reg, 2))) - -/* 16 bits insn */ -INSN(cmpgt, l, lx1c, 1cycle, C64XP, 0, - FIX1(FIX(op, 1)), - OP3(OACST, ORREG1, OWREG1), - ENC4(ENC(s, fu, 0), ENC(cst, ucst, 0), ENC(src2, reg, 1), - ENC(dst, reg, 2))) -INSN(cmpgt, l, l2c, 1cycle, C64XP, 0, - FIX1(FIX(op, 5)), - OP3(ORREG1, ORXREG1, OWREG1NORS), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -/**/ - -INSN(cmpgt2, s, 1_or_2_src, 1cycle, C64X, 0, - FIX1(FIX(op, 0x14)), - OP3(ORREG1, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSN(cmpgtdp, s, 1_or_2_src, dpcmp, C67X, 0, - FIX1(FIX(op, 0x29)), - OP3(ORREGD12, ORXREGD12, OWREG2), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSN(cmpgtsp, s, 1_or_2_src, 1cycle, C67X, 0, - FIX1(FIX(op, 0x39)), - OP3(ORREG1, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSNE(cmpgtu, l_ui_xui_ui, l, 1_or_2_src, 1cycle, C62X, 0, - FIX1(FIX(op, 0x4f)), - OP3(ORREG1, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -INSNE(cmpgtu, l_u4_xui_ui, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_PREFER(1), - FIX2(FIX(op, 0x4e), RAN(src1, 0, 15)), - OP3(OACST, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, ucst, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -/* Although not mentioned in SPRUFE8, CMPGTU and CMPLTU support a - 5-bit unsigned constant operand on C64X and above. */ -INSNE(cmpgtu, l_u5_xui_ui, l, 1_or_2_src, 1cycle, C64X, 0, - FIX2(FIX(op, 0x4e), RAN(src1, 16, 31)), - OP3(OACST, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, ucst, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -INSNE(cmpgtu, l_xui_ul_ui, l, 1_or_2_src, 1cycle, C62X, 0, - FIX1(FIX(op, 0x4d)), - OP3(ORXREG1, ORREGL1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -INSNE(cmpgtu, l_u4_ul_ui, l, 1_or_2_src, 1cycle, C62X, - TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1), - FIX3(FIX(op, 0x4c), FIX(x, 0), RAN(src1, 0, 15)), - OP3(OACST, ORREGL1, OWREG1), - ENC4(ENC(s, fu, 0), ENC(src1, ucst, 0), ENC(src2, reg, 1), - ENC(dst, reg, 2))) -INSNE(cmpgtu, l_u5_ul_ui, l, 1_or_2_src, 1cycle, C64X, TIC6X_FLAG_NO_CROSS, - FIX3(FIX(op, 0x4c), FIX(x, 0), RAN(src1, 16, 31)), - OP3(OACST, ORREGL1, OWREG1), - ENC4(ENC(s, fu, 0), ENC(src1, ucst, 0), ENC(src2, reg, 1), - ENC(dst, reg, 2))) - -/* 16 bits insn */ -INSN(cmpgtu, l, lx1c, 1cycle, C64XP, 0, - FIX1(FIX(op, 3)), - OP3(OACST, ORREG1, OWREG1), - ENC4(ENC(s, fu, 0), ENC(cst, ucst, 0), ENC(src2, reg, 1), - ENC(dst, reg, 2))) -INSN(cmpgtu, l, l2c, 1cycle, C64XP, 0, - FIX1(FIX(op, 7)), - OP3(ORREG1, ORXREG1, OWREG1NORS), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -/**/ - -INSN(cmpgtu4, s, 1_or_2_src, 1cycle, C64X, 0, - FIX1(FIX(op, 0x15)), - OP3(ORREG1, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSNE(cmplt, l_si_xsi_ui, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_PREFER(1), - FIX1(FIX(op, 0x57)), - OP3(ORREG1, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -INSNE(cmplt, l_s5_xsi_ui, l, 1_or_2_src, 1cycle, C62X, 0, - FIX1(FIX(op, 0x56)), - OP3(OACST, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -INSNE(cmplt, l_xsi_sl_ui, l, 1_or_2_src, 1cycle, C62X, 0, - FIX1(FIX(op, 0x55)), - OP3(ORXREG1, ORREGL1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -INSNE(cmplt, l_s5_sl_ui, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS, - FIX2(FIX(op, 0x54), FIX(x, 0)), - OP3(OACST, ORREGL1, OWREG1), - ENC4(ENC(s, fu, 0), ENC(src1, scst, 0), ENC(src2, reg, 1), - ENC(dst, reg, 2))) -INSNE(cmplt, l_xsi_si_ui, l, 1_or_2_src, 1cycle, C62X, - TIC6X_FLAG_MACRO|TIC6X_FLAG_PREFER(0), - FIX1(FIX(op, 0x47)), - OP3(ORXREG1, ORREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 1), - ENC(src2, reg, 0), ENC(dst, reg, 2))) -INSNE(cmplt, l_xsi_s5_ui, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_MACRO, - FIX1(FIX(op, 0x46)), - OP3(ORXREG1, OACST, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 1), - ENC(src2, reg, 0), ENC(dst, reg, 2))) -INSNE(cmplt, l_sl_xsi_ui, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_MACRO, - FIX1(FIX(op, 0x45)), - OP3(ORREGL1, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 1), - ENC(src2, reg, 0), ENC(dst, reg, 2))) -INSNE(cmplt, l_sl_s5_ui, l, 1_or_2_src, 1cycle, C62X, - TIC6X_FLAG_MACRO|TIC6X_FLAG_NO_CROSS, - FIX2(FIX(op, 0x44), FIX(x, 0)), - OP3(ORREGL1, OACST, OWREG1), - ENC4(ENC(s, fu, 0), ENC(src1, scst, 1), ENC(src2, reg, 0), - ENC(dst, reg, 2))) - -/* 16 bits insn */ -INSN(cmplt, l, lx1c, 1cycle, C64XP, 0, - FIX1(FIX(op, 0)), - OP3(OACST, ORREG1, OWREG1), - ENC4(ENC(s, fu, 0), ENC(cst, ucst, 0), ENC(src2, reg, 1), - ENC(dst, reg, 2))) -INSN(cmplt, l, l2c, 1cycle, C64XP, 0, - FIX1(FIX(op, 4)), - OP3(ORREG1, ORXREG1, OWREG1NORS), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -/**/ - -INSN(cmplt2, s, 1_or_2_src, 1cycle, C64X, TIC6X_FLAG_MACRO, - FIX1(FIX(op, 0x14)), - OP3(ORXREG1, ORREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), - ENC(src1, reg, 1), ENC(dst, reg, 2))) - -INSN(cmpltdp, s, 1_or_2_src, dpcmp, C67X, 0, - FIX1(FIX(op, 0x2a)), - OP3(ORREGD12, ORXREGD12, OWREG2), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSN(cmpltsp, s, 1_or_2_src, 1cycle, C67X, 0, - FIX1(FIX(op, 0x3a)), - OP3(ORREG1, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSNE(cmpltu, l_ui_xui_ui, l, 1_or_2_src, 1cycle, C62X, 0, - FIX1(FIX(op, 0x5f)), - OP3(ORREG1, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -INSNE(cmpltu, l_u4_xui_ui, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_PREFER(1), - FIX2(FIX(op, 0x5e), RAN(src1, 0, 15)), - OP3(OACST, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, ucst, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -INSNE(cmpltu, l_u5_xui_ui, l, 1_or_2_src, 1cycle, C64X, 0, - FIX2(FIX(op, 0x5e), RAN(src1, 16, 31)), - OP3(OACST, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, ucst, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -INSNE(cmpltu, l_xui_ul_ui, l, 1_or_2_src, 1cycle, C62X, 0, - FIX1(FIX(op, 0x5d)), - OP3(ORXREG1, ORREGL1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -INSNE(cmpltu, l_u4_ul_ui, l, 1_or_2_src, 1cycle, C62X, - TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1), - FIX3(FIX(op, 0x5c), FIX(x, 0), RAN(src1, 0, 15)), - OP3(OACST, ORREGL1, OWREG1), - ENC4(ENC(s, fu, 0), ENC(src1, ucst, 0), ENC(src2, reg, 1), - ENC(dst, reg, 2))) -INSNE(cmpltu, l_u5_ul_ui, l, 1_or_2_src, 1cycle, C64X, TIC6X_FLAG_NO_CROSS, - FIX3(FIX(op, 0x5c), FIX(x, 0), RAN(src1, 16, 31)), - OP3(OACST, ORREGL1, OWREG1), - ENC4(ENC(s, fu, 0), ENC(src1, ucst, 0), ENC(src2, reg, 1), - ENC(dst, reg, 2))) - -/* 16 bits insn */ -INSN(cmpltu, l, lx1c, 1cycle, C64XP, 0, - FIX1(FIX(op, 2)), - OP3(OACST, ORREG1, OWREG1), - ENC4(ENC(s, fu, 0), ENC(cst, ucst, 0), ENC(src2, reg, 1), - ENC(dst, reg, 2))) -INSN(cmpltu, l, l2c, 1cycle, C64XP, 0, - FIX1(FIX(op, 6)), - OP3(ORREG1, ORXREG1, OWREG1NORS), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -/**/ - -INSN(cmpltu4, s, 1_or_2_src, 1cycle, C64X, TIC6X_FLAG_MACRO, - FIX1(FIX(op, 0x15)), - OP3(ORXREG1, ORREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), - ENC(src1, reg, 1), ENC(dst, reg, 2))) - -INSN(cmpy, m, 1_or_2_src, 4cycle, C64XP, 0, - FIX1(FIX(op, 0xa)), - OP3(ORREG1, ORXREG1, OWREGD4), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSN(cmpyr, m, 1_or_2_src, 4cycle, C64XP, 0, - FIX1(FIX(op, 0xb)), - OP3(ORREG1, ORXREG1, OWREG4), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSN(cmpyr1, m, 1_or_2_src, 4cycle, C64XP, 0, - FIX1(FIX(op, 0xc)), - OP3(ORREG1, ORXREG1, OWREG4), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSN(cmtl, d, 1_or_2_src, load, C64XP, - TIC6X_FLAG_LOAD|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_SIDE_T2_ONLY|TIC6X_FLAG_NO_CROSS, - FIX3(FIX(s, 1), FIX(op, 0xe), FIX(src1, 0)), - OP2(ORMEMDW, OWDREG5), - ENC2(ENC(src2, reg, 0), ENC(dst, reg, 1))) - -INSN(ddotp4, m, 1_or_2_src, 4cycle, C64XP, 0, - FIX1(FIX(op, 0x18)), - OP3(ORREG1, ORXREG1, OWREGD4), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSN(ddotph2, m, 1_or_2_src, 4cycle, C64XP, 0, - FIX1(FIX(op, 0x17)), - OP3(ORREGD1, ORXREG1, OWREGD4), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSN(ddotph2r, m, 1_or_2_src, 4cycle, C64XP, 0, - FIX1(FIX(op, 0x15)), - OP3(ORREGD1, ORXREG1, OWREG4), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSN(ddotpl2, m, 1_or_2_src, 4cycle, C64XP, 0, - FIX1(FIX(op, 0x16)), - OP3(ORREGD1, ORXREG1, OWREGD4), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSN(ddotpl2r, m, 1_or_2_src, 4cycle, C64XP, 0, - FIX1(FIX(op, 0x14)), - OP3(ORREGD1, ORXREG1, OWREG4), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSN(deal, m, unary, 1616_m, C64X, 0, - FIX1(FIX(op, 0x1d)), - OP2(ORXREG1, OWREG2), - ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), - ENC(dst, reg, 1))) - -INSN(dint, nfu, dint, 1cycle, C64XP, 0, - FIX1(FIX(s, 0)), - OP0(), - ENC0()) - -INSN(dmv, s, ext_1_or_2_src, 1cycle, C64XP, 0, - FIX1(FIX(op, 0xb)), - OP3(ORREG1, ORXREG1, OWREGD1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSNE(dotp2, m_s2_xs2_si, m, compound, 4cycle, C64X, 0, - FIX1(FIX(op, 0xc)), - OP3(ORREG1, ORXREG1, OWREG4), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -INSNE(dotp2, m_s2_xs2_sll, m, compound, 4cycle, C64X, 0, - FIX1(FIX(op, 0xb)), - OP3(ORREG1, ORXREG1, OWREGD4), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSN(dotpn2, m, compound, 4cycle, C64X, 0, - FIX1(FIX(op, 0x9)), - OP3(ORREG1, ORXREG1, OWREG4), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSN(dotpnrsu2, m, compound, 4cycle, C64X, 0, - FIX1(FIX(op, 0x7)), - OP3(ORREG1, ORXREG1, OWREG4), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSN(dotpnrus2, m, compound, 4cycle, C64X, TIC6X_FLAG_MACRO, - FIX1(FIX(op, 0x7)), - OP3(ORXREG1, ORREG1, OWREG4), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), - ENC(src1, reg, 1), ENC(dst, reg, 2))) - -INSN(dotprsu2, m, compound, 4cycle, C64X, 0, - FIX1(FIX(op, 0xd)), - OP3(ORREG1, ORXREG1, OWREG4), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSN(dotprus2, m, compound, 4cycle, C64X, TIC6X_FLAG_MACRO, - FIX1(FIX(op, 0xd)), - OP3(ORXREG1, ORREG1, OWREG4), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), - ENC(src1, reg, 1), ENC(dst, reg, 2))) - -INSN(dotpsu4, m, compound, 4cycle, C64X, 0, - FIX1(FIX(op, 0x2)), - OP3(ORREG1, ORXREG1, OWREG4), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSN(dotpus4, m, compound, 4cycle, C64X, TIC6X_FLAG_MACRO, - FIX1(FIX(op, 0x2)), - OP3(ORXREG1, ORREG1, OWREG4), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), - ENC(src1, reg, 1), ENC(dst, reg, 2))) - -INSN(dotpu4, m, compound, 4cycle, C64X, 0, - FIX1(FIX(op, 0x6)), - OP3(ORREG1, ORXREG1, OWREG4), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSN(dpack2, l, 1_or_2_src_noncond, 1cycle, C64XP, 0, - FIX1(FIX(op, 0x34)), - OP3(ORREG1, ORXREG1, OWREGD1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSN(dpackx2, l, 1_or_2_src_noncond, 1cycle, C64XP, 0, - FIX1(FIX(op, 0x33)), - OP3(ORREG1, ORXREG1, OWREGD1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSN(dpint, l, 1_or_2_src, 4cycle, C67X, TIC6X_FLAG_NO_CROSS, - FIX2(FIX(op, 0x8), FIX(x, 0)), - OP2(ORREGD1, OWREG4), - ENC4(ENC(s, fu, 0), ENC(src2, regpair_msb, 0), ENC(src1, regpair_lsb, 0), - ENC(dst, reg, 1))) - -INSN(dpsp, l, 1_or_2_src, 4cycle, C67X, TIC6X_FLAG_NO_CROSS, - FIX2(FIX(op, 0x9), FIX(x, 0)), - OP2(ORREGD1, OWREG4), - ENC4(ENC(s, fu, 0), ENC(src2, regpair_msb, 0), ENC(src1, regpair_lsb, 0), - ENC(dst, reg, 1))) - -INSN(dptrunc, l, 1_or_2_src, 4cycle, C67X, TIC6X_FLAG_NO_CROSS, - FIX2(FIX(op, 0x1), FIX(x, 0)), - OP2(ORREGD1, OWREG4), - ENC4(ENC(s, fu, 0), ENC(src2, regpair_msb, 0), ENC(src1, regpair_lsb, 0), - ENC(dst, reg, 1))) - -INSN(ext, s, field, 1cycle, C62X, TIC6X_FLAG_NO_CROSS, - FIX1(FIX(op, 0x1)), - OP4(ORREG1, OACST, OACST, OWREG1), - ENC5(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(csta, ucst, 1), - ENC(cstb, ucst, 2), ENC(dst, reg, 3))) -INSN(ext, s, 1_or_2_src, 1cycle, C62X, 0, - FIX1(FIX(op, 0x2f)), - OP3(ORXREG1, ORREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), - ENC(src1, reg, 1), ENC(dst, reg, 2))) - -/* 16 bits insn */ -INSNE(ext, hwcst16, s, s2ext, 1cycle, C64XP, 0, - FIX1(FIX(op, 0x0)), - OP4(ORREG1, OHWCST16, OHWCST16, OWREG1), - ENC3(ENC(s, fu, 0), ENC(src, reg, 0), ENC(dst, reg, 3))) -INSNE(ext, hwcst24, s, s2ext, 1cycle, C64XP, 0, - FIX1(FIX(op, 0x1)), - OP4(ORREG1, OHWCST24, OHWCST24, OWREG1), - ENC3(ENC(s, fu, 0), ENC(src, reg, 0), ENC(dst, reg, 3))) -/**/ - -INSN(extu, s, field, 1cycle, C62X, TIC6X_FLAG_NO_CROSS, - FIX1(FIX(op, 0x0)), - OP4(ORREG1, OACST, OACST, OWREG1), - ENC5(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(csta, ucst, 1), - ENC(cstb, ucst, 2), ENC(dst, reg, 3))) -INSN(extu, s, 1_or_2_src, 1cycle, C62X, 0, - FIX1(FIX(op, 0x2b)), - OP3(ORXREG1, ORREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), - ENC(src1, reg, 1), ENC(dst, reg, 2))) - -/* 16 bits insn */ -INSNE(extu, hwcst16, s, s2ext, 1cycle, C64XP, 0, - FIX1(FIX(op, 0x2)), - OP4(ORREG1, OHWCST16, OHWCST16, OWREG1), - ENC3(ENC(s, fu, 0), ENC(src, reg, 0), ENC(dst, reg, 3))) -INSNE(extu, hwcst24, s, s2ext, 1cycle, C64XP, 0, - FIX1(FIX(op, 0x3)), - OP4(ORREG1, OHWCST24, OHWCST24, OWREG1), - ENC3(ENC(s, fu, 0), ENC(src, reg, 0), ENC(dst, reg, 3))) -INSN(extu, s, sc5, 1cycle, C64XP, 0, - FIX1(FIX(op, 0)), - OP4(ORREG1, OACST, OHWCST31, OWREG1Z), - ENC3(ENC(s, fu, 0), ENC(srcdst, reg, 0), ENC(cst, ucst, 1))) -/**/ - -INSN(gmpy, m, 1_or_2_src, 4cycle, C64XP, TIC6X_FLAG_NO_CROSS, - FIX2(FIX(op, 0x1f), FIX(x, 0)), - OP3(ORREG1, ORREG1, OWREG4), - ENC4(ENC(s, fu, 0), ENC(src1, reg, 0), ENC(src2, reg, 1), - ENC(dst, reg, 2))) - -/* This instruction can be predicated as usual; SPRUFE8 is incorrect - where it shows the "z" field as fixed to 1. */ -INSN(gmpy4, m, compound, 4cycle, C64X, 0, - FIX1(FIX(op, 0x11)), - OP3(ORREG1, ORXREG1, OWREG4), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSN(idle, nfu, nop_idle, nop, C62X, TIC6X_FLAG_MCNOP, - FIX2(FIX(s, 0), FIX(op, 0xf)), - OP0(), - ENC0()) - -INSN(intdp, l, 1_or_2_src, intdp, C67X, 0, - FIX2(FIX(op, 0x39), FIX(src1, 0)), - OP2(ORXREG1, OWREGD45), - ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), - ENC(dst, reg, 1))) - -INSN(intdpu, l, 1_or_2_src, intdp, C67X, 0, - FIX2(FIX(op, 0x3b), FIX(src1, 0)), - OP2(ORXREG1, OWREGD45), - ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), - ENC(dst, reg, 1))) - -INSN(intsp, l, 1_or_2_src, 4cycle, C67X, 0, - FIX2(FIX(op, 0x4a), FIX(src1, 0)), - OP2(ORXREG1, OWREG4), - ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), - ENC(dst, reg, 1))) - -INSN(intspu, l, 1_or_2_src, 4cycle, C67X, 0, - FIX2(FIX(op, 0x49), FIX(src1, 0)), - OP2(ORXREG1, OWREG4), - ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), - ENC(dst, reg, 1))) - -INSN(ldb, d, load_store, load, C62X, - TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1), - FIX2(FIX(op, 2), FIX(r, 0)), - OP2(ORMEMSB, OWDREG5), - ENC6(ENC(s, data_fu, 0), ENC(y, fu, 0), ENC(mode, mem_mode, 0), - ENC(offsetR, mem_offset, 0), ENC(baseR, reg, 0), - ENC(srcdst, reg, 1))) -INSN(ldb, d, load_store_long, load, C62X, - TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_PREFER(0), - FIX1(FIX(op, 2)), - OP2(ORMEMLB, OWDREG5), - ENC4(ENC(s, data_fu, 0), ENC(y, areg, 0), ENC(offsetR, ulcst_dpr_byte, 0), - ENC(dst, reg, 1))) - -/* 16 bits insn */ -INSN(ldb, d, doff4_dsz_x01, load, C64XP, - TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSITIVE), - FIX2(FIX(op, 1), FIX(sz, 1)), - OP2(ORMEMSB, OWTREG5), - ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 1), - ENC(ptr, reg_ptr, 0), ENC(cst, mem_offset, 0))) -INSN(ldb, d, dind_dsz_x01, load, C64XP, - TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(REG_POSITIVE), - FIX2(FIX(op, 1), FIX(sz, 1)), - OP2(ORMEMSB, OWTREG5), - ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 1), - ENC(ptr, reg_ptr, 0), ENC(src1, mem_offset, 0))) -INSN(ldb, d, dinc_dsz_x01, load, C64XP, - TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSTINCR), - FIX2(FIX(op, 1), FIX(sz, 1)), - OP2(ORMEMSB, OWTREG5), - ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 1), - ENC(ptr, reg_ptr, 0), ENC(cst, mem_offset_minus_one, 0))) -INSN(ldb, d, ddec_dsz_x01, load, C64XP, - TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(PREDECR), - FIX2(FIX(op, 1), FIX(sz, 1)), - OP2(ORMEMSB, OWTREG5), - ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 1), - ENC(ptr, reg_ptr, 0), ENC(cst, mem_offset_minus_one, 0))) -/**/ - -INSN(ldbu, d, load_store, load, C62X, - TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1), - FIX2(FIX(op, 1), FIX(r, 0)), - OP2(ORMEMSB, OWDREG5), - ENC6(ENC(s, data_fu, 0), ENC(y, fu, 0), ENC(mode, mem_mode, 0), - ENC(offsetR, mem_offset, 0), ENC(baseR, reg, 0), - ENC(srcdst, reg, 1))) -INSN(ldbu, d, load_store_long, load, C62X, - TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_PREFER(0), - FIX1(FIX(op, 1)), - OP2(ORMEMLB, OWDREG5), - ENC4(ENC(s, data_fu, 0), ENC(y, areg, 0), ENC(offsetR, ulcst_dpr_byte, 0), - ENC(dst, reg, 1))) - -/* 16 bits insn */ -INSN(ldbu, d, dinc_dsz_000, load, C64XP, - TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSTINCR), - FIX2(FIX(op, 1), FIX(sz, 1)), - OP2(ORMEMSB, OWTREG5), - ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(cst, mem_offset_minus_one, 0), - ENC(ptr, reg_ptr, 0), ENC(srcdst, reg, 1))) -INSN(ldbu, d, dind_dsz_000, load, C64XP, - TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(REG_POSITIVE), - FIX2(FIX(op, 1), FIX(sz, 1)), - OP2(ORMEMSB, OWTREG5), - ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(src1, mem_offset, 0), - ENC(ptr, reg_ptr, 0), ENC(srcdst, reg, 1))) -INSN(ldbu, d, doff4_dsz_000, load, C64XP, - TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSITIVE), - FIX2(FIX(op, 1), FIX(sz, 1)), - OP2(ORMEMSB, OWTREG5), - ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(cst, mem_offset, 0), - ENC(ptr, reg_ptr, 0), ENC(srcdst, reg, 1))) -INSN(ldbu, d, ddec_dsz_000, load, C64XP, - TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(PREDECR), - FIX2(FIX(op, 1), FIX(sz, 1)), - OP2(ORMEMSB, OWTREG5), - ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(cst, mem_offset_minus_one, 0), - ENC(ptr, reg_ptr, 0), ENC(srcdst, reg, 1))) -/**/ - -INSN(lddw, d, load_store, load, C64X_AND_C67X, - TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS, - FIX2(FIX(op, 6), FIX(r, 1)), - OP2(ORMEMSD, OWDREGD5), - ENC6(ENC(s, data_fu, 0), ENC(y, fu, 0), ENC(mode, mem_mode, 0), - ENC(offsetR, mem_offset, 0), ENC(baseR, reg, 0), - ENC(srcdst, reg, 1))) - -/* 16 bits insn */ -INSN(lddw, d, dpp, load, C64XP, - TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(PREINCR)|TIC6X_FLAG_INSN16_B15PTR|TIC6X_FLAG_INSN16_NORS, - FIX2(FIX(op, 1), FIX(dw, 1)), - OP2(ORMEMSD, OWDREGD5), - ENC4(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 1), - ENC(cst, mem_offset_minus_one, 0))) -INSN(lddw, d, ddecdw, load, C64XP, - TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(PREDECR), - FIX3(FIX(op, 1), FIX(na, 0), FIX(sz, 0)), - OP2(ORMEMSD, OWTREGD5), - ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg_shift, 1), - ENC(ptr, reg_ptr, 0), ENC(cst, mem_offset_minus_one, 0))) -INSN(lddw, d, dincdw, load, C64XP, - TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSTINCR), - FIX3(FIX(op, 1), FIX(na, 0), FIX(sz, 0)), - OP2(ORMEMSD, OWTREGD5), - ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg_shift, 1), - ENC(ptr, reg_ptr, 0), ENC(cst, mem_offset_minus_one, 0))) -INSN(lddw, d, dinddw, load, C64XP, - TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(REG_POSITIVE), - FIX3(FIX(op, 1), FIX(na, 0), FIX(sz, 0)), - OP2(ORMEMSD, OWTREGD5), - ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(src1, mem_offset, 0), - ENC(ptr, reg_ptr, 0), ENC(srcdst, reg_shift, 1))) -INSN(lddw, d, doff4dw, load, C64XP, - TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSITIVE), - FIX3(FIX(op, 1), FIX(na, 0), FIX(sz, 0)), - OP2(ORMEMSD, OWTREGD5), - ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(cst, mem_offset, 0), - ENC(ptr, reg_ptr, 0), ENC(srcdst, reg_shift, 1))) -/**/ - -INSN(ldh, d, load_store, load, C62X, - TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1), - FIX2(FIX(op, 4), FIX(r, 0)), - OP2(ORMEMSH, OWDREG5), - ENC6(ENC(s, data_fu, 0), ENC(y, fu, 0), ENC(mode, mem_mode, 0), - ENC(offsetR, mem_offset, 0), ENC(baseR, reg, 0), - ENC(srcdst, reg, 1))) -INSN(ldh, d, load_store_long, load, C62X, - TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_PREFER(0), - FIX1(FIX(op, 4)), - OP2(ORMEMLH, OWDREG5), - ENC4(ENC(s, data_fu, 0), ENC(y, areg, 0), ENC(offsetR, ulcst_dpr_half, 0), - ENC(dst, reg, 1))) - -/* 16 bits insn */ -INSN(ldh, d, doff4_dsz_x11, load, C64XP, - TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSITIVE), - FIX2(FIX(op, 1), FIX(sz, 1)), - OP2(ORMEMSH, OWTREG5), - ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(cst, mem_offset, 0), - ENC(ptr, reg_ptr, 0), ENC(srcdst, reg, 1))) -INSN(ldh, d, dind_dsz_x11, load, C64XP, - TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(REG_POSITIVE), - FIX2(FIX(op, 1), FIX(sz, 1)), - OP2(ORMEMSH, OWTREG5), - ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 1), - ENC(ptr, reg_ptr, 0), ENC(src1, mem_offset, 0))) -INSN(ldh, d, dinc_dsz_x11, load, C64XP, - TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSTINCR), - FIX2(FIX(op, 1), FIX(sz, 1)), - OP2(ORMEMSH, OWTREG5), - ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 1), - ENC(ptr, reg_ptr, 0), ENC(cst, mem_offset_minus_one, 0))) -INSN(ldh, d, ddec_dsz_x11, load, C64XP, - TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(PREDECR), - FIX2(FIX(op, 1), FIX(sz, 1)), - OP2(ORMEMSH, OWTREG5), - ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 1), - ENC(ptr, reg_ptr, 0), ENC(cst, mem_offset_minus_one, 0))) -/**/ - -INSN(ldhu, d, load_store, load, C62X, - TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1), - FIX2(FIX(op, 0), FIX(r, 0)), - OP2(ORMEMSH, OWDREG5), - ENC6(ENC(s, data_fu, 0), ENC(y, fu, 0), ENC(mode, mem_mode, 0), - ENC(offsetR, mem_offset, 0), ENC(baseR, reg, 0), - ENC(srcdst, reg, 1))) -INSN(ldhu, d, load_store_long, load, C62X, - TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_PREFER(0), - FIX1(FIX(op, 0)), - OP2(ORMEMLH, OWDREG5), - ENC4(ENC(s, data_fu, 0), ENC(y, areg, 0), ENC(offsetR, ulcst_dpr_half, 0), - ENC(dst, reg, 1))) - -/* 16 bits insn */ -INSN(ldhu, d, doff4_dsz_010, load, C64XP, - TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSITIVE), - FIX2(FIX(op, 1), FIX(sz, 1)), - OP2(ORMEMSH, OWTREG5), - ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(cst, mem_offset, 0), - ENC(ptr, reg_ptr, 0), ENC(srcdst, reg, 1))) -INSN(ldhu, d, dind_dsz_010, load, C64XP, - TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(REG_POSITIVE), - FIX2(FIX(op, 1), FIX(sz, 1)), - OP2(ORMEMSH, OWTREG5), - ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 1), - ENC(ptr, reg_ptr, 0), ENC(src1, mem_offset, 0))) -INSN(ldhu, d, dinc_dsz_010, load, C64XP, - TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSTINCR), - FIX2(FIX(op, 1), FIX(sz, 1)), - OP2(ORMEMSH, OWTREG5), - ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 1), - ENC(ptr, reg_ptr, 0), ENC(cst, mem_offset_minus_one, 0))) -INSN(ldhu, d, ddec_dsz_010, load, C64XP, - TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(PREDECR), - FIX2(FIX(op, 1), FIX(sz, 1)), - OP2(ORMEMSH, OWTREG5), - ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 1), - ENC(ptr, reg_ptr, 0), ENC(cst, mem_offset_minus_one, 0))) -/**/ - -INSN(ldndw, d, load_nonaligned, load, C64X, - TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_UNALIGNED, - FIX0(), - OP2(ORMEMND, OWDREGD5), - ENC7(ENC(s, data_fu, 0), ENC(y, fu, 0), ENC(mode, mem_mode, 0), - ENC(offsetR, mem_offset_noscale, 0), ENC(baseR, reg, 0), - ENC(sc, scaled, 0), ENC(dst, reg_shift, 1))) - -/* 16 bits insn */ -INSN(ldndw, d, ddecdw, load, C64XP, - TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(PREDECR), - FIX3(FIX(op, 1), FIX(na, 1), FIX(sz, 0)), - OP2(ORMEMND, OWTREGD5), - ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg_shift, 1), - ENC(ptr, reg_ptr, 0), ENC(cst, mem_offset_minus_one_noscale, 0))) -INSN(ldndw, d, dincdw, load, C64XP, - TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSTINCR), - FIX3(FIX(op, 1), FIX(na, 1), FIX(sz, 0)), - OP2(ORMEMND, OWTREGD5), - ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg_shift, 1), - ENC(ptr, reg_ptr, 0), ENC(cst, mem_offset_minus_one_noscale, 0))) -INSN(ldndw, d, dinddw, load, C64XP, - TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_UNALIGNED|TIC6X_FLAG_INSN16_MEM_MODE(REG_POSITIVE), - FIX3(FIX(op, 1), FIX(na, 1), FIX(sz, 0)), - OP2(ORMEMND, OWTREGD5), - ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(src1, mem_offset_noscale, 0), - ENC(ptr, reg_ptr, 0), ENC(srcdst, reg_shift, 1))) -INSN(ldndw, d, doff4dw, load, C64XP, - TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_UNALIGNED|TIC6X_FLAG_INSN16_MEM_MODE(POSITIVE), - FIX3(FIX(op, 1), FIX(na, 1), FIX(sz, 0)), - OP2(ORMEMND, OWTREGD5), - ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(cst, mem_offset_noscale, 0), - ENC(ptr, reg_ptr, 0), ENC(srcdst, reg_shift, 1))) -/**/ - -INSN(ldnw, d, load_store, load, C64X, - TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_UNALIGNED, - FIX2(FIX(op, 3), FIX(r, 1)), - OP2(ORMEMSW, OWDREG5), - ENC6(ENC(s, data_fu, 0), ENC(y, fu, 0), ENC(mode, mem_mode, 0), - ENC(offsetR, mem_offset, 0), ENC(baseR, reg, 0), - ENC(srcdst, reg, 1))) - -/* 16 bits insn */ -INSN(ldnw, d, doff4_dsz_110, load, C64XP, - TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSITIVE), - FIX2(FIX(op, 1), FIX(sz, 1)), - OP2(ORMEMSW, OWTREG5), - ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 1), - ENC(ptr, reg_ptr, 0), ENC(cst, mem_offset, 0))) -INSN(ldnw, d, dind_dsz_110, load, C64XP, - TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(REG_POSITIVE), - FIX2(FIX(op, 1), FIX(sz, 1)), - OP2(ORMEMSW, OWTREG5), - ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 1), - ENC(ptr, reg_ptr, 0), ENC(src1, mem_offset, 0))) -INSN(ldnw, d, dinc_dsz_110, load, C64XP, - TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSTINCR), - FIX2(FIX(op, 1), FIX(sz, 1)), - OP2(ORMEMSW, OWTREG5), - ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 1), - ENC(ptr, reg_ptr, 0), ENC(cst, mem_offset_minus_one, 0))) -INSN(ldnw, d, ddec_dsz_110, load, C64XP, - TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(PREDECR), - FIX2(FIX(op, 1), FIX(sz, 1)), - OP2(ORMEMSW, OWTREG5), - ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 1), - ENC(ptr, reg_ptr, 0), ENC(cst, mem_offset_minus_one, 0))) -/**/ - -INSN(ldw, d, load_store, load, C62X, - TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1), - FIX2(FIX(op, 6), FIX(r, 0)), - OP2(ORMEMSW, OWDREG5), - ENC6(ENC(s, data_fu, 0), ENC(y, fu, 0), ENC(mode, mem_mode, 0), - ENC(offsetR, mem_offset, 0), ENC(baseR, reg, 0), - ENC(srcdst, reg, 1))) -INSN(ldw, d, load_store_long, load, C62X, - TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_PREFER(0), - FIX1(FIX(op, 6)), - OP2(ORMEMLW, OWDREG5), - ENC4(ENC(s, data_fu, 0), ENC(y, areg, 0), ENC(offsetR, ulcst_dpr_word, 0), - ENC(dst, reg, 1))) - -/* 16 bits insn */ -INSN(ldw, d, doff4_dsz_0xx, load, C64XP, - TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSITIVE), - FIX2(FIX(op, 1), FIX(sz, 0)), - OP2(ORMEMSW, OWTREG5), - ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 1), - ENC(ptr, reg_ptr, 0), ENC(cst, mem_offset, 0))) -INSN(ldw, d, doff4_dsz_100, load, C64XP, - TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSITIVE), - FIX2(FIX(op, 1), FIX(sz, 1)), - OP2(ORMEMSW, OWTREG5), - ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 1), - ENC(ptr, reg_ptr, 0), ENC(cst, mem_offset, 0))) -INSN(ldw, d, dind_dsz_0xx, load, C64XP, - TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(REG_POSITIVE), - FIX2(FIX(op, 1), FIX(sz, 0)), - OP2(ORMEMSW, OWTREG5), - ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 1), - ENC(ptr, reg_ptr, 0), ENC(src1, mem_offset, 0))) -INSN(ldw, d, dind_dsz_100, load, C64XP, - TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(REG_POSITIVE), - FIX2(FIX(op, 1), FIX(sz, 1)), - OP2(ORMEMSW, OWTREG5), - ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 1), - ENC(ptr, reg_ptr, 0), ENC(src1, mem_offset, 0))) -INSN(ldw, d, dinc_dsz_0xx, load, C64XP, - TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSTINCR), - FIX2(FIX(op, 1), FIX(sz, 0)), - OP2(ORMEMSW, OWTREG5), - ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 1), - ENC(ptr, reg_ptr, 0), ENC(cst, mem_offset_minus_one, 0))) -INSN(ldw, d, dinc_dsz_100, load, C64XP, - TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSTINCR), - FIX2(FIX(op, 1), FIX(sz, 1)), - OP2(ORMEMSW, OWTREG5), - ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 1), - ENC(ptr, reg_ptr, 0), ENC(cst, mem_offset_minus_one, 0))) -INSN(ldw, d, ddec_dsz_0xx, load, C64XP, - TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(PREDECR), - FIX2(FIX(op, 1), FIX(sz, 0)), - OP2(ORMEMSW, OWTREG5), - ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 1), - ENC(ptr, reg_ptr, 0), ENC(cst, mem_offset_minus_one, 0))) -INSN(ldw, d, ddec_dsz_100, load, C64XP, - TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(PREDECR), - FIX2(FIX(op, 1), FIX(sz, 1)), - OP2(ORMEMSW, OWTREG5), - ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 1), - ENC(ptr, reg_ptr, 0), ENC(cst, mem_offset_minus_one, 0))) -INSN(ldw, d, dpp, load, C64XP, - TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(PREINCR)|TIC6X_FLAG_INSN16_B15PTR|TIC6X_FLAG_INSN16_NORS, - FIX2(FIX(op, 1), FIX(dw, 0)), - OP2(ORMEMSW, OWTREG5), - ENC4(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 1), - ENC(cst, mem_offset_minus_one, 0))) -INSN(ldw, d, dstk, load, C64XP, - TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSITIVE)|TIC6X_FLAG_INSN16_B15PTR, - FIX2(FIX(op, 0x1), FIX(s, 1)), - OP2(ORMEMSW, OWTREG5), - ENC4(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 1), - ENC(cst, mem_offset, 0))) -/**/ - -INSN(ll, d, 1_or_2_src, load, C64XP, - TIC6X_FLAG_LOAD|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_SIDE_T2_ONLY|TIC6X_FLAG_NO_CROSS, - FIX3(FIX(s, 1), FIX(op, 0xc), FIX(src1, 0)), - OP2(ORMEMDW, OWDREG5), - ENC2(ENC(src2, reg, 0), ENC(dst, reg, 1))) - -INSNE(lmbd, l_ui_xui_ui, l, 1_or_2_src, 1cycle, C62X, 0, - FIX1(FIX(op, 0x6b)), - OP3(ORREG1, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -INSNE(lmbd, l_s5_xui_ui, l, 1_or_2_src, 1cycle, C62X, 0, - FIX1(FIX(op, 0x6a)), - OP3(OACST, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSN(max2, l, 1_or_2_src, 1cycle, C64X, 0, - FIX1(FIX(op, 0x42)), - OP3(ORREG1, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -INSN(max2, s, ext_1_or_2_src, 1cycle, C64XP, 0, - FIX1(FIX(op, 0xd)), - OP3(ORREG1, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSN(maxu4, l, 1_or_2_src, 1cycle, C64X, 0, - FIX1(FIX(op, 0x43)), - OP3(ORREG1, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSN(min2, l, 1_or_2_src, 1cycle, C64X, 0, - FIX1(FIX(op, 0x41)), - OP3(ORREG1, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -INSN(min2, s, ext_1_or_2_src, 1cycle, C64XP, 0, - FIX1(FIX(op, 0xc)), - OP3(ORREG1, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSN(minu4, l, 1_or_2_src, 1cycle, C64X, 0, - FIX1(FIX(op, 0x48)), - OP3(ORREG1, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSNE(mpy, m_sl16_xsl16_si, m, mpy, 1616_m, C62X, 0, - FIX1(FIX(op, 0x19)), - OP3(ORREG1, ORXREG1, OWREG2), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -INSNE(mpy, m_s5_xsl16_si, m, mpy, 1616_m, C62X, 0, - FIX1(FIX(op, 0x18)), - OP3(OACST, ORXREG1, OWREG2), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -/* 16-bit insn. */ -INSN(mpy, m, m3_sat_0, 1616_m, C67X, 0, - FIX1(FIX(op, 0x0)), - OP3(ORREG1, ORXREG1, OWREG2), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg_shift, 2))) - -INSN(mpydp, m, mpy, mpydp, C67X, 0, - FIX1(FIX(op, 0x0e)), - OP3(ORREGD1234, ORXREGD1324, OWREGD910), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSN(mpyh, m, mpy, 1616_m, C62X, 0, - FIX1(FIX(op, 0x01)), - OP3(ORREG1, ORXREG1, OWREG2), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -/* 16 bits insn */ -INSN(mpyh, m, m3_sat_0, 1616_m, C67X, 0, - FIX1(FIX(op, 0x1)), - OP3(ORREG1, ORXREG1, OWREG2), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg_shift, 2))) -/**/ - -INSN(mpyhi, m, compound, 4cycle, C64X, 0, - FIX1(FIX(op, 0x14)), - OP3(ORREG1, ORXREG1, OWREGD4), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSN(mpyhir, m, compound, 4cycle, C64X, 0, - FIX1(FIX(op, 0x10)), - OP3(ORREG1, ORXREG1, OWREG4), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSN(mpyhl, m, mpy, 1616_m, C62X, 0, - FIX1(FIX(op, 0x09)), - OP3(ORREG1, ORXREG1, OWREG2), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -/* 16 bits insn */ -INSN(mpyhl, m, m3_sat_0, 1616_m, C67X, 0, - FIX1(FIX(op, 0x3)), - OP3(ORREG1, ORXREG1, OWREG2), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg_shift, 2))) -/**/ - -INSN(mpyhlu, m, mpy, 1616_m, C62X, 0, - FIX1(FIX(op, 0x0f)), - OP3(ORREG1, ORXREG1, OWREG2), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSN(mpyhslu, m, mpy, 1616_m, C62X, 0, - FIX1(FIX(op, 0x0b)), - OP3(ORREG1, ORXREG1, OWREG2), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSN(mpyhsu, m, mpy, 1616_m, C62X, 0, - FIX1(FIX(op, 0x03)), - OP3(ORREG1, ORXREG1, OWREG2), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSN(mpyhu, m, mpy, 1616_m, C62X, 0, - FIX1(FIX(op, 0x07)), - OP3(ORREG1, ORXREG1, OWREG2), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSN(mpyhuls, m, mpy, 1616_m, C62X, 0, - FIX1(FIX(op, 0x0d)), - OP3(ORREG1, ORXREG1, OWREG2), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSN(mpyhus, m, mpy, 1616_m, C62X, 0, - FIX1(FIX(op, 0x05)), - OP3(ORREG1, ORXREG1, OWREG2), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSNE(mpyi, m_si_xsi_si, m, mpy, mpyi, C67X, 0, - FIX1(FIX(op, 0x04)), - OP3(ORREG14, ORXREG14, OWREG9), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -INSNE(mpyi, m_s5_xsi_si, m, mpy, mpyi, C67X, 0, - FIX1(FIX(op, 0x06)), - OP3(OACST, ORXREG14, OWREG9), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSNE(mpyid, m_si_xsi_sll, m, mpy, mpyid, C67X, 0, - FIX1(FIX(op, 0x08)), - OP3(ORREG14, ORXREG14, OWREGD910), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -INSNE(mpyid, m_s5_xsi_sll, m, mpy, mpyid, C67X, 0, - FIX1(FIX(op, 0x0c)), - OP3(OACST, ORXREG14, OWREGD910), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSN(mpyih, m, compound, 4cycle, C64X, TIC6X_FLAG_MACRO, - FIX1(FIX(op, 0x14)), - OP3(ORXREG1, ORREG1, OWREGD4), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), - ENC(src1, reg, 1), ENC(dst, reg, 2))) - -INSN(mpyihr, m, compound, 4cycle, C64X, TIC6X_FLAG_MACRO, - FIX1(FIX(op, 0x10)), - OP3(ORXREG1, ORREG1, OWREG4), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), - ENC(src1, reg, 1), ENC(dst, reg, 2))) - -INSN(mpyil, m, compound, 4cycle, C64X, TIC6X_FLAG_MACRO, - FIX1(FIX(op, 0x15)), - OP3(ORXREG1, ORREG1, OWREGD4), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), - ENC(src1, reg, 1), ENC(dst, reg, 2))) - -INSN(mpyilr, m, compound, 4cycle, C64X, TIC6X_FLAG_MACRO, - FIX1(FIX(op, 0x0e)), - OP3(ORXREG1, ORREG1, OWREG4), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), - ENC(src1, reg, 1), ENC(dst, reg, 2))) - -INSN(mpylh, m, mpy, 1616_m, C62X, 0, - FIX1(FIX(op, 0x11)), - OP3(ORREG1, ORXREG1, OWREG2), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -/* 16 bits insn */ -INSN(mpylh, m, m3_sat_0, 1616_m, C67X, 0, - FIX1(FIX(op, 0x2)), - OP3(ORREG1, ORXREG1, OWREG2), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg_shift, 2))) -/**/ - -INSN(mpylhu, m, mpy, 1616_m, C62X, 0, - FIX1(FIX(op, 0x17)), - OP3(ORREG1, ORXREG1, OWREG2), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSN(mpyli, m, compound, 4cycle, C64X, 0, - FIX1(FIX(op, 0x15)), - OP3(ORREG1, ORXREG1, OWREGD4), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSN(mpylir, m, compound, 4cycle, C64X, 0, - FIX1(FIX(op, 0x0e)), - OP3(ORREG1, ORXREG1, OWREG4), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSN(mpylshu, m, mpy, 1616_m, C62X, 0, - FIX1(FIX(op, 0x13)), - OP3(ORREG1, ORXREG1, OWREG2), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSN(mpyluhs, m, mpy, 1616_m, C62X, 0, - FIX1(FIX(op, 0x15)), - OP3(ORREG1, ORXREG1, OWREG2), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSN(mpysp, m, mpy, 4cycle, C67X, 0, - FIX1(FIX(op, 0x1c)), - OP3(ORREG1, ORXREG1, OWREG4), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -/* Contrary to SPRU733A, MPYSPDP and MPYSP2DP are on both C67X and - C67X+. */ -INSN(mpyspdp, m, compound, mpyspdp, C67X, 0, - FIX1(FIX(op, 0x16)), - OP3(ORREG12, ORXREGD12, OWREGD67), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSN(mpysp2dp, m, compound, mpyspdp, C67X, 0, - FIX1(FIX(op, 0x17)), - OP3(ORREG1, ORXREG1, OWREGD45), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSNE(mpysu, m_sl16_xul16_si, m, mpy, 1616_m, C62X, 0, - FIX1(FIX(op, 0x1b)), - OP3(ORREG1, ORXREG1, OWREG2), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -INSNE(mpysu, m_s5_xul16_si, m, mpy, 1616_m, C62X, 0, - FIX1(FIX(op, 0x1e)), - OP3(OACST, ORXREG1, OWREG2), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSN(mpysu4, m, compound, 4cycle, C64X, 0, - FIX1(FIX(op, 0x05)), - OP3(ORREG1, ORXREG1, OWREGD4), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSN(mpyu, m, mpy, 1616_m, C62X, 0, - FIX1(FIX(op, 0x1f)), - OP3(ORREG1, ORXREG1, OWREG2), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSN(mpyu4, m, compound, 4cycle, C64X, 0, - FIX1(FIX(op, 0x04)), - OP3(ORREG1, ORXREG1, OWREGD4), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSN(mpyus, m, mpy, 1616_m, C62X, 0, - FIX1(FIX(op, 0x1d)), - OP3(ORREG1, ORXREG1, OWREG2), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSN(mpyus4, m, compound, 4cycle, C64X, TIC6X_FLAG_MACRO, - FIX1(FIX(op, 0x05)), - OP3(ORXREG1, ORREG1, OWREGD4), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), - ENC(src1, reg, 1), ENC(dst, reg, 2))) - -INSN(mpy2, m, compound, 4cycle, C64X, 0, - FIX1(FIX(op, 0x00)), - OP3(ORREG1, ORXREG1, OWREGD4), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSN(mpy2ir, m, 1_or_2_src, 4cycle, C64XP, 0, - FIX1(FIX(op, 0x0f)), - OP3(ORREG1, ORXREG1, OWREGD4), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSNE(mpy32, 32_32_32, m, mpy, 4cycle, C64XP, 0, - FIX1(FIX(op, 0x10)), - OP3(ORREG1, ORXREG1, OWREG4), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -INSNE(mpy32, 32_32_64, m, mpy, 4cycle, C64XP, 0, - FIX1(FIX(op, 0x14)), - OP3(ORREG1, ORXREG1, OWREGD4), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSN(mpy32su, m, mpy, 4cycle, C64XP, 0, - FIX1(FIX(op, 0x16)), - OP3(ORREG1, ORXREG1, OWREGD4), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSN(mpy32u, m, compound, 4cycle, C64XP, 0, - FIX1(FIX(op, 0x18)), - OP3(ORREG1, ORXREG1, OWREGD4), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSN(mpy32us, m, compound, 4cycle, C64XP, 0, - FIX1(FIX(op, 0x19)), - OP3(ORREG1, ORXREG1, OWREGD4), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -/* "or" forms of "mv" are preferred over "add" forms when available - because "or" uses less power. However, 40-bit moves are only - available through "add", and before C64X D-unit moves are only - available through "add" (without cross paths being available). */ -INSNE(mv, l_xui_ui, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_MACRO, - FIX2(FIX(op, 0x7e), FIX(src1, 0)), - OP2(ORXREG1, OWREG1), - ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), - ENC(dst, reg, 1))) -INSNE(mv, l_sl_sl, l, 1_or_2_src, 1cycle, C62X, - TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO, - FIX3(FIX(op, 0x20), FIX(x, 0), FIX(src1, 0)), - OP2(ORREGL1, OWREGL1), - ENC3(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(dst, reg, 1))) -INSNE(mv, s_xui_ui, s, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_MACRO, - FIX2(FIX(op, 0x1a), FIX(src1, 0)), - OP2(ORXREG1, OWREG1), - ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), - ENC(dst, reg, 1))) -INSNE(mv, d_si_si, d, 1_or_2_src, 1cycle, C62X, - TIC6X_FLAG_MACRO|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(0), - FIX2(FIX(op, 0x12), FIX(src1, 0)), - OP2(ORREG1, OWREG1), - ENC3(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(dst, reg, 1))) -INSNE(mv, d_xui_ui, d, ext_1_or_2_src, 1cycle, C64X, - TIC6X_FLAG_MACRO|TIC6X_FLAG_PREFER(1), - FIX2(FIX(op, 0x3), FIX(src1, 0)), - OP2(ORXREG1, OWREG1), - ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), - ENC(dst, reg, 1))) - -/* 16 bits insn */ -INSNU(mv, l, lsdmvto, 1cycle, C64X, 0, - FIX1(FIX(unit, 0x0)), - OP2(ORXREG1, OWREG1), - ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(x, xpath, 0), ENC(dst, reg, 1))) - -INSNU(mv, s, lsdmvto, 1cycle, C64X, 0, - FIX1(FIX(unit, 0x1)), - OP2(ORXREG1, OWREG1), - ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(x, xpath, 0), ENC(dst, reg, 1))) - -INSNU(mv, d, lsdmvto, 1cycle, C64X, 0, - FIX1(FIX(unit, 0x2)), - OP2(ORXREG1, OWREG1), - ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(x, xpath, 0), ENC(dst, reg, 1))) - -INSNU(mv, l, lsdmvfr, 1cycle, C64X, 0, - FIX1(FIX(unit, 0x0)), - OP2(ORXREG1, OWREG1), - ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(x, xpath, 0), ENC(dst, reg, 1))) - -INSNU(mv, s, lsdmvfr, 1cycle, C64X, 0, - FIX1(FIX(unit, 0x1)), - OP2(ORXREG1, OWREG1), - ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(x, xpath, 0), ENC(dst, reg, 1))) - -INSNU(mv, d, lsdmvfr, 1cycle, C64X, 0, - FIX1(FIX(unit, 0x2)), - OP2(ORXREG1, OWREG1), - ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(x, xpath, 0), ENC(dst, reg, 1))) -/**/ - -INSNE(mvc, from_cr, s, 1_or_2_src, 1cycle, C62X, - TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_NO_CROSS, - FIX3(FIX(s, 1), FIX(op, 0x0f), FIX(x, 0)), - OP2(ORCREG1, OWREG1), - ENC3(ENC(src1, crhi, 0), ENC(src2, crlo, 0), ENC(dst, reg, 1))) -INSNE(mvc, to_cr, s, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_SIDE_B_ONLY, - FIX2(FIX(s, 1), FIX(op, 0x0e)), - OP2(ORXREG1, OWCREG1), - ENC4(ENC(x, xpath, 0), ENC(src2, reg, 0), ENC(src1, crhi, 1), - ENC(dst, crlo, 1))) - -/* 16 bits insn */ -INSN(mvc, s, sx1, 1cycle, C64XP, - TIC6X_FLAG_NO_CROSS, - FIX1(FIX(op, 0x6)), - OP2(ORREG1B, OWILC1), - ENC2(ENC(s, fu, 0), ENC(srcdst, reg, 0))) -/**/ - -INSN(mvd, m, unary, 4cycle, C64X, 0, - FIX1(FIX(op, 0x1a)), - OP2(ORXREG1, OWREG4), - ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), - ENC(dst, reg, 1))) - -INSN(mvk, s, mvk, 1cycle, C62X, TIC6X_FLAG_NO_CROSS, - FIX1(FIX(h, 0)), - OP2(OLCST, OWREG1), - ENC3(ENC(s, fu, 0), ENC(cst, scst, 0), ENC(dst, reg, 1))) -INSN(mvk, l, unary, 1cycle, C64X, TIC6X_FLAG_NO_CROSS, - FIX2(FIX(x, 0), FIX(op, 0x05)), - OP2(OACST, OWREG1), - ENC3(ENC(s, fu, 0), ENC(src2, scst, 0), ENC(dst, reg, 1))) -INSN(mvk, d, 1_or_2_src, 1cycle, C64X, TIC6X_FLAG_NO_CROSS, - FIX2(FIX(op, 0x00), FIX(src2, 0)), - OP2(OACST, OWREG1), - ENC3(ENC(s, fu, 0), ENC(src1, scst, 0), ENC(dst, reg, 1))) - -/* 16 bits insn */ -INSN(mvk, l, lx5, 1cycle, C64XP, TIC6X_FLAG_NO_CROSS, - FIX0(), - OP2(OLCST, OWREG1), - ENC3(ENC(s, fu, 0), ENC(cst, scst, 0), ENC(dst, reg, 1))) -INSN(mvk, s, smvk8, 1cycle, C64XP, TIC6X_FLAG_NO_CROSS, - FIX0(), - OP2(OLCST, OWREG1), - ENC3(ENC(s, fu, 0), ENC(cst, ucst, 0), ENC(dst, reg, 1))) -INSNU(mvk, l, lsdx1c, 1cycle, C64XP, TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_SPRED, - FIX1(FIX(unit, 0x0)), - OP2(OACST, OWREG1), - ENC3(ENC(s, fu, 0), ENC(cst, ucst, 0), ENC(dst, reg, 1))) -INSNU(mvk, s, lsdx1c, 1cycle, C64XP, TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_SPRED, - FIX1(FIX(unit, 0x1)), - OP2(OACST, OWREG1), - ENC3(ENC(s, fu, 0), ENC(cst, ucst, 0), ENC(dst, reg, 1))) -INSNU(mvk, d, lsdx1c, 1cycle, C64XP, TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_SPRED, - FIX1(FIX(unit, 0x2)), - OP2(OACST, OWREG1), - ENC3(ENC(s, fu, 0), ENC(cst, ucst, 0), ENC(dst, reg, 1))) -INSNUE(mvk, zero, l, lsdx1, 1cycle, C64XP, TIC6X_FLAG_NO_CROSS, - FIX2(FIX(op, 0), FIX(unit, 0x0)), - OP2(OHWCST0, OWREG1), - ENC2(ENC(s, fu, 0), ENC(srcdst, reg, 1))) -INSNUE(mvk, zero, s, lsdx1, 1cycle, C64XP, TIC6X_FLAG_NO_CROSS, - FIX2(FIX(op, 0), FIX(unit, 0x1)), - OP2(OHWCST0, OWREG1), - ENC2(ENC(s, fu, 0), ENC(srcdst, reg, 1))) -INSNUE(mvk, zero, d, lsdx1, 1cycle, C64XP, TIC6X_FLAG_NO_CROSS, - FIX2(FIX(op, 0), FIX(unit, 0x2)), - OP2(OHWCST0, OWREG1), - ENC2(ENC(s, fu, 0), ENC(srcdst, reg, 1))) -INSNUE(mvk, one, l, lsdx1, 1cycle, C64XP, TIC6X_FLAG_NO_CROSS, - FIX2(FIX(op, 1), FIX(unit, 0x0)), - OP2(OHWCST1, OWREG1), - ENC2(ENC(s, fu, 0), ENC(srcdst, reg, 1))) -INSNUE(mvk, one, s, lsdx1, 1cycle, C64XP, TIC6X_FLAG_NO_CROSS, - FIX2(FIX(op, 1), FIX(unit, 0x1)), - OP2(OHWCST1, OWREG1), - ENC2(ENC(s, fu, 0), ENC(srcdst, reg, 1))) -INSNUE(mvk, one, d, lsdx1, 1cycle, C64XP, TIC6X_FLAG_NO_CROSS, - FIX2(FIX(op, 1), FIX(unit, 0x2)), - OP2(OHWCST1, OWREG1), - ENC2(ENC(s, fu, 0), ENC(srcdst, reg, 1))) -/**/ - -INSN(mvkh, s, mvk, 1cycle, C62X, TIC6X_FLAG_NO_CROSS, - FIX1(FIX(h, 1)), - OP2(OLCST, OWREG1), - ENC3(ENC(s, fu, 0), ENC(cst, lcst_high16, 0), ENC(dst, reg, 1))) - -INSN(mvklh, s, mvk, 1cycle, C62X, TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO, - FIX1(FIX(h, 1)), - OP2(OLCST, OWREG1), - ENC3(ENC(s, fu, 0), ENC(cst, lcst_low16, 0), ENC(dst, reg, 1))) - -INSN(mvkl, s, mvk, 1cycle, C62X, TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO, - FIX1(FIX(h, 0)), - OP2(OLCST, OWREG1), - ENC3(ENC(s, fu, 0), ENC(cst, lcst_low16, 0), ENC(dst, reg, 1))) - -INSNE(neg, s_xsi_si, s, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_MACRO, - FIX2(FIX(op, 0x16), FIX(src1, 0)), - OP2(ORXREG1, OWREG1), - ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), - ENC(dst, reg, 1))) -INSNE(neg, l_xsi_si, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_MACRO, - FIX2(FIX(op, 0x06), FIX(src1, 0)), - OP2(ORXREG1, OWREG1), - ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), - ENC(dst, reg, 1))) -INSNE(neg, l_sl_sl, l, 1_or_2_src, 1cycle, C62X, - TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO, - FIX2(FIX(op, 0x24), FIX(src1, 0)), - OP2(ORREGL1, OWREGL1), - ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), - ENC(dst, reg, 1))) - -INSN(nop, nfu, nop_idle, nop, C62X, 0, - FIX2(FIX(s, 0), RAN(op, 0, 8)), - OP1(OACST), - ENC1(ENC(op, ucst_minus_one, 0))) -INSNE(nop, 1, nfu, nop_idle, nop, C62X, TIC6X_FLAG_MACRO, - FIX2(FIX(s, 0), FIX(op, 0)), - OP0(), - ENC0()) - -/* 16 bits insn */ -/* contrary to sprufe8b.pdf p767, and accordingly to - * dis6x.exe output, unop3 opcode is decoded as NOP N3 + 1 */ -INSN(nop, nfu, unop, nop, C64XP, 0, - FIX0(), - OP1(OACST), - ENC1(ENC(n, ucst_minus_one, 0))) -/**/ - -INSNE(norm, l_xsi_ui, l, 1_or_2_src, 1cycle, C62X, 0, - FIX2(FIX(op, 0x63), FIX(src1, 0)), - OP2(ORXREG1, OWREG1), - ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), - ENC(dst, reg, 1))) -INSNE(norm, l_sl_ui, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS, - FIX3(FIX(op, 0x60), FIX(x, 0), FIX(src1, 0)), - OP2(ORREGL1, OWREG1), - ENC3(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(dst, reg, 1))) - -INSN(not, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_MACRO, - FIX2(FIX(op, 0x6e), FIX(src1, 0x1f)), - OP2(ORXREG1, OWREG1), - ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), - ENC(dst, reg, 1))) -INSN(not, s, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_MACRO, - FIX2(FIX(op, 0x0a), FIX(src1, 0x1f)), - OP2(ORXREG1, OWREG1), - ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), - ENC(dst, reg, 1))) -INSN(not, d, ext_1_or_2_src, 1cycle, C64X, TIC6X_FLAG_MACRO, - FIX2(FIX(op, 0xf), FIX(src1, 0x1f)), - OP2(ORXREG1, OWREG1), - ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), - ENC(dst, reg, 1))) - -INSNE(or, d_ui_xui_ui, d, ext_1_or_2_src, 1cycle, C64X, 0, - FIX1(FIX(op, 0x2)), - OP3(ORREG1, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -INSNE(or, d_s5_xui_ui, d, ext_1_or_2_src, 1cycle, C64X, 0, - FIX1(FIX(op, 0x3)), - OP3(OACST, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -INSNE(or, l_ui_xui_ui, l, 1_or_2_src, 1cycle, C62X, 0, - FIX1(FIX(op, 0x7f)), - OP3(ORREG1, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -INSNE(or, l_s5_xui_ui, l, 1_or_2_src, 1cycle, C62X, 0, - FIX1(FIX(op, 0x7e)), - OP3(OACST, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -INSNE(or, s_ui_xui_ui, s, 1_or_2_src, 1cycle, C62X, 0, - FIX1(FIX(op, 0x1b)), - OP3(ORREG1, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -INSNE(or, s_s5_xui_ui, s, 1_or_2_src, 1cycle, C62X, 0, - FIX1(FIX(op, 0x1a)), - OP3(OACST, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -/* 16 bits insn */ -INSN(or, l, l2c, 1cycle, C64XP, 0, - FIX1(FIX(op, 1)), - OP3(ORREG1, ORXREG1, OWREG1NORS), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -/**/ - -INSN(pack2, l, 1_or_2_src, 1cycle, C64X, 0, - FIX1(FIX(op, 0x0)), - OP3(ORREG1, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -INSN(pack2, s, ext_1_or_2_src, 1cycle, C64X, 0, - FIX1(FIX(op, 0xf)), - OP3(ORREG1, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSN(packh2, l, 1_or_2_src, 1cycle, C64X, 0, - FIX1(FIX(op, 0x1e)), - OP3(ORREG1, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -INSN(packh2, s, 1_or_2_src, 1cycle, C64X, 0, - FIX1(FIX(op, 0x9)), - OP3(ORREG1, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSN(packh4, l, 1_or_2_src, 1cycle, C64X, 0, - FIX1(FIX(op, 0x69)), - OP3(ORREG1, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSN(packhl2, l, 1_or_2_src, 1cycle, C64X, 0, - FIX1(FIX(op, 0x1c)), - OP3(ORREG1, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -INSN(packhl2, s, 1_or_2_src, 1cycle, C64X, 0, - FIX1(FIX(op, 0x8)), - OP3(ORREG1, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSN(packlh2, l, 1_or_2_src, 1cycle, C64X, 0, - FIX1(FIX(op, 0x1b)), - OP3(ORREG1, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -INSN(packlh2, s, 1_or_2_src, 1cycle, C64X, 0, - FIX1(FIX(op, 0x10)), - OP3(ORREG1, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSN(packl4, l, 1_or_2_src, 1cycle, C64X, 0, - FIX1(FIX(op, 0x68)), - OP3(ORREG1, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSN(rcpdp, s, 1_or_2_src, 2cycle_dp, C67X, TIC6X_FLAG_NO_CROSS, - FIX2(FIX(op, 0x2d), FIX(x, 0)), - OP2(ORREGD1, OWREGD12), - ENC4(ENC(s, fu, 0), ENC(src2, regpair_msb, 0), ENC(src1, regpair_lsb, 0), - ENC(dst, reg, 1))) - -INSN(rcpsp, s, 1_or_2_src, 1cycle, C67X, 0, - FIX2(FIX(op, 0x3d), FIX(src1, 0)), - OP2(ORXREG1, OWREG1), - ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), - ENC(dst, reg, 1))) - -INSN(ret, s, ext_branch_cond_imm, branch, C62X, - TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO|TIC6X_FLAG_RETURN, - FIX0(), - OP1(OLCST), - ENC2(ENC(s, fu, 0), ENC(cst, pcrel, 0))) -INSN(ret, s, branch, branch, C62X, - TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_MACRO|TIC6X_FLAG_RETURN, - FIX1(FIX(s, 1)), - OP1(ORXREG1), - ENC2(ENC(x, xpath, 0), ENC(src2, reg, 0))) -INSN(ret, s, b_irp, branch, C62X, - TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_MACRO|TIC6X_FLAG_RETURN, - FIX3(FIX(s, 1), FIX(x, 0), FIX(dst, 0)), - OP1(ORIRP1), - ENC0()) -INSN(ret, s, b_nrp, branch, C62X, - TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_MACRO|TIC6X_FLAG_RETURN, - FIX3(FIX(s, 1), FIX(x, 0), FIX(dst, 0)), - OP1(ORNRP1), - ENC0()) - -INSN(retp, s, call_imm_nop, branch, C64XP, - TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MCNOP|TIC6X_FLAG_MACRO|TIC6X_FLAG_RETURN, - FIX1(FIX(z, 1)), - OP2(OLCST, OWRETREG1), - ENC2(ENC(s, fu, 0), ENC(cst, pcrel, 0))) - -INSN(rint, nfu, rint, 1cycle, C64XP, 0, - FIX1(FIX(s, 0)), - OP0(), - ENC0()) - -INSNE(rotl, m_ui_xui_ui, m, compound, 1616_m, C64X, 0, - FIX1(FIX(op, 0x1d)), - OP3(ORXREG1, ORREG1, OWREG2), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), - ENC(src1, reg, 1), ENC(dst, reg, 2))) -INSNE(rotl, m_u5_xui_ui, m, compound, 1616_m, C64X, 0, - FIX1(FIX(op, 0x1e)), - OP3(ORXREG1, OACST, OWREG2), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), - ENC(src1, ucst, 1), ENC(dst, reg, 2))) - -INSN(rpack2, s, ext_1_or_2_src_noncond, 1cycle, C64XP, 0, - FIX2(FIX(op, 0xb), FIX(z, 1)), - OP3(ORREG1, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSN(rsqrdp, s, 1_or_2_src, 2cycle_dp, C67X, TIC6X_FLAG_NO_CROSS, - FIX2(FIX(op, 0x2e), FIX(x, 0)), - OP2(ORREGD1, OWREGD12), - ENC4(ENC(s, fu, 0), ENC(src2, regpair_msb, 0), ENC(src1, regpair_lsb, 0), - ENC(dst, reg, 1))) - -INSN(rsqrsp, s, 1_or_2_src, 1cycle, C67X, 0, - FIX2(FIX(op, 0x3e), FIX(src1, 0)), - OP2(ORXREG1, OWREG1), - ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), - ENC(dst, reg, 1))) - -INSNE(sadd, l_si_xsi_si, l, 1_or_2_src, 1cycle, C62X, 0, - FIX1(FIX(op, 0x13)), - OP3(ORREG1, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -INSNE(sadd, l_xsi_sl_sl, l, 1_or_2_src, 1cycle, C62X, 0, - FIX1(FIX(op, 0x31)), - OP3(ORXREG1, ORREGL1, OWREGL1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -INSNE(sadd, l_s5_xsi_si, l, 1_or_2_src, 1cycle, C62X, 0, - FIX1(FIX(op, 0x12)), - OP3(OACST, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -INSNE(sadd, l_s5_sl_sl, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS, - FIX1(FIX(op, 0x30)), - OP3(OACST, ORREGL1, OWREGL1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -INSNE(sadd, s_si_xsi_si, s, 1_or_2_src, 1cycle, C64X, 0, - FIX1(FIX(op, 0x20)), - OP3(ORREG1, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -/* 16 bits insn */ -INSN(sadd, l, l3_sat_1, 1cycle, C64XP, 0, - FIX1(FIX(op, 0)), - OP3(ORREG1, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSN(sadd, s, s3_sat_1, 1cycle, C64XP,0, - FIX1(FIX(op, 0x0)), - OP3(ORREG1, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -/**/ - -INSN(sadd2, s, ext_1_or_2_src, 1cycle, C64X, 0, - FIX1(FIX(op, 0x0)), - OP3(ORREG1, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSN(saddsub, l, 1_or_2_src_noncond, 1cycle, C64XP, 0, - FIX1(FIX(op, 0x0e)), - OP3(ORREG1, ORXREG1, OWREGD1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSN(saddsub2, l, 1_or_2_src_noncond, 1cycle, C64XP, 0, - FIX1(FIX(op, 0x0f)), - OP3(ORREG1, ORXREG1, OWREGD1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSN(saddsu2, s, ext_1_or_2_src, 1cycle, C64X, TIC6X_FLAG_MACRO, - FIX1(FIX(op, 0x1)), - OP3(ORXREG1, ORREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), - ENC(src1, reg, 1), ENC(dst, reg, 2))) - -INSN(saddus2, s, ext_1_or_2_src, 1cycle, C64X, 0, - FIX1(FIX(op, 0x1)), - OP3(ORREG1, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSN(saddu4, s, ext_1_or_2_src, 1cycle, C64X, 0, - FIX1(FIX(op, 0x3)), - OP3(ORREG1, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSN(sat, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS, - FIX3(FIX(op, 0x40), FIX(x, 0), FIX(src1, 0)), - OP2(ORREGL1, OWREG1), - ENC3(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(dst, reg, 1))) - -INSN(set, s, field, 1cycle, C62X, TIC6X_FLAG_NO_CROSS, - FIX1(FIX(op, 0x2)), - OP4(ORREG1, OACST, OACST, OWREG1), - ENC5(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(csta, ucst, 1), - ENC(cstb, ucst, 2), ENC(dst, reg, 3))) -INSN(set, s, 1_or_2_src, 1cycle, C62X, 0, - FIX1(FIX(op, 0x3b)), - OP3(ORXREG1, ORREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), - ENC(src1, reg, 1), ENC(dst, reg, 2))) - -/* 16 bits insn */ -INSN(set, s, sc5, 1cycle, C64XP, 0, - FIX1(FIX(op, 1)), - OP4(ORREG1, OACST, OACST, OWREG1), - ENC5(ENC(s, fu, 0), ENC(srcdst, reg, 0), ENC(cst, ucst, 1), - ENC(cst, ucst, 2), ENC(srcdst, reg, 3))) -/**/ - -INSN(shfl, m, unary, 1616_m, C64X, 0, - FIX1(FIX(op, 0x1c)), - OP2(ORXREG1, OWREG2), - ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), - ENC(dst, reg, 1))) - -INSN(shfl3, l, 1_or_2_src_noncond, 1cycle, C64XP, 0, - FIX1(FIX(op, 0x36)), - OP3(ORREG1, ORXREG1, OWREGD1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSNE(shl, s_xsi_ui_si, s, 1_or_2_src, 1cycle, C62X, 0, - FIX1(FIX(op, 0x33)), - OP3(ORXREG1, ORREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), - ENC(src1, reg, 1), ENC(dst, reg, 2))) -INSNE(shl, s_sl_ui_sl, s, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS, - FIX2(FIX(op, 0x31), FIX(x, 0)), - OP3(ORREGL1, ORREG1, OWREGL1), - ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, reg, 1), - ENC(dst, reg, 2))) -INSNE(shl, s_xui_ui_ul, s, 1_or_2_src, 1cycle, C62X, 0, - FIX1(FIX(op, 0x13)), - OP3(ORXREG1, ORREG1, OWREGL1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), - ENC(src1, reg, 1), ENC(dst, reg, 2))) -INSNE(shl, s_xsi_u5_si, s, 1_or_2_src, 1cycle, C62X, 0, - FIX1(FIX(op, 0x32)), - OP3(ORXREG1, OACST, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), - ENC(src1, ucst, 1), ENC(dst, reg, 2))) -INSNE(shl, s_sl_u5_sl, s, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS, - FIX2(FIX(op, 0x30), FIX(x, 0)), - OP3(ORREGL1, OACST, OWREGL1), - ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1), - ENC(dst, reg, 2))) -INSNE(shl, s_xui_u5_ul, s, 1_or_2_src, 1cycle, C62X, 0, - FIX1(FIX(op, 0x12)), - OP3(ORXREG1, OACST, OWREGL1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), - ENC(src1, ucst, 1), ENC(dst, reg, 2))) - -/* 16bit insn */ -INSN(shl, s, s3i, 1cycle, C64XP, 0, - FIX1(FIX(op, 0x0)), - OP3(ORXREG1, OACST, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), - ENC(cst, cst_s3i, 1), ENC(dst, reg, 2))) -INSN(shl, s, ssh5_sat_x, 1cycle, C64XP, - TIC6X_FLAG_NO_CROSS, - FIX1(FIX(op, 0x0)), - OP3(ORREG1, OACST, OWREG1), - ENC4(ENC(s, fu, 0), ENC(srcdst, reg, 0), - ENC(cst, ucst, 1), ENC(srcdst, reg, 2))) -INSN(shl, s, s2sh, 1cycle, C64XP, 0, - FIX1(FIX(op, 0x0)), - OP3(ORREG1, ORREG1, OWREG1), - ENC4(ENC(s, fu, 0), ENC(srcdst, reg, 0), ENC(src1, reg, 1), - ENC(srcdst, reg, 2))) -/**/ - -INSN(shlmb, l, 1_or_2_src, 1cycle, C64X, 0, - FIX1(FIX(op, 0x61)), - OP3(ORREG1, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -INSN(shlmb, s, ext_1_or_2_src, 1cycle, C64X, 0, - FIX1(FIX(op, 0x9)), - OP3(ORREG1, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSNE(shr, s_xsi_ui_si, s, 1_or_2_src, 1cycle, C62X, 0, - FIX1(FIX(op, 0x37)), - OP3(ORXREG1, ORREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), - ENC(src1, reg, 1), ENC(dst, reg, 2))) -INSNE(shr, s_sl_ui_sl, s, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS, - FIX2(FIX(op, 0x35), FIX(x, 0)), - OP3(ORREGL1, ORREG1, OWREGL1), - ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, reg, 1), - ENC(dst, reg, 2))) -INSNE(shr, s_xsi_u5_si, s, 1_or_2_src, 1cycle, C62X, 0, - FIX1(FIX(op, 0x36)), - OP3(ORXREG1, OACST, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), - ENC(src1, ucst, 1), ENC(dst, reg, 2))) -INSNE(shr, s_sl_u5_sl, s, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS, - FIX2(FIX(op, 0x34), FIX(x, 0)), - OP3(ORREGL1, OACST, OWREGL1), - ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1), - ENC(dst, reg, 2))) - -/* 16bit insn */ -INSN(shr, s, s3i, 1cycle, C64XP, 0, - FIX1(FIX(op, 0x1)), - OP3(ORXREG1, OACST, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), - ENC(cst, cst_s3i, 1), ENC(dst, reg, 2))) -INSN(shr, s, ssh5_sat_x, 1cycle, C64XP, - TIC6X_FLAG_NO_CROSS, - FIX1(FIX(op, 0x1)), - OP3(ORREG1, OACST, OWREG1), - ENC4(ENC(s, fu, 0), ENC(srcdst, reg, 0), - ENC(cst, ucst, 1), ENC(srcdst, reg, 2))) -INSN(shr, s, s2sh, 1cycle, C64XP, 0, - FIX1(FIX(op, 0x1)), - OP3(ORREG1, ORREG1, OWREG1), - ENC4(ENC(s, fu, 0), ENC(srcdst, reg, 0), ENC(src1, reg, 1), - ENC(srcdst, reg, 2))) -/**/ - -INSNE(shr2, s_xs2_ui_s2, s, ext_1_or_2_src, 1cycle, C64X, 0, - FIX1(FIX(op, 0x7)), - OP3(ORXREG1, ORREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), - ENC(src1, reg, 1), ENC(dst, reg, 2))) -INSNE(shr2, s_xs2_u5_s2, s, 1_or_2_src, 1cycle, C64X, 0, - FIX1(FIX(op, 0x18)), - OP3(ORXREG1, OACST, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), - ENC(src1, ucst, 1), ENC(dst, reg, 2))) - -INSN(shrmb, l, 1_or_2_src, 1cycle, C64X, 0, - FIX1(FIX(op, 0x62)), - OP3(ORREG1, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -INSN(shrmb, s, ext_1_or_2_src, 1cycle, C64X, 0, - FIX1(FIX(op, 0xa)), - OP3(ORREG1, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSNE(shru, s_xui_ui_ui, s, 1_or_2_src, 1cycle, C62X, 0, - FIX1(FIX(op, 0x27)), - OP3(ORXREG1, ORREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), - ENC(src1, reg, 1), ENC(dst, reg, 2))) -INSNE(shru, s_ul_ui_ul, s, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS, - FIX2(FIX(op, 0x25), FIX(x, 0)), - OP3(ORREGL1, ORREG1, OWREGL1), - ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, reg, 1), - ENC(dst, reg, 2))) -INSNE(shru, s_xui_u5_ui, s, 1_or_2_src, 1cycle, C62X, 0, - FIX1(FIX(op, 0x26)), - OP3(ORXREG1, OACST, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), - ENC(src1, ucst, 1), ENC(dst, reg, 2))) -INSNE(shru, s_ul_u5_ul, s, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS, - FIX2(FIX(op, 0x24), FIX(x, 0)), - OP3(ORREGL1, OACST, OWREGL1), - ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1), - ENC(dst, reg, 2))) - -/* 16 bits insn */ -INSN(shru, s, ssh5_sat_0, 1cycle, C64XP, - TIC6X_FLAG_NO_CROSS, - FIX1(FIX(op, 0x2)), - OP3(ORREG1, OACST, OWREG1), - ENC4(ENC(s, fu, 0), ENC(srcdst, reg, 0), - ENC(cst, ucst, 1), ENC(srcdst, reg, 2))) -INSN(shru, s, s2sh, 1cycle, C64XP, 0, - FIX1(FIX(op, 0x2)), - OP3(ORREG1, ORREG1, OWREG1), - ENC4(ENC(s, fu, 0), ENC(srcdst, reg, 0), ENC(src1, reg, 1), - ENC(srcdst, reg, 2))) -/**/ - -INSNE(shru2, s_xu2_ui_u2, s, ext_1_or_2_src, 1cycle, C64X, 0, - FIX1(FIX(op, 0x8)), - OP3(ORXREG1, ORREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), - ENC(src1, reg, 1), ENC(dst, reg, 2))) -INSNE(shru2, s_xu2_u5_u2, s, 1_or_2_src, 1cycle, C64X, 0, - FIX1(FIX(op, 0x19)), - OP3(ORXREG1, OACST, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), - ENC(src1, ucst, 1), ENC(dst, reg, 2))) - -INSN(sl, d, 1_or_2_src, store, C64XP, - TIC6X_FLAG_STORE|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_SIDE_T2_ONLY|TIC6X_FLAG_NO_CROSS, - FIX3(FIX(s, 1), FIX(op, 0xd), FIX(src1, 0)), - OP2(ORDREG1, OWMEMDW), - ENC2(ENC(dst, reg, 0), ENC(src2, reg, 1))) - -INSN(smpy, m, mpy, 1616_m, C62X, 0, - FIX1(FIX(op, 0x1a)), - OP3(ORREG1, ORXREG1, OWREG2), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -/* 16 bits insn */ -INSN(smpy, m, m3_sat_1, 1616_m, C67X, 0, - FIX1(FIX(op, 0x0)), - OP3(ORREG1, ORXREG1, OWREG2), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg_shift, 2))) -/**/ - -INSN(smpyh, m, mpy, 1616_m, C62X, 0, - FIX1(FIX(op, 0x02)), - OP3(ORREG1, ORXREG1, OWREG2), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -/* 16 bits insn */ -INSN(smpyh, m, m3_sat_1, 1616_m, C67X, 0, - FIX1(FIX(op, 0x1)), - OP3(ORREG1, ORXREG1, OWREG2), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg_shift, 2))) -/**/ - -INSN(smpyhl, m, mpy, 1616_m, C62X, 0, - FIX1(FIX(op, 0x0a)), - OP3(ORREG1, ORXREG1, OWREG2), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -/* 16 bits insn */ -INSN(smpyhl, m, m3_sat_1, 1616_m, C67X, 0, - FIX1(FIX(op, 0x3)), - OP3(ORREG1, ORXREG1, OWREG2), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg_shift, 2))) -/**/ - -INSN(smpylh, m, mpy, 1616_m, C62X, 0, - FIX1(FIX(op, 0x12)), - OP3(ORREG1, ORXREG1, OWREG2), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -/* 16 bits insn */ -INSN(smpylh, m, m3_sat_1, 1616_m, C67X, 0, - FIX1(FIX(op, 0x2)), - OP3(ORREG1, ORXREG1, OWREG2), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg_shift, 2))) -/**/ - -INSN(smpy2, m, compound, 4cycle, C64X, 0, - FIX1(FIX(op, 0x01)), - OP3(ORREG1, ORXREG1, OWREGD4), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -/* Contrary to SPRUFE8, this is the correct operand order for this - instruction. */ -INSN(smpy32, m, 1_or_2_src, 4cycle, C64XP, 0, - FIX1(FIX(op, 0x19)), - OP3(ORREG1, ORXREG1, OWREG4), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSN(spack2, s, ext_1_or_2_src, 1cycle, C64X, 0, - FIX1(FIX(op, 0x2)), - OP3(ORREG1, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSN(spacku4, s, ext_1_or_2_src, 1cycle, C64X, 0, - FIX1(FIX(op, 0x4)), - OP3(ORREG1, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSN(spdp, s, 1_or_2_src, 2cycle_dp, C67X, 0, - FIX2(FIX(op, 0x02), FIX(src1, 0)), - OP2(ORXREG1, OWREGD12), - ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), - ENC(dst, reg, 1))) - -INSN(spint, l, 1_or_2_src, 4cycle, C67X, 0, - FIX2(FIX(op, 0x0a), FIX(src1, 0)), - OP2(ORXREG1, OWREG4), - ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), - ENC(dst, reg, 1))) - -INSNE(spkernel, nfu_2, nfu, spkernel, 1cycle, C64XP, - TIC6X_FLAG_FIRST|TIC6X_FLAG_NO_MCNOP|TIC6X_FLAG_SPKERNEL, - FIX1(FIX(s, 0)), - OP2(OACST, OACST), - ENC2(ENC(fstgfcyc, fstg, 0), ENC(fstgfcyc, fcyc, 1))) -INSNE(spkernel, nfu_0, nfu, spkernel, 1cycle, C64XP, - TIC6X_FLAG_FIRST|TIC6X_FLAG_NO_MCNOP|TIC6X_FLAG_SPKERNEL|TIC6X_FLAG_MACRO, - FIX2(FIX(s, 0), FIX(fstgfcyc, 0)), - OP0(), - ENC0()) - -/* 16 bits insn */ -INSN(spkernel, nfu, uspk, 1cycle, C64XP, - TIC6X_FLAG_FIRST|TIC6X_FLAG_NO_MCNOP|TIC6X_FLAG_SPKERNEL, - FIX0(), - OP2(OACST, OACST), - ENC2(ENC(fstgfcyc, fstg, 0), ENC(fstgfcyc, fcyc, 1))) -/**/ - -INSN(spkernelr, nfu, spkernelr, 1cycle, C64XP, - TIC6X_FLAG_FIRST|TIC6X_FLAG_NO_MCNOP|TIC6X_FLAG_SPKERNEL, - FIX1(FIX(s, 0)), - OP0(), - ENC0()) - -INSN(sploop, nfu, loop_buffer, 1cycle, C64XP, - TIC6X_FLAG_FIRST|TIC6X_FLAG_NO_MCNOP|TIC6X_FLAG_SPLOOP, - FIX4(FIX(s, 0), FIX(op, 0xc), FIX(csta, 0), RAN(cstb, 0, 13)), - OP1(OACST), - ENC1(ENC(cstb, ucst_minus_one, 0))) - -INSN(sploopd, nfu, loop_buffer, 1cycle, C64XP, - TIC6X_FLAG_FIRST|TIC6X_FLAG_NO_MCNOP|TIC6X_FLAG_SPLOOP, - FIX4(FIX(s, 0), FIX(op, 0xd), FIX(csta, 0), RAN(cstb, 0, 13)), - OP1(OACST), - ENC1(ENC(cstb, ucst_minus_one, 0))) - -INSN(sploopw, nfu, loop_buffer, 1cycle, C64XP, - TIC6X_FLAG_FIRST|TIC6X_FLAG_NO_MCNOP|TIC6X_FLAG_SPLOOP, - FIX4(FIX(s, 0), FIX(op, 0xf), FIX(csta, 0), RAN(cstb, 0, 13)), - OP1(OACST), - ENC1(ENC(cstb, ucst_minus_one, 0))) - -/* 16 bits insn */ -INSN(sploop, nfu, uspl, 1cycle, C64XP, - TIC6X_FLAG_FIRST|TIC6X_FLAG_NO_MCNOP|TIC6X_FLAG_SPLOOP, - FIX1(FIX(op, 0)), - OP1(OACST), - ENC1(ENC(ii, ucst_minus_one, 0))) - -INSN(sploopd, nfu, uspl, 1cycle, C64XP, - TIC6X_FLAG_FIRST|TIC6X_FLAG_NO_MCNOP|TIC6X_FLAG_SPLOOP, - FIX1(FIX(op, 1)), - OP1(OACST), - ENC1(ENC(ii, ucst_minus_one, 0))) - -INSN(sploopd, nfu, uspldr, 1cycle, C64XP, - TIC6X_FLAG_FIRST|TIC6X_FLAG_NO_MCNOP|TIC6X_FLAG_SPLOOP|TIC6X_FLAG_INSN16_SPRED, - FIX0(), - OP1(OACST), - ENC1(ENC(ii, ucst_minus_one, 0))) -/**/ - - -/* Contrary to SPRUFE8, this is the correct encoding for this - instruction. */ -INSN(spmask, nfu, spmask, 1cycle, C64XP, TIC6X_FLAG_FIRST|TIC6X_FLAG_SPMASK, - FIX2(FIX(s, 0), FIX(op, 0x8)), - OP1(OFULIST), - ENC1(ENC(mask, spmask, 0))) - -/* 16 bits insn */ -INSN(spmask, nfu, uspma, 1cycle, C64XP, TIC6X_FLAG_FIRST|TIC6X_FLAG_SPMASK, - FIX0(), - OP1(OFULIST), - ENC1(ENC(mask, spmask, 0))) -/**/ - -INSN(spmaskr, nfu, spmask, 1cycle, C64XP, TIC6X_FLAG_FIRST|TIC6X_FLAG_SPMASK, - FIX2(FIX(s, 0), FIX(op, 0x9)), - OP1(OFULIST), - ENC1(ENC(mask, spmask, 0))) - -/* 16 bits insn */ -INSN(spmaskr, nfu, uspmb, 1cycle, C64XP, TIC6X_FLAG_FIRST|TIC6X_FLAG_SPMASK, - FIX0(), - OP1(OFULIST), - ENC1(ENC(mask, spmask, 0))) -/**/ - -INSN(sptrunc, l, 1_or_2_src, 4cycle, C67X, 0, - FIX2(FIX(op, 0x0b), FIX(src1, 0)), - OP2(ORXREG1, OWREG4), - ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), - ENC(dst, reg, 1))) - -INSNE(sshl, s_xsi_ui_si, s, 1_or_2_src, 1cycle, C62X, 0, - FIX1(FIX(op, 0x23)), - OP3(ORXREG1, ORREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), - ENC(src1, reg, 1), ENC(dst, reg, 2))) -INSNE(sshl, s_xsi_u5_si, s, 1_or_2_src, 1cycle, C62X, 0, - FIX1(FIX(op, 0x22)), - OP3(ORXREG1, OACST, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), - ENC(src1, ucst, 1), ENC(dst, reg, 2))) - -/* 16 bits insn */ -INSN(sshl, s, ssh5_sat_1, 1cycle, C64XP, - TIC6X_FLAG_NO_CROSS, - FIX1(FIX(op, 0x2)), - OP3(ORREG1, OACST, OWREG1), - ENC4(ENC(s, fu, 0), ENC(srcdst, reg, 0), - ENC(cst, ucst, 1), ENC(srcdst, reg, 2))) -INSN(sshl, s, s2sh, 1cycle, C64XP, 0, - FIX1(FIX(op, 0x3)), - OP3(ORREG1, ORREG1, OWREG1), - ENC4(ENC(s, fu, 0), ENC(srcdst, reg, 0), ENC(src1, reg, 1), - ENC(srcdst, reg, 2))) -/**/ - -INSN(sshvl, m, compound, 1616_m, C64X, 0, - FIX1(FIX(op, 0x1c)), - OP3(ORXREG1, ORREG1, OWREG2), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), - ENC(src1, reg, 1), ENC(dst, reg, 2))) - -/* Contrary to SPRUFE8, this is the correct encoding for this - instruction. */ -INSN(sshvr, m, compound, 1616_m, C64X, 0, - FIX1(FIX(op, 0x1a)), - OP3(ORXREG1, ORREG1, OWREG2), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), - ENC(src1, reg, 1), ENC(dst, reg, 2))) - -INSNE(ssub, l_si_xsi_si, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_PREFER(1), - FIX1(FIX(op, 0x0f)), - OP3(ORREG1, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -INSNE(ssub, l_xsi_si_si, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_PREFER(0), - FIX1(FIX(op, 0x1f)), - OP3(ORXREG1, ORREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -INSNE(ssub, l_s5_xsi_si, l, 1_or_2_src, 1cycle, C62X, 0, - FIX1(FIX(op, 0x0e)), - OP3(OACST, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -INSNE(ssub, l_s5_sl_sl, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS, - FIX1(FIX(op, 0x2c)), - OP3(OACST, ORREGL1, OWREGL1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -/* 16 bits insn */ -INSN(ssub, l, l3_sat_1, 1cycle, C64XP, 0, - FIX1(FIX(op, 1)), - OP3(ORREG1, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -/**/ - -INSN(ssub2, l, 1_or_2_src, 1cycle, C64XP, 0, - FIX1(FIX(op, 0x64)), - OP3(ORREG1, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSN(stb, d, load_store, store, C62X, - TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1), - FIX2(FIX(op, 3), FIX(r, 0)), - OP2(ORDREG1, OWMEMSB), - ENC6(ENC(s, data_fu, 0), ENC(y, fu, 0), ENC(mode, mem_mode, 1), - ENC(offsetR, mem_offset, 1), ENC(baseR, reg, 1), - ENC(srcdst, reg, 0))) -INSN(stb, d, load_store_long, store, C62X, - TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_PREFER(0), - FIX1(FIX(op, 3)), - OP2(ORDREG1, OWMEMLB), - ENC4(ENC(s, data_fu, 0), ENC(y, areg, 1), ENC(offsetR, ulcst_dpr_byte, 1), - ENC(dst, reg, 0))) - -/* 16 bits insn */ -INSN(stb, d, doff4_dsz_000, store, C64XP, - TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSITIVE), - FIX2(FIX(op, 0), FIX(sz, 1)), - OP2(ORTREG1, OWMEMSB), - ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 0), - ENC(ptr, reg_ptr, 1), ENC(cst, mem_offset, 1))) -INSN(stb, d, doff4_dsz_x01, store, C64XP, - TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSITIVE), - FIX2(FIX(op, 0), FIX(sz, 1)), - OP2(ORTREG1, OWMEMSB), - ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 0), - ENC(ptr, reg_ptr, 1), ENC(cst, mem_offset, 1))) -INSN(stb, d, dind_dsz_000, store, C64XP, - TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(REG_POSITIVE), - FIX2(FIX(op, 0), FIX(sz, 1)), - OP2(ORTREG1, OWMEMSB), - ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(src1, mem_offset, 1), - ENC(ptr, reg_ptr, 1), ENC(srcdst, reg, 0))) -INSN(stb, d, dind_dsz_x01, store, C64XP, - TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(REG_POSITIVE), - FIX2(FIX(op, 0), FIX(sz, 1)), - OP2(ORTREG1, OWMEMSB), - ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(src1, mem_offset, 1), - ENC(ptr, reg_ptr, 1), ENC(srcdst, reg, 0))) -INSN(stb, d, dinc_dsz_000, store, C64XP, - TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSTINCR), - FIX2(FIX(op, 0), FIX(sz, 1)), - OP2(ORTREG1, OWMEMSB), - ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 0), - ENC(ptr, reg_ptr, 1), ENC(cst, mem_offset_minus_one, 1))) -INSN(stb, d, dinc_dsz_x01, store, C64XP, - TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSTINCR), - FIX2(FIX(op, 0), FIX(sz, 1)), - OP2(ORTREG1, OWMEMSB), - ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 0), - ENC(ptr, reg_ptr, 1), ENC(cst, mem_offset_minus_one, 1))) -INSN(stb, d, ddec_dsz_000, store, C64XP, - TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(PREDECR), - FIX2(FIX(op, 0), FIX(sz, 1)), - OP2(ORTREG1, OWMEMSB), - ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 0), - ENC(ptr, reg_ptr, 1), ENC(cst, mem_offset_minus_one, 1))) -INSN(stb, d, ddec_dsz_x01, store, C64XP, - TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(PREDECR), - FIX2(FIX(op, 0), FIX(sz, 1)), - OP2(ORTREG1, OWMEMSB), - ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 0), - ENC(ptr, reg_ptr, 1), ENC(cst, mem_offset_minus_one, 1))) -/**/ - -INSN(stdw, d, load_store, store, C64X, TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS, - FIX2(FIX(op, 4), FIX(r, 1)), - OP2(ORDREGD1, OWMEMSD), - ENC6(ENC(s, data_fu, 0), ENC(y, fu, 0), ENC(mode, mem_mode, 1), - ENC(offsetR, mem_offset, 1), ENC(baseR, reg, 1), - ENC(srcdst, reg, 0))) - -/* 16 bits insn */ -INSN(stdw, d, dpp, store, C64XP, - TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSTDECR)|TIC6X_FLAG_INSN16_B15PTR|TIC6X_FLAG_INSN16_NORS, - FIX3(FIX(op, 0), FIX(dw, 1), FIX(s, 1)), - OP2(ORTREGD1, OWMEMSD), - ENC4(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 0), - ENC(cst, mem_offset_minus_one, 1))) -INSN(stdw, d, ddecdw, store, C64XP, - TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(PREDECR), - FIX3(FIX(op, 0), FIX(na, 0), FIX(sz, 0)), - OP2(ORTREGD1, OWMEMSD), - ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg_shift, 0), - ENC(ptr, reg_ptr, 1), ENC(cst, mem_offset_minus_one, 1))) -INSN(stdw, d, dincdw, store, C64XP, - TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSTINCR), - FIX3(FIX(op, 0), FIX(na, 0), FIX(sz, 0)), - OP2(ORTREGD1, OWMEMSD), - ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg_shift, 0), - ENC(ptr, reg_ptr, 1), ENC(cst, mem_offset_minus_one, 1))) -INSN(stdw, d, dinddw, store, C64XP, - TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(REG_POSITIVE), - FIX3(FIX(op, 0), FIX(na, 0), FIX(sz, 0)), - OP2(ORTREGD1, OWMEMSD), - ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(src1, mem_offset, 1), - ENC(ptr, reg_ptr, 1), ENC(srcdst, reg_shift, 0))) -INSN(stdw, d, doff4dw, store, C64XP, - TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSITIVE), - FIX3(FIX(op, 0), FIX(na, 0), FIX(sz, 0)), - OP2(ORTREGD1, OWMEMSD), - ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(cst, mem_offset, 1), - ENC(ptr, reg_ptr, 1), ENC(srcdst, reg_shift, 0))) -/**/ - -INSN(sth, d, load_store, store, C62X, - TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1), - FIX2(FIX(op, 5), FIX(r, 0)), - OP2(ORDREG1, OWMEMSH), - ENC6(ENC(s, data_fu, 0), ENC(y, fu, 0), ENC(mode, mem_mode, 1), - ENC(offsetR, mem_offset, 1), ENC(baseR, reg, 1), - ENC(srcdst, reg, 0))) -INSN(sth, d, load_store_long, store, C62X, - TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_PREFER(0), - FIX1(FIX(op, 5)), - OP2(ORDREG1, OWMEMLH), - ENC4(ENC(s, data_fu, 0), ENC(y, areg, 1), ENC(offsetR, ulcst_dpr_half, 1), - ENC(dst, reg, 0))) - -/* 16 bits insn */ -INSN(sth, d, doff4_dsz_01x, store, C64XP, - TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSITIVE), - FIX2(FIX(op, 0), FIX(sz, 1)), - OP2(ORTREG1, OWMEMSH), - ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 0), - ENC(ptr, reg_ptr, 1), ENC(cst, mem_offset, 1))) -INSN(sth, d, doff4_dsz_111, store, C64XP, - TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSITIVE), - FIX2(FIX(op, 0), FIX(sz, 1)), - OP2(ORTREG1, OWMEMSH), - ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 0), - ENC(ptr, reg_ptr, 1), ENC(cst, mem_offset, 1))) -INSN(sth, d, dind_dsz_01x, store, C64XP, - TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(REG_POSITIVE), - FIX2(FIX(op, 0), FIX(sz, 1)), - OP2(ORTREG1, OWMEMSH), - ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 0), - ENC(ptr, reg_ptr, 1), ENC(src1, mem_offset, 1))) -INSN(sth, d, dind_dsz_111, store, C64XP, - TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(REG_POSITIVE), - FIX2(FIX(op, 0), FIX(sz, 1)), - OP2(ORTREG1, OWMEMSH), - ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 0), - ENC(ptr, reg_ptr, 1), ENC(src1, mem_offset, 1))) -INSN(sth, d, dinc_dsz_01x, store, C64XP, - TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSTINCR), - FIX2(FIX(op, 0), FIX(sz, 1)), - OP2(ORTREG1, OWMEMSH), - ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 0), - ENC(ptr, reg_ptr, 1), ENC(cst, mem_offset_minus_one, 1))) -INSN(sth, d, dinc_dsz_111, store, C64XP, - TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSTINCR), - FIX2(FIX(op, 0), FIX(sz, 1)), - OP2(ORTREG1, OWMEMSH), - ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 0), - ENC(ptr, reg_ptr, 1), ENC(cst, mem_offset_minus_one, 1))) -INSN(sth, d, ddec_dsz_01x, store, C64XP, - TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(PREDECR), - FIX2(FIX(op, 0), FIX(sz, 1)), - OP2(ORTREG1, OWMEMSH), - ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 0), - ENC(ptr, reg_ptr, 1), ENC(cst, mem_offset_minus_one, 1))) -INSN(sth, d, ddec_dsz_111, store, C64XP, - TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(PREDECR), - FIX2(FIX(op, 0), FIX(sz, 1)), - OP2(ORTREG1, OWMEMSH), - ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 0), - ENC(ptr, reg_ptr, 1), ENC(cst, mem_offset_minus_one, 1))) -/**/ - -INSN(stndw, d, store_nonaligned, store, C64X, - TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_UNALIGNED, - FIX0(), - OP2(ORDREGD1, OWMEMND), - ENC7(ENC(s, data_fu, 0), ENC(y, fu, 0), ENC(mode, mem_mode, 1), - ENC(offsetR, mem_offset_noscale, 1), ENC(baseR, reg, 1), - ENC(sc, scaled, 1), ENC(src, reg_shift, 0))) - -/* 16 bits insn */ -INSN(stndw, d, ddecdw, store, C64XP, - TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_UNALIGNED|TIC6X_FLAG_INSN16_MEM_MODE(PREDECR), - FIX3(FIX(op, 0), FIX(na, 1), FIX(sz, 0)), - OP2(ORTREGD1, OWMEMND), - ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg_shift, 0), - ENC(ptr, reg_ptr, 1), ENC(cst, mem_offset_minus_one_noscale, 1))) -INSN(stndw, d, dincdw, store, C64XP, - TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_UNALIGNED|TIC6X_FLAG_INSN16_MEM_MODE(POSTINCR), - FIX3(FIX(op, 0), FIX(na, 1), FIX(sz, 0)), - OP2(ORTREGD1, OWMEMND), - ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg_shift, 0), - ENC(ptr, reg_ptr, 1), ENC(cst, mem_offset_minus_one_noscale, 1))) -INSN(stndw, d, dinddw, store, C64XP, - TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_UNALIGNED|TIC6X_FLAG_INSN16_MEM_MODE(REG_POSITIVE), - FIX3(FIX(op, 0), FIX(na, 1), FIX(sz, 0)), - OP2(ORTREGD1, OWMEMND), - ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(src1, mem_offset_noscale, 1), - ENC(ptr, reg_ptr, 1), ENC(srcdst, reg_shift, 0))) -INSN(stndw, d, doff4dw, store, C64XP, - TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_UNALIGNED|TIC6X_FLAG_INSN16_MEM_MODE(POSITIVE), - FIX3(FIX(op, 0), FIX(na, 1), FIX(sz, 0)), - OP2(ORTREGD1, OWMEMND), - ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(cst, mem_offset_noscale, 1), - ENC(ptr, reg_ptr, 1), ENC(srcdst, reg_shift, 0))) -/**/ - -INSN(stnw, d, load_store, store, C64X, - TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_UNALIGNED, - FIX2(FIX(op, 5), FIX(r, 1)), - OP2(ORDREG1, OWMEMSW), - ENC6(ENC(s, data_fu, 0), ENC(y, fu, 0), ENC(mode, mem_mode, 1), - ENC(offsetR, mem_offset, 1), ENC(baseR, reg, 1), - ENC(srcdst, reg, 0))) - -/* 16 bits insn */ -INSN(stnw, d, doff4_dsz_110, store, C64XP, - TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSITIVE), - FIX2(FIX(op, 0), FIX(sz, 1)), - OP2(ORTREG1, OWMEMSW), - ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 0), - ENC(ptr, reg_ptr, 1), ENC(cst, mem_offset, 1))) -INSN(stnw, d, dind_dsz_110, store, C64XP, - TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(REG_POSITIVE), - FIX2(FIX(op, 0), FIX(sz, 1)), - OP2(ORTREG1, OWMEMSW), - ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 0), - ENC(ptr, reg_ptr, 1), ENC(src1, mem_offset, 1))) -INSN(stnw, d, dinc_dsz_110, store, C64XP, - TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSTINCR), - FIX2(FIX(op, 0), FIX(sz, 1)), - OP2(ORTREG1, OWMEMSW), - ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 0), - ENC(ptr, reg_ptr, 1), ENC(cst, mem_offset_minus_one, 1))) -INSN(stnw, d, ddec_dsz_110, store, C64XP, - TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(PREDECR), - FIX2(FIX(op, 0), FIX(sz, 1)), - OP2(ORTREG1, OWMEMSW), - ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 0), - ENC(ptr, reg_ptr, 1), ENC(cst, mem_offset_minus_one, 1))) -/**/ - -INSN(stw, d, load_store, store, C62X, - TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1), - FIX2(FIX(op, 7), FIX(r, 0)), - OP2(ORDREG1, OWMEMSW), - ENC6(ENC(s, data_fu, 0), ENC(y, fu, 0), ENC(mode, mem_mode, 1), - ENC(offsetR, mem_offset, 1), ENC(baseR, reg, 1), - ENC(srcdst, reg, 0))) -INSN(stw, d, load_store_long, store, C62X, - TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_PREFER(0), - FIX1(FIX(op, 7)), - OP2(ORDREG1, OWMEMLW), - ENC4(ENC(s, data_fu, 0), ENC(y, areg, 1), ENC(offsetR, ulcst_dpr_word, 1), - ENC(dst, reg, 0))) - -/* 16 bits insn */ -INSN(stw, d, doff4_dsz_0xx, store, C64XP, - TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSITIVE), - FIX2(FIX(op, 0), FIX(sz, 0)), - OP2(ORTREG1, OWMEMSW), - ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 0), - ENC(ptr, reg_ptr, 1), ENC(cst, mem_offset, 1))) -INSN(stw, d, doff4_dsz_100, store, C64XP, - TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSITIVE), - FIX2(FIX(op, 0), FIX(sz, 1)), - OP2(ORTREG1, OWMEMSW), - ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 0), - ENC(ptr, reg_ptr, 1), ENC(cst, mem_offset, 1))) -INSN(stw, d, dind_dsz_0xx, store, C64XP, - TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(REG_POSITIVE), - FIX2(FIX(op, 0), FIX(sz, 0)), - OP2(ORTREG1, OWMEMSW), - ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 0), - ENC(ptr, reg_ptr, 1), ENC(src1, mem_offset, 1))) -INSN(stw, d, dind_dsz_100, store, C64XP, - TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(REG_POSITIVE), - FIX2(FIX(op, 0), FIX(sz, 1)), - OP2(ORTREG1, OWMEMSW), - ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 0), - ENC(ptr, reg_ptr, 1), ENC(src1, mem_offset, 1))) -INSN(stw, d, dinc_dsz_0xx, store, C64XP, - TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSTINCR), - FIX2(FIX(op, 0), FIX(sz, 0)), - OP2(ORTREG1, OWMEMSW), - ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 0), - ENC(ptr, reg_ptr, 1), ENC(cst, mem_offset_minus_one, 1))) -INSN(stw, d, dinc_dsz_100, store, C64XP, - TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSTINCR), - FIX2(FIX(op, 0), FIX(sz, 1)), - OP2(ORTREG1, OWMEMSW), - ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 0), - ENC(ptr, reg_ptr, 1), ENC(cst, mem_offset_minus_one, 1))) -INSN(stw, d, ddec_dsz_0xx, store, C64XP, - TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(PREDECR), - FIX2(FIX(op, 0), FIX(sz, 0)), - OP2(ORTREG1, OWMEMSW), - ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 0), - ENC(ptr, reg_ptr, 1), ENC(cst, mem_offset_minus_one, 1))) -INSN(stw, d, ddec_dsz_100, store, C64XP, - TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(PREDECR), - FIX2(FIX(op, 0), FIX(sz, 1)), - OP2(ORTREG1, OWMEMSW), - ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 0), - ENC(ptr, reg_ptr, 1), ENC(cst, mem_offset_minus_one, 1))) -INSN(stw, d, dpp, store, C64XP, - TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSTDECR)|TIC6X_FLAG_INSN16_B15PTR|TIC6X_FLAG_INSN16_NORS, - FIX2(FIX(op, 0), FIX(dw, 0)), - OP2(ORTREG1, OWMEMSW), - ENC4(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 0), - ENC(cst, mem_offset_minus_one, 1))) -INSN(stw, d, dstk, store, C64XP, - TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSITIVE)|TIC6X_FLAG_INSN16_B15PTR, - FIX2(FIX(op, 0x0), FIX(s, 1)), - OP2(ORTREG1, OWMEMSW), - ENC4(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 0), - ENC(cst, mem_offset, 1))) -/**/ - -INSNE(sub, l_si_xsi_si, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_PREFER(1), - FIX1(FIX(op, 0x07)), - OP3(ORREG1, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -INSNE(sub, l_xsi_si_si, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_PREFER(0), - FIX1(FIX(op, 0x17)), - OP3(ORXREG1, ORREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -INSNE(sub, l_si_xsi_sl, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_PREFER(1), - FIX1(FIX(op, 0x27)), - OP3(ORREG1, ORXREG1, OWREGL1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -INSNE(sub, l_xsi_si_sl, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_PREFER(0), - FIX1(FIX(op, 0x37)), - OP3(ORXREG1, ORREG1, OWREGL1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -INSNE(sub, l_s5_xsi_si, l, 1_or_2_src, 1cycle, C62X, 0, - FIX1(FIX(op, 0x06)), - OP3(OACST, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -INSNE(sub, l_s5_sl_sl, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS, - FIX1(FIX(op, 0x24)), - OP3(OACST, ORREGL1, OWREGL1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -INSNE(sub, l_xsi_s5_si, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_MACRO, - FIX1(FIX(op, 0x2)), - OP3(ORXREG1, OACST, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst_negate, 1), - ENC(src2, reg, 0), ENC(dst, reg, 2))) -INSNE(sub, l_sl_s5_sl, l, 1_or_2_src, 1cycle, C62X, - TIC6X_FLAG_MACRO|TIC6X_FLAG_NO_CROSS, - FIX2(FIX(op, 0x20), FIX(x, 0)), - OP3(ORREGL1, OACST, OWREGL1), - ENC4(ENC(s, fu, 0), ENC(src1, scst_negate, 1), ENC(src2, reg, 0), - ENC(dst, reg, 2))) -INSNE(sub, s_si_xsi_si, s, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_PREFER(1), - FIX1(FIX(op, 0x17)), - OP3(ORREG1, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -INSNE(sub, s_s5_xsi_si, s, 1_or_2_src, 1cycle, C62X, 0, - FIX1(FIX(op, 0x16)), - OP3(OACST, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -/* Contrary to SPRUFE8, this is the correct encoding for this - instruction; this instruction can be predicated. */ -INSNE(sub, s_xsi_si_si, s, ext_1_or_2_src, 1cycle, C64X, TIC6X_FLAG_PREFER(0), - FIX1(FIX(op, 0x5)), - OP3(ORXREG1, ORREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), - ENC(src1, reg, 1), ENC(dst, reg, 2))) -INSNE(sub, s_xsi_s5_si, s, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_MACRO, - FIX1(FIX(op, 0x6)), - OP3(ORXREG1, OACST, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst_negate, 1), - ENC(src2, reg, 0), ENC(dst, reg, 2))) -INSNE(sub, d_si_si_si, d, 1_or_2_src, 1cycle, C62X, - TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1), - FIX1(FIX(op, 0x11)), - OP3(ORREG1, ORREG1, OWREG1), - ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, reg, 1), - ENC(dst, reg, 2))) -INSNE(sub, d_si_u5_si, d, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS, - FIX1(FIX(op, 0x13)), - OP3(ORREG1, OACST, OWREG1), - ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1), - ENC(dst, reg, 2))) -INSNE(sub, d_si_xsi_si, d, ext_1_or_2_src, 1cycle, C64X, TIC6X_FLAG_PREFER(0), - FIX1(FIX(op, 0xc)), - OP3(ORREG1, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -/* 16 bits insn */ -INSN(sub, l, l3_sat_0, 1cycle, C64XP, 0, - FIX1(FIX(op, 0x1)), - OP3(ORREG1, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -INSN(sub, l, lx1, 1cycle, C64XP, TIC6X_FLAG_NO_CROSS, - FIX1(FIX(op, 0x2)), - OP3(OHWCST0, ORREG1, OWREG1), - ENC3(ENC(s, fu, 0), ENC(srcdst, reg, 1), ENC(srcdst, reg, 2))) -INSN(sub, s, sx1, 1cycle, C64XP, TIC6X_FLAG_NO_CROSS, - FIX1(FIX(op, 0x2)), - OP3(OHWCST0, ORREG1, OWREG1), - ENC3(ENC(s, fu, 0), ENC(srcdst, reg, 1), ENC(srcdst, reg, 2))) -INSN(sub, s, sx2op, 1cycle, C64XP, 0, - FIX1(FIX(op, 0x1)), - OP3(ORREG1, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(srcdst, reg, 0), ENC(srcdst, reg, 2), - ENC(src2, reg, 1), ENC(x, xpath, 1))) -INSN(sub, s, s3_sat_x, 1cycle, C64XP, 0, - FIX1(FIX(op, 0x1)), - OP3(ORREG1, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -INSN(sub, d, dx1, 1cycle, C64XP, TIC6X_FLAG_NO_CROSS, - FIX1(FIX(op, 0x3)), - OP3(ORREG1, OHWCST1, OWREG1), - ENC3(ENC(s, fu, 0), ENC(srcdst, reg, 0), ENC(srcdst, reg, 2))) -INSN(sub, d, dx2op, 1cycle, C64XP, 0, - FIX1(FIX(op, 0x1)), - OP3(ORREG1, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(srcdst, reg, 0), - ENC(src2, reg, 1), ENC(srcdst, reg, 2))) -/**/ - -INSNE(subab, d_si_si_si, d, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS, - FIX1(FIX(op, 0x31)), - OP3(ORREG1, ORREG1, OWREG1), - ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, reg, 1), - ENC(dst, reg, 2))) -INSNE(subab, d_si_u5_si, d, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS, - FIX1(FIX(op, 0x33)), - OP3(ORREG1, OACST, OWREG1), - ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1), - ENC(dst, reg, 2))) - -INSN(subabs4, l, 1_or_2_src, 1cycle, C64X, 0, - FIX1(FIX(op, 0x5a)), - OP3(ORREG1, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSNE(subah, d_si_si_si, d, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS, - FIX1(FIX(op, 0x35)), - OP3(ORREG1, ORREG1, OWREG1), - ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, reg, 1), - ENC(dst, reg, 2))) -INSNE(subah, d_si_u5_si, d, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS, - FIX1(FIX(op, 0x37)), - OP3(ORREG1, OACST, OWREG1), - ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1), - ENC(dst, reg, 2))) - -INSNE(subaw, d_si_si_si, d, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS, - FIX1(FIX(op, 0x39)), - OP3(ORREG1, ORREG1, OWREG1), - ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, reg, 1), - ENC(dst, reg, 2))) -INSNE(subaw, d_si_u5_si, d, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS, - FIX1(FIX(op, 0x3b)), - OP3(ORREG1, OACST, OWREG1), - ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1), - ENC(dst, reg, 2))) - -/* 16 bits insn */ -INSN(subaw, d, dx5p, 1cycle, C64XP, 0, - FIX1(FIX(op, 1)), - OP3(ORB15REG1, OACST, OWB15REG1), - ENC2(ENC(s, fu, 0), ENC(cst, ucst, 1))) -/**/ - -INSN(subc, l, 1_or_2_src, 1cycle, C62X, 0, - FIX1(FIX(op, 0x4b)), - OP3(ORREG1, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSNE(subdp, l_dp_xdp_dp, l, 1_or_2_src, addsubdp, C67X, TIC6X_FLAG_PREFER(1), - FIX1(FIX(op, 0x19)), - OP3(ORREGD12, ORXREGD12, OWREGD67), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -INSNE(subdp, l_xdp_dp_dp, l, 1_or_2_src, addsubdp, C67X, TIC6X_FLAG_PREFER(0), - FIX1(FIX(op, 0x1d)), - OP3(ORXREGD12, ORREGD12, OWREGD67), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -INSNE(subdp, s_dp_xdp_dp, s, l_1_or_2_src, addsubdp, C67XP, - TIC6X_FLAG_PREFER(1), - FIX1(FIX(op, 0x73)), - OP3(ORREGD12, ORXREGD12, OWREGD67), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -INSNE(subdp, s_xdp_dp_dp, s, l_1_or_2_src, addsubdp, C67XP, - TIC6X_FLAG_PREFER(0), - FIX1(FIX(op, 0x77)), - OP3(ORXREGD12, ORREGD12, OWREGD67), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), - ENC(src1, reg, 1), ENC(dst, reg, 2))) - -INSNE(subsp, l_sp_xsp_sp, l, 1_or_2_src, 4cycle, C67X, TIC6X_FLAG_PREFER(1), - FIX1(FIX(op, 0x11)), - OP3(ORREG1, ORXREG1, OWREG4), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -INSNE(subsp, l_xsp_sp_sp, l, 1_or_2_src, 4cycle, C67X, TIC6X_FLAG_PREFER(0), - FIX1(FIX(op, 0x15)), - OP3(ORXREG1, ORREG1, OWREG4), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -INSNE(subsp, s_sp_xsp_sp, s, l_1_or_2_src, 4cycle, C67XP, - TIC6X_FLAG_PREFER(1), - FIX1(FIX(op, 0x71)), - OP3(ORREG1, ORXREG1, OWREG4), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -INSNE(subsp, s_xsp_sp_sp, s, l_1_or_2_src, 4cycle, C67XP, - TIC6X_FLAG_PREFER(0), - FIX1(FIX(op, 0x75)), - OP3(ORXREG1, ORREG1, OWREG4), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), - ENC(src1, reg, 1), ENC(dst, reg, 2))) - -INSNE(subu, l_ui_xui_ul, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_PREFER(1), - FIX1(FIX(op, 0x2f)), - OP3(ORREG1, ORXREG1, OWREGL1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -INSNE(subu, l_xui_ui_ul, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_PREFER(0), - FIX1(FIX(op, 0x3f)), - OP3(ORXREG1, ORREG1, OWREGL1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSN(sub2, l, 1_or_2_src, 1cycle, C64X, 0, - FIX1(FIX(op, 0x04)), - OP3(ORREG1, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -INSN(sub2, s, 1_or_2_src, 1cycle, C62X, 0, - FIX1(FIX(op, 0x11)), - OP3(ORREG1, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -INSN(sub2, d, ext_1_or_2_src, 1cycle, C64X, 0, - FIX1(FIX(op, 0x5)), - OP3(ORREG1, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSN(sub4, l, 1_or_2_src, 1cycle, C64X, 0, - FIX1(FIX(op, 0x66)), - OP3(ORREG1, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSN(swap2, l, 1_or_2_src, 1cycle, C64X, TIC6X_FLAG_MACRO|TIC6X_FLAG_NO_CROSS, - FIX2(FIX(op, 0x1b), FIX(x, 0)), - OP2(ORREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 0), ENC(dst, reg, 1))) -INSN(swap2, s, 1_or_2_src, 1cycle, C64X, TIC6X_FLAG_MACRO|TIC6X_FLAG_NO_CROSS, - FIX2(FIX(op, 0x10), FIX(x, 0)), - OP2(ORREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 0), ENC(dst, reg, 1))) - -/* Contrary to SPRUFE8, this is the correct encoding for this - instruction. */ -INSN(swap4, l, unary, 1cycle, C64X, 0, - FIX1(FIX(op, 0x1)), - OP2(ORXREG1, OWREG1), - ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), - ENC(dst, reg, 1))) - -INSN(swe, nfu, swe, 1cycle, C64XP, 0, - FIX1(FIX(s, 0)), - OP0(), - ENC0()) - -INSN(swenr, nfu, swenr, 1cycle, C64XP, 0, - FIX1(FIX(s, 0)), - OP0(), - ENC0()) - -INSN(unpkhu4, l, unary, 1cycle, C64X, 0, - FIX1(FIX(op, 0x03)), - OP2(ORXREG1, OWREG1), - ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), - ENC(dst, reg, 1))) -INSN(unpkhu4, s, unary, 1cycle, C64X, 0, - FIX1(FIX(op, 0x03)), - OP2(ORXREG1, OWREG1), - ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), - ENC(dst, reg, 1))) - -INSN(unpklu4, l, unary, 1cycle, C64X, 0, - FIX1(FIX(op, 0x02)), - OP2(ORXREG1, OWREG1), - ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), - ENC(dst, reg, 1))) -INSN(unpklu4, s, unary, 1cycle, C64X, 0, - FIX1(FIX(op, 0x02)), - OP2(ORXREG1, OWREG1), - ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), - ENC(dst, reg, 1))) - -INSNE(xor, l_ui_xui_ui, l, 1_or_2_src, 1cycle, C62X, 0, - FIX1(FIX(op, 0x6f)), - OP3(ORREG1, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -INSNE(xor, l_s5_xui_ui, l, 1_or_2_src, 1cycle, C62X, 0, - FIX1(FIX(op, 0x6e)), - OP3(OACST, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -INSNE(xor, s_ui_xui_ui, s, 1_or_2_src, 1cycle, C62X, 0, - FIX1(FIX(op, 0x0b)), - OP3(ORREG1, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -INSNE(xor, s_s5_xui_ui, s, 1_or_2_src, 1cycle, C62X, 0, - FIX1(FIX(op, 0x0a)), - OP3(OACST, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -INSNE(xor, d_ui_xui_ui, d, ext_1_or_2_src, 1cycle, C64X, 0, - FIX1(FIX(op, 0xe)), - OP3(ORREG1, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -INSNE(xor, d_s5_xui_ui, d, ext_1_or_2_src, 1cycle, C64X, 0, - FIX1(FIX(op, 0xf)), - OP3(OACST, ORXREG1, OWREG1), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -/* 16 bits insn */ -INSN(xor, l, l2c, 1cycle, C64XP, 0, - FIX1(FIX(op, 0x2)), - OP3(ORREG1, ORXREG1, OWREG1NORS), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) -INSNU(xor, l, lsdx1, 1cycle, C64XP, TIC6X_FLAG_NO_CROSS, - FIX2(FIX(op, 0x7), FIX(unit, 0x0)), - OP3(ORREG1, OHWCST1, OWREG1), - ENC3(ENC(s, fu, 0), ENC(srcdst, reg, 0), ENC(srcdst, reg, 2))) -INSNU(xor, s, lsdx1, 1cycle, C64XP, TIC6X_FLAG_NO_CROSS, - FIX2(FIX(op, 0x7), FIX(unit, 0x1)), - OP3(ORREG1, OHWCST1, OWREG1), - ENC3(ENC(s, fu, 0), ENC(srcdst, reg, 0), ENC(srcdst, reg, 2))) -INSNU(xor, d, lsdx1, 1cycle, C64XP, TIC6X_FLAG_NO_CROSS, - FIX2(FIX(op, 0x7), FIX(unit, 0x2)), - OP3(ORREG1, OHWCST1, OWREG1), - ENC3(ENC(s, fu, 0), ENC(srcdst, reg, 0), ENC(srcdst, reg, 2))) -/**/ - -INSN(xormpy, m, 1_or_2_src, 4cycle, C64XP, 0, - FIX1(FIX(op, 0x1b)), - OP3(ORREG1, ORXREG1, OWREG4), - ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), - ENC(src2, reg, 1), ENC(dst, reg, 2))) - -INSN(xpnd2, m, unary, 1616_m, C64X, 0, - FIX1(FIX(op, 0x19)), - OP2(ORXREG1, OWREG2), - ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), - ENC(dst, reg, 1))) - -INSN(xpnd4, m, unary, 1616_m, C64X, 0, - FIX1(FIX(op, 0x18)), - OP2(ORXREG1, OWREG2), - ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), - ENC(dst, reg, 1))) - -INSN(zero, s, mvk, 1cycle, C62X, TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO, - FIX2(FIX(h, 0), FIX(cst, 0)), - OP1(OWREG1), - ENC2(ENC(s, fu, 0), ENC(dst, reg, 0))) -INSN(zero, l, unary, 1cycle, C64X, - TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO|TIC6X_FLAG_PREFER(1), - FIX3(FIX(x, 0), FIX(op, 0x05), FIX(src2, 0)), - OP1(OWREG1), - ENC2(ENC(s, fu, 0), ENC(dst, reg, 0))) -INSNE(zero, l_sub, l, 1_or_2_src, 1cycle, C62X, - TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO|TIC6X_FLAG_PREFER(0), - FIX2(FIX(op, 0x07), FIX(x, 0)), - OP1(OWREG1), - ENC4(ENC(s, fu, 0), ENC(src1, reg_unused, 0), ENC(src2, reg_unused, 0), - ENC(dst, reg, 0))) -INSNE(zero, l_sub_sl, l, 1_or_2_src, 1cycle, C62X, - TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO, - FIX2(FIX(op, 0x27), FIX(x, 0)), - OP1(OWREGL1), - ENC4(ENC(s, fu, 0), ENC(src1, reg_unused, 0), ENC(src2, reg_unused, 0), - ENC(dst, reg, 0))) -INSNE(zero, d_mvk, d, 1_or_2_src, 1cycle, C64X, - TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO|TIC6X_FLAG_PREFER(1), - FIX3(FIX(op, 0x00), FIX(src1, 0), FIX(src2, 0)), - OP1(OWREG1), - ENC2(ENC(s, fu, 0), ENC(dst, reg, 0))) -INSNE(zero, d_sub, d, 1_or_2_src, 1cycle, C62X, - TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO|TIC6X_FLAG_PREFER(0), - FIX1(FIX(op, 0x11)), - OP1(OWREG1), - ENC4(ENC(s, fu, 0), ENC(src2, reg_unused, 0), ENC(src1, reg_unused, 0), - ENC(dst, reg, 0))) - -#undef TIC6X_INSN_C64X_AND_C67X -#undef tic6x_insn_format_nfu_s_branch_nop_cst -#undef tic6x_insn_format_s_l_1_or_2_src -#undef RAN -#undef FIX -#undef FIX0 -#undef FIX1 -#undef FIX2 -#undef FIX3 -#undef FIX4 -#undef OP0 -#undef OP1 -#undef OP2 -#undef OP3 -#undef OP4 -#undef OACST -#undef OLCST -#undef OHWCSTM1 -#undef OHWCST0 -#undef OHWCST1 -#undef OHWCST5 -#undef OHWCST16 -#undef OHWCST24 -#undef OHWCST31 -#undef OFULIST -#undef ORIRP1 -#undef ORNRP1 -#undef OWREG1 -#undef OWRETREG1 -#undef ORREG1 -#undef ORDREG1 -#undef ORWREG1 -#undef ORAREG1 -#undef ORXREG1 -#undef ORREG12 -#undef ORREG14 -#undef ORXREG14 -#undef OWREG2 -#undef OWREG4 -#undef OWREG9 -#undef OWDREG5 -#undef OWREGL1 -#undef ORREGL1 -#undef OWREGD1 -#undef ORTREG1 -#undef ORTREGD1 -#undef OWTREG5 -#undef OWTREGD5 -#undef OWREGD12 -#undef OWREGD4 -#undef ORREGD1 -#undef OWREGD45 -#undef OWREGD67 -#undef ORDREGD1 -#undef OWDREGD5 -#undef ORREGD12 -#undef ORXREGD12 -#undef ORXREGD1234 -#undef ORREGD1324 -#undef OWREGD910 -#undef OWILC1 -#undef ORCREG1 -#undef OWCREG1 -#undef OWREG1Z -#undef ORB15REG1 -#undef OWB15REG1 -#undef ORMEMDW -#undef OWMEMDW -#undef ORMEMSB -#undef OWMEMSB -#undef ORMEMLB -#undef OWMEMLB -#undef ORMEMSH -#undef OWMEMSH -#undef ORMEMLH -#undef OWMEMLH -#undef ORMEMSW -#undef OWMEMSW -#undef ORMEMLW -#undef OWMEMLW -#undef ORMEMSD -#undef OWMEMSD -#undef ORMEMND -#undef OWMEMND -#undef ENC -#undef ENC0 -#undef ENC1 -#undef ENC2 -#undef ENC3 -#undef ENC4 -#undef ENC5 -#undef ENC6 -#undef ENC7 diff --git a/include/opcode/tic6x.h b/include/opcode/tic6x.h deleted file mode 100644 index d76c5e1..0000000 --- a/include/opcode/tic6x.h +++ /dev/null @@ -1,718 +0,0 @@ -/* TI C6X opcode information. - Copyright 2010-2013 Free Software Foundation, Inc. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, - MA 02110-1301, USA. */ - -#ifndef OPCODE_TIC6X_H -#define OPCODE_TIC6X_H - -#include "bfd.h" -#include "symcat.h" - -/* A field in an instruction format. The names are based on those - used in the architecture manuals. */ -typedef enum - { - tic6x_field_baseR, - tic6x_field_cc, - tic6x_field_creg, - tic6x_field_cst, - tic6x_field_csta, - tic6x_field_cstb, - tic6x_field_dst, - tic6x_field_dstms, - tic6x_field_dw, - tic6x_field_fstgfcyc, - tic6x_field_h, - tic6x_field_ii, - tic6x_field_mask, - tic6x_field_mode, - tic6x_field_n, - tic6x_field_na, - tic6x_field_offsetR, - tic6x_field_op, - tic6x_field_p, - tic6x_field_ptr, - tic6x_field_r, - tic6x_field_s, - tic6x_field_sc, - tic6x_field_src, - tic6x_field_src1, - tic6x_field_src2, - tic6x_field_srcdst, - tic6x_field_srcms, - tic6x_field_sn, - tic6x_field_sz, - tic6x_field_unit, - tic6x_field_t, - tic6x_field_x, - tic6x_field_y, - tic6x_field_z - } tic6x_insn_field_id; - -typedef struct -{ - /* The least-significant bit position in the field. */ - unsigned short low_pos; - - /* The number of bits in the field. */ - unsigned short width; - /* The position of the bitfield in the field. */ - unsigned short pos; -} tic6x_bitfield; - -/* Maximum number of subfields in composite field. */ -#define TIC6X_MAX_BITFIELDS 4 - -typedef struct -{ - /* The name used to reference the field. */ - tic6x_insn_field_id field_id; - unsigned int num_bitfields; - tic6x_bitfield bitfields[TIC6X_MAX_BITFIELDS]; -} tic6x_insn_field; - -/* Maximum number of variable fields in an instruction format. */ -#define TIC6X_MAX_INSN_FIELDS 11 - -/* A particular instruction format. */ -typedef struct -{ - /* How many bits in the instruction. */ - unsigned int num_bits; - - /* Constant bits in the instruction. */ - unsigned int cst_bits; - - /* Mask matching those bits. */ - unsigned int mask; - - /* The number of instruction fields. */ - unsigned int num_fields; - - /* Descriptions of instruction fields. */ - tic6x_insn_field fields[TIC6X_MAX_INSN_FIELDS]; -} tic6x_insn_format; - -/* An index into the table of instruction formats. */ -typedef enum - { -#define FMT(name, num_bits, cst_bits, mask, fields) \ - CONCAT2(tic6x_insn_format_, name), -#include "tic6x-insn-formats.h" -#undef FMT - tic6x_insn_format_max - } tic6x_insn_format_id; - -/* The table itself. */ -extern const tic6x_insn_format tic6x_insn_format_table[tic6x_insn_format_max]; - -/* If instruction format FMT has a field FIELD, return a pointer to - the description of that field; otherwise return NULL. */ - -const tic6x_insn_field *tic6x_field_from_fmt (const tic6x_insn_format *fmt, - tic6x_insn_field_id field); - -/* Description of a field (in an instruction format) whose value is - fixed, or constrained to be in a particular range, in a particular - opcode. */ -typedef struct -{ - /* The name of the field. */ - tic6x_insn_field_id field_id; - - /* The least value of the field in this instruction. */ - unsigned int min_val; - - /* The greatest value of the field in this instruction. */ - unsigned int max_val; -} tic6x_fixed_field; - -/* Pseudo opcode fields position for compact instructions - If 16 bits instruction detected, the opcode is enriched - [DSZ/3][BR][SAT][opcode] */ -#define TIC6X_COMPACT_SAT_POS 16 -#define TIC6X_COMPACT_BR_POS 17 -#define TIC6X_COMPACT_DSZ_POS 18 - -/* Bit-masks for defining instructions present on some subset of - processors; each indicates an instruction present on that processor - and those that are supersets of it. The options passed to the - assembler determine a bit-mask ANDed with the bit-mask indicating - when the instruction was added to determine whether the instruction - is enabled. */ -#define TIC6X_INSN_C62X 0x0001 -#define TIC6X_INSN_C64X 0x0002 -#define TIC6X_INSN_C64XP 0x0004 -#define TIC6X_INSN_C67X 0x0008 -#define TIC6X_INSN_C67XP 0x0010 -#define TIC6X_INSN_C674X 0x0020 - -/* Flags with further information about an opcode table entry. */ - -/* Only used by the assembler, not the disassembler. */ -#define TIC6X_FLAG_MACRO 0x0001 - -/* Must be first in its execute packet. */ -#define TIC6X_FLAG_FIRST 0x0002 - -/* Multi-cycle NOP (not used for the NOP n instruction itself, which - is only a multicycle NOP if n > 1). */ -#define TIC6X_FLAG_MCNOP 0x0004 - -/* Cannot be in parallel with a multi-cycle NOP. */ -#define TIC6X_FLAG_NO_MCNOP 0x0008 - -/* Load instruction. */ -#define TIC6X_FLAG_LOAD 0x0010 - -/* Store instruction. */ -#define TIC6X_FLAG_STORE 0x0020 - -/* Unaligned memory operation. */ -#define TIC6X_FLAG_UNALIGNED 0x0040 - -/* Only on side B. */ -#define TIC6X_FLAG_SIDE_B_ONLY 0x0080 - -/* Only on data path T2. */ -#define TIC6X_FLAG_SIDE_T2_ONLY 0x0100 - -/* Does not support cross paths. */ -#define TIC6X_FLAG_NO_CROSS 0x0200 - -/* Annotate this branch instruction as a call. */ -#define TIC6X_FLAG_CALL 0x0400 - -/* Annotate this branch instruction as a return. */ -#define TIC6X_FLAG_RETURN 0x0800 - -/* This instruction starts a software pipelined loop. */ -#define TIC6X_FLAG_SPLOOP 0x1000 - -/* This instruction ends a software pipelined loop. */ -#define TIC6X_FLAG_SPKERNEL 0x2000 - -/* This instruction takes a list of functional units as parameters; - although described as having one parameter, the number may be 0 to - 8. */ -#define TIC6X_FLAG_SPMASK 0x4000 - -/* When more than one opcode matches the assembly source, prefer the - one with the highest value for this bit-field. If two opcode table - entries can match the same syntactic form, they must have different - values here. */ -#define TIC6X_PREFER_VAL(n) (((n) & 0x8000) >> 15) -#define TIC6X_FLAG_PREFER(n) ((n) << 15) - -/* 16 bits opcode is predicated by register a0 (s = 0) or b0 (s = 1) */ -#define TIC6X_FLAG_INSN16_SPRED 0x00100000 -/* 16 bits opcode ignores RS bit of fetch packet header */ -#define TIC6X_FLAG_INSN16_NORS 0x00200000 -/* 16 bits opcode only on side B */ -#define TIC6X_FLAG_INSN16_BSIDE 0x00400000 -/* 16 bits opcode ptr reg is b15 */ -#define TIC6X_FLAG_INSN16_B15PTR 0x00800000 -/* 16 bits opcode memory access modes */ -#define TIC6X_INSN16_MEM_MODE(n) ((n) << 16) -#define TIC6X_INSN16_MEM_MODE_VAL(n) (((n) & 0x000F0000) >> 16) -#define TIC6X_MEM_MODE_NEGATIVE 0 -#define TIC6X_MEM_MODE_POSITIVE 1 -#define TIC6X_MEM_MODE_REG_NEGATIVE 4 -#define TIC6X_MEM_MODE_REG_POSITIVE 5 -#define TIC6X_MEM_MODE_PREDECR 8 -#define TIC6X_MEM_MODE_PREINCR 9 -#define TIC6X_MEM_MODE_POSTDECR 10 -#define TIC6X_MEM_MODE_POSTINCR 11 - -#define TIC6X_FLAG_INSN16_MEM_MODE(mode) TIC6X_INSN16_MEM_MODE(TIC6X_MEM_MODE_##mode) - -#define TIC6X_NUM_PREFER 2 - -/* Maximum number of fixed fields for a particular opcode. */ -#define TIC6X_MAX_FIXED_FIELDS 4 - -/* Maximum number of operands in the opcode table for a particular - opcode. */ -#define TIC6X_MAX_OPERANDS 4 - -/* Maximum number of operands in the source code for a particular - opcode (different from the number in the opcode table for SPMASK - and SPMASKR). */ -#define TIC6X_MAX_SOURCE_OPERANDS 8 - -/* Maximum number of variable fields for a particular opcode. */ -#define TIC6X_MAX_VAR_FIELDS 7 - -/* Which functional units an opcode uses. This only describes the - basic choice of D, L, M, S or no functional unit; other fields are - used to describe further restrictions (instructions only operating - on one side), use of cross paths and load/store instructions using - one side for the address and the other side for the source or - destination register. */ -typedef enum - { - tic6x_func_unit_d, - tic6x_func_unit_l, - tic6x_func_unit_m, - tic6x_func_unit_s, - tic6x_func_unit_nfu - } tic6x_func_unit_base; - -/* Possible forms of source operand. */ -typedef enum - { - /* An assembly-time constant. */ - tic6x_operand_asm_const, - /* A link-time constant. */ - tic6x_operand_link_const, - /* A register, from the same side as the functional unit - selected. */ - tic6x_operand_reg, - /* A register, from the same side as the functional unit - selected that ignore RS header bit */ - tic6x_operand_reg_nors, - /* A register, from the b side */ - tic6x_operand_reg_bside, - /* A register, from the b side and from the low register set */ - tic6x_operand_reg_bside_nors, - /* A register, that is from the other side if a cross path is - used. */ - tic6x_operand_xreg, - /* A register, that is from the side of the data path - selected. */ - tic6x_operand_dreg, - /* An address register usable with 15-bit offsets (B14 or B15). - This is from the same side as the functional unit if a cross - path is not used, and the other side if a cross path is - used. */ - tic6x_operand_areg, - /* The B15 register */ - tic6x_operand_b15reg, - /* A register coded as an offset from either A16 or B16 depending - on the value of the t bit. */ - tic6x_operand_treg, - /* A register (A0 or B0), from the same side as the - functional unit selected. */ - tic6x_operand_zreg, - /* A return address register (A3 or B3), from the same side as the - functional unit selected. */ - tic6x_operand_retreg, - /* A register pair, from the same side as the functional unit - selected. */ - tic6x_operand_regpair, - /* A register pair, that is from the other side if a cross path is - used. */ - tic6x_operand_xregpair, - /* A register pair, from the side of the data path selected. */ - tic6x_operand_dregpair, - /* A register pair coded as an offset from either A16 or B16 depending - on the value of the t bit. */ - tic6x_operand_tregpair, - /* The literal string "irp" (case-insensitive). */ - tic6x_operand_irp, - /* The literal string "nrp" (case-insensitive). */ - tic6x_operand_nrp, - /* The literal string "ilc" (case-insensitive). */ - tic6x_operand_ilc, - /* A control register. */ - tic6x_operand_ctrl, - /* A memory reference (base and offset registers from the side of - the functional unit selected), using either unsigned 5-bit - constant or register offset, if any offset; register offsets - cannot use unscaled () syntax. */ - tic6x_operand_mem_short, - /* A memory reference (base and offset registers from the side of - the functional unit selected), using either unsigned 5-bit - constant or register offset, if any offset; register offsets - can use unscaled () syntax (for LDNDW and STNDW). */ - tic6x_operand_mem_ndw, - /* A memory reference using 15-bit link-time constant offset - relative to B14 or B15. */ - tic6x_operand_mem_long, - /* A memory reference that only dereferences a register with no - further adjustments (*REG), that register being from the side - of the functional unit selected. */ - tic6x_operand_mem_deref, - /* A functional unit name or a list thereof (for SPMASK and - SPMASKR). */ - tic6x_operand_func_unit, - /* Hardwired constant '5' in Sbu8 Scs10 and Sbu8c 16 bits - instruction formats - spru732j.pdf Appendix F.4 */ - tic6x_operand_hw_const_minus_1, - tic6x_operand_hw_const_0, - tic6x_operand_hw_const_1, - tic6x_operand_hw_const_5, - tic6x_operand_hw_const_16, - tic6x_operand_hw_const_24, - tic6x_operand_hw_const_31 - } tic6x_operand_form; - -/* Whether something is, or can be, read or written. */ -typedef enum - { - tic6x_rw_none, - tic6x_rw_read, - tic6x_rw_write, - tic6x_rw_read_write - } tic6x_rw; - -/* Description of a source operand and how it is used. */ -typedef struct -{ - /* The syntactic form of the operand. */ - tic6x_operand_form form; - - /* For non-constant operands, the size in bytes (1, 2, 4, 5 or - 8). Ignored for constant operands. */ - unsigned int size; - - /* Whether the operand is read, written or both. In addition to the - operations described here, address registers are read on cycle 1 - regardless of when the memory operand is read or written, and may - be modified as described by the addressing mode, and control - registers may be implicitly read by some instructions. There are - also some special cases not fully described by this - structure. - - - For mpydp, the low part of src2 is read on cycles 1 and 3 but - not 2, and the high part on cycles 2 and 4 but not 3. - - - The swap2 pseudo-operation maps to packlh2, reading the first - operand of swap2 twice. */ - tic6x_rw rw; - - /* The first and last cycles (1 for E1, etc.) at which the operand, - or the low part for two-register operands, is read or - written. */ - unsigned short low_first; - unsigned short low_last; - - /* Likewise, for the high part. */ - unsigned short high_first; - unsigned short high_last; -} tic6x_operand_info; - -/* Ways of converting an operand or functional unit specifier to a - field value. */ -typedef enum - { - /* Store an unsigned assembly-time constant (which must fit) in - the field. */ - tic6x_coding_ucst, - /* Store a signed constant (which must fit) in the field. This - may be used both for assembly-time constants and for link-time - constants. */ - tic6x_coding_scst, - /* Subtract one from an unsigned assembly-time constant (which - must be strictly positive before the subtraction) and store the - value (which must fit) in the field. */ - tic6x_coding_ucst_minus_one, - /* Negate a signed assembly-time constant, and store the result of - negation (which must fit) in the field. Used only for - pseudo-operations. */ - tic6x_coding_scst_negate, - /* Store an unsigned link-time constant, implicitly DP-relative - and counting in bytes, in the field. For expression operands, - assembly-time constants are encoded as-is. For memory - reference operands, the offset is encoded as-is if [] syntax is - used and shifted if () is used. */ - tic6x_coding_ulcst_dpr_byte, - /* Store an unsigned link-time constant, implicitly DP-relative - and counting in half-words, in the field. For expression - operands, assembly-time constants are encoded as-is. For - memory reference operands, the offset is encoded as-is if [] - syntax is used and shifted if () is used. */ - tic6x_coding_ulcst_dpr_half, - /* Store an unsigned link-time constant, implicitly DP-relative - and counting in words, in the field. For expression operands, - assembly-time constants are encoded as-is. For memory - reference operands, the offset is encoded as-is if [] syntax is - used and shifted if () is used. */ - tic6x_coding_ulcst_dpr_word, - /* Store the low 16 bits of a link-time constant in the field; - considered unsigned for disassembly. */ - tic6x_coding_lcst_low16, - /* Store the high 16 bits of a link-time constant in the field; - considered unsigned for disassembly. */ - tic6x_coding_lcst_high16, - /* Store a signed PC-relative value (address of label minus - address of fetch packet containing the current instruction, - counted in words) in the field. */ - tic6x_coding_pcrel, - /* Likewise, but counting in half-words if in a header-based fetch - packet. */ - tic6x_coding_pcrel_half, - /* Store an unsigned PC-relative value used in compact insn */ - tic6x_coding_pcrel_half_unsigned, - /* Encode the register number (even number for a register pair) in - the field. When applied to a memory reference, encode the base - register. */ - tic6x_coding_reg, - /* Encode the register-pair's lsb (even register) for instructions - that use src1 as port for loading lsb of double-precision - operand value (absdp, dpint, dpsp, dptrunc, rcpdp, rsqrdp). */ - tic6x_coding_regpair_lsb, - /* Encode the register-pair's msb (odd register), see above. */ - tic6x_coding_regpair_msb, - /* Store 0 for register B14, 1 for register B15. When applied to - a memory reference, encode the base register. */ - tic6x_coding_areg, - /* Compact instruction offset base register */ - tic6x_coding_reg_ptr, - /* Store the low part of a control register address. */ - tic6x_coding_crlo, - /* Store the high part of a control register address. */ - tic6x_coding_crhi, - /* Encode the even register number for a register pair, shifted - right by one bit. */ - tic6x_coding_reg_shift, - /* Store either the offset register or the 5-bit unsigned offset - for a memory reference. If an offset uses the unscaled () - form, which is only permitted with constants, it is scaled - according to the access size of the operand before being - stored. */ - tic6x_coding_mem_offset, - /* Store either the offset register or the 5-bit unsigned offset - for a memory reference, but with no scaling applied to the - offset (for nonaligned doubleword operations). */ - tic6x_coding_mem_offset_noscale, - /* Store the addressing mode for a memory reference. */ - tic6x_coding_mem_mode, - /* Store whether a memory reference is scaled. */ - tic6x_coding_scaled, - /* Store the stage in an SPKERNEL instruction in the upper part of - the field. */ - tic6x_coding_fstg, - /* Store the cycle in an SPKERNEL instruction in the lower part of - the field. */ - tic6x_coding_fcyc, - /* Store the mask bits for functional units in the field in an - SPMASK or SPMASKR instruction. */ - tic6x_coding_spmask, - /* Store the number of a register that is unused, or minimally - used, in this execute packet. The number must be the same for - all uses of this coding in a single instruction, but may be - different for different instructions in the execute packet. - This is for the "zero" pseudo-operation. This is not safe when - reads may occur from instructions in previous execute packets; - in such cases the programmer or compiler should use explicit - "sub" instructions for those cases of "zero" that cannot be - implemented as "mvk" for the processor specified. */ - tic6x_coding_reg_unused, - /* Store 1 if the functional unit used is on side B, 0 for side - A. */ - tic6x_coding_fu, - /* Store 1 if the data path used (source register for store, - destination for load) is on side B, 0 for side A. */ - tic6x_coding_data_fu, - /* Store 1 if the cross path is being used, 0 otherwise. */ - tic6x_coding_xpath, - /* L3i constant coding */ - tic6x_coding_scst_l3i, - /* S3i constant coding */ - tic6x_coding_cst_s3i, - /* mem offset minus 1 */ - tic6x_coding_mem_offset_minus_one, - /* non aligned mem offset minus 1 */ - tic6x_coding_mem_offset_minus_one_noscale, - tic6x_coding_rside - } tic6x_coding_method; - -/* How to generate the value of a particular field. */ -typedef struct -{ - /* The name of the field. */ - tic6x_insn_field_id field_id; - - /* How it is encoded. */ - tic6x_coding_method coding_method; - - /* Source operand number, if any. */ - unsigned int operand_num; -} tic6x_coding_field; - -/* Types of instruction for pipeline purposes. The type determines - functional unit and cross path latency (when the same functional - unit can be used by other instructions, when the same cross path - can be used by other instructions). */ -typedef enum - { - tic6x_pipeline_nop, - tic6x_pipeline_1cycle, - tic6x_pipeline_1616_m, - tic6x_pipeline_store, - tic6x_pipeline_mul_ext, - tic6x_pipeline_load, - tic6x_pipeline_branch, - tic6x_pipeline_2cycle_dp, - tic6x_pipeline_4cycle, - tic6x_pipeline_intdp, - tic6x_pipeline_dpcmp, - tic6x_pipeline_addsubdp, - tic6x_pipeline_mpyi, - tic6x_pipeline_mpyid, - tic6x_pipeline_mpydp, - tic6x_pipeline_mpyspdp, - tic6x_pipeline_mpysp2dp - } tic6x_pipeline_type; - -/* Description of a control register. */ -typedef struct -{ - /* The name of the register. */ - const char *name; - - /* Which ISA variants include this control register. */ - unsigned short isa_variants; - - /* Whether it can be read, written or both (in supervisor mode). - Some registers use the same address, but different names, for - reading and writing. */ - tic6x_rw rw; - - /* crlo value for this register. */ - unsigned int crlo; - - /* Mask that, ANDed with the crhi value in the instruction, must be - 0. 0 is always generated when generating code. */ - unsigned int crhi_mask; -} tic6x_ctrl; - -/* An index into the table of control registers. */ -typedef enum - { -#define CTRL(name, isa, rw, crlo, crhi_mask) \ - CONCAT2(tic6x_ctrl_,name), -#include "tic6x-control-registers.h" -#undef CTRL - tic6x_ctrl_max - } tic6x_ctrl_id; - -/* The table itself. */ -extern const tic6x_ctrl tic6x_ctrl_table[tic6x_ctrl_max]; - -/* An entry in the opcode table. */ -typedef struct -{ - /* The name of the instruction. */ - const char *name; - - /* Functional unit used by this instruction (basic information). */ - tic6x_func_unit_base func_unit; - - /* The format of this instruction. */ - tic6x_insn_format_id format; - - /* The pipeline type of this instruction. */ - tic6x_pipeline_type type; - - /* Which ISA variants include this instruction. */ - unsigned short isa_variants; - - /* Flags for this instruction. */ - unsigned int flags; - - /* Number of fixed fields, or fields with restricted value ranges, - for this instruction. */ - unsigned int num_fixed_fields; - - /* Values of fields fixed for this instruction. */ - tic6x_fixed_field fixed_fields[TIC6X_MAX_FIXED_FIELDS]; - - /* The number of operands in the source form of this - instruction. */ - unsigned int num_operands; - - /* Information about individual operands. */ - tic6x_operand_info operand_info[TIC6X_MAX_OPERANDS]; - - /* The number of variable fields for this instruction with encoding - instructions explicitly given. */ - unsigned int num_variable_fields; - - /* How fields (other than ones with fixed value) are computed from - the source operands and functional unit specifiers. In addition - to fields specified here: - - - creg, if present, is set from the predicate, along with z which - must be present if creg is present. - - - p, if present (on all non-compact instructions), is set from - the parallel bars. - */ - tic6x_coding_field variable_fields[TIC6X_MAX_VAR_FIELDS]; -} tic6x_opcode; - -/* An index into the table of opcodes. */ -typedef enum - { -#define INSN(name, func_unit, format, type, isa, flags, fixed, ops, var) \ - CONCAT6(tic6x_opcode_,name,_,func_unit,_,format), -#define INSNE(name, e, func_unit, format, type, isa, flags, fixed, ops, var) \ - CONCAT4(tic6x_opcode_,name,_,e), -#define INSNU(name, func_unit, format, type, isa, flags, fixed, ops, var) \ - CONCAT6(tic6x_opcode_,name,_,func_unit,_,format), -#define INSNUE(name, e, func_unit, format, type, isa, flags, fixed, ops, var) \ - CONCAT6(tic6x_opcode_,name,_,func_unit,_,e), -#include "tic6x-opcode-table.h" -#undef INSN -#undef INSNE -#undef INSNU -#undef INSNUE - tic6x_opcode_max - } tic6x_opcode_id; - -/* The table itself. */ -extern const tic6x_opcode tic6x_opcode_table[tic6x_opcode_max]; - -/* A linked list of opcodes. */ -typedef struct tic6x_opcode_list_tag -{ - tic6x_opcode_id id; - struct tic6x_opcode_list_tag *next; -} tic6x_opcode_list; - -/* The information from a fetch packet header. */ -typedef struct -{ - /* The header itself. */ - unsigned int header; - - /* Whether each word uses compact instructions. */ - bfd_boolean word_compact[7]; - - /* Whether loads are protected. */ - bfd_boolean prot; - - /* Whether instructions use the high register set. */ - bfd_boolean rs; - - /* Data size. */ - unsigned int dsz; - - /* Whether compact instructions in the S unit are decoded as - branches. */ - bfd_boolean br; - - /* Whether compact instructions saturate. */ - bfd_boolean sat; - - /* P-bits. */ - bfd_boolean p_bits[14]; -} tic6x_fetch_packet_header; - -#endif /* OPCODE_TIC6X_H */ diff --git a/include/opcode/tic80.h b/include/opcode/tic80.h deleted file mode 100644 index 43c84be..0000000 --- a/include/opcode/tic80.h +++ /dev/null @@ -1,283 +0,0 @@ -/* tic80.h -- Header file for TI TMS320C80 (MV) opcode table - Copyright 1996, 1997, 2003, 2010 Free Software Foundation, Inc. - Written by Fred Fish (fnf@cygnus.com), Cygnus Support - - This file is part of GDB, GAS, and the GNU binutils. - - GDB, GAS, and the GNU binutils are free software; you can redistribute - them and/or modify them under the terms of the GNU General Public - License as published by the Free Software Foundation; either version 3, - or (at your option) any later version. - - GDB, GAS, and the GNU binutils are distributed in the hope that they - will be useful, but WITHOUT ANY WARRANTY; without even the implied - warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See - the GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this file; see the file COPYING3. If not, write to the Free - Software Foundation, 51 Franklin Street - Fifth Floor, Boston, - MA 02110-1301, USA. */ - -#ifndef TIC80_H -#define TIC80_H - -/* The opcode table is an array of struct tic80_opcode. */ - -struct tic80_opcode -{ - /* The opcode name. */ - - const char *name; - - /* The opcode itself. Those bits which will be filled in with operands - are zeroes. */ - - unsigned long opcode; - - /* The opcode mask. This is used by the disassembler. This is a mask - containing ones indicating those bits which must match the opcode - field, and zeroes indicating those bits which need not match (and are - presumably filled in by operands). */ - - unsigned long mask; - - /* Special purpose flags for this opcode. */ - - unsigned char flags; - - /* An array of operand codes. Each code is an index into the operand - table. They appear in the order which the operands must appear in - assembly code, and are terminated by a zero. FIXME: Adjust size to - match actual requirements when TIc80 support is complete */ - - unsigned char operands[8]; -}; - -/* The table itself is sorted by major opcode number, and is otherwise in - the order in which the disassembler should consider instructions. - FIXME: This isn't currently true. */ - -extern const struct tic80_opcode tic80_opcodes[]; -extern const int tic80_num_opcodes; - - -/* The operands table is an array of struct tic80_operand. */ - -struct tic80_operand -{ - /* The number of bits in the operand. */ - - int bits; - - /* How far the operand is left shifted in the instruction. */ - - int shift; - - /* Insertion function. This is used by the assembler. To insert an - operand value into an instruction, check this field. - - If it is NULL, execute - i |= (op & ((1 << o->bits) - 1)) << o->shift; - (i is the instruction which we are filling in, o is a pointer to - this structure, and op is the opcode value; this assumes twos - complement arithmetic). - - If this field is not NULL, then simply call it with the - instruction and the operand value. It will return the new value - of the instruction. If the ERRMSG argument is not NULL, then if - the operand value is illegal, *ERRMSG will be set to a warning - string (the operand will be inserted in any case). If the - operand value is legal, *ERRMSG will be unchanged (most operands - can accept any value). */ - - unsigned long (*insert) - (unsigned long instruction, long op, const char **errmsg); - - /* Extraction function. This is used by the disassembler. To - extract this operand type from an instruction, check this field. - - If it is NULL, compute - op = ((i) >> o->shift) & ((1 << o->bits) - 1); - if ((o->flags & TIC80_OPERAND_SIGNED) != 0 - && (op & (1 << (o->bits - 1))) != 0) - op -= 1 << o->bits; - (i is the instruction, o is a pointer to this structure, and op - is the result; this assumes twos complement arithmetic). - - If this field is not NULL, then simply call it with the - instruction value. It will return the value of the operand. If - the INVALID argument is not NULL, *INVALID will be set to - non-zero if this operand type can not actually be extracted from - this operand (i.e., the instruction does not match). If the - operand is valid, *INVALID will not be changed. */ - - long (*extract) (unsigned long instruction, int *invalid); - - /* One bit syntax flags. */ - - unsigned long flags; -}; - -/* Elements in the table are retrieved by indexing with values from - the operands field of the tic80_opcodes table. */ - -extern const struct tic80_operand tic80_operands[]; - - -/* Values defined for the flags field of a struct tic80_operand. - - Note that flags for all predefined symbols, such as the general purpose - registers (ex: r10), control registers (ex: FPST), condition codes (ex: - eq0.b), bit numbers (ex: gt.b), etc are large enough that they can be - or'd into an int where the lower bits contain the actual numeric value - that correponds to this predefined symbol. This way a single int can - contain both the value of the symbol and it's type. - */ - -/* This operand must be an even register number. Floating point numbers - for example are stored in even/odd register pairs. */ - -#define TIC80_OPERAND_EVEN (1 << 0) - -/* This operand must be an odd register number and must be one greater than - the register number of the previous operand. I.E. the second register in - an even/odd register pair. */ - -#define TIC80_OPERAND_ODD (1 << 1) - -/* This operand takes signed values. */ - -#define TIC80_OPERAND_SIGNED (1 << 2) - -/* This operand may be either a predefined constant name or a numeric value. - An example would be a condition code like "eq0.b" which has the numeric - value 0x2. */ - -#define TIC80_OPERAND_NUM (1 << 3) - -/* This operand should be wrapped in parentheses rather than separated - from the previous one by a comma. This is used for various - instructions, like the load and store instructions, which want - their operands to look like "displacement(reg)" */ - -#define TIC80_OPERAND_PARENS (1 << 4) - -/* This operand is a PC relative branch offset. The disassembler prints - these symbolically if possible. Note that the offsets are taken as word - offsets. */ - -#define TIC80_OPERAND_PCREL (1 << 5) - -/* This flag is a hint to the disassembler for using hex as the prefered - printing format, even for small positive or negative immediate values. - Normally values in the range -999 to 999 are printed as signed decimal - values and other values are printed in hex. */ - -#define TIC80_OPERAND_BITFIELD (1 << 6) - -/* This operand may have a ":m" modifier specified by bit 17 in a short - immediate form instruction. */ - -#define TIC80_OPERAND_M_SI (1 << 7) - -/* This operand may have a ":m" modifier specified by bit 15 in a long - immediate or register form instruction. */ - -#define TIC80_OPERAND_M_LI (1 << 8) - -/* This operand may have a ":s" modifier specified in bit 11 in a long - immediate or register form instruction. */ - -#define TIC80_OPERAND_SCALED (1 << 9) - -/* This operand is a floating point value */ - -#define TIC80_OPERAND_FLOAT (1 << 10) - -/* This operand is an byte offset from a base relocation. The lower - two bits of the final relocated address are ignored when the value is - written to the program counter. */ - -#define TIC80_OPERAND_BASEREL (1 << 11) - -/* This operand is an "endmask" field for a shift instruction. - It is treated special in that it can have values of 0-32, - where 0 and 32 result in the same instruction. The assembler - must be able to accept both endmask values. This disassembler - has no way of knowing from the instruction which value was - given at assembly time, so it just uses '0'. */ - -#define TIC80_OPERAND_ENDMASK (1 << 12) - -/* This operand is one of the 32 general purpose registers. - The disassembler prints these with a leading 'r'. */ - -#define TIC80_OPERAND_GPR (1 << 27) - -/* This operand is a floating point accumulator register. - The disassembler prints these with a leading 'a'. */ - -#define TIC80_OPERAND_FPA ( 1 << 28) - -/* This operand is a control register number, either numeric or - symbolic (like "EIF", "EPC", etc). - The disassembler prints these symbolically. */ - -#define TIC80_OPERAND_CR (1 << 29) - -/* This operand is a condition code, either numeric or - symbolic (like "eq0.b", "ne0.w", etc). - The disassembler prints these symbolically. */ - -#define TIC80_OPERAND_CC (1 << 30) - -/* This operand is a bit number, either numeric or - symbolic (like "eq.b", "or.f", etc). - The disassembler prints these symbolically. - Note that they appear in the instruction in 1's complement relative - to the values given in the manual. */ - -#define TIC80_OPERAND_BITNUM (1 << 31) - -/* This mask is used to strip operand bits from an int that contains - both operand bits and a numeric value in the lsbs. */ - -#define TIC80_OPERAND_MASK (TIC80_OPERAND_GPR | TIC80_OPERAND_FPA | TIC80_OPERAND_CR | TIC80_OPERAND_CC | TIC80_OPERAND_BITNUM) - - -/* Flag bits for the struct tic80_opcode flags field. */ - -#define TIC80_VECTOR 01 /* Is a vector instruction */ -#define TIC80_NO_R0_DEST 02 /* Register r0 cannot be a destination register */ - - -/* The opcodes library contains a table that allows translation from predefined - symbol names to numeric values, and vice versa. */ - -/* Structure to hold information about predefined symbols. */ - -struct predefined_symbol -{ - char *name; /* name to recognize */ - int value; -}; - -#define PDS_NAME(pdsp) ((pdsp) -> name) -#define PDS_VALUE(pdsp) ((pdsp) -> value) - -/* Translation array. */ -extern const struct predefined_symbol tic80_predefined_symbols[]; -/* How many members in the array. */ -extern const int tic80_num_predefined_symbols; - -/* Translate value to symbolic name. */ -const char *tic80_value_to_symbol (int val, int class); - -/* Translate symbolic name to value. */ -int tic80_symbol_to_value (char *name, int class); - -const struct predefined_symbol *tic80_next_predefined_symbol - (const struct predefined_symbol *); - -#endif /* TIC80_H */ diff --git a/include/opcode/tilegx.h b/include/opcode/tilegx.h deleted file mode 100644 index c11fc16..0000000 --- a/include/opcode/tilegx.h +++ /dev/null @@ -1,1304 +0,0 @@ -/* TILE-Gx opcode information. - * - * Copyright 2011 Free Software Foundation, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -#ifndef opcode_tile_h -#define opcode_tile_h - -typedef unsigned long long tilegx_bundle_bits; - - -enum -{ - TILEGX_MAX_OPERANDS = 4 /* bfexts */ -}; - -typedef enum -{ - TILEGX_OPC_BPT, - TILEGX_OPC_INFO, - TILEGX_OPC_INFOL, - TILEGX_OPC_LD4S_TLS, - TILEGX_OPC_LD_TLS, - TILEGX_OPC_MOVE, - TILEGX_OPC_MOVEI, - TILEGX_OPC_MOVELI, - TILEGX_OPC_PREFETCH, - TILEGX_OPC_PREFETCH_ADD_L1, - TILEGX_OPC_PREFETCH_ADD_L1_FAULT, - TILEGX_OPC_PREFETCH_ADD_L2, - TILEGX_OPC_PREFETCH_ADD_L2_FAULT, - TILEGX_OPC_PREFETCH_ADD_L3, - TILEGX_OPC_PREFETCH_ADD_L3_FAULT, - TILEGX_OPC_PREFETCH_L1, - TILEGX_OPC_PREFETCH_L1_FAULT, - TILEGX_OPC_PREFETCH_L2, - TILEGX_OPC_PREFETCH_L2_FAULT, - TILEGX_OPC_PREFETCH_L3, - TILEGX_OPC_PREFETCH_L3_FAULT, - TILEGX_OPC_RAISE, - TILEGX_OPC_ADD, - TILEGX_OPC_ADDI, - TILEGX_OPC_ADDLI, - TILEGX_OPC_ADDX, - TILEGX_OPC_ADDXI, - TILEGX_OPC_ADDXLI, - TILEGX_OPC_ADDXSC, - TILEGX_OPC_AND, - TILEGX_OPC_ANDI, - TILEGX_OPC_BEQZ, - TILEGX_OPC_BEQZT, - TILEGX_OPC_BFEXTS, - TILEGX_OPC_BFEXTU, - TILEGX_OPC_BFINS, - TILEGX_OPC_BGEZ, - TILEGX_OPC_BGEZT, - TILEGX_OPC_BGTZ, - TILEGX_OPC_BGTZT, - TILEGX_OPC_BLBC, - TILEGX_OPC_BLBCT, - TILEGX_OPC_BLBS, - TILEGX_OPC_BLBST, - TILEGX_OPC_BLEZ, - TILEGX_OPC_BLEZT, - TILEGX_OPC_BLTZ, - TILEGX_OPC_BLTZT, - TILEGX_OPC_BNEZ, - TILEGX_OPC_BNEZT, - TILEGX_OPC_CLZ, - TILEGX_OPC_CMOVEQZ, - TILEGX_OPC_CMOVNEZ, - TILEGX_OPC_CMPEQ, - TILEGX_OPC_CMPEQI, - TILEGX_OPC_CMPEXCH, - TILEGX_OPC_CMPEXCH4, - TILEGX_OPC_CMPLES, - TILEGX_OPC_CMPLEU, - TILEGX_OPC_CMPLTS, - TILEGX_OPC_CMPLTSI, - TILEGX_OPC_CMPLTU, - TILEGX_OPC_CMPLTUI, - TILEGX_OPC_CMPNE, - TILEGX_OPC_CMUL, - TILEGX_OPC_CMULA, - TILEGX_OPC_CMULAF, - TILEGX_OPC_CMULF, - TILEGX_OPC_CMULFR, - TILEGX_OPC_CMULH, - TILEGX_OPC_CMULHR, - TILEGX_OPC_CRC32_32, - TILEGX_OPC_CRC32_8, - TILEGX_OPC_CTZ, - TILEGX_OPC_DBLALIGN, - TILEGX_OPC_DBLALIGN2, - TILEGX_OPC_DBLALIGN4, - TILEGX_OPC_DBLALIGN6, - TILEGX_OPC_DRAIN, - TILEGX_OPC_DTLBPR, - TILEGX_OPC_EXCH, - TILEGX_OPC_EXCH4, - TILEGX_OPC_FDOUBLE_ADD_FLAGS, - TILEGX_OPC_FDOUBLE_ADDSUB, - TILEGX_OPC_FDOUBLE_MUL_FLAGS, - TILEGX_OPC_FDOUBLE_PACK1, - TILEGX_OPC_FDOUBLE_PACK2, - TILEGX_OPC_FDOUBLE_SUB_FLAGS, - TILEGX_OPC_FDOUBLE_UNPACK_MAX, - TILEGX_OPC_FDOUBLE_UNPACK_MIN, - TILEGX_OPC_FETCHADD, - TILEGX_OPC_FETCHADD4, - TILEGX_OPC_FETCHADDGEZ, - TILEGX_OPC_FETCHADDGEZ4, - TILEGX_OPC_FETCHAND, - TILEGX_OPC_FETCHAND4, - TILEGX_OPC_FETCHOR, - TILEGX_OPC_FETCHOR4, - TILEGX_OPC_FINV, - TILEGX_OPC_FLUSH, - TILEGX_OPC_FLUSHWB, - TILEGX_OPC_FNOP, - TILEGX_OPC_FSINGLE_ADD1, - TILEGX_OPC_FSINGLE_ADDSUB2, - TILEGX_OPC_FSINGLE_MUL1, - TILEGX_OPC_FSINGLE_MUL2, - TILEGX_OPC_FSINGLE_PACK1, - TILEGX_OPC_FSINGLE_PACK2, - TILEGX_OPC_FSINGLE_SUB1, - TILEGX_OPC_ICOH, - TILEGX_OPC_ILL, - TILEGX_OPC_INV, - TILEGX_OPC_IRET, - TILEGX_OPC_J, - TILEGX_OPC_JAL, - TILEGX_OPC_JALR, - TILEGX_OPC_JALRP, - TILEGX_OPC_JR, - TILEGX_OPC_JRP, - TILEGX_OPC_LD, - TILEGX_OPC_LD1S, - TILEGX_OPC_LD1S_ADD, - TILEGX_OPC_LD1U, - TILEGX_OPC_LD1U_ADD, - TILEGX_OPC_LD2S, - TILEGX_OPC_LD2S_ADD, - TILEGX_OPC_LD2U, - TILEGX_OPC_LD2U_ADD, - TILEGX_OPC_LD4S, - TILEGX_OPC_LD4S_ADD, - TILEGX_OPC_LD4U, - TILEGX_OPC_LD4U_ADD, - TILEGX_OPC_LD_ADD, - TILEGX_OPC_LDNA, - TILEGX_OPC_LDNA_ADD, - TILEGX_OPC_LDNT, - TILEGX_OPC_LDNT1S, - TILEGX_OPC_LDNT1S_ADD, - TILEGX_OPC_LDNT1U, - TILEGX_OPC_LDNT1U_ADD, - TILEGX_OPC_LDNT2S, - TILEGX_OPC_LDNT2S_ADD, - TILEGX_OPC_LDNT2U, - TILEGX_OPC_LDNT2U_ADD, - TILEGX_OPC_LDNT4S, - TILEGX_OPC_LDNT4S_ADD, - TILEGX_OPC_LDNT4U, - TILEGX_OPC_LDNT4U_ADD, - TILEGX_OPC_LDNT_ADD, - TILEGX_OPC_LNK, - TILEGX_OPC_MF, - TILEGX_OPC_MFSPR, - TILEGX_OPC_MM, - TILEGX_OPC_MNZ, - TILEGX_OPC_MTSPR, - TILEGX_OPC_MUL_HS_HS, - TILEGX_OPC_MUL_HS_HU, - TILEGX_OPC_MUL_HS_LS, - TILEGX_OPC_MUL_HS_LU, - TILEGX_OPC_MUL_HU_HU, - TILEGX_OPC_MUL_HU_LS, - TILEGX_OPC_MUL_HU_LU, - TILEGX_OPC_MUL_LS_LS, - TILEGX_OPC_MUL_LS_LU, - TILEGX_OPC_MUL_LU_LU, - TILEGX_OPC_MULA_HS_HS, - TILEGX_OPC_MULA_HS_HU, - TILEGX_OPC_MULA_HS_LS, - TILEGX_OPC_MULA_HS_LU, - TILEGX_OPC_MULA_HU_HU, - TILEGX_OPC_MULA_HU_LS, - TILEGX_OPC_MULA_HU_LU, - TILEGX_OPC_MULA_LS_LS, - TILEGX_OPC_MULA_LS_LU, - TILEGX_OPC_MULA_LU_LU, - TILEGX_OPC_MULAX, - TILEGX_OPC_MULX, - TILEGX_OPC_MZ, - TILEGX_OPC_NAP, - TILEGX_OPC_NOP, - TILEGX_OPC_NOR, - TILEGX_OPC_OR, - TILEGX_OPC_ORI, - TILEGX_OPC_PCNT, - TILEGX_OPC_REVBITS, - TILEGX_OPC_REVBYTES, - TILEGX_OPC_ROTL, - TILEGX_OPC_ROTLI, - TILEGX_OPC_SHL, - TILEGX_OPC_SHL16INSLI, - TILEGX_OPC_SHL1ADD, - TILEGX_OPC_SHL1ADDX, - TILEGX_OPC_SHL2ADD, - TILEGX_OPC_SHL2ADDX, - TILEGX_OPC_SHL3ADD, - TILEGX_OPC_SHL3ADDX, - TILEGX_OPC_SHLI, - TILEGX_OPC_SHLX, - TILEGX_OPC_SHLXI, - TILEGX_OPC_SHRS, - TILEGX_OPC_SHRSI, - TILEGX_OPC_SHRU, - TILEGX_OPC_SHRUI, - TILEGX_OPC_SHRUX, - TILEGX_OPC_SHRUXI, - TILEGX_OPC_SHUFFLEBYTES, - TILEGX_OPC_ST, - TILEGX_OPC_ST1, - TILEGX_OPC_ST1_ADD, - TILEGX_OPC_ST2, - TILEGX_OPC_ST2_ADD, - TILEGX_OPC_ST4, - TILEGX_OPC_ST4_ADD, - TILEGX_OPC_ST_ADD, - TILEGX_OPC_STNT, - TILEGX_OPC_STNT1, - TILEGX_OPC_STNT1_ADD, - TILEGX_OPC_STNT2, - TILEGX_OPC_STNT2_ADD, - TILEGX_OPC_STNT4, - TILEGX_OPC_STNT4_ADD, - TILEGX_OPC_STNT_ADD, - TILEGX_OPC_SUB, - TILEGX_OPC_SUBX, - TILEGX_OPC_SUBXSC, - TILEGX_OPC_SWINT0, - TILEGX_OPC_SWINT1, - TILEGX_OPC_SWINT2, - TILEGX_OPC_SWINT3, - TILEGX_OPC_TBLIDXB0, - TILEGX_OPC_TBLIDXB1, - TILEGX_OPC_TBLIDXB2, - TILEGX_OPC_TBLIDXB3, - TILEGX_OPC_V1ADD, - TILEGX_OPC_V1ADDI, - TILEGX_OPC_V1ADDUC, - TILEGX_OPC_V1ADIFFU, - TILEGX_OPC_V1AVGU, - TILEGX_OPC_V1CMPEQ, - TILEGX_OPC_V1CMPEQI, - TILEGX_OPC_V1CMPLES, - TILEGX_OPC_V1CMPLEU, - TILEGX_OPC_V1CMPLTS, - TILEGX_OPC_V1CMPLTSI, - TILEGX_OPC_V1CMPLTU, - TILEGX_OPC_V1CMPLTUI, - TILEGX_OPC_V1CMPNE, - TILEGX_OPC_V1DDOTPU, - TILEGX_OPC_V1DDOTPUA, - TILEGX_OPC_V1DDOTPUS, - TILEGX_OPC_V1DDOTPUSA, - TILEGX_OPC_V1DOTP, - TILEGX_OPC_V1DOTPA, - TILEGX_OPC_V1DOTPU, - TILEGX_OPC_V1DOTPUA, - TILEGX_OPC_V1DOTPUS, - TILEGX_OPC_V1DOTPUSA, - TILEGX_OPC_V1INT_H, - TILEGX_OPC_V1INT_L, - TILEGX_OPC_V1MAXU, - TILEGX_OPC_V1MAXUI, - TILEGX_OPC_V1MINU, - TILEGX_OPC_V1MINUI, - TILEGX_OPC_V1MNZ, - TILEGX_OPC_V1MULTU, - TILEGX_OPC_V1MULU, - TILEGX_OPC_V1MULUS, - TILEGX_OPC_V1MZ, - TILEGX_OPC_V1SADAU, - TILEGX_OPC_V1SADU, - TILEGX_OPC_V1SHL, - TILEGX_OPC_V1SHLI, - TILEGX_OPC_V1SHRS, - TILEGX_OPC_V1SHRSI, - TILEGX_OPC_V1SHRU, - TILEGX_OPC_V1SHRUI, - TILEGX_OPC_V1SUB, - TILEGX_OPC_V1SUBUC, - TILEGX_OPC_V2ADD, - TILEGX_OPC_V2ADDI, - TILEGX_OPC_V2ADDSC, - TILEGX_OPC_V2ADIFFS, - TILEGX_OPC_V2AVGS, - TILEGX_OPC_V2CMPEQ, - TILEGX_OPC_V2CMPEQI, - TILEGX_OPC_V2CMPLES, - TILEGX_OPC_V2CMPLEU, - TILEGX_OPC_V2CMPLTS, - TILEGX_OPC_V2CMPLTSI, - TILEGX_OPC_V2CMPLTU, - TILEGX_OPC_V2CMPLTUI, - TILEGX_OPC_V2CMPNE, - TILEGX_OPC_V2DOTP, - TILEGX_OPC_V2DOTPA, - TILEGX_OPC_V2INT_H, - TILEGX_OPC_V2INT_L, - TILEGX_OPC_V2MAXS, - TILEGX_OPC_V2MAXSI, - TILEGX_OPC_V2MINS, - TILEGX_OPC_V2MINSI, - TILEGX_OPC_V2MNZ, - TILEGX_OPC_V2MULFSC, - TILEGX_OPC_V2MULS, - TILEGX_OPC_V2MULTS, - TILEGX_OPC_V2MZ, - TILEGX_OPC_V2PACKH, - TILEGX_OPC_V2PACKL, - TILEGX_OPC_V2PACKUC, - TILEGX_OPC_V2SADAS, - TILEGX_OPC_V2SADAU, - TILEGX_OPC_V2SADS, - TILEGX_OPC_V2SADU, - TILEGX_OPC_V2SHL, - TILEGX_OPC_V2SHLI, - TILEGX_OPC_V2SHLSC, - TILEGX_OPC_V2SHRS, - TILEGX_OPC_V2SHRSI, - TILEGX_OPC_V2SHRU, - TILEGX_OPC_V2SHRUI, - TILEGX_OPC_V2SUB, - TILEGX_OPC_V2SUBSC, - TILEGX_OPC_V4ADD, - TILEGX_OPC_V4ADDSC, - TILEGX_OPC_V4INT_H, - TILEGX_OPC_V4INT_L, - TILEGX_OPC_V4PACKSC, - TILEGX_OPC_V4SHL, - TILEGX_OPC_V4SHLSC, - TILEGX_OPC_V4SHRS, - TILEGX_OPC_V4SHRU, - TILEGX_OPC_V4SUB, - TILEGX_OPC_V4SUBSC, - TILEGX_OPC_WH64, - TILEGX_OPC_XOR, - TILEGX_OPC_XORI, - TILEGX_OPC_NONE -} tilegx_mnemonic; - -/* 64-bit pattern for a { bpt ; nop } bundle. */ -#define TILEGX_BPT_BUNDLE 0x286a44ae51485000ULL - - - -static __inline unsigned int -get_BFEnd_X0(tilegx_bundle_bits num) -{ - const unsigned int n = (unsigned int)num; - return (((n >> 12)) & 0x3f); -} - -static __inline unsigned int -get_BFOpcodeExtension_X0(tilegx_bundle_bits num) -{ - const unsigned int n = (unsigned int)num; - return (((n >> 24)) & 0xf); -} - -static __inline unsigned int -get_BFStart_X0(tilegx_bundle_bits num) -{ - const unsigned int n = (unsigned int)num; - return (((n >> 18)) & 0x3f); -} - -static __inline unsigned int -get_BrOff_X1(tilegx_bundle_bits n) -{ - return (((unsigned int)(n >> 31)) & 0x0000003f) | - (((unsigned int)(n >> 37)) & 0x0001ffc0); -} - -static __inline unsigned int -get_BrType_X1(tilegx_bundle_bits n) -{ - return (((unsigned int)(n >> 54)) & 0x1f); -} - -static __inline unsigned int -get_Dest_Imm8_X1(tilegx_bundle_bits n) -{ - return (((unsigned int)(n >> 31)) & 0x0000003f) | - (((unsigned int)(n >> 43)) & 0x000000c0); -} - -static __inline unsigned int -get_Dest_X0(tilegx_bundle_bits num) -{ - const unsigned int n = (unsigned int)num; - return (((n >> 0)) & 0x3f); -} - -static __inline unsigned int -get_Dest_X1(tilegx_bundle_bits n) -{ - return (((unsigned int)(n >> 31)) & 0x3f); -} - -static __inline unsigned int -get_Dest_Y0(tilegx_bundle_bits num) -{ - const unsigned int n = (unsigned int)num; - return (((n >> 0)) & 0x3f); -} - -static __inline unsigned int -get_Dest_Y1(tilegx_bundle_bits n) -{ - return (((unsigned int)(n >> 31)) & 0x3f); -} - -static __inline unsigned int -get_Imm16_X0(tilegx_bundle_bits num) -{ - const unsigned int n = (unsigned int)num; - return (((n >> 12)) & 0xffff); -} - -static __inline unsigned int -get_Imm16_X1(tilegx_bundle_bits n) -{ - return (((unsigned int)(n >> 43)) & 0xffff); -} - -static __inline unsigned int -get_Imm8OpcodeExtension_X0(tilegx_bundle_bits num) -{ - const unsigned int n = (unsigned int)num; - return (((n >> 20)) & 0xff); -} - -static __inline unsigned int -get_Imm8OpcodeExtension_X1(tilegx_bundle_bits n) -{ - return (((unsigned int)(n >> 51)) & 0xff); -} - -static __inline unsigned int -get_Imm8_X0(tilegx_bundle_bits num) -{ - const unsigned int n = (unsigned int)num; - return (((n >> 12)) & 0xff); -} - -static __inline unsigned int -get_Imm8_X1(tilegx_bundle_bits n) -{ - return (((unsigned int)(n >> 43)) & 0xff); -} - -static __inline unsigned int -get_Imm8_Y0(tilegx_bundle_bits num) -{ - const unsigned int n = (unsigned int)num; - return (((n >> 12)) & 0xff); -} - -static __inline unsigned int -get_Imm8_Y1(tilegx_bundle_bits n) -{ - return (((unsigned int)(n >> 43)) & 0xff); -} - -static __inline unsigned int -get_JumpOff_X1(tilegx_bundle_bits n) -{ - return (((unsigned int)(n >> 31)) & 0x7ffffff); -} - -static __inline unsigned int -get_JumpOpcodeExtension_X1(tilegx_bundle_bits n) -{ - return (((unsigned int)(n >> 58)) & 0x1); -} - -static __inline unsigned int -get_MF_Imm14_X1(tilegx_bundle_bits n) -{ - return (((unsigned int)(n >> 37)) & 0x3fff); -} - -static __inline unsigned int -get_MT_Imm14_X1(tilegx_bundle_bits n) -{ - return (((unsigned int)(n >> 31)) & 0x0000003f) | - (((unsigned int)(n >> 37)) & 0x00003fc0); -} - -static __inline unsigned int -get_Mode(tilegx_bundle_bits n) -{ - return (((unsigned int)(n >> 62)) & 0x3); -} - -static __inline unsigned int -get_Opcode_X0(tilegx_bundle_bits num) -{ - const unsigned int n = (unsigned int)num; - return (((n >> 28)) & 0x7); -} - -static __inline unsigned int -get_Opcode_X1(tilegx_bundle_bits n) -{ - return (((unsigned int)(n >> 59)) & 0x7); -} - -static __inline unsigned int -get_Opcode_Y0(tilegx_bundle_bits num) -{ - const unsigned int n = (unsigned int)num; - return (((n >> 27)) & 0xf); -} - -static __inline unsigned int -get_Opcode_Y1(tilegx_bundle_bits n) -{ - return (((unsigned int)(n >> 58)) & 0xf); -} - -static __inline unsigned int -get_Opcode_Y2(tilegx_bundle_bits n) -{ - return (((n >> 26)) & 0x00000001) | - (((unsigned int)(n >> 56)) & 0x00000002); -} - -static __inline unsigned int -get_RRROpcodeExtension_X0(tilegx_bundle_bits num) -{ - const unsigned int n = (unsigned int)num; - return (((n >> 18)) & 0x3ff); -} - -static __inline unsigned int -get_RRROpcodeExtension_X1(tilegx_bundle_bits n) -{ - return (((unsigned int)(n >> 49)) & 0x3ff); -} - -static __inline unsigned int -get_RRROpcodeExtension_Y0(tilegx_bundle_bits num) -{ - const unsigned int n = (unsigned int)num; - return (((n >> 18)) & 0x3); -} - -static __inline unsigned int -get_RRROpcodeExtension_Y1(tilegx_bundle_bits n) -{ - return (((unsigned int)(n >> 49)) & 0x3); -} - -static __inline unsigned int -get_ShAmt_X0(tilegx_bundle_bits num) -{ - const unsigned int n = (unsigned int)num; - return (((n >> 12)) & 0x3f); -} - -static __inline unsigned int -get_ShAmt_X1(tilegx_bundle_bits n) -{ - return (((unsigned int)(n >> 43)) & 0x3f); -} - -static __inline unsigned int -get_ShAmt_Y0(tilegx_bundle_bits num) -{ - const unsigned int n = (unsigned int)num; - return (((n >> 12)) & 0x3f); -} - -static __inline unsigned int -get_ShAmt_Y1(tilegx_bundle_bits n) -{ - return (((unsigned int)(n >> 43)) & 0x3f); -} - -static __inline unsigned int -get_ShiftOpcodeExtension_X0(tilegx_bundle_bits num) -{ - const unsigned int n = (unsigned int)num; - return (((n >> 18)) & 0x3ff); -} - -static __inline unsigned int -get_ShiftOpcodeExtension_X1(tilegx_bundle_bits n) -{ - return (((unsigned int)(n >> 49)) & 0x3ff); -} - -static __inline unsigned int -get_ShiftOpcodeExtension_Y0(tilegx_bundle_bits num) -{ - const unsigned int n = (unsigned int)num; - return (((n >> 18)) & 0x3); -} - -static __inline unsigned int -get_ShiftOpcodeExtension_Y1(tilegx_bundle_bits n) -{ - return (((unsigned int)(n >> 49)) & 0x3); -} - -static __inline unsigned int -get_SrcA_X0(tilegx_bundle_bits num) -{ - const unsigned int n = (unsigned int)num; - return (((n >> 6)) & 0x3f); -} - -static __inline unsigned int -get_SrcA_X1(tilegx_bundle_bits n) -{ - return (((unsigned int)(n >> 37)) & 0x3f); -} - -static __inline unsigned int -get_SrcA_Y0(tilegx_bundle_bits num) -{ - const unsigned int n = (unsigned int)num; - return (((n >> 6)) & 0x3f); -} - -static __inline unsigned int -get_SrcA_Y1(tilegx_bundle_bits n) -{ - return (((unsigned int)(n >> 37)) & 0x3f); -} - -static __inline unsigned int -get_SrcA_Y2(tilegx_bundle_bits num) -{ - const unsigned int n = (unsigned int)num; - return (((n >> 20)) & 0x3f); -} - -static __inline unsigned int -get_SrcBDest_Y2(tilegx_bundle_bits n) -{ - return (((unsigned int)(n >> 51)) & 0x3f); -} - -static __inline unsigned int -get_SrcB_X0(tilegx_bundle_bits num) -{ - const unsigned int n = (unsigned int)num; - return (((n >> 12)) & 0x3f); -} - -static __inline unsigned int -get_SrcB_X1(tilegx_bundle_bits n) -{ - return (((unsigned int)(n >> 43)) & 0x3f); -} - -static __inline unsigned int -get_SrcB_Y0(tilegx_bundle_bits num) -{ - const unsigned int n = (unsigned int)num; - return (((n >> 12)) & 0x3f); -} - -static __inline unsigned int -get_SrcB_Y1(tilegx_bundle_bits n) -{ - return (((unsigned int)(n >> 43)) & 0x3f); -} - -static __inline unsigned int -get_UnaryOpcodeExtension_X0(tilegx_bundle_bits num) -{ - const unsigned int n = (unsigned int)num; - return (((n >> 12)) & 0x3f); -} - -static __inline unsigned int -get_UnaryOpcodeExtension_X1(tilegx_bundle_bits n) -{ - return (((unsigned int)(n >> 43)) & 0x3f); -} - -static __inline unsigned int -get_UnaryOpcodeExtension_Y0(tilegx_bundle_bits num) -{ - const unsigned int n = (unsigned int)num; - return (((n >> 12)) & 0x3f); -} - -static __inline unsigned int -get_UnaryOpcodeExtension_Y1(tilegx_bundle_bits n) -{ - return (((unsigned int)(n >> 43)) & 0x3f); -} - - -static __inline int -sign_extend(int n, int num_bits) -{ - int shift = (int)(sizeof(int) * 8 - num_bits); - return (n << shift) >> shift; -} - - - -static __inline tilegx_bundle_bits -create_BFEnd_X0(int num) -{ - const unsigned int n = (unsigned int)num; - return ((n & 0x3f) << 12); -} - -static __inline tilegx_bundle_bits -create_BFOpcodeExtension_X0(int num) -{ - const unsigned int n = (unsigned int)num; - return ((n & 0xf) << 24); -} - -static __inline tilegx_bundle_bits -create_BFStart_X0(int num) -{ - const unsigned int n = (unsigned int)num; - return ((n & 0x3f) << 18); -} - -static __inline tilegx_bundle_bits -create_BrOff_X1(int num) -{ - const unsigned int n = (unsigned int)num; - return (((tilegx_bundle_bits)(n & 0x0000003f)) << 31) | - (((tilegx_bundle_bits)(n & 0x0001ffc0)) << 37); -} - -static __inline tilegx_bundle_bits -create_BrType_X1(int num) -{ - const unsigned int n = (unsigned int)num; - return (((tilegx_bundle_bits)(n & 0x1f)) << 54); -} - -static __inline tilegx_bundle_bits -create_Dest_Imm8_X1(int num) -{ - const unsigned int n = (unsigned int)num; - return (((tilegx_bundle_bits)(n & 0x0000003f)) << 31) | - (((tilegx_bundle_bits)(n & 0x000000c0)) << 43); -} - -static __inline tilegx_bundle_bits -create_Dest_X0(int num) -{ - const unsigned int n = (unsigned int)num; - return ((n & 0x3f) << 0); -} - -static __inline tilegx_bundle_bits -create_Dest_X1(int num) -{ - const unsigned int n = (unsigned int)num; - return (((tilegx_bundle_bits)(n & 0x3f)) << 31); -} - -static __inline tilegx_bundle_bits -create_Dest_Y0(int num) -{ - const unsigned int n = (unsigned int)num; - return ((n & 0x3f) << 0); -} - -static __inline tilegx_bundle_bits -create_Dest_Y1(int num) -{ - const unsigned int n = (unsigned int)num; - return (((tilegx_bundle_bits)(n & 0x3f)) << 31); -} - -static __inline tilegx_bundle_bits -create_Imm16_X0(int num) -{ - const unsigned int n = (unsigned int)num; - return ((n & 0xffff) << 12); -} - -static __inline tilegx_bundle_bits -create_Imm16_X1(int num) -{ - const unsigned int n = (unsigned int)num; - return (((tilegx_bundle_bits)(n & 0xffff)) << 43); -} - -static __inline tilegx_bundle_bits -create_Imm8OpcodeExtension_X0(int num) -{ - const unsigned int n = (unsigned int)num; - return ((n & 0xff) << 20); -} - -static __inline tilegx_bundle_bits -create_Imm8OpcodeExtension_X1(int num) -{ - const unsigned int n = (unsigned int)num; - return (((tilegx_bundle_bits)(n & 0xff)) << 51); -} - -static __inline tilegx_bundle_bits -create_Imm8_X0(int num) -{ - const unsigned int n = (unsigned int)num; - return ((n & 0xff) << 12); -} - -static __inline tilegx_bundle_bits -create_Imm8_X1(int num) -{ - const unsigned int n = (unsigned int)num; - return (((tilegx_bundle_bits)(n & 0xff)) << 43); -} - -static __inline tilegx_bundle_bits -create_Imm8_Y0(int num) -{ - const unsigned int n = (unsigned int)num; - return ((n & 0xff) << 12); -} - -static __inline tilegx_bundle_bits -create_Imm8_Y1(int num) -{ - const unsigned int n = (unsigned int)num; - return (((tilegx_bundle_bits)(n & 0xff)) << 43); -} - -static __inline tilegx_bundle_bits -create_JumpOff_X1(int num) -{ - const unsigned int n = (unsigned int)num; - return (((tilegx_bundle_bits)(n & 0x7ffffff)) << 31); -} - -static __inline tilegx_bundle_bits -create_JumpOpcodeExtension_X1(int num) -{ - const unsigned int n = (unsigned int)num; - return (((tilegx_bundle_bits)(n & 0x1)) << 58); -} - -static __inline tilegx_bundle_bits -create_MF_Imm14_X1(int num) -{ - const unsigned int n = (unsigned int)num; - return (((tilegx_bundle_bits)(n & 0x3fff)) << 37); -} - -static __inline tilegx_bundle_bits -create_MT_Imm14_X1(int num) -{ - const unsigned int n = (unsigned int)num; - return (((tilegx_bundle_bits)(n & 0x0000003f)) << 31) | - (((tilegx_bundle_bits)(n & 0x00003fc0)) << 37); -} - -static __inline tilegx_bundle_bits -create_Mode(int num) -{ - const unsigned int n = (unsigned int)num; - return (((tilegx_bundle_bits)(n & 0x3)) << 62); -} - -static __inline tilegx_bundle_bits -create_Opcode_X0(int num) -{ - const unsigned int n = (unsigned int)num; - return ((n & 0x7) << 28); -} - -static __inline tilegx_bundle_bits -create_Opcode_X1(int num) -{ - const unsigned int n = (unsigned int)num; - return (((tilegx_bundle_bits)(n & 0x7)) << 59); -} - -static __inline tilegx_bundle_bits -create_Opcode_Y0(int num) -{ - const unsigned int n = (unsigned int)num; - return ((n & 0xf) << 27); -} - -static __inline tilegx_bundle_bits -create_Opcode_Y1(int num) -{ - const unsigned int n = (unsigned int)num; - return (((tilegx_bundle_bits)(n & 0xf)) << 58); -} - -static __inline tilegx_bundle_bits -create_Opcode_Y2(int num) -{ - const unsigned int n = (unsigned int)num; - return ((n & 0x00000001) << 26) | - (((tilegx_bundle_bits)(n & 0x00000002)) << 56); -} - -static __inline tilegx_bundle_bits -create_RRROpcodeExtension_X0(int num) -{ - const unsigned int n = (unsigned int)num; - return ((n & 0x3ff) << 18); -} - -static __inline tilegx_bundle_bits -create_RRROpcodeExtension_X1(int num) -{ - const unsigned int n = (unsigned int)num; - return (((tilegx_bundle_bits)(n & 0x3ff)) << 49); -} - -static __inline tilegx_bundle_bits -create_RRROpcodeExtension_Y0(int num) -{ - const unsigned int n = (unsigned int)num; - return ((n & 0x3) << 18); -} - -static __inline tilegx_bundle_bits -create_RRROpcodeExtension_Y1(int num) -{ - const unsigned int n = (unsigned int)num; - return (((tilegx_bundle_bits)(n & 0x3)) << 49); -} - -static __inline tilegx_bundle_bits -create_ShAmt_X0(int num) -{ - const unsigned int n = (unsigned int)num; - return ((n & 0x3f) << 12); -} - -static __inline tilegx_bundle_bits -create_ShAmt_X1(int num) -{ - const unsigned int n = (unsigned int)num; - return (((tilegx_bundle_bits)(n & 0x3f)) << 43); -} - -static __inline tilegx_bundle_bits -create_ShAmt_Y0(int num) -{ - const unsigned int n = (unsigned int)num; - return ((n & 0x3f) << 12); -} - -static __inline tilegx_bundle_bits -create_ShAmt_Y1(int num) -{ - const unsigned int n = (unsigned int)num; - return (((tilegx_bundle_bits)(n & 0x3f)) << 43); -} - -static __inline tilegx_bundle_bits -create_ShiftOpcodeExtension_X0(int num) -{ - const unsigned int n = (unsigned int)num; - return ((n & 0x3ff) << 18); -} - -static __inline tilegx_bundle_bits -create_ShiftOpcodeExtension_X1(int num) -{ - const unsigned int n = (unsigned int)num; - return (((tilegx_bundle_bits)(n & 0x3ff)) << 49); -} - -static __inline tilegx_bundle_bits -create_ShiftOpcodeExtension_Y0(int num) -{ - const unsigned int n = (unsigned int)num; - return ((n & 0x3) << 18); -} - -static __inline tilegx_bundle_bits -create_ShiftOpcodeExtension_Y1(int num) -{ - const unsigned int n = (unsigned int)num; - return (((tilegx_bundle_bits)(n & 0x3)) << 49); -} - -static __inline tilegx_bundle_bits -create_SrcA_X0(int num) -{ - const unsigned int n = (unsigned int)num; - return ((n & 0x3f) << 6); -} - -static __inline tilegx_bundle_bits -create_SrcA_X1(int num) -{ - const unsigned int n = (unsigned int)num; - return (((tilegx_bundle_bits)(n & 0x3f)) << 37); -} - -static __inline tilegx_bundle_bits -create_SrcA_Y0(int num) -{ - const unsigned int n = (unsigned int)num; - return ((n & 0x3f) << 6); -} - -static __inline tilegx_bundle_bits -create_SrcA_Y1(int num) -{ - const unsigned int n = (unsigned int)num; - return (((tilegx_bundle_bits)(n & 0x3f)) << 37); -} - -static __inline tilegx_bundle_bits -create_SrcA_Y2(int num) -{ - const unsigned int n = (unsigned int)num; - return ((n & 0x3f) << 20); -} - -static __inline tilegx_bundle_bits -create_SrcBDest_Y2(int num) -{ - const unsigned int n = (unsigned int)num; - return (((tilegx_bundle_bits)(n & 0x3f)) << 51); -} - -static __inline tilegx_bundle_bits -create_SrcB_X0(int num) -{ - const unsigned int n = (unsigned int)num; - return ((n & 0x3f) << 12); -} - -static __inline tilegx_bundle_bits -create_SrcB_X1(int num) -{ - const unsigned int n = (unsigned int)num; - return (((tilegx_bundle_bits)(n & 0x3f)) << 43); -} - -static __inline tilegx_bundle_bits -create_SrcB_Y0(int num) -{ - const unsigned int n = (unsigned int)num; - return ((n & 0x3f) << 12); -} - -static __inline tilegx_bundle_bits -create_SrcB_Y1(int num) -{ - const unsigned int n = (unsigned int)num; - return (((tilegx_bundle_bits)(n & 0x3f)) << 43); -} - -static __inline tilegx_bundle_bits -create_UnaryOpcodeExtension_X0(int num) -{ - const unsigned int n = (unsigned int)num; - return ((n & 0x3f) << 12); -} - -static __inline tilegx_bundle_bits -create_UnaryOpcodeExtension_X1(int num) -{ - const unsigned int n = (unsigned int)num; - return (((tilegx_bundle_bits)(n & 0x3f)) << 43); -} - -static __inline tilegx_bundle_bits -create_UnaryOpcodeExtension_Y0(int num) -{ - const unsigned int n = (unsigned int)num; - return ((n & 0x3f) << 12); -} - -static __inline tilegx_bundle_bits -create_UnaryOpcodeExtension_Y1(int num) -{ - const unsigned int n = (unsigned int)num; - return (((tilegx_bundle_bits)(n & 0x3f)) << 43); -} - - -typedef enum -{ - TILEGX_PIPELINE_X0, - TILEGX_PIPELINE_X1, - TILEGX_PIPELINE_Y0, - TILEGX_PIPELINE_Y1, - TILEGX_PIPELINE_Y2, -} tilegx_pipeline; - -#define tilegx_is_x_pipeline(p) ((int)(p) <= (int)TILEGX_PIPELINE_X1) - -typedef enum -{ - TILEGX_OP_TYPE_REGISTER, - TILEGX_OP_TYPE_IMMEDIATE, - TILEGX_OP_TYPE_ADDRESS, - TILEGX_OP_TYPE_SPR -} tilegx_operand_type; - -/* These are the bits that determine if a bundle is in the X encoding. */ -#define TILEGX_BUNDLE_MODE_MASK ((tilegx_bundle_bits)3 << 62) - -enum -{ - /* Maximum number of instructions in a bundle (2 for X, 3 for Y). */ - TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE = 3, - - /* How many different pipeline encodings are there? X0, X1, Y0, Y1, Y2. */ - TILEGX_NUM_PIPELINE_ENCODINGS = 5, - - /* Log base 2 of TILEGX_BUNDLE_SIZE_IN_BYTES. */ - TILEGX_LOG2_BUNDLE_SIZE_IN_BYTES = 3, - - /* Instructions take this many bytes. */ - TILEGX_BUNDLE_SIZE_IN_BYTES = 1 << TILEGX_LOG2_BUNDLE_SIZE_IN_BYTES, - - /* Log base 2 of TILEGX_BUNDLE_ALIGNMENT_IN_BYTES. */ - TILEGX_LOG2_BUNDLE_ALIGNMENT_IN_BYTES = 3, - - /* Bundles should be aligned modulo this number of bytes. */ - TILEGX_BUNDLE_ALIGNMENT_IN_BYTES = - (1 << TILEGX_LOG2_BUNDLE_ALIGNMENT_IN_BYTES), - - /* Number of registers (some are magic, such as network I/O). */ - TILEGX_NUM_REGISTERS = 64, -}; - - -struct tilegx_operand -{ - /* Is this operand a register, immediate or address? */ - tilegx_operand_type type; - - /* The default relocation type for this operand. */ - signed int default_reloc : 16; - - /* How many bits is this value? (used for range checking) */ - unsigned int num_bits : 5; - - /* Is the value signed? (used for range checking) */ - unsigned int is_signed : 1; - - /* Is this operand a source register? */ - unsigned int is_src_reg : 1; - - /* Is this operand written? (i.e. is it a destination register) */ - unsigned int is_dest_reg : 1; - - /* Is this operand PC-relative? */ - unsigned int is_pc_relative : 1; - - /* By how many bits do we right shift the value before inserting? */ - unsigned int rightshift : 2; - - /* Return the bits for this operand to be ORed into an existing bundle. */ - tilegx_bundle_bits (*insert) (int op); - - /* Extract this operand and return it. */ - unsigned int (*extract) (tilegx_bundle_bits bundle); -}; - - -extern const struct tilegx_operand tilegx_operands[]; - -/* One finite-state machine per pipe for rapid instruction decoding. */ -extern const unsigned short * const -tilegx_bundle_decoder_fsms[TILEGX_NUM_PIPELINE_ENCODINGS]; - - -struct tilegx_opcode -{ - /* The opcode mnemonic, e.g. "add" */ - const char *name; - - /* The enum value for this mnemonic. */ - tilegx_mnemonic mnemonic; - - /* A bit mask of which of the five pipes this instruction - is compatible with: - X0 0x01 - X1 0x02 - Y0 0x04 - Y1 0x08 - Y2 0x10 */ - unsigned char pipes; - - /* How many operands are there? */ - unsigned char num_operands; - - /* Which register does this write implicitly, or TREG_ZERO if none? */ - unsigned char implicitly_written_register; - - /* Can this be bundled with other instructions (almost always true). */ - unsigned char can_bundle; - - /* The description of the operands. Each of these is an - * index into the tilegx_operands[] table. */ - unsigned char operands[TILEGX_NUM_PIPELINE_ENCODINGS][TILEGX_MAX_OPERANDS]; - -#if !defined(__KERNEL__) && !defined(_LIBC) - /* A mask of which bits have predefined values for each pipeline. - * This is useful for disassembly. */ - tilegx_bundle_bits fixed_bit_masks[TILEGX_NUM_PIPELINE_ENCODINGS]; - - /* For each bit set in fixed_bit_masks, what the value is for this - * instruction. */ - tilegx_bundle_bits fixed_bit_values[TILEGX_NUM_PIPELINE_ENCODINGS]; -#endif -}; - -extern const struct tilegx_opcode tilegx_opcodes[]; - -/* Used for non-textual disassembly into structs. */ -struct tilegx_decoded_instruction -{ - const struct tilegx_opcode *opcode; - const struct tilegx_operand *operands[TILEGX_MAX_OPERANDS]; - long long operand_values[TILEGX_MAX_OPERANDS]; -}; - - -/* Disassemble a bundle into a struct for machine processing. */ -extern int parse_insn_tilegx(tilegx_bundle_bits bits, - unsigned long long pc, - struct tilegx_decoded_instruction - decoded[TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE]); - - -#if !defined(__KERNEL__) && !defined(_LIBC) -/* Canonical names of all the registers. */ -/* ISSUE: This table lives in "tile-dis.c" */ -extern const char * const tilegx_register_names[]; - -/* Descriptor for a special-purpose register. */ -struct tilegx_spr -{ - /* The number */ - int number; - - /* The name */ - const char *name; -}; - -/* List of all the SPRs; ordered by increasing number. */ -extern const struct tilegx_spr tilegx_sprs[]; - -/* Number of special-purpose registers. */ -extern const int tilegx_num_sprs; - -extern const char * -get_tilegx_spr_name (int num); -#endif /* !__KERNEL__ && !_LIBC */ - -/* Make a few "tile_" variables to simply common code between - architectures. */ - -typedef tilegx_bundle_bits tile_bundle_bits; -#define TILE_BUNDLE_SIZE_IN_BYTES TILEGX_BUNDLE_SIZE_IN_BYTES -#define TILE_BUNDLE_ALIGNMENT_IN_BYTES TILEGX_BUNDLE_ALIGNMENT_IN_BYTES -#define TILE_LOG2_BUNDLE_ALIGNMENT_IN_BYTES \ - TILEGX_LOG2_BUNDLE_ALIGNMENT_IN_BYTES - -#endif /* opcode_tilegx_h */ diff --git a/include/opcode/tilepro.h b/include/opcode/tilepro.h deleted file mode 100644 index 767926b..0000000 --- a/include/opcode/tilepro.h +++ /dev/null @@ -1,1638 +0,0 @@ -/* TILEPro opcode information. - * - * Copyright 2011 Free Software Foundation, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -#ifndef opcode_tilepro_h -#define opcode_tilepro_h - -typedef unsigned long long tilepro_bundle_bits; - - -enum -{ - TILEPRO_MAX_OPERANDS = 5 /* mm */ -}; - -typedef enum -{ - TILEPRO_OPC_BPT, - TILEPRO_OPC_INFO, - TILEPRO_OPC_INFOL, - TILEPRO_OPC_J, - TILEPRO_OPC_JAL, - TILEPRO_OPC_LW_TLS, - TILEPRO_OPC_LW_TLS_SN, - TILEPRO_OPC_MOVE, - TILEPRO_OPC_MOVE_SN, - TILEPRO_OPC_MOVEI, - TILEPRO_OPC_MOVEI_SN, - TILEPRO_OPC_MOVELI, - TILEPRO_OPC_MOVELI_SN, - TILEPRO_OPC_MOVELIS, - TILEPRO_OPC_PREFETCH, - TILEPRO_OPC_RAISE, - TILEPRO_OPC_ADD, - TILEPRO_OPC_ADD_SN, - TILEPRO_OPC_ADDB, - TILEPRO_OPC_ADDB_SN, - TILEPRO_OPC_ADDBS_U, - TILEPRO_OPC_ADDBS_U_SN, - TILEPRO_OPC_ADDH, - TILEPRO_OPC_ADDH_SN, - TILEPRO_OPC_ADDHS, - TILEPRO_OPC_ADDHS_SN, - TILEPRO_OPC_ADDI, - TILEPRO_OPC_ADDI_SN, - TILEPRO_OPC_ADDIB, - TILEPRO_OPC_ADDIB_SN, - TILEPRO_OPC_ADDIH, - TILEPRO_OPC_ADDIH_SN, - TILEPRO_OPC_ADDLI, - TILEPRO_OPC_ADDLI_SN, - TILEPRO_OPC_ADDLIS, - TILEPRO_OPC_ADDS, - TILEPRO_OPC_ADDS_SN, - TILEPRO_OPC_ADIFFB_U, - TILEPRO_OPC_ADIFFB_U_SN, - TILEPRO_OPC_ADIFFH, - TILEPRO_OPC_ADIFFH_SN, - TILEPRO_OPC_AND, - TILEPRO_OPC_AND_SN, - TILEPRO_OPC_ANDI, - TILEPRO_OPC_ANDI_SN, - TILEPRO_OPC_AULI, - TILEPRO_OPC_AVGB_U, - TILEPRO_OPC_AVGB_U_SN, - TILEPRO_OPC_AVGH, - TILEPRO_OPC_AVGH_SN, - TILEPRO_OPC_BBNS, - TILEPRO_OPC_BBNS_SN, - TILEPRO_OPC_BBNST, - TILEPRO_OPC_BBNST_SN, - TILEPRO_OPC_BBS, - TILEPRO_OPC_BBS_SN, - TILEPRO_OPC_BBST, - TILEPRO_OPC_BBST_SN, - TILEPRO_OPC_BGEZ, - TILEPRO_OPC_BGEZ_SN, - TILEPRO_OPC_BGEZT, - TILEPRO_OPC_BGEZT_SN, - TILEPRO_OPC_BGZ, - TILEPRO_OPC_BGZ_SN, - TILEPRO_OPC_BGZT, - TILEPRO_OPC_BGZT_SN, - TILEPRO_OPC_BITX, - TILEPRO_OPC_BITX_SN, - TILEPRO_OPC_BLEZ, - TILEPRO_OPC_BLEZ_SN, - TILEPRO_OPC_BLEZT, - TILEPRO_OPC_BLEZT_SN, - TILEPRO_OPC_BLZ, - TILEPRO_OPC_BLZ_SN, - TILEPRO_OPC_BLZT, - TILEPRO_OPC_BLZT_SN, - TILEPRO_OPC_BNZ, - TILEPRO_OPC_BNZ_SN, - TILEPRO_OPC_BNZT, - TILEPRO_OPC_BNZT_SN, - TILEPRO_OPC_BYTEX, - TILEPRO_OPC_BYTEX_SN, - TILEPRO_OPC_BZ, - TILEPRO_OPC_BZ_SN, - TILEPRO_OPC_BZT, - TILEPRO_OPC_BZT_SN, - TILEPRO_OPC_CLZ, - TILEPRO_OPC_CLZ_SN, - TILEPRO_OPC_CRC32_32, - TILEPRO_OPC_CRC32_32_SN, - TILEPRO_OPC_CRC32_8, - TILEPRO_OPC_CRC32_8_SN, - TILEPRO_OPC_CTZ, - TILEPRO_OPC_CTZ_SN, - TILEPRO_OPC_DRAIN, - TILEPRO_OPC_DTLBPR, - TILEPRO_OPC_DWORD_ALIGN, - TILEPRO_OPC_DWORD_ALIGN_SN, - TILEPRO_OPC_FINV, - TILEPRO_OPC_FLUSH, - TILEPRO_OPC_FNOP, - TILEPRO_OPC_ICOH, - TILEPRO_OPC_ILL, - TILEPRO_OPC_INTHB, - TILEPRO_OPC_INTHB_SN, - TILEPRO_OPC_INTHH, - TILEPRO_OPC_INTHH_SN, - TILEPRO_OPC_INTLB, - TILEPRO_OPC_INTLB_SN, - TILEPRO_OPC_INTLH, - TILEPRO_OPC_INTLH_SN, - TILEPRO_OPC_INV, - TILEPRO_OPC_IRET, - TILEPRO_OPC_JALB, - TILEPRO_OPC_JALF, - TILEPRO_OPC_JALR, - TILEPRO_OPC_JALRP, - TILEPRO_OPC_JB, - TILEPRO_OPC_JF, - TILEPRO_OPC_JR, - TILEPRO_OPC_JRP, - TILEPRO_OPC_LB, - TILEPRO_OPC_LB_SN, - TILEPRO_OPC_LB_U, - TILEPRO_OPC_LB_U_SN, - TILEPRO_OPC_LBADD, - TILEPRO_OPC_LBADD_SN, - TILEPRO_OPC_LBADD_U, - TILEPRO_OPC_LBADD_U_SN, - TILEPRO_OPC_LH, - TILEPRO_OPC_LH_SN, - TILEPRO_OPC_LH_U, - TILEPRO_OPC_LH_U_SN, - TILEPRO_OPC_LHADD, - TILEPRO_OPC_LHADD_SN, - TILEPRO_OPC_LHADD_U, - TILEPRO_OPC_LHADD_U_SN, - TILEPRO_OPC_LNK, - TILEPRO_OPC_LNK_SN, - TILEPRO_OPC_LW, - TILEPRO_OPC_LW_SN, - TILEPRO_OPC_LW_NA, - TILEPRO_OPC_LW_NA_SN, - TILEPRO_OPC_LWADD, - TILEPRO_OPC_LWADD_SN, - TILEPRO_OPC_LWADD_NA, - TILEPRO_OPC_LWADD_NA_SN, - TILEPRO_OPC_MAXB_U, - TILEPRO_OPC_MAXB_U_SN, - TILEPRO_OPC_MAXH, - TILEPRO_OPC_MAXH_SN, - TILEPRO_OPC_MAXIB_U, - TILEPRO_OPC_MAXIB_U_SN, - TILEPRO_OPC_MAXIH, - TILEPRO_OPC_MAXIH_SN, - TILEPRO_OPC_MF, - TILEPRO_OPC_MFSPR, - TILEPRO_OPC_MINB_U, - TILEPRO_OPC_MINB_U_SN, - TILEPRO_OPC_MINH, - TILEPRO_OPC_MINH_SN, - TILEPRO_OPC_MINIB_U, - TILEPRO_OPC_MINIB_U_SN, - TILEPRO_OPC_MINIH, - TILEPRO_OPC_MINIH_SN, - TILEPRO_OPC_MM, - TILEPRO_OPC_MNZ, - TILEPRO_OPC_MNZ_SN, - TILEPRO_OPC_MNZB, - TILEPRO_OPC_MNZB_SN, - TILEPRO_OPC_MNZH, - TILEPRO_OPC_MNZH_SN, - TILEPRO_OPC_MTSPR, - TILEPRO_OPC_MULHH_SS, - TILEPRO_OPC_MULHH_SS_SN, - TILEPRO_OPC_MULHH_SU, - TILEPRO_OPC_MULHH_SU_SN, - TILEPRO_OPC_MULHH_UU, - TILEPRO_OPC_MULHH_UU_SN, - TILEPRO_OPC_MULHHA_SS, - TILEPRO_OPC_MULHHA_SS_SN, - TILEPRO_OPC_MULHHA_SU, - TILEPRO_OPC_MULHHA_SU_SN, - TILEPRO_OPC_MULHHA_UU, - TILEPRO_OPC_MULHHA_UU_SN, - TILEPRO_OPC_MULHHSA_UU, - TILEPRO_OPC_MULHHSA_UU_SN, - TILEPRO_OPC_MULHL_SS, - TILEPRO_OPC_MULHL_SS_SN, - TILEPRO_OPC_MULHL_SU, - TILEPRO_OPC_MULHL_SU_SN, - TILEPRO_OPC_MULHL_US, - TILEPRO_OPC_MULHL_US_SN, - TILEPRO_OPC_MULHL_UU, - TILEPRO_OPC_MULHL_UU_SN, - TILEPRO_OPC_MULHLA_SS, - TILEPRO_OPC_MULHLA_SS_SN, - TILEPRO_OPC_MULHLA_SU, - TILEPRO_OPC_MULHLA_SU_SN, - TILEPRO_OPC_MULHLA_US, - TILEPRO_OPC_MULHLA_US_SN, - TILEPRO_OPC_MULHLA_UU, - TILEPRO_OPC_MULHLA_UU_SN, - TILEPRO_OPC_MULHLSA_UU, - TILEPRO_OPC_MULHLSA_UU_SN, - TILEPRO_OPC_MULLL_SS, - TILEPRO_OPC_MULLL_SS_SN, - TILEPRO_OPC_MULLL_SU, - TILEPRO_OPC_MULLL_SU_SN, - TILEPRO_OPC_MULLL_UU, - TILEPRO_OPC_MULLL_UU_SN, - TILEPRO_OPC_MULLLA_SS, - TILEPRO_OPC_MULLLA_SS_SN, - TILEPRO_OPC_MULLLA_SU, - TILEPRO_OPC_MULLLA_SU_SN, - TILEPRO_OPC_MULLLA_UU, - TILEPRO_OPC_MULLLA_UU_SN, - TILEPRO_OPC_MULLLSA_UU, - TILEPRO_OPC_MULLLSA_UU_SN, - TILEPRO_OPC_MVNZ, - TILEPRO_OPC_MVNZ_SN, - TILEPRO_OPC_MVZ, - TILEPRO_OPC_MVZ_SN, - TILEPRO_OPC_MZ, - TILEPRO_OPC_MZ_SN, - TILEPRO_OPC_MZB, - TILEPRO_OPC_MZB_SN, - TILEPRO_OPC_MZH, - TILEPRO_OPC_MZH_SN, - TILEPRO_OPC_NAP, - TILEPRO_OPC_NOP, - TILEPRO_OPC_NOR, - TILEPRO_OPC_NOR_SN, - TILEPRO_OPC_OR, - TILEPRO_OPC_OR_SN, - TILEPRO_OPC_ORI, - TILEPRO_OPC_ORI_SN, - TILEPRO_OPC_PACKBS_U, - TILEPRO_OPC_PACKBS_U_SN, - TILEPRO_OPC_PACKHB, - TILEPRO_OPC_PACKHB_SN, - TILEPRO_OPC_PACKHS, - TILEPRO_OPC_PACKHS_SN, - TILEPRO_OPC_PACKLB, - TILEPRO_OPC_PACKLB_SN, - TILEPRO_OPC_PCNT, - TILEPRO_OPC_PCNT_SN, - TILEPRO_OPC_RL, - TILEPRO_OPC_RL_SN, - TILEPRO_OPC_RLI, - TILEPRO_OPC_RLI_SN, - TILEPRO_OPC_S1A, - TILEPRO_OPC_S1A_SN, - TILEPRO_OPC_S2A, - TILEPRO_OPC_S2A_SN, - TILEPRO_OPC_S3A, - TILEPRO_OPC_S3A_SN, - TILEPRO_OPC_SADAB_U, - TILEPRO_OPC_SADAB_U_SN, - TILEPRO_OPC_SADAH, - TILEPRO_OPC_SADAH_SN, - TILEPRO_OPC_SADAH_U, - TILEPRO_OPC_SADAH_U_SN, - TILEPRO_OPC_SADB_U, - TILEPRO_OPC_SADB_U_SN, - TILEPRO_OPC_SADH, - TILEPRO_OPC_SADH_SN, - TILEPRO_OPC_SADH_U, - TILEPRO_OPC_SADH_U_SN, - TILEPRO_OPC_SB, - TILEPRO_OPC_SBADD, - TILEPRO_OPC_SEQ, - TILEPRO_OPC_SEQ_SN, - TILEPRO_OPC_SEQB, - TILEPRO_OPC_SEQB_SN, - TILEPRO_OPC_SEQH, - TILEPRO_OPC_SEQH_SN, - TILEPRO_OPC_SEQI, - TILEPRO_OPC_SEQI_SN, - TILEPRO_OPC_SEQIB, - TILEPRO_OPC_SEQIB_SN, - TILEPRO_OPC_SEQIH, - TILEPRO_OPC_SEQIH_SN, - TILEPRO_OPC_SH, - TILEPRO_OPC_SHADD, - TILEPRO_OPC_SHL, - TILEPRO_OPC_SHL_SN, - TILEPRO_OPC_SHLB, - TILEPRO_OPC_SHLB_SN, - TILEPRO_OPC_SHLH, - TILEPRO_OPC_SHLH_SN, - TILEPRO_OPC_SHLI, - TILEPRO_OPC_SHLI_SN, - TILEPRO_OPC_SHLIB, - TILEPRO_OPC_SHLIB_SN, - TILEPRO_OPC_SHLIH, - TILEPRO_OPC_SHLIH_SN, - TILEPRO_OPC_SHR, - TILEPRO_OPC_SHR_SN, - TILEPRO_OPC_SHRB, - TILEPRO_OPC_SHRB_SN, - TILEPRO_OPC_SHRH, - TILEPRO_OPC_SHRH_SN, - TILEPRO_OPC_SHRI, - TILEPRO_OPC_SHRI_SN, - TILEPRO_OPC_SHRIB, - TILEPRO_OPC_SHRIB_SN, - TILEPRO_OPC_SHRIH, - TILEPRO_OPC_SHRIH_SN, - TILEPRO_OPC_SLT, - TILEPRO_OPC_SLT_SN, - TILEPRO_OPC_SLT_U, - TILEPRO_OPC_SLT_U_SN, - TILEPRO_OPC_SLTB, - TILEPRO_OPC_SLTB_SN, - TILEPRO_OPC_SLTB_U, - TILEPRO_OPC_SLTB_U_SN, - TILEPRO_OPC_SLTE, - TILEPRO_OPC_SLTE_SN, - TILEPRO_OPC_SLTE_U, - TILEPRO_OPC_SLTE_U_SN, - TILEPRO_OPC_SLTEB, - TILEPRO_OPC_SLTEB_SN, - TILEPRO_OPC_SLTEB_U, - TILEPRO_OPC_SLTEB_U_SN, - TILEPRO_OPC_SLTEH, - TILEPRO_OPC_SLTEH_SN, - TILEPRO_OPC_SLTEH_U, - TILEPRO_OPC_SLTEH_U_SN, - TILEPRO_OPC_SLTH, - TILEPRO_OPC_SLTH_SN, - TILEPRO_OPC_SLTH_U, - TILEPRO_OPC_SLTH_U_SN, - TILEPRO_OPC_SLTI, - TILEPRO_OPC_SLTI_SN, - TILEPRO_OPC_SLTI_U, - TILEPRO_OPC_SLTI_U_SN, - TILEPRO_OPC_SLTIB, - TILEPRO_OPC_SLTIB_SN, - TILEPRO_OPC_SLTIB_U, - TILEPRO_OPC_SLTIB_U_SN, - TILEPRO_OPC_SLTIH, - TILEPRO_OPC_SLTIH_SN, - TILEPRO_OPC_SLTIH_U, - TILEPRO_OPC_SLTIH_U_SN, - TILEPRO_OPC_SNE, - TILEPRO_OPC_SNE_SN, - TILEPRO_OPC_SNEB, - TILEPRO_OPC_SNEB_SN, - TILEPRO_OPC_SNEH, - TILEPRO_OPC_SNEH_SN, - TILEPRO_OPC_SRA, - TILEPRO_OPC_SRA_SN, - TILEPRO_OPC_SRAB, - TILEPRO_OPC_SRAB_SN, - TILEPRO_OPC_SRAH, - TILEPRO_OPC_SRAH_SN, - TILEPRO_OPC_SRAI, - TILEPRO_OPC_SRAI_SN, - TILEPRO_OPC_SRAIB, - TILEPRO_OPC_SRAIB_SN, - TILEPRO_OPC_SRAIH, - TILEPRO_OPC_SRAIH_SN, - TILEPRO_OPC_SUB, - TILEPRO_OPC_SUB_SN, - TILEPRO_OPC_SUBB, - TILEPRO_OPC_SUBB_SN, - TILEPRO_OPC_SUBBS_U, - TILEPRO_OPC_SUBBS_U_SN, - TILEPRO_OPC_SUBH, - TILEPRO_OPC_SUBH_SN, - TILEPRO_OPC_SUBHS, - TILEPRO_OPC_SUBHS_SN, - TILEPRO_OPC_SUBS, - TILEPRO_OPC_SUBS_SN, - TILEPRO_OPC_SW, - TILEPRO_OPC_SWADD, - TILEPRO_OPC_SWINT0, - TILEPRO_OPC_SWINT1, - TILEPRO_OPC_SWINT2, - TILEPRO_OPC_SWINT3, - TILEPRO_OPC_TBLIDXB0, - TILEPRO_OPC_TBLIDXB0_SN, - TILEPRO_OPC_TBLIDXB1, - TILEPRO_OPC_TBLIDXB1_SN, - TILEPRO_OPC_TBLIDXB2, - TILEPRO_OPC_TBLIDXB2_SN, - TILEPRO_OPC_TBLIDXB3, - TILEPRO_OPC_TBLIDXB3_SN, - TILEPRO_OPC_TNS, - TILEPRO_OPC_TNS_SN, - TILEPRO_OPC_WH64, - TILEPRO_OPC_XOR, - TILEPRO_OPC_XOR_SN, - TILEPRO_OPC_XORI, - TILEPRO_OPC_XORI_SN, - TILEPRO_OPC_NONE -} tilepro_mnemonic; - -/* 64-bit pattern for a { bpt ; nop } bundle. */ -#define TILEPRO_BPT_BUNDLE 0x400b3cae70166000ULL - -#ifndef DISASM_ONLY - -enum -{ - TILEPRO_SN_MAX_OPERANDS = 6 /* route */ -}; - -typedef enum -{ - TILEPRO_SN_OPC_BZ, - TILEPRO_SN_OPC_BNZ, - TILEPRO_SN_OPC_JRR, - TILEPRO_SN_OPC_FNOP, - TILEPRO_SN_OPC_BLZ, - TILEPRO_SN_OPC_NOP, - TILEPRO_SN_OPC_MOVEI, - TILEPRO_SN_OPC_MOVE, - TILEPRO_SN_OPC_BGEZ, - TILEPRO_SN_OPC_JR, - TILEPRO_SN_OPC_BLEZ, - TILEPRO_SN_OPC_BBNS, - TILEPRO_SN_OPC_JALRR, - TILEPRO_SN_OPC_BPT, - TILEPRO_SN_OPC_JALR, - TILEPRO_SN_OPC_SHR1, - TILEPRO_SN_OPC_BGZ, - TILEPRO_SN_OPC_BBS, - TILEPRO_SN_OPC_SHL8II, - TILEPRO_SN_OPC_ADDI, - TILEPRO_SN_OPC_HALT, - TILEPRO_SN_OPC_ROUTE, - TILEPRO_SN_OPC_NONE -} tilepro_sn_mnemonic; - -extern const unsigned char tilepro_sn_route_encode[6 * 6 * 6]; -extern const signed char tilepro_sn_route_decode[256][3]; -extern const char tilepro_sn_direction_names[6][5]; -extern const signed char tilepro_sn_dest_map[6][6]; -#endif /* DISASM_ONLY */ - - -static __inline unsigned int -get_BrOff_SN(tilepro_bundle_bits num) -{ - const unsigned int n = (unsigned int)num; - return (((n >> 0)) & 0x3ff); -} - -static __inline unsigned int -get_BrOff_X1(tilepro_bundle_bits n) -{ - return (((unsigned int)(n >> 43)) & 0x00007fff) | - (((unsigned int)(n >> 20)) & 0x00018000); -} - -static __inline unsigned int -get_BrType_X1(tilepro_bundle_bits n) -{ - return (((unsigned int)(n >> 31)) & 0xf); -} - -static __inline unsigned int -get_Dest_Imm8_X1(tilepro_bundle_bits n) -{ - return (((unsigned int)(n >> 31)) & 0x0000003f) | - (((unsigned int)(n >> 43)) & 0x000000c0); -} - -static __inline unsigned int -get_Dest_SN(tilepro_bundle_bits num) -{ - const unsigned int n = (unsigned int)num; - return (((n >> 2)) & 0x3); -} - -static __inline unsigned int -get_Dest_X0(tilepro_bundle_bits num) -{ - const unsigned int n = (unsigned int)num; - return (((n >> 0)) & 0x3f); -} - -static __inline unsigned int -get_Dest_X1(tilepro_bundle_bits n) -{ - return (((unsigned int)(n >> 31)) & 0x3f); -} - -static __inline unsigned int -get_Dest_Y0(tilepro_bundle_bits num) -{ - const unsigned int n = (unsigned int)num; - return (((n >> 0)) & 0x3f); -} - -static __inline unsigned int -get_Dest_Y1(tilepro_bundle_bits n) -{ - return (((unsigned int)(n >> 31)) & 0x3f); -} - -static __inline unsigned int -get_Imm16_X0(tilepro_bundle_bits num) -{ - const unsigned int n = (unsigned int)num; - return (((n >> 12)) & 0xffff); -} - -static __inline unsigned int -get_Imm16_X1(tilepro_bundle_bits n) -{ - return (((unsigned int)(n >> 43)) & 0xffff); -} - -static __inline unsigned int -get_Imm8_SN(tilepro_bundle_bits num) -{ - const unsigned int n = (unsigned int)num; - return (((n >> 0)) & 0xff); -} - -static __inline unsigned int -get_Imm8_X0(tilepro_bundle_bits num) -{ - const unsigned int n = (unsigned int)num; - return (((n >> 12)) & 0xff); -} - -static __inline unsigned int -get_Imm8_X1(tilepro_bundle_bits n) -{ - return (((unsigned int)(n >> 43)) & 0xff); -} - -static __inline unsigned int -get_Imm8_Y0(tilepro_bundle_bits num) -{ - const unsigned int n = (unsigned int)num; - return (((n >> 12)) & 0xff); -} - -static __inline unsigned int -get_Imm8_Y1(tilepro_bundle_bits n) -{ - return (((unsigned int)(n >> 43)) & 0xff); -} - -static __inline unsigned int -get_ImmOpcodeExtension_X0(tilepro_bundle_bits num) -{ - const unsigned int n = (unsigned int)num; - return (((n >> 20)) & 0x7f); -} - -static __inline unsigned int -get_ImmOpcodeExtension_X1(tilepro_bundle_bits n) -{ - return (((unsigned int)(n >> 51)) & 0x7f); -} - -static __inline unsigned int -get_ImmRROpcodeExtension_SN(tilepro_bundle_bits num) -{ - const unsigned int n = (unsigned int)num; - return (((n >> 8)) & 0x3); -} - -static __inline unsigned int -get_JOffLong_X1(tilepro_bundle_bits n) -{ - return (((unsigned int)(n >> 43)) & 0x00007fff) | - (((unsigned int)(n >> 20)) & 0x00018000) | - (((unsigned int)(n >> 14)) & 0x001e0000) | - (((unsigned int)(n >> 16)) & 0x07e00000) | - (((unsigned int)(n >> 31)) & 0x18000000); -} - -static __inline unsigned int -get_JOff_X1(tilepro_bundle_bits n) -{ - return (((unsigned int)(n >> 43)) & 0x00007fff) | - (((unsigned int)(n >> 20)) & 0x00018000) | - (((unsigned int)(n >> 14)) & 0x001e0000) | - (((unsigned int)(n >> 16)) & 0x07e00000) | - (((unsigned int)(n >> 31)) & 0x08000000); -} - -static __inline unsigned int -get_MF_Imm15_X1(tilepro_bundle_bits n) -{ - return (((unsigned int)(n >> 37)) & 0x00003fff) | - (((unsigned int)(n >> 44)) & 0x00004000); -} - -static __inline unsigned int -get_MMEnd_X0(tilepro_bundle_bits num) -{ - const unsigned int n = (unsigned int)num; - return (((n >> 18)) & 0x1f); -} - -static __inline unsigned int -get_MMEnd_X1(tilepro_bundle_bits n) -{ - return (((unsigned int)(n >> 49)) & 0x1f); -} - -static __inline unsigned int -get_MMStart_X0(tilepro_bundle_bits num) -{ - const unsigned int n = (unsigned int)num; - return (((n >> 23)) & 0x1f); -} - -static __inline unsigned int -get_MMStart_X1(tilepro_bundle_bits n) -{ - return (((unsigned int)(n >> 54)) & 0x1f); -} - -static __inline unsigned int -get_MT_Imm15_X1(tilepro_bundle_bits n) -{ - return (((unsigned int)(n >> 31)) & 0x0000003f) | - (((unsigned int)(n >> 37)) & 0x00003fc0) | - (((unsigned int)(n >> 44)) & 0x00004000); -} - -static __inline unsigned int -get_Mode(tilepro_bundle_bits n) -{ - return (((unsigned int)(n >> 63)) & 0x1); -} - -static __inline unsigned int -get_NoRegOpcodeExtension_SN(tilepro_bundle_bits num) -{ - const unsigned int n = (unsigned int)num; - return (((n >> 0)) & 0xf); -} - -static __inline unsigned int -get_Opcode_SN(tilepro_bundle_bits num) -{ - const unsigned int n = (unsigned int)num; - return (((n >> 10)) & 0x3f); -} - -static __inline unsigned int -get_Opcode_X0(tilepro_bundle_bits num) -{ - const unsigned int n = (unsigned int)num; - return (((n >> 28)) & 0x7); -} - -static __inline unsigned int -get_Opcode_X1(tilepro_bundle_bits n) -{ - return (((unsigned int)(n >> 59)) & 0xf); -} - -static __inline unsigned int -get_Opcode_Y0(tilepro_bundle_bits num) -{ - const unsigned int n = (unsigned int)num; - return (((n >> 27)) & 0xf); -} - -static __inline unsigned int -get_Opcode_Y1(tilepro_bundle_bits n) -{ - return (((unsigned int)(n >> 59)) & 0xf); -} - -static __inline unsigned int -get_Opcode_Y2(tilepro_bundle_bits n) -{ - return (((unsigned int)(n >> 56)) & 0x7); -} - -static __inline unsigned int -get_RROpcodeExtension_SN(tilepro_bundle_bits num) -{ - const unsigned int n = (unsigned int)num; - return (((n >> 4)) & 0xf); -} - -static __inline unsigned int -get_RRROpcodeExtension_X0(tilepro_bundle_bits num) -{ - const unsigned int n = (unsigned int)num; - return (((n >> 18)) & 0x1ff); -} - -static __inline unsigned int -get_RRROpcodeExtension_X1(tilepro_bundle_bits n) -{ - return (((unsigned int)(n >> 49)) & 0x1ff); -} - -static __inline unsigned int -get_RRROpcodeExtension_Y0(tilepro_bundle_bits num) -{ - const unsigned int n = (unsigned int)num; - return (((n >> 18)) & 0x3); -} - -static __inline unsigned int -get_RRROpcodeExtension_Y1(tilepro_bundle_bits n) -{ - return (((unsigned int)(n >> 49)) & 0x3); -} - -static __inline unsigned int -get_RouteOpcodeExtension_SN(tilepro_bundle_bits num) -{ - const unsigned int n = (unsigned int)num; - return (((n >> 0)) & 0x3ff); -} - -static __inline unsigned int -get_S_X0(tilepro_bundle_bits num) -{ - const unsigned int n = (unsigned int)num; - return (((n >> 27)) & 0x1); -} - -static __inline unsigned int -get_S_X1(tilepro_bundle_bits n) -{ - return (((unsigned int)(n >> 58)) & 0x1); -} - -static __inline unsigned int -get_ShAmt_X0(tilepro_bundle_bits num) -{ - const unsigned int n = (unsigned int)num; - return (((n >> 12)) & 0x1f); -} - -static __inline unsigned int -get_ShAmt_X1(tilepro_bundle_bits n) -{ - return (((unsigned int)(n >> 43)) & 0x1f); -} - -static __inline unsigned int -get_ShAmt_Y0(tilepro_bundle_bits num) -{ - const unsigned int n = (unsigned int)num; - return (((n >> 12)) & 0x1f); -} - -static __inline unsigned int -get_ShAmt_Y1(tilepro_bundle_bits n) -{ - return (((unsigned int)(n >> 43)) & 0x1f); -} - -static __inline unsigned int -get_SrcA_X0(tilepro_bundle_bits num) -{ - const unsigned int n = (unsigned int)num; - return (((n >> 6)) & 0x3f); -} - -static __inline unsigned int -get_SrcA_X1(tilepro_bundle_bits n) -{ - return (((unsigned int)(n >> 37)) & 0x3f); -} - -static __inline unsigned int -get_SrcA_Y0(tilepro_bundle_bits num) -{ - const unsigned int n = (unsigned int)num; - return (((n >> 6)) & 0x3f); -} - -static __inline unsigned int -get_SrcA_Y1(tilepro_bundle_bits n) -{ - return (((unsigned int)(n >> 37)) & 0x3f); -} - -static __inline unsigned int -get_SrcA_Y2(tilepro_bundle_bits n) -{ - return (((n >> 26)) & 0x00000001) | - (((unsigned int)(n >> 50)) & 0x0000003e); -} - -static __inline unsigned int -get_SrcBDest_Y2(tilepro_bundle_bits num) -{ - const unsigned int n = (unsigned int)num; - return (((n >> 20)) & 0x3f); -} - -static __inline unsigned int -get_SrcB_X0(tilepro_bundle_bits num) -{ - const unsigned int n = (unsigned int)num; - return (((n >> 12)) & 0x3f); -} - -static __inline unsigned int -get_SrcB_X1(tilepro_bundle_bits n) -{ - return (((unsigned int)(n >> 43)) & 0x3f); -} - -static __inline unsigned int -get_SrcB_Y0(tilepro_bundle_bits num) -{ - const unsigned int n = (unsigned int)num; - return (((n >> 12)) & 0x3f); -} - -static __inline unsigned int -get_SrcB_Y1(tilepro_bundle_bits n) -{ - return (((unsigned int)(n >> 43)) & 0x3f); -} - -static __inline unsigned int -get_Src_SN(tilepro_bundle_bits num) -{ - const unsigned int n = (unsigned int)num; - return (((n >> 0)) & 0x3); -} - -static __inline unsigned int -get_UnOpcodeExtension_X0(tilepro_bundle_bits num) -{ - const unsigned int n = (unsigned int)num; - return (((n >> 12)) & 0x1f); -} - -static __inline unsigned int -get_UnOpcodeExtension_X1(tilepro_bundle_bits n) -{ - return (((unsigned int)(n >> 43)) & 0x1f); -} - -static __inline unsigned int -get_UnOpcodeExtension_Y0(tilepro_bundle_bits num) -{ - const unsigned int n = (unsigned int)num; - return (((n >> 12)) & 0x1f); -} - -static __inline unsigned int -get_UnOpcodeExtension_Y1(tilepro_bundle_bits n) -{ - return (((unsigned int)(n >> 43)) & 0x1f); -} - -static __inline unsigned int -get_UnShOpcodeExtension_X0(tilepro_bundle_bits num) -{ - const unsigned int n = (unsigned int)num; - return (((n >> 17)) & 0x3ff); -} - -static __inline unsigned int -get_UnShOpcodeExtension_X1(tilepro_bundle_bits n) -{ - return (((unsigned int)(n >> 48)) & 0x3ff); -} - -static __inline unsigned int -get_UnShOpcodeExtension_Y0(tilepro_bundle_bits num) -{ - const unsigned int n = (unsigned int)num; - return (((n >> 17)) & 0x7); -} - -static __inline unsigned int -get_UnShOpcodeExtension_Y1(tilepro_bundle_bits n) -{ - return (((unsigned int)(n >> 48)) & 0x7); -} - - -static __inline int -sign_extend(int n, int num_bits) -{ - int shift = (int)(sizeof(int) * 8 - num_bits); - return (n << shift) >> shift; -} - - - -static __inline tilepro_bundle_bits -create_BrOff_SN(int num) -{ - const unsigned int n = (unsigned int)num; - return ((n & 0x3ff) << 0); -} - -static __inline tilepro_bundle_bits -create_BrOff_X1(int num) -{ - const unsigned int n = (unsigned int)num; - return (((tilepro_bundle_bits)(n & 0x00007fff)) << 43) | - (((tilepro_bundle_bits)(n & 0x00018000)) << 20); -} - -static __inline tilepro_bundle_bits -create_BrType_X1(int num) -{ - const unsigned int n = (unsigned int)num; - return (((tilepro_bundle_bits)(n & 0xf)) << 31); -} - -static __inline tilepro_bundle_bits -create_Dest_Imm8_X1(int num) -{ - const unsigned int n = (unsigned int)num; - return (((tilepro_bundle_bits)(n & 0x0000003f)) << 31) | - (((tilepro_bundle_bits)(n & 0x000000c0)) << 43); -} - -static __inline tilepro_bundle_bits -create_Dest_SN(int num) -{ - const unsigned int n = (unsigned int)num; - return ((n & 0x3) << 2); -} - -static __inline tilepro_bundle_bits -create_Dest_X0(int num) -{ - const unsigned int n = (unsigned int)num; - return ((n & 0x3f) << 0); -} - -static __inline tilepro_bundle_bits -create_Dest_X1(int num) -{ - const unsigned int n = (unsigned int)num; - return (((tilepro_bundle_bits)(n & 0x3f)) << 31); -} - -static __inline tilepro_bundle_bits -create_Dest_Y0(int num) -{ - const unsigned int n = (unsigned int)num; - return ((n & 0x3f) << 0); -} - -static __inline tilepro_bundle_bits -create_Dest_Y1(int num) -{ - const unsigned int n = (unsigned int)num; - return (((tilepro_bundle_bits)(n & 0x3f)) << 31); -} - -static __inline tilepro_bundle_bits -create_Imm16_X0(int num) -{ - const unsigned int n = (unsigned int)num; - return ((n & 0xffff) << 12); -} - -static __inline tilepro_bundle_bits -create_Imm16_X1(int num) -{ - const unsigned int n = (unsigned int)num; - return (((tilepro_bundle_bits)(n & 0xffff)) << 43); -} - -static __inline tilepro_bundle_bits -create_Imm8_SN(int num) -{ - const unsigned int n = (unsigned int)num; - return ((n & 0xff) << 0); -} - -static __inline tilepro_bundle_bits -create_Imm8_X0(int num) -{ - const unsigned int n = (unsigned int)num; - return ((n & 0xff) << 12); -} - -static __inline tilepro_bundle_bits -create_Imm8_X1(int num) -{ - const unsigned int n = (unsigned int)num; - return (((tilepro_bundle_bits)(n & 0xff)) << 43); -} - -static __inline tilepro_bundle_bits -create_Imm8_Y0(int num) -{ - const unsigned int n = (unsigned int)num; - return ((n & 0xff) << 12); -} - -static __inline tilepro_bundle_bits -create_Imm8_Y1(int num) -{ - const unsigned int n = (unsigned int)num; - return (((tilepro_bundle_bits)(n & 0xff)) << 43); -} - -static __inline tilepro_bundle_bits -create_ImmOpcodeExtension_X0(int num) -{ - const unsigned int n = (unsigned int)num; - return ((n & 0x7f) << 20); -} - -static __inline tilepro_bundle_bits -create_ImmOpcodeExtension_X1(int num) -{ - const unsigned int n = (unsigned int)num; - return (((tilepro_bundle_bits)(n & 0x7f)) << 51); -} - -static __inline tilepro_bundle_bits -create_ImmRROpcodeExtension_SN(int num) -{ - const unsigned int n = (unsigned int)num; - return ((n & 0x3) << 8); -} - -static __inline tilepro_bundle_bits -create_JOffLong_X1(int num) -{ - const unsigned int n = (unsigned int)num; - return (((tilepro_bundle_bits)(n & 0x00007fff)) << 43) | - (((tilepro_bundle_bits)(n & 0x00018000)) << 20) | - (((tilepro_bundle_bits)(n & 0x001e0000)) << 14) | - (((tilepro_bundle_bits)(n & 0x07e00000)) << 16) | - (((tilepro_bundle_bits)(n & 0x18000000)) << 31); -} - -static __inline tilepro_bundle_bits -create_JOff_X1(int num) -{ - const unsigned int n = (unsigned int)num; - return (((tilepro_bundle_bits)(n & 0x00007fff)) << 43) | - (((tilepro_bundle_bits)(n & 0x00018000)) << 20) | - (((tilepro_bundle_bits)(n & 0x001e0000)) << 14) | - (((tilepro_bundle_bits)(n & 0x07e00000)) << 16) | - (((tilepro_bundle_bits)(n & 0x08000000)) << 31); -} - -static __inline tilepro_bundle_bits -create_MF_Imm15_X1(int num) -{ - const unsigned int n = (unsigned int)num; - return (((tilepro_bundle_bits)(n & 0x00003fff)) << 37) | - (((tilepro_bundle_bits)(n & 0x00004000)) << 44); -} - -static __inline tilepro_bundle_bits -create_MMEnd_X0(int num) -{ - const unsigned int n = (unsigned int)num; - return ((n & 0x1f) << 18); -} - -static __inline tilepro_bundle_bits -create_MMEnd_X1(int num) -{ - const unsigned int n = (unsigned int)num; - return (((tilepro_bundle_bits)(n & 0x1f)) << 49); -} - -static __inline tilepro_bundle_bits -create_MMStart_X0(int num) -{ - const unsigned int n = (unsigned int)num; - return ((n & 0x1f) << 23); -} - -static __inline tilepro_bundle_bits -create_MMStart_X1(int num) -{ - const unsigned int n = (unsigned int)num; - return (((tilepro_bundle_bits)(n & 0x1f)) << 54); -} - -static __inline tilepro_bundle_bits -create_MT_Imm15_X1(int num) -{ - const unsigned int n = (unsigned int)num; - return (((tilepro_bundle_bits)(n & 0x0000003f)) << 31) | - (((tilepro_bundle_bits)(n & 0x00003fc0)) << 37) | - (((tilepro_bundle_bits)(n & 0x00004000)) << 44); -} - -static __inline tilepro_bundle_bits -create_Mode(int num) -{ - const unsigned int n = (unsigned int)num; - return (((tilepro_bundle_bits)(n & 0x1)) << 63); -} - -static __inline tilepro_bundle_bits -create_NoRegOpcodeExtension_SN(int num) -{ - const unsigned int n = (unsigned int)num; - return ((n & 0xf) << 0); -} - -static __inline tilepro_bundle_bits -create_Opcode_SN(int num) -{ - const unsigned int n = (unsigned int)num; - return ((n & 0x3f) << 10); -} - -static __inline tilepro_bundle_bits -create_Opcode_X0(int num) -{ - const unsigned int n = (unsigned int)num; - return ((n & 0x7) << 28); -} - -static __inline tilepro_bundle_bits -create_Opcode_X1(int num) -{ - const unsigned int n = (unsigned int)num; - return (((tilepro_bundle_bits)(n & 0xf)) << 59); -} - -static __inline tilepro_bundle_bits -create_Opcode_Y0(int num) -{ - const unsigned int n = (unsigned int)num; - return ((n & 0xf) << 27); -} - -static __inline tilepro_bundle_bits -create_Opcode_Y1(int num) -{ - const unsigned int n = (unsigned int)num; - return (((tilepro_bundle_bits)(n & 0xf)) << 59); -} - -static __inline tilepro_bundle_bits -create_Opcode_Y2(int num) -{ - const unsigned int n = (unsigned int)num; - return (((tilepro_bundle_bits)(n & 0x7)) << 56); -} - -static __inline tilepro_bundle_bits -create_RROpcodeExtension_SN(int num) -{ - const unsigned int n = (unsigned int)num; - return ((n & 0xf) << 4); -} - -static __inline tilepro_bundle_bits -create_RRROpcodeExtension_X0(int num) -{ - const unsigned int n = (unsigned int)num; - return ((n & 0x1ff) << 18); -} - -static __inline tilepro_bundle_bits -create_RRROpcodeExtension_X1(int num) -{ - const unsigned int n = (unsigned int)num; - return (((tilepro_bundle_bits)(n & 0x1ff)) << 49); -} - -static __inline tilepro_bundle_bits -create_RRROpcodeExtension_Y0(int num) -{ - const unsigned int n = (unsigned int)num; - return ((n & 0x3) << 18); -} - -static __inline tilepro_bundle_bits -create_RRROpcodeExtension_Y1(int num) -{ - const unsigned int n = (unsigned int)num; - return (((tilepro_bundle_bits)(n & 0x3)) << 49); -} - -static __inline tilepro_bundle_bits -create_RouteOpcodeExtension_SN(int num) -{ - const unsigned int n = (unsigned int)num; - return ((n & 0x3ff) << 0); -} - -static __inline tilepro_bundle_bits -create_S_X0(int num) -{ - const unsigned int n = (unsigned int)num; - return ((n & 0x1) << 27); -} - -static __inline tilepro_bundle_bits -create_S_X1(int num) -{ - const unsigned int n = (unsigned int)num; - return (((tilepro_bundle_bits)(n & 0x1)) << 58); -} - -static __inline tilepro_bundle_bits -create_ShAmt_X0(int num) -{ - const unsigned int n = (unsigned int)num; - return ((n & 0x1f) << 12); -} - -static __inline tilepro_bundle_bits -create_ShAmt_X1(int num) -{ - const unsigned int n = (unsigned int)num; - return (((tilepro_bundle_bits)(n & 0x1f)) << 43); -} - -static __inline tilepro_bundle_bits -create_ShAmt_Y0(int num) -{ - const unsigned int n = (unsigned int)num; - return ((n & 0x1f) << 12); -} - -static __inline tilepro_bundle_bits -create_ShAmt_Y1(int num) -{ - const unsigned int n = (unsigned int)num; - return (((tilepro_bundle_bits)(n & 0x1f)) << 43); -} - -static __inline tilepro_bundle_bits -create_SrcA_X0(int num) -{ - const unsigned int n = (unsigned int)num; - return ((n & 0x3f) << 6); -} - -static __inline tilepro_bundle_bits -create_SrcA_X1(int num) -{ - const unsigned int n = (unsigned int)num; - return (((tilepro_bundle_bits)(n & 0x3f)) << 37); -} - -static __inline tilepro_bundle_bits -create_SrcA_Y0(int num) -{ - const unsigned int n = (unsigned int)num; - return ((n & 0x3f) << 6); -} - -static __inline tilepro_bundle_bits -create_SrcA_Y1(int num) -{ - const unsigned int n = (unsigned int)num; - return (((tilepro_bundle_bits)(n & 0x3f)) << 37); -} - -static __inline tilepro_bundle_bits -create_SrcA_Y2(int num) -{ - const unsigned int n = (unsigned int)num; - return ((n & 0x00000001) << 26) | - (((tilepro_bundle_bits)(n & 0x0000003e)) << 50); -} - -static __inline tilepro_bundle_bits -create_SrcBDest_Y2(int num) -{ - const unsigned int n = (unsigned int)num; - return ((n & 0x3f) << 20); -} - -static __inline tilepro_bundle_bits -create_SrcB_X0(int num) -{ - const unsigned int n = (unsigned int)num; - return ((n & 0x3f) << 12); -} - -static __inline tilepro_bundle_bits -create_SrcB_X1(int num) -{ - const unsigned int n = (unsigned int)num; - return (((tilepro_bundle_bits)(n & 0x3f)) << 43); -} - -static __inline tilepro_bundle_bits -create_SrcB_Y0(int num) -{ - const unsigned int n = (unsigned int)num; - return ((n & 0x3f) << 12); -} - -static __inline tilepro_bundle_bits -create_SrcB_Y1(int num) -{ - const unsigned int n = (unsigned int)num; - return (((tilepro_bundle_bits)(n & 0x3f)) << 43); -} - -static __inline tilepro_bundle_bits -create_Src_SN(int num) -{ - const unsigned int n = (unsigned int)num; - return ((n & 0x3) << 0); -} - -static __inline tilepro_bundle_bits -create_UnOpcodeExtension_X0(int num) -{ - const unsigned int n = (unsigned int)num; - return ((n & 0x1f) << 12); -} - -static __inline tilepro_bundle_bits -create_UnOpcodeExtension_X1(int num) -{ - const unsigned int n = (unsigned int)num; - return (((tilepro_bundle_bits)(n & 0x1f)) << 43); -} - -static __inline tilepro_bundle_bits -create_UnOpcodeExtension_Y0(int num) -{ - const unsigned int n = (unsigned int)num; - return ((n & 0x1f) << 12); -} - -static __inline tilepro_bundle_bits -create_UnOpcodeExtension_Y1(int num) -{ - const unsigned int n = (unsigned int)num; - return (((tilepro_bundle_bits)(n & 0x1f)) << 43); -} - -static __inline tilepro_bundle_bits -create_UnShOpcodeExtension_X0(int num) -{ - const unsigned int n = (unsigned int)num; - return ((n & 0x3ff) << 17); -} - -static __inline tilepro_bundle_bits -create_UnShOpcodeExtension_X1(int num) -{ - const unsigned int n = (unsigned int)num; - return (((tilepro_bundle_bits)(n & 0x3ff)) << 48); -} - -static __inline tilepro_bundle_bits -create_UnShOpcodeExtension_Y0(int num) -{ - const unsigned int n = (unsigned int)num; - return ((n & 0x7) << 17); -} - -static __inline tilepro_bundle_bits -create_UnShOpcodeExtension_Y1(int num) -{ - const unsigned int n = (unsigned int)num; - return (((tilepro_bundle_bits)(n & 0x7)) << 48); -} - - - -typedef enum -{ - TILEPRO_PIPELINE_X0, - TILEPRO_PIPELINE_X1, - TILEPRO_PIPELINE_Y0, - TILEPRO_PIPELINE_Y1, - TILEPRO_PIPELINE_Y2, -} tilepro_pipeline; - -#define tilepro_is_x_pipeline(p) ((int)(p) <= (int)TILEPRO_PIPELINE_X1) - -typedef enum -{ - TILEPRO_OP_TYPE_REGISTER, - TILEPRO_OP_TYPE_IMMEDIATE, - TILEPRO_OP_TYPE_ADDRESS, - TILEPRO_OP_TYPE_SPR -} tilepro_operand_type; - -/* This is the bit that determines if a bundle is in the Y encoding. */ -#define TILEPRO_BUNDLE_Y_ENCODING_MASK ((tilepro_bundle_bits)1 << 63) - -enum -{ - /* Maximum number of instructions in a bundle (2 for X, 3 for Y). */ - TILEPRO_MAX_INSTRUCTIONS_PER_BUNDLE = 3, - - /* How many different pipeline encodings are there? X0, X1, Y0, Y1, Y2. */ - TILEPRO_NUM_PIPELINE_ENCODINGS = 5, - - /* Log base 2 of TILEPRO_BUNDLE_SIZE_IN_BYTES. */ - TILEPRO_LOG2_BUNDLE_SIZE_IN_BYTES = 3, - - /* Instructions take this many bytes. */ - TILEPRO_BUNDLE_SIZE_IN_BYTES = 1 << TILEPRO_LOG2_BUNDLE_SIZE_IN_BYTES, - - /* Log base 2 of TILEPRO_BUNDLE_ALIGNMENT_IN_BYTES. */ - TILEPRO_LOG2_BUNDLE_ALIGNMENT_IN_BYTES = 3, - - /* Bundles should be aligned modulo this number of bytes. */ - TILEPRO_BUNDLE_ALIGNMENT_IN_BYTES = - (1 << TILEPRO_LOG2_BUNDLE_ALIGNMENT_IN_BYTES), - - /* Log base 2 of TILEPRO_SN_INSTRUCTION_SIZE_IN_BYTES. */ - TILEPRO_LOG2_SN_INSTRUCTION_SIZE_IN_BYTES = 1, - - /* Static network instructions take this many bytes. */ - TILEPRO_SN_INSTRUCTION_SIZE_IN_BYTES = - (1 << TILEPRO_LOG2_SN_INSTRUCTION_SIZE_IN_BYTES), - - /* Number of registers (some are magic, such as network I/O). */ - TILEPRO_NUM_REGISTERS = 64, - - /* Number of static network registers. */ - TILEPRO_NUM_SN_REGISTERS = 4 -}; - - -struct tilepro_operand -{ - /* Is this operand a register, immediate or address? */ - tilepro_operand_type type; - - /* The default relocation type for this operand. */ - signed int default_reloc : 16; - - /* How many bits is this value? (used for range checking) */ - unsigned int num_bits : 5; - - /* Is the value signed? (used for range checking) */ - unsigned int is_signed : 1; - - /* Is this operand a source register? */ - unsigned int is_src_reg : 1; - - /* Is this operand written? (i.e. is it a destination register) */ - unsigned int is_dest_reg : 1; - - /* Is this operand PC-relative? */ - unsigned int is_pc_relative : 1; - - /* By how many bits do we right shift the value before inserting? */ - unsigned int rightshift : 2; - - /* Return the bits for this operand to be ORed into an existing bundle. */ - tilepro_bundle_bits (*insert) (int op); - - /* Extract this operand and return it. */ - unsigned int (*extract) (tilepro_bundle_bits bundle); -}; - - -extern const struct tilepro_operand tilepro_operands[]; - -/* One finite-state machine per pipe for rapid instruction decoding. */ -extern const unsigned short * const -tilepro_bundle_decoder_fsms[TILEPRO_NUM_PIPELINE_ENCODINGS]; - - -struct tilepro_opcode -{ - /* The opcode mnemonic, e.g. "add" */ - const char *name; - - /* The enum value for this mnemonic. */ - tilepro_mnemonic mnemonic; - - /* A bit mask of which of the five pipes this instruction - is compatible with: - X0 0x01 - X1 0x02 - Y0 0x04 - Y1 0x08 - Y2 0x10 */ - unsigned char pipes; - - /* How many operands are there? */ - unsigned char num_operands; - - /* Which register does this write implicitly, or TREG_ZERO if none? */ - unsigned char implicitly_written_register; - - /* Can this be bundled with other instructions (almost always true). */ - unsigned char can_bundle; - - /* The description of the operands. Each of these is an - * index into the tilepro_operands[] table. */ - unsigned char operands[TILEPRO_NUM_PIPELINE_ENCODINGS][TILEPRO_MAX_OPERANDS]; - -#if !defined(__KERNEL__) && !defined(_LIBC) - /* A mask of which bits have predefined values for each pipeline. - * This is useful for disassembly. */ - tilepro_bundle_bits fixed_bit_masks[TILEPRO_NUM_PIPELINE_ENCODINGS]; - - /* For each bit set in fixed_bit_masks, what the value is for this - * instruction. */ - tilepro_bundle_bits fixed_bit_values[TILEPRO_NUM_PIPELINE_ENCODINGS]; -#endif -}; - -extern const struct tilepro_opcode tilepro_opcodes[]; - -#if !defined(__KERNEL__) && !defined(_LIBC) - -typedef unsigned short tilepro_sn_instruction_bits; - -struct tilepro_sn_opcode -{ - /* The opcode mnemonic, e.g. "add" */ - const char *name; - - /* The enum value for this mnemonic. */ - tilepro_sn_mnemonic mnemonic; - - /* How many operands are there? */ - unsigned char num_operands; - - /* The description of the operands. Each of these is an - * index into the tilepro_operands[] table. */ - unsigned char operands[TILEPRO_SN_MAX_OPERANDS]; - - /* A mask of which bits have predefined values. - * This is useful for disassembly. */ - tilepro_sn_instruction_bits fixed_bit_mask; - - /* For each bit set in fixed_bit_masks, what its value is. */ - tilepro_sn_instruction_bits fixed_bit_values; -}; - -extern const struct tilepro_sn_opcode tilepro_sn_opcodes[]; - -#endif /* !__KERNEL__ && !_LIBC */ - -/* Used for non-textual disassembly into structs. */ -struct tilepro_decoded_instruction -{ - const struct tilepro_opcode *opcode; - const struct tilepro_operand *operands[TILEPRO_MAX_OPERANDS]; - int operand_values[TILEPRO_MAX_OPERANDS]; -}; - - -/* Disassemble a bundle into a struct for machine processing. */ -extern int parse_insn_tilepro(tilepro_bundle_bits bits, - unsigned int pc, - struct tilepro_decoded_instruction - decoded[TILEPRO_MAX_INSTRUCTIONS_PER_BUNDLE]); - - -/* Given a set of bundle bits and a specific pipe, returns which - * instruction the bundle contains in that pipe. - */ -extern const struct tilepro_opcode * -find_opcode(tilepro_bundle_bits bits, tilepro_pipeline pipe); - - -#if !defined(__KERNEL__) && !defined(_LIBC) -/* Canonical names of all the registers. */ -/* ISSUE: This table lives in "tilepro-dis.c" */ -extern const char * const tilepro_register_names[]; - -/* Descriptor for a special-purpose register. */ -struct tilepro_spr -{ - /* The number */ - int number; - - /* The name */ - const char *name; -}; - -/* List of all the SPRs; ordered by increasing number. */ -extern const struct tilepro_spr tilepro_sprs[]; - -/* Number of special-purpose registers. */ -extern const int tilepro_num_sprs; - -extern const char * -get_tilepro_spr_name (int num); -#endif /* !__KERNEL__ && !_LIBC */ - -/* Make a few "tile_" variables to simply common code between - architectures. */ - -typedef tilepro_bundle_bits tile_bundle_bits; -#define TILE_BUNDLE_SIZE_IN_BYTES TILEPRO_BUNDLE_SIZE_IN_BYTES -#define TILE_BUNDLE_ALIGNMENT_IN_BYTES TILEPRO_BUNDLE_ALIGNMENT_IN_BYTES -#define TILE_LOG2_BUNDLE_ALIGNMENT_IN_BYTES \ - TILEPRO_LOG2_BUNDLE_ALIGNMENT_IN_BYTES - -#endif /* opcode_tilepro_h */ diff --git a/include/opcode/v850.h b/include/opcode/v850.h deleted file mode 100644 index 02ef3d4..0000000 --- a/include/opcode/v850.h +++ /dev/null @@ -1,240 +0,0 @@ -/* v850.h -- Header file for NEC V850 opcode table - Copyright 1996-2013 Free Software Foundation, Inc. - Written by J.T. Conklin, Cygnus Support - - This file is part of GDB, GAS, and the GNU binutils. - - GDB, GAS, and the GNU binutils are free software; you can redistribute - them and/or modify them under the terms of the GNU General Public - License as published by the Free Software Foundation; either version 3, - or (at your option) any later version. - - GDB, GAS, and the GNU binutils are distributed in the hope that they - will be useful, but WITHOUT ANY WARRANTY; without even the implied - warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See - the GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this file; see the file COPYING3. If not, write to the Free - Software Foundation, 51 Franklin Street - Fifth Floor, Boston, - MA 02110-1301, USA. */ - -#ifndef V850_H -#define V850_H - -/* The opcode table is an array of struct v850_opcode. */ - -struct v850_opcode -{ - /* The opcode name. */ - const char *name; - - /* The opcode itself. Those bits which will be filled in with - operands are zeroes. */ - unsigned long opcode; - - /* The opcode mask. This is used by the disassembler. This is a - mask containing ones indicating those bits which must match the - opcode field, and zeroes indicating those bits which need not - match (and are presumably filled in by operands). */ - unsigned long mask; - - /* An array of operand codes. Each code is an index into the - operand table. They appear in the order which the operands must - appear in assembly code, and are terminated by a zero. */ - unsigned char operands[8]; - - /* Which (if any) operand is a memory operand. */ - unsigned int memop; - - /* Target processor(s). A bit field of processors which support - this instruction. Note a bit field is used as some instructions - are available on multiple, different processor types, whereas - other instructions are only available on one specific type. */ - unsigned int processors; -}; - -/* Values for architecture number. */ -#define arch_V850 0 -#define arch_V850E (arch_V850 + 1) -#define arch_V850E1 (arch_V850E + 1) -#define arch_V850E2 (arch_V850E1 + 1) -#define arch_V850E2V3 (arch_V850E2 + 1) -#define arch_V850E3V5 (arch_V850E2V3 + 1) -#define arch_separator (arch_V850E3V5 + 1) - -#define opt_EXTENSION (arch_separator) -#define opt_ALIAS (opt_EXTENSION + 1) - -/* Values for the processors field in the v850_opcode structure. */ -#define PROCESSOR_V850 (1 << (arch_V850)) /* Just the V850. */ -#define PROCESSOR_V850E (1 << (arch_V850E)) /* Just the V850E. */ -#define PROCESSOR_V850E1 (1 << (arch_V850E1)) /* Just the V850E1. */ -#define PROCESSOR_V850E2 (1 << (arch_V850E2)) /* Just the V850E2. */ -#define PROCESSOR_V850E2V3 (1 << (arch_V850E2V3)) /* Just the V850E2V3. */ -#define PROCESSOR_V850E3V5 (1 << (arch_V850E3V5)) /* Just the V850E3V5. */ - -/* UPPERS */ -#define PROCESSOR_V850E3V5_UP (PROCESSOR_V850E3V5) -#define PROCESSOR_V850E2V3_UP (PROCESSOR_V850E2V3 | PROCESSOR_V850E3V5_UP) -#define PROCESSOR_V850E2_UP (PROCESSOR_V850E2 | PROCESSOR_V850E2V3_UP) -#define PROCESSOR_V850E_UP (PROCESSOR_V850E | PROCESSOR_V850E1 | PROCESSOR_V850E2_UP) -#define PROCESSOR_ALL (PROCESSOR_V850 | PROCESSOR_V850E_UP) - -#define PROCESSOR_MASK (PROCESSOR_ALL) -#define PROCESSOR_NOT_V850 (PROCESSOR_ALL & (~ PROCESSOR_V850)) /* Any processor except the V850. */ - -#define PROCESSOR_UNKNOWN ~(PROCESSOR_MASK) - -/* OPTIONS */ -#define PROCESSOR_OPTION_EXTENSION (1 << (opt_EXTENSION)) /* Enable extension opcodes. */ -#define PROCESSOR_OPTION_ALIAS (1 << (opt_ALIAS)) /* Enable alias opcodes. */ - -#define SET_PROCESSOR_MASK(mask,set) ((mask) = ((mask) & ~PROCESSOR_MASK) | (set)) - -/* The table itself is sorted by major opcode number, and is otherwise - in the order in which the disassembler should consider - instructions. */ -extern const struct v850_opcode v850_opcodes[]; -extern const int v850_num_opcodes; - - -/* The operands table is an array of struct v850_operand. */ - -struct v850_operand -{ - /* The number of bits in the operand. */ - /* If this value is -1 then the operand's bits are in a discontinous - distribution in the instruction. */ - int bits; - - /* (bits >= 0): How far the operand is left shifted in the instruction. */ - /* (bits == -1): Bit mask of the bits in the operand. */ - int shift; - - /* Insertion function. This is used by the assembler. To insert an - operand value into an instruction, check this field. - - If it is NULL, execute - i |= (op & ((1 << o->bits) - 1)) << o->shift; - (i is the instruction which we are filling in, o is a pointer to - this structure, and op is the opcode value; this assumes twos - complement arithmetic). - - If this field is not NULL, then simply call it with the - instruction and the operand value. It will return the new value - of the instruction. If the ERRMSG argument is not NULL, then if - the operand value is illegal, *ERRMSG will be set to a warning - string (the operand will be inserted in any case). If the - operand value is legal, *ERRMSG will be unchanged (most operands - can accept any value). */ - unsigned long (* insert) - (unsigned long instruction, long op, const char ** errmsg); - - /* Extraction function. This is used by the disassembler. To - extract this operand type from an instruction, check this field. - - If it is NULL, compute - op = o->bits == -1 ? ((i) & o->shift) : ((i) >> o->shift) & ((1 << o->bits) - 1); - if (o->flags & V850_OPERAND_SIGNED) - op = (op << (32 - o->bits)) >> (32 - o->bits); - (i is the instruction, o is a pointer to this structure, and op - is the result; this assumes twos complement arithmetic). - - If this field is not NULL, then simply call it with the - instruction value. It will return the value of the operand. If - the INVALID argument is not NULL, *INVALID will be set to - non-zero if this operand type can not actually be extracted from - this operand (i.e., the instruction does not match). If the - operand is valid, *INVALID will not be changed. */ - unsigned long (* extract) (unsigned long instruction, int * invalid); - - /* One bit syntax flags. */ - int flags; - - int default_reloc; -}; - -/* Elements in the table are retrieved by indexing with values from - the operands field of the v850_opcodes table. */ - -extern const struct v850_operand v850_operands[]; - -/* Values defined for the flags field of a struct v850_operand. */ - -/* This operand names a general purpose register. */ -#define V850_OPERAND_REG 0x01 - -/* This operand is the ep register. */ -#define V850_OPERAND_EP 0x02 - -/* This operand names a system register. */ -#define V850_OPERAND_SRG 0x04 - -/* Prologue eilogue type instruction, V850E specific. */ -#define V850E_OPERAND_REG_LIST 0x08 - -/* This operand names a condition code used in the setf instruction. */ -#define V850_OPERAND_CC 0x10 - -#define V850_OPERAND_FLOAT_CC 0x20 - -/* This operand names a vector purpose register. */ -#define V850_OPERAND_VREG 0x40 - -/* 16 bit immediate follows instruction, V850E specific. */ -#define V850E_IMMEDIATE16 0x80 - -/* hi16 bit immediate follows instruction, V850E specific. */ -#define V850E_IMMEDIATE16HI 0x100 - -/* 23 bit immediate follows instruction, V850E specific. */ -#define V850E_IMMEDIATE23 0x200 - -/* 32 bit immediate follows instruction, V850E specific. */ -#define V850E_IMMEDIATE32 0x400 - -/* This is a relaxable operand. Only used for D9->D22 branch relaxing - right now. We may need others in the future (or maybe handle them like - promoted operands on the mn10300?). */ -#define V850_OPERAND_RELAX 0x800 - -/* This operand takes signed values. */ -#define V850_OPERAND_SIGNED 0x1000 - -/* This operand is a displacement. */ -#define V850_OPERAND_DISP 0x2000 - -/* This operand is a PC displacement. */ -#define V850_PCREL 0x4000 - -/* The register specified must be even number. */ -#define V850_REG_EVEN 0x8000 - -/* The register specified must not be r0. */ -#define V850_NOT_R0 0x20000 - -/* The register specified must not be 0. */ -#define V850_NOT_IMM0 0x40000 - -/* The condition code must not be SA CONDITION. */ -#define V850_NOT_SA 0x80000 - -/* The operand has '!' prefix. */ -#define V850_OPERAND_BANG 0x100000 - -/* The operand has '%' prefix. */ -#define V850_OPERAND_PERCENT 0x200000 - -/* This operand is a cache oparation. */ -#define V850_OPERAND_CACHEOP 0x400000 - -/* This operand is a prefetch oparation. */ -#define V850_OPERAND_PREFOP 0x800000 - -/* A PC-relative displacement where a positive value indicates a backwards displacement. */ -#define V850_INVERSE_PCREL 0x1000000 - -extern int v850_msg_is_out_of_range (const char *); - -#endif /* V850_H */ diff --git a/include/opcode/vax.h b/include/opcode/vax.h deleted file mode 100644 index f5cdd24..0000000 --- a/include/opcode/vax.h +++ /dev/null @@ -1,383 +0,0 @@ -/* Vax opcde list. - Copyright 1989, 1991, 1992, 1995, 2010 Free Software Foundation, Inc. - - This file is part of GDB and GAS. - - GDB and GAS are free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3, or (at your option) - any later version. - - GDB and GAS are distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with GDB or GAS; see the file COPYING3. If not, write to - the Free Software Foundation, 51 Franklin Street - Fifth Floor, - Boston, MA 02110-1301, USA. */ - -#ifndef vax_opcodeT -#define vax_opcodeT int -#endif /* no vax_opcodeT */ - -struct vot_wot /* vax opcode table: wot to do with this */ - /* particular opcode */ -{ - const char *args; /* how to compile said opcode */ - vax_opcodeT code; /* op-code (may be > 8 bits!) */ -}; - -struct vot /* vax opcode text */ -{ - const char *name; /* opcode name: lowercase string [key] */ - struct vot_wot detail; /* rest of opcode table [datum] */ -}; - -#define vot_how args -#define vot_code code -#define vot_detail detail -#define vot_name name - -static const struct vot -votstrs[] = -{ -{ "halt", {"", 0x00 } }, -{ "nop", {"", 0x01 } }, -{ "rei", {"", 0x02 } }, -{ "bpt", {"", 0x03 } }, -{ "ret", {"", 0x04 } }, -{ "rsb", {"", 0x05 } }, -{ "ldpctx", {"", 0x06 } }, -{ "svpctx", {"", 0x07 } }, -{ "cvtps", {"rwabrwab", 0x08 } }, -{ "cvtsp", {"rwabrwab", 0x09 } }, -{ "index", {"rlrlrlrlrlwl", 0x0a } }, -{ "crc", {"abrlrwab", 0x0b } }, -{ "prober", {"rbrwab", 0x0c } }, -{ "probew", {"rbrwab", 0x0d } }, -{ "insque", {"abab", 0x0e } }, -{ "remque", {"abwl", 0x0f } }, -{ "bsbb", {"bb", 0x10 } }, -{ "brb", {"bb", 0x11 } }, -{ "bneq", {"bb", 0x12 } }, -{ "bnequ", {"bb", 0x12 } }, -{ "beql", {"bb", 0x13 } }, -{ "beqlu", {"bb", 0x13 } }, -{ "bgtr", {"bb", 0x14 } }, -{ "bleq", {"bb", 0x15 } }, -{ "jsb", {"ab", 0x16 } }, -{ "jmp", {"ab", 0x17 } }, -{ "bgeq", {"bb", 0x18 } }, -{ "blss", {"bb", 0x19 } }, -{ "bgtru", {"bb", 0x1a } }, -{ "blequ", {"bb", 0x1b } }, -{ "bvc", {"bb", 0x1c } }, -{ "bvs", {"bb", 0x1d } }, -{ "bcc", {"bb", 0x1e } }, -{ "bgequ", {"bb", 0x1e } }, -{ "blssu", {"bb", 0x1f } }, -{ "bcs", {"bb", 0x1f } }, -{ "addp4", {"rwabrwab", 0x20 } }, -{ "addp6", {"rwabrwabrwab", 0x21 } }, -{ "subp4", {"rwabrwab", 0x22 } }, -{ "subp6", {"rwabrwabrwab", 0x23 } }, -{ "cvtpt", {"rwababrwab", 0x24 } }, -{ "mulp", {"rwabrwabrwab", 0x25 } }, -{ "cvttp", {"rwababrwab", 0x26 } }, -{ "divp", {"rwabrwabrwab", 0x27 } }, -{ "movc3", {"rwabab", 0x28 } }, -{ "cmpc3", {"rwabab", 0x29 } }, -{ "scanc", {"rwababrb", 0x2a } }, -{ "spanc", {"rwababrb", 0x2b } }, -{ "movc5", {"rwabrbrwab", 0x2c } }, -{ "cmpc5", {"rwabrbrwab", 0x2d } }, -{ "movtc", {"rwabrbabrwab", 0x2e } }, -{ "movtuc", {"rwabrbabrwab", 0x2f } }, -{ "bsbw", {"bw", 0x30 } }, -{ "brw", {"bw", 0x31 } }, -{ "cvtwl", {"rwwl", 0x32 } }, -{ "cvtwb", {"rwwb", 0x33 } }, -{ "movp", {"rwabab", 0x34 } }, -{ "cmpp3", {"rwabab", 0x35 } }, -{ "cvtpl", {"rwabwl", 0x36 } }, -{ "cmpp4", {"rwabrwab", 0x37 } }, -{ "editpc", {"rwababab", 0x38 } }, -{ "matchc", {"rwabrwab", 0x39 } }, -{ "locc", {"rbrwab", 0x3a } }, -{ "skpc", {"rbrwab", 0x3b } }, -{ "movzwl", {"rwwl", 0x3c } }, -{ "acbw", {"rwrwmwbw", 0x3d } }, -{ "movaw", {"awwl", 0x3e } }, -{ "pushaw", {"aw", 0x3f } }, -{ "addf2", {"rfmf", 0x40 } }, -{ "addf3", {"rfrfwf", 0x41 } }, -{ "subf2", {"rfmf", 0x42 } }, -{ "subf3", {"rfrfwf", 0x43 } }, -{ "mulf2", {"rfmf", 0x44 } }, -{ "mulf3", {"rfrfwf", 0x45 } }, -{ "divf2", {"rfmf", 0x46 } }, -{ "divf3", {"rfrfwf", 0x47 } }, -{ "cvtfb", {"rfwb", 0x48 } }, -{ "cvtfw", {"rfww", 0x49 } }, -{ "cvtfl", {"rfwl", 0x4a } }, -{ "cvtrfl", {"rfwl", 0x4b } }, -{ "cvtbf", {"rbwf", 0x4c } }, -{ "cvtwf", {"rwwf", 0x4d } }, -{ "cvtlf", {"rlwf", 0x4e } }, -{ "acbf", {"rfrfmfbw", 0x4f } }, -{ "movf", {"rfwf", 0x50 } }, -{ "cmpf", {"rfrf", 0x51 } }, -{ "mnegf", {"rfwf", 0x52 } }, -{ "tstf", {"rf", 0x53 } }, -{ "emodf", {"rfrbrfwlwf", 0x54 } }, -{ "polyf", {"rfrwab", 0x55 } }, -{ "cvtfd", {"rfwd", 0x56 } }, - /* opcode 57 is not defined yet */ -{ "adawi", {"rwmw", 0x58 } }, - /* opcode 59 is not defined yet */ - /* opcode 5a is not defined yet */ - /* opcode 5b is not defined yet */ -{ "insqhi", {"abaq", 0x5c } }, -{ "insqti", {"abaq", 0x5d } }, -{ "remqhi", {"aqwl", 0x5e } }, -{ "remqti", {"aqwl", 0x5f } }, -{ "addd2", {"rdmd", 0x60 } }, -{ "addd3", {"rdrdwd", 0x61 } }, -{ "subd2", {"rdmd", 0x62 } }, -{ "subd3", {"rdrdwd", 0x63 } }, -{ "muld2", {"rdmd", 0x64 } }, -{ "muld3", {"rdrdwd", 0x65 } }, -{ "divd2", {"rdmd", 0x66 } }, -{ "divd3", {"rdrdwd", 0x67 } }, -{ "cvtdb", {"rdwb", 0x68 } }, -{ "cvtdw", {"rdww", 0x69 } }, -{ "cvtdl", {"rdwl", 0x6a } }, -{ "cvtrdl", {"rdwl", 0x6b } }, -{ "cvtbd", {"rbwd", 0x6c } }, -{ "cvtwd", {"rwwd", 0x6d } }, -{ "cvtld", {"rlwd", 0x6e } }, -{ "acbd", {"rdrdmdbw", 0x6f } }, -{ "movd", {"rdwd", 0x70 } }, -{ "cmpd", {"rdrd", 0x71 } }, -{ "mnegd", {"rdwd", 0x72 } }, -{ "tstd", {"rd", 0x73 } }, -{ "emodd", {"rdrbrdwlwd", 0x74 } }, -{ "polyd", {"rdrwab", 0x75 } }, -{ "cvtdf", {"rdwf", 0x76 } }, - /* opcode 77 is not defined yet */ -{ "ashl", {"rbrlwl", 0x78 } }, -{ "ashq", {"rbrqwq", 0x79 } }, -{ "emul", {"rlrlrlwq", 0x7a } }, -{ "ediv", {"rlrqwlwl", 0x7b } }, -{ "clrd", {"wd", 0x7c } }, -{ "clrg", {"wg", 0x7c } }, -{ "clrq", {"wd", 0x7c } }, -{ "movq", {"rqwq", 0x7d } }, -{ "movaq", {"aqwl", 0x7e } }, -{ "movad", {"adwl", 0x7e } }, -{ "pushaq", {"aq", 0x7f } }, -{ "pushad", {"ad", 0x7f } }, -{ "addb2", {"rbmb", 0x80 } }, -{ "addb3", {"rbrbwb", 0x81 } }, -{ "subb2", {"rbmb", 0x82 } }, -{ "subb3", {"rbrbwb", 0x83 } }, -{ "mulb2", {"rbmb", 0x84 } }, -{ "mulb3", {"rbrbwb", 0x85 } }, -{ "divb2", {"rbmb", 0x86 } }, -{ "divb3", {"rbrbwb", 0x87 } }, -{ "bisb2", {"rbmb", 0x88 } }, -{ "bisb3", {"rbrbwb", 0x89 } }, -{ "bicb2", {"rbmb", 0x8a } }, -{ "bicb3", {"rbrbwb", 0x8b } }, -{ "xorb2", {"rbmb", 0x8c } }, -{ "xorb3", {"rbrbwb", 0x8d } }, -{ "mnegb", {"rbwb", 0x8e } }, -{ "caseb", {"rbrbrb", 0x8f } }, -{ "movb", {"rbwb", 0x90 } }, -{ "cmpb", {"rbrb", 0x91 } }, -{ "mcomb", {"rbwb", 0x92 } }, -{ "bitb", {"rbrb", 0x93 } }, -{ "clrb", {"wb", 0x94 } }, -{ "tstb", {"rb", 0x95 } }, -{ "incb", {"mb", 0x96 } }, -{ "decb", {"mb", 0x97 } }, -{ "cvtbl", {"rbwl", 0x98 } }, -{ "cvtbw", {"rbww", 0x99 } }, -{ "movzbl", {"rbwl", 0x9a } }, -{ "movzbw", {"rbww", 0x9b } }, -{ "rotl", {"rbrlwl", 0x9c } }, -{ "acbb", {"rbrbmbbw", 0x9d } }, -{ "movab", {"abwl", 0x9e } }, -{ "pushab", {"ab", 0x9f } }, -{ "addw2", {"rwmw", 0xa0 } }, -{ "addw3", {"rwrwww", 0xa1 } }, -{ "subw2", {"rwmw", 0xa2 } }, -{ "subw3", {"rwrwww", 0xa3 } }, -{ "mulw2", {"rwmw", 0xa4 } }, -{ "mulw3", {"rwrwww", 0xa5 } }, -{ "divw2", {"rwmw", 0xa6 } }, -{ "divw3", {"rwrwww", 0xa7 } }, -{ "bisw2", {"rwmw", 0xa8 } }, -{ "bisw3", {"rwrwww", 0xa9 } }, -{ "bicw2", {"rwmw", 0xaa } }, -{ "bicw3", {"rwrwww", 0xab } }, -{ "xorw2", {"rwmw", 0xac } }, -{ "xorw3", {"rwrwww", 0xad } }, -{ "mnegw", {"rwww", 0xae } }, -{ "casew", {"rwrwrw", 0xaf } }, -{ "movw", {"rwww", 0xb0 } }, -{ "cmpw", {"rwrw", 0xb1 } }, -{ "mcomw", {"rwww", 0xb2 } }, -{ "bitw", {"rwrw", 0xb3 } }, -{ "clrw", {"ww", 0xb4 } }, -{ "tstw", {"rw", 0xb5 } }, -{ "incw", {"mw", 0xb6 } }, -{ "decw", {"mw", 0xb7 } }, -{ "bispsw", {"rw", 0xb8 } }, -{ "bicpsw", {"rw", 0xb9 } }, -{ "popr", {"rw", 0xba } }, -{ "pushr", {"rw", 0xbb } }, -{ "chmk", {"rw", 0xbc } }, -{ "chme", {"rw", 0xbd } }, -{ "chms", {"rw", 0xbe } }, -{ "chmu", {"rw", 0xbf } }, -{ "addl2", {"rlml", 0xc0 } }, -{ "addl3", {"rlrlwl", 0xc1 } }, -{ "subl2", {"rlml", 0xc2 } }, -{ "subl3", {"rlrlwl", 0xc3 } }, -{ "mull2", {"rlml", 0xc4 } }, -{ "mull3", {"rlrlwl", 0xc5 } }, -{ "divl2", {"rlml", 0xc6 } }, -{ "divl3", {"rlrlwl", 0xc7 } }, -{ "bisl2", {"rlml", 0xc8 } }, -{ "bisl3", {"rlrlwl", 0xc9 } }, -{ "bicl2", {"rlml", 0xca } }, -{ "bicl3", {"rlrlwl", 0xcb } }, -{ "xorl2", {"rlml", 0xcc } }, -{ "xorl3", {"rlrlwl", 0xcd } }, -{ "mnegl", {"rlwl", 0xce } }, -{ "casel", {"rlrlrl", 0xcf } }, -{ "movl", {"rlwl", 0xd0 } }, -{ "cmpl", {"rlrl", 0xd1 } }, -{ "mcoml", {"rlwl", 0xd2 } }, -{ "bitl", {"rlrl", 0xd3 } }, -{ "clrf", {"wf", 0xd4 } }, -{ "clrl", {"wl", 0xd4 } }, -{ "tstl", {"rl", 0xd5 } }, -{ "incl", {"ml", 0xd6 } }, -{ "decl", {"ml", 0xd7 } }, -{ "adwc", {"rlml", 0xd8 } }, -{ "sbwc", {"rlml", 0xd9 } }, -{ "mtpr", {"rlrl", 0xda } }, -{ "mfpr", {"rlwl", 0xdb } }, -{ "movpsl", {"wl", 0xdc } }, -{ "pushl", {"rl", 0xdd } }, -{ "moval", {"alwl", 0xde } }, -{ "movaf", {"afwl", 0xde } }, -{ "pushal", {"al", 0xdf } }, -{ "pushaf", {"af", 0xdf } }, -{ "bbs", {"rlvbbb", 0xe0 } }, -{ "bbc", {"rlvbbb", 0xe1 } }, -{ "bbss", {"rlvbbb", 0xe2 } }, -{ "bbcs", {"rlvbbb", 0xe3 } }, -{ "bbsc", {"rlvbbb", 0xe4 } }, -{ "bbcc", {"rlvbbb", 0xe5 } }, -{ "bbssi", {"rlvbbb", 0xe6 } }, -{ "bbcci", {"rlvbbb", 0xe7 } }, -{ "blbs", {"rlbb", 0xe8 } }, -{ "blbc", {"rlbb", 0xe9 } }, -{ "ffs", {"rlrbvbwl", 0xea } }, -{ "ffc", {"rlrbvbwl", 0xeb } }, -{ "cmpv", {"rlrbvbrl", 0xec } }, -{ "cmpzv", {"rlrbvbrl", 0xed } }, -{ "extv", {"rlrbvbwl", 0xee } }, -{ "extzv", {"rlrbvbwl", 0xef } }, -{ "insv", {"rlrlrbvb", 0xf0 } }, -{ "acbl", {"rlrlmlbw", 0xf1 } }, -{ "aoblss", {"rlmlbb", 0xf2 } }, -{ "aobleq", {"rlmlbb", 0xf3 } }, -{ "sobgeq", {"mlbb", 0xf4 } }, -{ "sobgtr", {"mlbb", 0xf5 } }, -{ "cvtlb", {"rlwb", 0xf6 } }, -{ "cvtlw", {"rlww", 0xf7 } }, -{ "ashp", {"rbrwabrbrwab", 0xf8 } }, -{ "cvtlp", {"rlrwab", 0xf9 } }, -{ "callg", {"abab", 0xfa } }, -{ "calls", {"rlab", 0xfb } }, -{ "xfc", {"", 0xfc } }, - /* undefined opcodes here */ -{ "cvtdh", {"rdwh", 0x32fd } }, -{ "cvtgf", {"rgwh", 0x33fd } }, -{ "addg2", {"rgmg", 0x40fd } }, -{ "addg3", {"rgrgwg", 0x41fd } }, -{ "subg2", {"rgmg", 0x42fd } }, -{ "subg3", {"rgrgwg", 0x43fd } }, -{ "mulg2", {"rgmg", 0x44fd } }, -{ "mulg3", {"rgrgwg", 0x45fd } }, -{ "divg2", {"rgmg", 0x46fd } }, -{ "divg3", {"rgrgwg", 0x47fd } }, -{ "cvtgb", {"rgwb", 0x48fd } }, -{ "cvtgw", {"rgww", 0x49fd } }, -{ "cvtgl", {"rgwl", 0x4afd } }, -{ "cvtrgl", {"rgwl", 0x4bfd } }, -{ "cvtbg", {"rbwg", 0x4cfd } }, -{ "cvtwg", {"rwwg", 0x4dfd } }, -{ "cvtlg", {"rlwg", 0x4efd } }, -{ "acbg", {"rgrgmgbw", 0x4ffd } }, -{ "movg", {"rgwg", 0x50fd } }, -{ "cmpg", {"rgrg", 0x51fd } }, -{ "mnegg", {"rgwg", 0x52fd } }, -{ "tstg", {"rg", 0x53fd } }, -{ "emodg", {"rgrwrgwlwg", 0x54fd } }, -{ "polyg", {"rgrwab", 0x55fd } }, -{ "cvtgh", {"rgwh", 0x56fd } }, - /* undefined opcodes here */ -{ "addh2", {"rhmh", 0x60fd } }, -{ "addh3", {"rhrhwh", 0x61fd } }, -{ "subh2", {"rhmh", 0x62fd } }, -{ "subh3", {"rhrhwh", 0x63fd } }, -{ "mulh2", {"rhmh", 0x64fd } }, -{ "mulh3", {"rhrhwh", 0x65fd } }, -{ "divh2", {"rhmh", 0x66fd } }, -{ "divh3", {"rhrhwh", 0x67fd } }, -{ "cvthb", {"rhwb", 0x68fd } }, -{ "cvthw", {"rhww", 0x69fd } }, -{ "cvthl", {"rhwl", 0x6afd } }, -{ "cvtrhl", {"rhwl", 0x6bfd } }, -{ "cvtbh", {"rbwh", 0x6cfd } }, -{ "cvtwh", {"rwwh", 0x6dfd } }, -{ "cvtlh", {"rlwh", 0x6efd } }, -{ "acbh", {"rhrhmhbw", 0x6ffd } }, -{ "movh", {"rhwh", 0x70fd } }, -{ "cmph", {"rhrh", 0x71fd } }, -{ "mnegh", {"rhwh", 0x72fd } }, -{ "tsth", {"rh", 0x73fd } }, -{ "emodh", {"rhrwrhwlwh", 0x74fd } }, -{ "polyh", {"rhrwab", 0x75fd } }, -{ "cvthg", {"rhwg", 0x76fd } }, - /* undefined opcodes here */ -{ "clrh", {"wh", 0x7cfd } }, -{ "clro", {"wo", 0x7cfd } }, -{ "movo", {"rowo", 0x7dfd } }, -{ "movah", {"ahwl", 0x7efd } }, -{ "movao", {"aowl", 0x7efd } }, -{ "pushah", {"ah", 0x7ffd } }, -{ "pushao", {"ao", 0x7ffd } }, - /* undefined opcodes here */ -{ "cvtfh", {"rfwh", 0x98fd } }, -{ "cvtfg", {"rfwg", 0x99fd } }, - /* undefined opcodes here */ -{ "cvthf", {"rhwf", 0xf6fd } }, -{ "cvthd", {"rhwd", 0xf7fd } }, - /* undefined opcodes here */ -{ "bugl", {"rl", 0xfdff } }, -{ "bugw", {"rw", 0xfeff } }, - /* undefined opcodes here */ - -{ "", {"", 0} } /* empty is end sentinel */ - -}; /* votstrs */ - -/* end: vax.opcode.h */ diff --git a/include/opcode/xgate.h b/include/opcode/xgate.h deleted file mode 100644 index 77a521f..0000000 --- a/include/opcode/xgate.h +++ /dev/null @@ -1,120 +0,0 @@ -/* xgate.h -- Freescale XGATE opcode list - Copyright 2010, 2011, 2012 Free Software Foundation, Inc. - Written by Sean Keys (skeys@ipdatasys.com) - - This file is part of the GNU opcodes library. - - This library is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3, or (at your option) - any later version. - - It is distributed in the hope that it will be useful, but WITHOUT - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public - License for more details. - - You should have received a copy of the GNU General Public License - along with this file; see the file COPYING. If not, write to the - Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, - MA 02110-1301, USA. */ - -#ifndef _OPCODE_XGATE_H -#define _OPCODE_XGATE_H - -/* XGATE CCR flag definitions. */ -#define XGATE_N_BIT 0x08 /* XGN - Sign Flag */ -#define XGATE_Z_BIT 0x04 /* XGZ - Zero Flag */ -#define XGATE_V_BIT 0x02 /* XGV - Overflow Flag */ -#define XGATE_C_BIT 0x01 /* XGC - Carry Flag */ - -/* Access Detail Notation - V — Vector fetch: always an aligned word read, lasts for at least one RISC core cycle - P — Program word fetch: always an aligned word read, lasts for at least one RISC core cycle - r — 8-bit data read: lasts for at least one RISC core cycle - R — 16-bit data read: lasts for at least one RISC core cycle - w — 8-bit data write: lasts for at least one RISC core cycle - W — 16-bit data write: lasts for at least one RISC core cycle - A — Alignment cycle: no read or write, lasts for zero or one RISC core cycles - f — Free cycle: no read or write, lasts for one RISC core cycles. */ -#define XGATE_CYCLE_V 0x01 -#define XGATE_CYCLE_P 0x02 -#define XGATE_CYCLE_r 0x04 -#define XGATE_CYCLE_R 0x08 -#define XGATE_CYCLE_w 0x10 -#define XGATE_CYCLE_W 0x20 -#define XGATE_CYCLE_A 0x40 -#define XGATE_CYCLE_f 0x80 - -/* Opcode format abbreviations. */ -#define XG_INH 0x0001 /* Inherent. */ -#define XG_I 0x0002 /* 3-bit immediate address. */ -#define XG_R_I 0x0004 /* Register followed by 4/8-bit immediate value. */ -#define XG_R_R 0x0008 /* Register followed by a register. */ -#define XG_R_R_R 0x0010 /* Register followed by two registers. */ -#define XG_R 0x0020 /* Single register. */ -#define XG_PC 0x0040 /* PC relative 10 or 11 bit. */ -#define XG_R_C 0x0080 /* General register followed by ccr register. */ -#define XG_C_R 0x0100 /* CCR register followed by a general register. */ -#define XG_R_P 0x0200 /* General register followed by pc register. */ -#define XG_R_R_I 0x0400 /* Two general registers followed by an immediate value. */ -#define XG_PCREL 0x0800 /* Immediate value that is relative to the current pc. */ - -/* XGATE operand formats as stored in the XGATE_opcode table. - They are only used by GAS to recognize operands. */ -#define XGATE_OP_INH "" -#define XGATE_OP_TRI "r,r,r" -#define XGATE_OP_DYA "r,r" -#define XGATE_OP_IMM16 "r,if" -#define XGATE_OP_IMM8 "r,i8" -#define XGATE_OP_IMM4 "r,i4" -#define XGATE_OP_IMM3 "i3" -#define XGATE_OP_MON "r" -#define XGATE_OP_MON_R_C "r,c" -#define XGATE_OP_MON_C_R "c,r" -#define XGATE_OP_MON_R_P "r,p" -#define XGATE_OP_IDR "r,r,+" -#define XGATE_OP_IDO5 "r,r,i5" -#define XGATE_OP_REL9 "b9" -#define XGATE_OP_REL10 "ba" -#define XGATE_OP_DYA_MON "=r" -/* Macro definitions. */ -#define XGATE_OP_IMM16mADD "r,if; addl addh" -#define XGATE_OP_IMM16mAND "r,if; andl andh" -#define XGATE_OP_IMM16mCPC "r,if; cmpl cpch" -#define XGATE_OP_IMM16mSUB "r,if; subl subh" -#define XGATE_OP_IMM16mLDW "r,if; ldl ldh" - -/* CPU variant identification. */ -#define XGATE_V1 0x1 -#define XGATE_V2 0x2 -#define XGATE_V3 0x4 - -/* Max opcodes per opcode handle. */ -#define MAX_OPCODES 0x05 - -#define MAX_DETECT_CHARS 0x10 - -/* The opcode table definitions. */ -struct xgate_opcode -{ - char * name; /* Op-code name. */ - char * constraints; /* Constraint chars. */ - char * format; /* Bit definitions. */ - unsigned int sh_format; /* Shorthand format mask. */ - unsigned int size; /* Opcode size in bytes. */ - unsigned int bin_opcode; /* Binary opcode with operands masked off. */ - unsigned char cycles_min; /* Minimum cpu cycles needed. */ - unsigned char cycles_max; /* Maximum cpu cycles needed. */ - unsigned char set_flags_mask; /* CCR flags set. */ - unsigned char clr_flags_mask; /* CCR flags cleared. */ - unsigned char chg_flags_mask; /* CCR flags changed. */ - unsigned char arch; /* CPU variant. */ -}; - -/* The opcode table. The table contains all the opcodes (all pages). - You can't rely on the order. */ -extern const struct xgate_opcode xgate_opcodes[]; -extern const int xgate_num_opcodes; - -#endif /* _OPCODE_XGATE_H */ |