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| author | Srinath Parvathaneni <srinath.parvathaneni@arm.com> | 2023-03-03 12:45:40 +0000 |
|---|---|---|
| committer | Richard Earnshaw <rearnsha@arm.com> | 2023-03-03 13:20:29 +0000 |
| commit | b782dcb2b363974da249c94adedd95d218d89bef (patch) | |
| tree | adc6af5c8882a0883cd3b309278cfed5fae02c97 /libgloss/arm | |
| parent | 68db1fa7babf9c9c19b36fa4cf4bb747190c0769 (diff) | |
| download | newlib-b782dcb2b363974da249c94adedd95d218d89bef.zip newlib-b782dcb2b363974da249c94adedd95d218d89bef.tar.gz newlib-b782dcb2b363974da249c94adedd95d218d89bef.tar.bz2 | |
arm: Fix the SP used in setting stack limit for standalone application.
Move the instruction that saves SP before the mode check so that
applications that start in USER mode correctly set the stack limit.
Diffstat (limited to 'libgloss/arm')
| -rw-r--r-- | libgloss/arm/crt0.S | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/libgloss/arm/crt0.S b/libgloss/arm/crt0.S index 7851518..79ae1e2 100644 --- a/libgloss/arm/crt0.S +++ b/libgloss/arm/crt0.S @@ -149,13 +149,12 @@ #if (__ARM_ARCH_PROFILE != 'M') /* Following code is compatible for both ARM and Thumb ISA. */ mrs r4, CPSR + mov r3, sp /* Save input SP value. */ /* Test mode bits - in User of all are 0. */ tst r4, #(CPSR_M_MASK) /* "eq" means r4 AND #0x0F is 0. */ beq .Lskip_cpu_modes - mov r3, sp /* Save input SP value. */ - /* FIQ mode, interrupts disabled. */ mov r1, #(CPSR_M_FIQ|CPSR_M_32BIT|CPSR_I_MASK|CPSR_F_MASK) msr CPSR_c, r1 |