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| author | David S. Miller <davem@davemloft.net> | 2011-08-05 16:52:48 +0000 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2011-08-05 16:52:48 +0000 |
| commit | 1ae83025399d564b40eebf64539e1da320fe311b (patch) | |
| tree | 0b0c7fc082b75692e5acb7e6b9d4207a92412099 /include | |
| parent | e5366c218d1a7f67566cc20ce65818f06ce4e574 (diff) | |
| download | newlib-1ae83025399d564b40eebf64539e1da320fe311b.zip newlib-1ae83025399d564b40eebf64539e1da320fe311b.tar.gz newlib-1ae83025399d564b40eebf64539e1da320fe311b.tar.bz2 | |
include/opcode/
* sparc.h: Document new format codes '4', '5', and '('.
(OPF_LOW4, RS3): New macros.
opcodes/
* sparc-dis.c (v9a_ast_reg_names): Add "cps".
(X_RS3): New macro.
(print_insn_sparc): Handle '4', '5', and '(' format codes.
Accept %asr numbers below 28.
* sparc-opc.c (sparc_opcodes): Add entries for HPC and VIS3
instructions.
gas/
* config/tc-sparc.c (v9a_asr_table): Add "cps".
(sparc_ip): Handle '4', '5' and '(' format codes.
gas/testsuite
* gas/sparc/hpcvis3.d: New test.
* gas/sparc/hpcvis3.s: New test source.
* gas/sparc/sparc.exp: Run new test.
Diffstat (limited to 'include')
| -rw-r--r-- | include/opcode/ChangeLog | 5 | ||||
| -rw-r--r-- | include/opcode/sparc.h | 8 |
2 files changed, 10 insertions, 3 deletions
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog index b21812e..84b862f 100644 --- a/include/opcode/ChangeLog +++ b/include/opcode/ChangeLog @@ -1,3 +1,8 @@ +2011-08-05 David S. Miller <davem@davemloft.net> + + * sparc.h: Document new format codes '4', '5', and '('. + (OPF_LOW4, RS3): New macros. + 2011-08-03 Maciej W. Rozycki <macro@codesourcery.com> * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the diff --git a/include/opcode/sparc.h b/include/opcode/sparc.h index 0d6511c..7203df7 100644 --- a/include/opcode/sparc.h +++ b/include/opcode/sparc.h @@ -131,6 +131,8 @@ typedef struct sparc_opcode f frs2 floating point register. B frs2 floating point register (double/even). R frs2 floating point register (quad/multiple of 4). + 4 frs3 floating point register. + 5 frs3 floating point register (doube/even). g frsd floating point register. H frsd floating point register (double/even). J frsd floating point register (quad/multiple of 4). @@ -187,15 +189,14 @@ typedef struct sparc_opcode 0 32/64 bit immediate for set or setx (v9) insns _ Ancillary state register in rd (v9a) / Ancillary state register in rs1 (v9a) - - The following chars are unused: (note: ,[] are used as punctuation) - [45]. */ + ( entire floating point state register (%efsr). */ #define OP2(x) (((x) & 0x7) << 22) /* Op2 field of format2 insns. */ #define OP3(x) (((x) & 0x3f) << 19) /* Op3 field of format3 insns. */ #define OP(x) ((unsigned) ((x) & 0x3) << 30) /* Op field of all insns. */ #define OPF(x) (((x) & 0x1ff) << 5) /* Opf field of float insns. */ #define OPF_LOW5(x) OPF ((x) & 0x1f) /* V9. */ +#define OPF_LOW4(x) OPF ((x) & 0xf) /* V9. */ #define F3F(x, y, z) (OP (x) | OP3 (y) | OPF (z)) /* Format3 float insns. */ #define F3I(x) (((x) & 0x1) << 13) /* Immediate field of format 3 insns. */ #define F2(x, y) (OP (x) | OP2(y)) /* Format 2 insns. */ @@ -207,6 +208,7 @@ typedef struct sparc_opcode #define SIMM13(x) ((x) & 0x1fff) /* Simm13 field. */ #define RD(x) (((x) & 0x1f) << 25) /* Destination register field. */ #define RS1(x) (((x) & 0x1f) << 14) /* Rs1 field. */ +#define RS3(x) (((x) & 0x1f) << 9) /* Rs3 field. */ #define ASI_RS2(x) (SIMM13 (x)) #define MEMBAR(x) ((x) & 0x7f) #define SLCPOP(x) (((x) & 0x7f) << 6) /* Sparclet cpop. */ |