diff options
author | Alexey Lapshin <alexey.lapshin@espressif.com> | 2023-08-17 02:05:53 +0400 |
---|---|---|
committer | Jeff Johnston <jjohnstn@redhat.com> | 2023-08-17 18:14:15 -0400 |
commit | 7ba103eb1a95703c7803e4ca48e6ba5c8e1f3d56 (patch) | |
tree | 36b6a578131e28363728a2ed685d66348c747d78 | |
parent | 65d34484e9097fd9036dd577028423355cb5f5bc (diff) | |
download | newlib-7ba103eb1a95703c7803e4ca48e6ba5c8e1f3d56.zip newlib-7ba103eb1a95703c7803e4ca48e6ba5c8e1f3d56.tar.gz newlib-7ba103eb1a95703c7803e4ca48e6ba5c8e1f3d56.tar.bz2 |
newlib: add Xtensa port
42 files changed, 3646 insertions, 255 deletions
diff --git a/newlib/Makefile.in b/newlib/Makefile.in index 93a97b5..6c7a7ae 100644 --- a/newlib/Makefile.in +++ b/newlib/Makefile.in @@ -585,8 +585,9 @@ check_PROGRAMS = @HAVE_LIBC_SYS_TIRTOS_DIR_TRUE@am__append_62 = libc/sys/tirtos/lock.c @HAVE_LIBC_SYS_W65_DIR_TRUE@am__append_63 = libc/sys/w65/syscalls.c libc/sys/w65/trap.c -@HAVE_LIBC_SYS_Z8KSIM_DIR_TRUE@am__append_64 = libc/sys/z8ksim/glue.c -@HAVE_LIBC_MACHINE_AARCH64_TRUE@am__append_65 = \ +@HAVE_LIBC_SYS_XTENSA_DIR_TRUE@am__append_64 = libc/sys/xtensa/creat.c libc/sys/xtensa/isatty.c libc/sys/xtensa/clibrary_init.c +@HAVE_LIBC_SYS_Z8KSIM_DIR_TRUE@am__append_65 = libc/sys/z8ksim/glue.c +@HAVE_LIBC_MACHINE_AARCH64_TRUE@am__append_66 = \ @HAVE_LIBC_MACHINE_AARCH64_TRUE@ libc/machine/aarch64/memchr-stub.c \ @HAVE_LIBC_MACHINE_AARCH64_TRUE@ libc/machine/aarch64/memchr.S \ @HAVE_LIBC_MACHINE_AARCH64_TRUE@ libc/machine/aarch64/memcmp-stub.c \ @@ -619,7 +620,7 @@ check_PROGRAMS = @HAVE_LIBC_MACHINE_AARCH64_TRUE@ libc/machine/aarch64/strrchr-stub.c \ @HAVE_LIBC_MACHINE_AARCH64_TRUE@ libc/machine/aarch64/strrchr.S -@HAVE_LIBC_MACHINE_AMDGCN_TRUE@am__append_66 = \ +@HAVE_LIBC_MACHINE_AMDGCN_TRUE@am__append_67 = \ @HAVE_LIBC_MACHINE_AMDGCN_TRUE@ libc/machine/amdgcn/abort.c \ @HAVE_LIBC_MACHINE_AMDGCN_TRUE@ libc/machine/amdgcn/exit.c \ @HAVE_LIBC_MACHINE_AMDGCN_TRUE@ libc/machine/amdgcn/atexit.c \ @@ -627,7 +628,7 @@ check_PROGRAMS = @HAVE_LIBC_MACHINE_AMDGCN_TRUE@ libc/machine/amdgcn/getreent.c \ @HAVE_LIBC_MACHINE_AMDGCN_TRUE@ libc/machine/amdgcn/signal.c -@HAVE_LIBC_MACHINE_ARC_TRUE@am__append_67 = \ +@HAVE_LIBC_MACHINE_ARC_TRUE@am__append_68 = \ @HAVE_LIBC_MACHINE_ARC_TRUE@ libc/machine/arc/memcmp.S \ @HAVE_LIBC_MACHINE_ARC_TRUE@ libc/machine/arc/memcmp-bs-norm.S \ @HAVE_LIBC_MACHINE_ARC_TRUE@ libc/machine/arc/memcmp-stub.c \ @@ -659,7 +660,7 @@ check_PROGRAMS = @HAVE_LIBC_MACHINE_ARC_TRUE@ libc/machine/arc/strncpy-stub.c \ @HAVE_LIBC_MACHINE_ARC_TRUE@ libc/machine/arc/strncpy-bs.S -@HAVE_LIBC_MACHINE_ARM_TRUE@am__append_68 = \ +@HAVE_LIBC_MACHINE_ARM_TRUE@am__append_69 = \ @HAVE_LIBC_MACHINE_ARM_TRUE@ libc/machine/arm/setjmp.S libc/machine/arm/strcmp.S libc/machine/arm/strcpy.c \ @HAVE_LIBC_MACHINE_ARM_TRUE@ libc/machine/arm/aeabi_memcpy.c libc/machine/arm/aeabi_memcpy-armv7a.S \ @HAVE_LIBC_MACHINE_ARM_TRUE@ libc/machine/arm/aeabi_memmove.c libc/machine/arm/aeabi_memmove-soft.S \ @@ -671,39 +672,39 @@ check_PROGRAMS = @HAVE_LIBC_MACHINE_ARM_TRUE@ libc/machine/arm/strlen-stub.c \ @HAVE_LIBC_MACHINE_ARM_TRUE@ libc/machine/arm/strlen.S -@HAVE_LIBC_MACHINE_BFIN_TRUE@am__append_69 = libc/machine/bfin/setjmp.S libc/machine/bfin/longjmp.S -@HAVE_LIBC_MACHINE_CR16_TRUE@am__append_70 = libc/machine/cr16/setjmp.S libc/machine/cr16/getenv.c -@HAVE_LIBC_MACHINE_CRIS_TRUE@am__append_71 = libc/machine/cris/setjmp.c libc/machine/cris/memcpy.c libc/machine/cris/memset.c libc/machine/cris/memmove.c libc/machine/cris/libcdtor.c +@HAVE_LIBC_MACHINE_BFIN_TRUE@am__append_70 = libc/machine/bfin/setjmp.S libc/machine/bfin/longjmp.S +@HAVE_LIBC_MACHINE_CR16_TRUE@am__append_71 = libc/machine/cr16/setjmp.S libc/machine/cr16/getenv.c +@HAVE_LIBC_MACHINE_CRIS_TRUE@am__append_72 = libc/machine/cris/setjmp.c libc/machine/cris/memcpy.c libc/machine/cris/memset.c libc/machine/cris/memmove.c libc/machine/cris/libcdtor.c # We also make a library with just the useful # machine-but-not-system-specific functions, usable as an add-on # by itself together with e.g. uclibc. -@HAVE_LIBC_MACHINE_CRIS_TRUE@am__append_72 = libc/machine/cris/libic.a -@HAVE_LIBC_MACHINE_CRX_TRUE@am__append_73 = libc/machine/crx/setjmp.S libc/machine/crx/getenv.c -@HAVE_LIBC_MACHINE_CSKY_TRUE@am__append_74 = libc/machine/csky/setjmp.S -@HAVE_LIBC_MACHINE_D10V_TRUE@am__append_75 = libc/machine/d10v/setjmp.S -@HAVE_LIBC_MACHINE_D30V_TRUE@am__append_76 = libc/machine/d30v/setjmp.S -@HAVE_LIBC_MACHINE_EPIPHANY_TRUE@am__append_77 = libc/machine/epiphany/setjmp.S -@HAVE_LIBC_MACHINE_FR30_TRUE@am__append_78 = libc/machine/fr30/setjmp.S -@HAVE_LIBC_MACHINE_FRV_TRUE@am__append_79 = libc/machine/frv/setjmp.S -@HAVE_LIBC_MACHINE_FT32_TRUE@am__append_80 = libc/machine/ft32/setjmp.S libc/machine/ft32/strlen.S libc/machine/ft32/memcpy.S libc/machine/ft32/strcmp.S libc/machine/ft32/memset.S libc/machine/ft32/strcpy.S -@HAVE_LIBC_MACHINE_H8300_TRUE@am__append_81 = \ +@HAVE_LIBC_MACHINE_CRIS_TRUE@am__append_73 = libc/machine/cris/libic.a +@HAVE_LIBC_MACHINE_CRX_TRUE@am__append_74 = libc/machine/crx/setjmp.S libc/machine/crx/getenv.c +@HAVE_LIBC_MACHINE_CSKY_TRUE@am__append_75 = libc/machine/csky/setjmp.S +@HAVE_LIBC_MACHINE_D10V_TRUE@am__append_76 = libc/machine/d10v/setjmp.S +@HAVE_LIBC_MACHINE_D30V_TRUE@am__append_77 = libc/machine/d30v/setjmp.S +@HAVE_LIBC_MACHINE_EPIPHANY_TRUE@am__append_78 = libc/machine/epiphany/setjmp.S +@HAVE_LIBC_MACHINE_FR30_TRUE@am__append_79 = libc/machine/fr30/setjmp.S +@HAVE_LIBC_MACHINE_FRV_TRUE@am__append_80 = libc/machine/frv/setjmp.S +@HAVE_LIBC_MACHINE_FT32_TRUE@am__append_81 = libc/machine/ft32/setjmp.S libc/machine/ft32/strlen.S libc/machine/ft32/memcpy.S libc/machine/ft32/strcmp.S libc/machine/ft32/memset.S libc/machine/ft32/strcpy.S +@HAVE_LIBC_MACHINE_H8300_TRUE@am__append_82 = \ @HAVE_LIBC_MACHINE_H8300_TRUE@ libc/machine/h8300/reg_memcpy.S libc/machine/h8300/reg_memset.S libc/machine/h8300/strcmp.S libc/machine/h8300/memcpy.S libc/machine/h8300/memset.S \ @HAVE_LIBC_MACHINE_H8300_TRUE@ libc/machine/h8300/setjmp.S libc/machine/h8300/h8sx_strcpy.S -@HAVE_LIBC_MACHINE_H8500_TRUE@am__append_82 = libc/machine/h8500/divsi3.c libc/machine/h8500/mulsi3.c libc/machine/h8500/divhi3.S libc/machine/h8500/shifts.c libc/machine/h8500/cmpsi.c libc/machine/h8500/psi.S libc/machine/h8500/setjmp.S -@HAVE_LIBC_MACHINE_HPPA_TRUE@am__append_83 = \ +@HAVE_LIBC_MACHINE_H8500_TRUE@am__append_83 = libc/machine/h8500/divsi3.c libc/machine/h8500/mulsi3.c libc/machine/h8500/divhi3.S libc/machine/h8500/shifts.c libc/machine/h8500/cmpsi.c libc/machine/h8500/psi.S libc/machine/h8500/setjmp.S +@HAVE_LIBC_MACHINE_HPPA_TRUE@am__append_84 = \ @HAVE_LIBC_MACHINE_HPPA_TRUE@ libc/machine/hppa/memchr.S libc/machine/hppa/memcmp.S libc/machine/hppa/memcpy.S libc/machine/hppa/memset.S \ @HAVE_LIBC_MACHINE_HPPA_TRUE@ libc/machine/hppa/setjmp.S \ @HAVE_LIBC_MACHINE_HPPA_TRUE@ libc/machine/hppa/strcat.S libc/machine/hppa/strcmp.S \ @HAVE_LIBC_MACHINE_HPPA_TRUE@ libc/machine/hppa/strcpy.S libc/machine/hppa/strlen.S libc/machine/hppa/strncat.S libc/machine/hppa/strncmp.S libc/machine/hppa/strncpy.S -@HAVE_LIBC_MACHINE_I386_TRUE@@MACH_ADD_SETJMP_TRUE@am__append_84 = libc/machine/i386/setjmp.S -@HAVE_LIBC_MACHINE_I386_TRUE@am__append_85 = \ +@HAVE_LIBC_MACHINE_I386_TRUE@@MACH_ADD_SETJMP_TRUE@am__append_85 = libc/machine/i386/setjmp.S +@HAVE_LIBC_MACHINE_I386_TRUE@am__append_86 = \ @HAVE_LIBC_MACHINE_I386_TRUE@ libc/machine/i386/memchr.S libc/machine/i386/memcmp.S libc/machine/i386/memcpy.S libc/machine/i386/memset.S libc/machine/i386/strchr.S \ @HAVE_LIBC_MACHINE_I386_TRUE@ libc/machine/i386/memmove.S libc/machine/i386/strlen.S libc/machine/i386/i386mach.h -@HAVE_LIBC_MACHINE_I960_TRUE@am__append_86 = \ +@HAVE_LIBC_MACHINE_I960_TRUE@am__append_87 = \ @HAVE_LIBC_MACHINE_I960_TRUE@ libc/machine/i960/memccpy_ca.S \ @HAVE_LIBC_MACHINE_I960_TRUE@ libc/machine/i960/memccpy.S \ @HAVE_LIBC_MACHINE_I960_TRUE@ libc/machine/i960/memchr_ca.S \ @@ -733,43 +734,43 @@ check_PROGRAMS = @HAVE_LIBC_MACHINE_I960_TRUE@ libc/machine/i960/strpbrk.S \ @HAVE_LIBC_MACHINE_I960_TRUE@ libc/machine/i960/strrchr.S -@HAVE_LIBC_MACHINE_IQ2000_TRUE@am__append_87 = libc/machine/iq2000/setjmp.S -@HAVE_LIBC_MACHINE_LM32_TRUE@am__append_88 = libc/machine/lm32/setjmp.S -@HAVE_LIBC_MACHINE_M32C_TRUE@am__append_89 = libc/machine/m32c/setjmp.S -@HAVE_LIBC_MACHINE_M32R_TRUE@am__append_90 = libc/machine/m32r/setjmp.S -@HAVE_LIBC_MACHINE_M68HC11_TRUE@am__append_91 = libc/machine/m68hc11/setjmp.S -@HAVE_LIBC_MACHINE_M68K_TRUE@am__append_92 = libc/machine/m68k/setjmp.S libc/machine/m68k/strcpy.c libc/machine/m68k/strlen.c libc/machine/m68k/memcpy.S libc/machine/m68k/memset.S -@HAVE_LIBC_MACHINE_M88K_TRUE@am__append_93 = libc/machine/m88k/setjmp.S -@HAVE_LIBC_MACHINE_MEP_TRUE@am__append_94 = libc/machine/mep/setjmp.S -@HAVE_LIBC_MACHINE_MICROBLAZE_TRUE@am__append_95 = libc/machine/microblaze/strlen.c libc/machine/microblaze/strcmp.c libc/machine/microblaze/strcpy.c libc/machine/microblaze/setjmp.S libc/machine/microblaze/longjmp.S -@HAVE_LIBC_MACHINE_MIPS_TRUE@am__append_96 = libc/machine/mips/setjmp.S libc/machine/mips/strlen.c libc/machine/mips/strcmp.S libc/machine/mips/strncpy.c libc/machine/mips/memset.S libc/machine/mips/memcpy.S -@HAVE_LIBC_MACHINE_MN10200_TRUE@am__append_97 = libc/machine/mn10200/setjmp.S -@HAVE_LIBC_MACHINE_MN10300_TRUE@am__append_98 = \ +@HAVE_LIBC_MACHINE_IQ2000_TRUE@am__append_88 = libc/machine/iq2000/setjmp.S +@HAVE_LIBC_MACHINE_LM32_TRUE@am__append_89 = libc/machine/lm32/setjmp.S +@HAVE_LIBC_MACHINE_M32C_TRUE@am__append_90 = libc/machine/m32c/setjmp.S +@HAVE_LIBC_MACHINE_M32R_TRUE@am__append_91 = libc/machine/m32r/setjmp.S +@HAVE_LIBC_MACHINE_M68HC11_TRUE@am__append_92 = libc/machine/m68hc11/setjmp.S +@HAVE_LIBC_MACHINE_M68K_TRUE@am__append_93 = libc/machine/m68k/setjmp.S libc/machine/m68k/strcpy.c libc/machine/m68k/strlen.c libc/machine/m68k/memcpy.S libc/machine/m68k/memset.S +@HAVE_LIBC_MACHINE_M88K_TRUE@am__append_94 = libc/machine/m88k/setjmp.S +@HAVE_LIBC_MACHINE_MEP_TRUE@am__append_95 = libc/machine/mep/setjmp.S +@HAVE_LIBC_MACHINE_MICROBLAZE_TRUE@am__append_96 = libc/machine/microblaze/strlen.c libc/machine/microblaze/strcmp.c libc/machine/microblaze/strcpy.c libc/machine/microblaze/setjmp.S libc/machine/microblaze/longjmp.S +@HAVE_LIBC_MACHINE_MIPS_TRUE@am__append_97 = libc/machine/mips/setjmp.S libc/machine/mips/strlen.c libc/machine/mips/strcmp.S libc/machine/mips/strncpy.c libc/machine/mips/memset.S libc/machine/mips/memcpy.S +@HAVE_LIBC_MACHINE_MN10200_TRUE@am__append_98 = libc/machine/mn10200/setjmp.S +@HAVE_LIBC_MACHINE_MN10300_TRUE@am__append_99 = \ @HAVE_LIBC_MACHINE_MN10300_TRUE@ libc/machine/mn10300/setjmp.S libc/machine/mn10300/memchr.S libc/machine/mn10300/memcmp.S libc/machine/mn10300/memcpy.S libc/machine/mn10300/memset.S libc/machine/mn10300/strchr.S \ @HAVE_LIBC_MACHINE_MN10300_TRUE@ libc/machine/mn10300/strcmp.S libc/machine/mn10300/strcpy.S libc/machine/mn10300/strlen.S -@HAVE_LIBC_MACHINE_MOXIE_TRUE@am__append_99 = libc/machine/moxie/setjmp.S -@HAVE_LIBC_MACHINE_MSP430_TRUE@am__append_100 = libc/machine/msp430/setjmp.S -@HAVE_LIBC_MACHINE_MSP430_TRUE@@NEWLIB_NANO_FORMATTED_IO_TRUE@am__append_101 = libc/machine/msp430/tiny-puts.c libc/machine/msp430/tiny-printf.c -@HAVE_LIBC_MACHINE_MT_TRUE@am__append_102 = libc/machine/mt/setjmp.S -@HAVE_LIBC_MACHINE_NDS32_TRUE@am__append_103 = \ +@HAVE_LIBC_MACHINE_MOXIE_TRUE@am__append_100 = libc/machine/moxie/setjmp.S +@HAVE_LIBC_MACHINE_MSP430_TRUE@am__append_101 = libc/machine/msp430/setjmp.S +@HAVE_LIBC_MACHINE_MSP430_TRUE@@NEWLIB_NANO_FORMATTED_IO_TRUE@am__append_102 = libc/machine/msp430/tiny-puts.c libc/machine/msp430/tiny-printf.c +@HAVE_LIBC_MACHINE_MT_TRUE@am__append_103 = libc/machine/mt/setjmp.S +@HAVE_LIBC_MACHINE_NDS32_TRUE@am__append_104 = \ @HAVE_LIBC_MACHINE_NDS32_TRUE@ libc/machine/nds32/abort.c \ @HAVE_LIBC_MACHINE_NDS32_TRUE@ libc/machine/nds32/setjmp.S \ @HAVE_LIBC_MACHINE_NDS32_TRUE@ libc/machine/nds32/strcmp.S \ @HAVE_LIBC_MACHINE_NDS32_TRUE@ libc/machine/nds32/strcpy.S -@HAVE_LIBC_MACHINE_NDS32_TRUE@@IS_NDS32_ISA_V3M_FALSE@am__append_104 = libc/machine/nds32/memcpy.S libc/machine/nds32/memset.S -@HAVE_LIBC_MACHINE_NECV70_TRUE@am__append_105 = libc/machine/necv70/fastmath.S libc/machine/necv70/setjmp.S -@HAVE_LIBC_MACHINE_NIOS2_TRUE@am__append_106 = libc/machine/nios2/setjmp.s -@HAVE_LIBC_MACHINE_NVPTX_TRUE@am__append_107 = \ +@HAVE_LIBC_MACHINE_NDS32_TRUE@@IS_NDS32_ISA_V3M_FALSE@am__append_105 = libc/machine/nds32/memcpy.S libc/machine/nds32/memset.S +@HAVE_LIBC_MACHINE_NECV70_TRUE@am__append_106 = libc/machine/necv70/fastmath.S libc/machine/necv70/setjmp.S +@HAVE_LIBC_MACHINE_NIOS2_TRUE@am__append_107 = libc/machine/nios2/setjmp.s +@HAVE_LIBC_MACHINE_NVPTX_TRUE@am__append_108 = \ @HAVE_LIBC_MACHINE_NVPTX_TRUE@ libc/machine/nvptx/_exit.c \ @HAVE_LIBC_MACHINE_NVPTX_TRUE@ libc/machine/nvptx/calloc.c libc/machine/nvptx/callocr.c libc/machine/nvptx/malloc.c libc/machine/nvptx/mallocr.c libc/machine/nvptx/realloc.c libc/machine/nvptx/reallocr.c \ @HAVE_LIBC_MACHINE_NVPTX_TRUE@ libc/machine/nvptx/free.c libc/machine/nvptx/write.c libc/machine/nvptx/assert.c libc/machine/nvptx/puts.c libc/machine/nvptx/putchar.c libc/machine/nvptx/printf.c libc/machine/nvptx/abort.c \ @HAVE_LIBC_MACHINE_NVPTX_TRUE@ libc/machine/nvptx/misc.c libc/machine/nvptx/clock.c -@HAVE_LIBC_MACHINE_OR1K_TRUE@am__append_108 = libc/machine/or1k/setjmp.S -@HAVE_LIBC_MACHINE_POWERPC_TRUE@am__append_109 = libc/machine/powerpc/setjmp.S -@HAVE_LIBC_MACHINE_POWERPC_TRUE@@HAVE_POWERPC_ALTIVEC_TRUE@am__append_110 = \ +@HAVE_LIBC_MACHINE_OR1K_TRUE@am__append_109 = libc/machine/or1k/setjmp.S +@HAVE_LIBC_MACHINE_POWERPC_TRUE@am__append_110 = libc/machine/powerpc/setjmp.S +@HAVE_LIBC_MACHINE_POWERPC_TRUE@@HAVE_POWERPC_ALTIVEC_TRUE@am__append_111 = \ @HAVE_LIBC_MACHINE_POWERPC_TRUE@@HAVE_POWERPC_ALTIVEC_TRUE@ libc/machine/powerpc/vfprintf.c \ @HAVE_LIBC_MACHINE_POWERPC_TRUE@@HAVE_POWERPC_ALTIVEC_TRUE@ libc/machine/powerpc/vfscanf.c \ @HAVE_LIBC_MACHINE_POWERPC_TRUE@@HAVE_POWERPC_ALTIVEC_TRUE@ libc/machine/powerpc/vec_malloc.c \ @@ -780,7 +781,7 @@ check_PROGRAMS = @HAVE_LIBC_MACHINE_POWERPC_TRUE@@HAVE_POWERPC_ALTIVEC_TRUE@ libc/machine/powerpc/vec_callocr.c \ @HAVE_LIBC_MACHINE_POWERPC_TRUE@@HAVE_POWERPC_ALTIVEC_TRUE@ libc/machine/powerpc/vec_reallocr.c -@HAVE_LIBC_MACHINE_POWERPC_TRUE@@HAVE_POWERPC_SPE_TRUE@am__append_111 = \ +@HAVE_LIBC_MACHINE_POWERPC_TRUE@@HAVE_POWERPC_SPE_TRUE@am__append_112 = \ @HAVE_LIBC_MACHINE_POWERPC_TRUE@@HAVE_POWERPC_SPE_TRUE@ libc/machine/powerpc/atosfix16.c \ @HAVE_LIBC_MACHINE_POWERPC_TRUE@@HAVE_POWERPC_SPE_TRUE@ libc/machine/powerpc/atosfix32.c \ @HAVE_LIBC_MACHINE_POWERPC_TRUE@@HAVE_POWERPC_SPE_TRUE@ libc/machine/powerpc/atosfix64.c \ @@ -798,21 +799,21 @@ check_PROGRAMS = @HAVE_LIBC_MACHINE_POWERPC_TRUE@@HAVE_POWERPC_SPE_TRUE@ libc/machine/powerpc/vfprintf.c \ @HAVE_LIBC_MACHINE_POWERPC_TRUE@@HAVE_POWERPC_SPE_TRUE@ libc/machine/powerpc/vfscanf.c -@HAVE_LIBC_MACHINE_PRU_TRUE@am__append_112 = libc/machine/pru/setjmp.s -@HAVE_LIBC_MACHINE_RISCV_TRUE@am__append_113 = \ +@HAVE_LIBC_MACHINE_PRU_TRUE@am__append_113 = libc/machine/pru/setjmp.s +@HAVE_LIBC_MACHINE_RISCV_TRUE@am__append_114 = \ @HAVE_LIBC_MACHINE_RISCV_TRUE@ libc/machine/riscv/memmove.S libc/machine/riscv/memmove-stub.c libc/machine/riscv/memset.S libc/machine/riscv/memcpy-asm.S libc/machine/riscv/memcpy.c libc/machine/riscv/strlen.c \ @HAVE_LIBC_MACHINE_RISCV_TRUE@ libc/machine/riscv/strcpy.c libc/machine/riscv/strcmp.S libc/machine/riscv/setjmp.S libc/machine/riscv/ieeefp.c libc/machine/riscv/ffs.c -@HAVE_LIBC_MACHINE_RL78_TRUE@am__append_114 = libc/machine/rl78/setjmp.S -@HAVE_LIBC_MACHINE_RX_TRUE@am__append_115 = \ +@HAVE_LIBC_MACHINE_RL78_TRUE@am__append_115 = libc/machine/rl78/setjmp.S +@HAVE_LIBC_MACHINE_RX_TRUE@am__append_116 = \ @HAVE_LIBC_MACHINE_RX_TRUE@ libc/machine/rx/setjmp.S \ @HAVE_LIBC_MACHINE_RX_TRUE@ libc/machine/rx/strncmp.S libc/machine/rx/strcmp.S libc/machine/rx/strncpy.S libc/machine/rx/strcpy.S libc/machine/rx/strlen.S libc/machine/rx/strcat.S libc/machine/rx/strncat.S \ @HAVE_LIBC_MACHINE_RX_TRUE@ libc/machine/rx/memset.S libc/machine/rx/mempcpy.S libc/machine/rx/memcpy.S libc/machine/rx/memmove.S libc/machine/rx/memchr.S -@HAVE_LIBC_MACHINE_SH_TRUE@am__append_116 = libc/machine/sh/memcpy.S libc/machine/sh/memset.S libc/machine/sh/setjmp.S libc/machine/sh/strcpy.S libc/machine/sh/strlen.S libc/machine/sh/strcmp.S -@HAVE_LIBC_MACHINE_SH_TRUE@@SH64_TRUE@am__append_117 = libc/machine/sh/strncpy.S -@HAVE_LIBC_MACHINE_SPARC_TRUE@am__append_118 = libc/machine/sparc/scan.c libc/machine/sparc/shuffle.c libc/machine/sparc/setjmp.S -@HAVE_LIBC_MACHINE_SPU_TRUE@am__append_119 = \ +@HAVE_LIBC_MACHINE_SH_TRUE@am__append_117 = libc/machine/sh/memcpy.S libc/machine/sh/memset.S libc/machine/sh/setjmp.S libc/machine/sh/strcpy.S libc/machine/sh/strlen.S libc/machine/sh/strcmp.S +@HAVE_LIBC_MACHINE_SH_TRUE@@SH64_TRUE@am__append_118 = libc/machine/sh/strncpy.S +@HAVE_LIBC_MACHINE_SPARC_TRUE@am__append_119 = libc/machine/sparc/scan.c libc/machine/sparc/shuffle.c libc/machine/sparc/setjmp.S +@HAVE_LIBC_MACHINE_SPU_TRUE@am__append_120 = \ @HAVE_LIBC_MACHINE_SPU_TRUE@ libc/machine/spu/setjmp.S libc/machine/spu/assert.c libc/machine/spu/clearerr.c libc/machine/spu/creat.c libc/machine/spu/fclose.c libc/machine/spu/feof.c \ @HAVE_LIBC_MACHINE_SPU_TRUE@ libc/machine/spu/ferror.c libc/machine/spu/fflush.c libc/machine/spu/fgetc.c libc/machine/spu/fgetpos.c libc/machine/spu/fgets.c libc/machine/spu/fileno.c libc/machine/spu/fiprintf.S \ @HAVE_LIBC_MACHINE_SPU_TRUE@ libc/machine/spu/fiscanf.S libc/machine/spu/fopen.c libc/machine/spu/fprintf.S libc/machine/spu/fputc.c libc/machine/spu/fputs.c libc/machine/spu/fread.c libc/machine/spu/freopen.c \ @@ -830,7 +831,7 @@ check_PROGRAMS = @HAVE_LIBC_MACHINE_SPU_TRUE@ libc/machine/spu/spu_timer_slih.c libc/machine/spu/spu_timer_slih_reg.c libc/machine/spu/spu_timer_svcs.c \ @HAVE_LIBC_MACHINE_SPU_TRUE@ libc/machine/spu/spu_timer_stop.c libc/machine/spu/spu_timer_free.c libc/machine/spu/spu_timebase.c libc/machine/spu/fdopen.c -@HAVE_LIBC_MACHINE_SPU_TRUE@@HAVE_SPU_EA_TRUE@am__append_120 = \ +@HAVE_LIBC_MACHINE_SPU_TRUE@@HAVE_SPU_EA_TRUE@am__append_121 = \ @HAVE_LIBC_MACHINE_SPU_TRUE@@HAVE_SPU_EA_TRUE@ libc/machine/spu/calloc_ea.c libc/machine/spu/free_ea.c libc/machine/spu/malloc_ea.c libc/machine/spu/memchr_ea.c libc/machine/spu/memcmp_ea.c \ @HAVE_LIBC_MACHINE_SPU_TRUE@@HAVE_SPU_EA_TRUE@ libc/machine/spu/memcpy_ea.c libc/machine/spu/memmove_ea.c libc/machine/spu/memset_ea.c libc/machine/spu/mmap_ea.c libc/machine/spu/mremap_ea.c libc/machine/spu/msync_ea.c \ @HAVE_LIBC_MACHINE_SPU_TRUE@@HAVE_SPU_EA_TRUE@ libc/machine/spu/munmap_ea.c libc/machine/spu/posix_memalign_ea.c libc/machine/spu/realloc_ea.c libc/machine/spu/strcat_ea.c libc/machine/spu/strchr_ea.c \ @@ -839,18 +840,18 @@ check_PROGRAMS = @HAVE_LIBC_MACHINE_SPU_TRUE@@HAVE_SPU_EA_TRUE@ libc/machine/spu/pread_ea.c libc/machine/spu/readv_ea.c libc/machine/spu/write_ea.c libc/machine/spu/pwrite_ea.c libc/machine/spu/writev_ea.c libc/machine/spu/spu-mcount.S \ @HAVE_LIBC_MACHINE_SPU_TRUE@@HAVE_SPU_EA_TRUE@ libc/machine/spu/spu-gmon.c -@HAVE_LIBC_MACHINE_TIC4X_TRUE@am__append_121 = libc/machine/tic4x/setjmp.S -@HAVE_LIBC_MACHINE_TIC6X_TRUE@am__append_122 = libc/machine/tic6x/setjmp.S -@HAVE_LIBC_MACHINE_TIC80_TRUE@am__append_123 = libc/machine/tic80/setjmp.S -@HAVE_LIBC_MACHINE_V850_TRUE@am__append_124 = libc/machine/v850/setjmp.S -@HAVE_LIBC_MACHINE_VISIUM_TRUE@am__append_125 = libc/machine/visium/memcpy.c libc/machine/visium/memset.c libc/machine/visium/memmove.c libc/machine/visium/setjmp.S -@HAVE_LIBC_MACHINE_W65_TRUE@am__append_126 = \ +@HAVE_LIBC_MACHINE_TIC4X_TRUE@am__append_122 = libc/machine/tic4x/setjmp.S +@HAVE_LIBC_MACHINE_TIC6X_TRUE@am__append_123 = libc/machine/tic6x/setjmp.S +@HAVE_LIBC_MACHINE_TIC80_TRUE@am__append_124 = libc/machine/tic80/setjmp.S +@HAVE_LIBC_MACHINE_V850_TRUE@am__append_125 = libc/machine/v850/setjmp.S +@HAVE_LIBC_MACHINE_VISIUM_TRUE@am__append_126 = libc/machine/visium/memcpy.c libc/machine/visium/memset.c libc/machine/visium/memmove.c libc/machine/visium/setjmp.S +@HAVE_LIBC_MACHINE_W65_TRUE@am__append_127 = \ @HAVE_LIBC_MACHINE_W65_TRUE@ libc/machine/w65/udivhi3.S libc/machine/w65/umodhi3.S libc/machine/w65/smulhi3.S libc/machine/w65/lshrhi.S libc/machine/w65/sdivhi3.S libc/machine/w65/mulsi3.c \ @HAVE_LIBC_MACHINE_W65_TRUE@ libc/machine/w65/divsi3.c libc/machine/w65/cmpsi.c -@HAVE_LIBC_MACHINE_X86_64_TRUE@am__append_127 = libc/machine/x86_64/setjmp.S libc/machine/x86_64/memcpy.S libc/machine/x86_64/memset.S -@HAVE_LIBC_MACHINE_XC16X_TRUE@am__append_128 = libc/machine/xc16x/setjmp.S libc/machine/xc16x/puts.c libc/machine/xc16x/putchar.c -@HAVE_LIBC_MACHINE_XSTORMY16_TRUE@am__append_129 = \ +@HAVE_LIBC_MACHINE_X86_64_TRUE@am__append_128 = libc/machine/x86_64/setjmp.S libc/machine/x86_64/memcpy.S libc/machine/x86_64/memset.S +@HAVE_LIBC_MACHINE_XC16X_TRUE@am__append_129 = libc/machine/xc16x/setjmp.S libc/machine/xc16x/puts.c libc/machine/xc16x/putchar.c +@HAVE_LIBC_MACHINE_XSTORMY16_TRUE@am__append_130 = \ @HAVE_LIBC_MACHINE_XSTORMY16_TRUE@ libc/machine/xstormy16/setjmp.S \ @HAVE_LIBC_MACHINE_XSTORMY16_TRUE@ libc/machine/xstormy16/calloc.c \ @HAVE_LIBC_MACHINE_XSTORMY16_TRUE@ libc/machine/xstormy16/callocr.c \ @@ -865,9 +866,13 @@ check_PROGRAMS = @HAVE_LIBC_MACHINE_XSTORMY16_TRUE@ libc/machine/xstormy16/reallocr.c \ @HAVE_LIBC_MACHINE_XSTORMY16_TRUE@ libc/machine/xstormy16/valloc.c -@HAVE_LIBC_MACHINE_Z8K_TRUE@am__append_130 = libc/machine/z8k/setjmp.S libc/machine/z8k/memset.S libc/machine/z8k/memcpy.S libc/machine/z8k/memmove.S libc/machine/z8k/memcmp.S -@NEWLIB_HW_FP_TRUE@am__append_131 = $(libm_mathfp_src) $(libm_mathfp_fsrc) -@NEWLIB_HW_FP_TRUE@am__append_132 = \ +@HAVE_LIBC_MACHINE_XTENSA_TRUE@am__append_131 = \ +@HAVE_LIBC_MACHINE_XTENSA_TRUE@ libc/machine/xtensa/memcpy.S libc/machine/xtensa/memset.S libc/machine/xtensa/setjmp.S libc/machine/xtensa/strcmp.S libc/machine/xtensa/strcpy.S \ +@HAVE_LIBC_MACHINE_XTENSA_TRUE@ libc/machine/xtensa/strlen.S libc/machine/xtensa/strncpy.S + +@HAVE_LIBC_MACHINE_Z8K_TRUE@am__append_132 = libc/machine/z8k/setjmp.S libc/machine/z8k/memset.S libc/machine/z8k/memcpy.S libc/machine/z8k/memmove.S libc/machine/z8k/memcmp.S +@NEWLIB_HW_FP_TRUE@am__append_133 = $(libm_mathfp_src) $(libm_mathfp_fsrc) +@NEWLIB_HW_FP_TRUE@am__append_134 = \ @NEWLIB_HW_FP_TRUE@ libm/mathfp/e_acosh.def \ @NEWLIB_HW_FP_TRUE@ libm/mathfp/e_atanh.def \ @NEWLIB_HW_FP_TRUE@ libm/mathfp/e_hypot.def \ @@ -897,9 +902,9 @@ check_PROGRAMS = @NEWLIB_HW_FP_TRUE@ libm/mathfp/s_tanh.def \ @NEWLIB_HW_FP_TRUE@ libm/mathfp/w_jn.def -@NEWLIB_HW_FP_TRUE@am__append_133 = libm/mathfp/mathfp.tex -@NEWLIB_HW_FP_FALSE@am__append_134 = $(libm_math_src) $(libm_math_fsrc) $(libm_math_lsrc) -@NEWLIB_HW_FP_FALSE@am__append_135 = \ +@NEWLIB_HW_FP_TRUE@am__append_135 = libm/mathfp/mathfp.tex +@NEWLIB_HW_FP_FALSE@am__append_136 = $(libm_math_src) $(libm_math_fsrc) $(libm_math_lsrc) +@NEWLIB_HW_FP_FALSE@am__append_137 = \ @NEWLIB_HW_FP_FALSE@ libm/math/w_acos.def libm/math/w_acosh.def libm/math/w_asin.def libm/math/s_asinh.def \ @NEWLIB_HW_FP_FALSE@ libm/math/s_atan.def libm/math/w_atan2.def libm/math/w_atanh.def libm/math/w_j0.def \ @NEWLIB_HW_FP_FALSE@ libm/math/w_cosh.def libm/math/s_erf.def libm/math/w_exp.def libm/math/w_exp2.def \ @@ -909,34 +914,38 @@ check_PROGRAMS = @NEWLIB_HW_FP_FALSE@ libm/math/w_pow.def libm/math/w_remainder.def libm/math/s_sin.def libm/math/w_sinh.def \ @NEWLIB_HW_FP_FALSE@ libm/math/w_sqrt.def libm/math/s_tan.def libm/math/s_tanh.def -@NEWLIB_HW_FP_FALSE@am__append_136 = libm/math/math.tex -@HAVE_LONG_DOUBLE_TRUE@am__append_137 = $(libm_common_lsrc) -@HAVE_FPMATH_H_TRUE@@HAVE_LONG_DOUBLE_TRUE@am__append_138 = $(libm_ld_lsrc) -@HAVE_FPMATH_H_TRUE@am__append_139 = -@HAVE_FPMATH_H_TRUE@am__append_140 = -@HAVE_LIBM_MACHINE_AARCH64_TRUE@am__append_141 = $(libm_machine_aarch64_src) -@HAVE_LIBM_MACHINE_AARCH64_TRUE@@HAVE_LONG_DOUBLE_TRUE@am__append_142 = $(libm_ld128_lsrc) -@HAVE_LIBM_MACHINE_AARCH64_TRUE@am__append_143 = -@HAVE_LIBM_MACHINE_AARCH64_TRUE@am__append_144 = -@HAVE_LIBM_MACHINE_AMDGCN_TRUE@am__append_145 = $(libm_machine_amdgcn_src) -@HAVE_LIBM_MACHINE_ARM_TRUE@am__append_146 = $(libm_machine_arm_src) -@HAVE_LIBM_MACHINE_I386_TRUE@am__append_147 = $(libm_machine_i386_src) -@HAVE_LIBM_MACHINE_I386_TRUE@@HAVE_LONG_DOUBLE_TRUE@am__append_148 = $(libm_ld80_lsrc) -@HAVE_LIBM_MACHINE_I386_TRUE@am__append_149 = -@HAVE_LIBM_MACHINE_I386_TRUE@am__append_150 = -@HAVE_LIBM_MACHINE_MIPS_TRUE@am__append_151 = $(libm_machine_mips_src) -@HAS_NDS32_FPU_SP_TRUE@@HAVE_LIBM_MACHINE_NDS32_TRUE@am__append_152 = libm/machine/nds32/wf_sqrt.S -@HAS_NDS32_FPU_DP_TRUE@@HAVE_LIBM_MACHINE_NDS32_TRUE@am__append_153 = libm/machine/nds32/w_sqrt.S -@HAVE_LIBM_MACHINE_NDS32_TRUE@am__append_154 = $(libm_machine_nds32_src) -@HAVE_LIBM_MACHINE_POWERPC_TRUE@am__append_155 = $(libm_machine_powerpc_src) -@HAVE_LIBM_MACHINE_PRU_TRUE@am__append_156 = $(libm_machine_pru_src) -@HAVE_LIBM_MACHINE_SPARC_TRUE@am__append_157 = $(libm_machine_sparc_src) -@HAVE_LIBM_MACHINE_SPU_TRUE@am__append_158 = $(libm_machine_spu_src) -@HAVE_LIBM_MACHINE_RISCV_TRUE@am__append_159 = $(libm_machine_riscv_src) -@HAVE_LIBM_MACHINE_X86_64_TRUE@am__append_160 = $(libm_machine_x86_64_src) -@HAVE_LIBM_MACHINE_X86_64_TRUE@@HAVE_LONG_DOUBLE_TRUE@am__append_161 = $(libm_ld80_lsrc) -@HAVE_LIBM_MACHINE_X86_64_TRUE@am__append_162 = -@HAVE_LIBM_MACHINE_X86_64_TRUE@am__append_163 = +@NEWLIB_HW_FP_FALSE@am__append_138 = libm/math/math.tex +@HAVE_LONG_DOUBLE_TRUE@am__append_139 = $(libm_common_lsrc) +@HAVE_FPMATH_H_TRUE@@HAVE_LONG_DOUBLE_TRUE@am__append_140 = $(libm_ld_lsrc) +@HAVE_FPMATH_H_TRUE@am__append_141 = +@HAVE_FPMATH_H_TRUE@am__append_142 = +@HAVE_LIBM_MACHINE_AARCH64_TRUE@am__append_143 = $(libm_machine_aarch64_src) +@HAVE_LIBM_MACHINE_AARCH64_TRUE@@HAVE_LONG_DOUBLE_TRUE@am__append_144 = $(libm_ld128_lsrc) +@HAVE_LIBM_MACHINE_AARCH64_TRUE@am__append_145 = +@HAVE_LIBM_MACHINE_AARCH64_TRUE@am__append_146 = +@HAVE_LIBM_MACHINE_AMDGCN_TRUE@am__append_147 = $(libm_machine_amdgcn_src) +@HAVE_LIBM_MACHINE_ARM_TRUE@am__append_148 = $(libm_machine_arm_src) +@HAVE_LIBM_MACHINE_I386_TRUE@am__append_149 = $(libm_machine_i386_src) +@HAVE_LIBM_MACHINE_I386_TRUE@@HAVE_LONG_DOUBLE_TRUE@am__append_150 = $(libm_ld80_lsrc) +@HAVE_LIBM_MACHINE_I386_TRUE@am__append_151 = +@HAVE_LIBM_MACHINE_I386_TRUE@am__append_152 = +@HAVE_LIBM_MACHINE_MIPS_TRUE@am__append_153 = $(libm_machine_mips_src) +@HAS_NDS32_FPU_SP_TRUE@@HAVE_LIBM_MACHINE_NDS32_TRUE@am__append_154 = libm/machine/nds32/wf_sqrt.S +@HAS_NDS32_FPU_DP_TRUE@@HAVE_LIBM_MACHINE_NDS32_TRUE@am__append_155 = libm/machine/nds32/w_sqrt.S +@HAVE_LIBM_MACHINE_NDS32_TRUE@am__append_156 = $(libm_machine_nds32_src) +@HAVE_LIBM_MACHINE_POWERPC_TRUE@am__append_157 = $(libm_machine_powerpc_src) +@HAVE_LIBM_MACHINE_PRU_TRUE@am__append_158 = $(libm_machine_pru_src) +@HAVE_LIBM_MACHINE_SPARC_TRUE@am__append_159 = $(libm_machine_sparc_src) +@HAVE_LIBM_MACHINE_SPU_TRUE@am__append_160 = $(libm_machine_spu_src) +@HAVE_LIBM_MACHINE_RISCV_TRUE@am__append_161 = $(libm_machine_riscv_src) +@HAVE_LIBM_MACHINE_X86_64_TRUE@am__append_162 = $(libm_machine_x86_64_src) +@HAVE_LIBM_MACHINE_X86_64_TRUE@@HAVE_LONG_DOUBLE_TRUE@am__append_163 = $(libm_ld80_lsrc) +@HAVE_LIBM_MACHINE_X86_64_TRUE@am__append_164 = +@HAVE_LIBM_MACHINE_X86_64_TRUE@am__append_165 = +@HAVE_LIBM_MACHINE_XTENSA_TRUE@@XTENSA_XCHAL_HAVE_FP_SQRT_TRUE@am__append_166 = \ +@HAVE_LIBM_MACHINE_XTENSA_TRUE@@XTENSA_XCHAL_HAVE_FP_SQRT_TRUE@ libm/machine/xtensa/ef_sqrt.c + +@HAVE_LIBM_MACHINE_XTENSA_TRUE@am__append_167 = $(libm_machine_xtensa_src) subdir = . ACLOCAL_M4 = $(top_srcdir)/aclocal.m4 am__aclocal_m4_deps = $(top_srcdir)/../config/depstand.m4 \ @@ -948,8 +957,10 @@ am__aclocal_m4_deps = $(top_srcdir)/../config/depstand.m4 \ $(top_srcdir)/libc/machine/powerpc/acinclude.m4 \ $(top_srcdir)/libc/machine/sh/acinclude.m4 \ $(top_srcdir)/libc/machine/spu/acinclude.m4 \ + $(top_srcdir)/libc/machine/xtensa/acinclude.m4 \ $(top_srcdir)/libm/acinclude.m4 \ $(top_srcdir)/libm/machine/nds32/acinclude.m4 \ + $(top_srcdir)/libm/machine/xtensa/acinclude.m4 \ $(top_srcdir)/configure.ac am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \ $(ACLOCAL_M4) @@ -1824,8 +1835,11 @@ am__objects_51 = libc/ssp/libc_a-chk_fail.$(OBJEXT) \ @HAVE_LIBC_SYS_TIRTOS_DIR_TRUE@am__objects_73 = libc/sys/tirtos/libc_a-lock.$(OBJEXT) @HAVE_LIBC_SYS_W65_DIR_TRUE@am__objects_74 = libc/sys/w65/libc_a-syscalls.$(OBJEXT) \ @HAVE_LIBC_SYS_W65_DIR_TRUE@ libc/sys/w65/libc_a-trap.$(OBJEXT) -@HAVE_LIBC_SYS_Z8KSIM_DIR_TRUE@am__objects_75 = libc/sys/z8ksim/libc_a-glue.$(OBJEXT) -@HAVE_LIBC_MACHINE_AARCH64_TRUE@am__objects_76 = libc/machine/aarch64/libc_a-memchr-stub.$(OBJEXT) \ +@HAVE_LIBC_SYS_XTENSA_DIR_TRUE@am__objects_75 = libc/sys/xtensa/libc_a-creat.$(OBJEXT) \ +@HAVE_LIBC_SYS_XTENSA_DIR_TRUE@ libc/sys/xtensa/libc_a-isatty.$(OBJEXT) \ +@HAVE_LIBC_SYS_XTENSA_DIR_TRUE@ libc/sys/xtensa/libc_a-clibrary_init.$(OBJEXT) +@HAVE_LIBC_SYS_Z8KSIM_DIR_TRUE@am__objects_76 = libc/sys/z8ksim/libc_a-glue.$(OBJEXT) +@HAVE_LIBC_MACHINE_AARCH64_TRUE@am__objects_77 = libc/machine/aarch64/libc_a-memchr-stub.$(OBJEXT) \ @HAVE_LIBC_MACHINE_AARCH64_TRUE@ libc/machine/aarch64/libc_a-memchr.$(OBJEXT) \ @HAVE_LIBC_MACHINE_AARCH64_TRUE@ libc/machine/aarch64/libc_a-memcmp-stub.$(OBJEXT) \ @HAVE_LIBC_MACHINE_AARCH64_TRUE@ libc/machine/aarch64/libc_a-memcmp.$(OBJEXT) \ @@ -1856,13 +1870,13 @@ am__objects_51 = libc/ssp/libc_a-chk_fail.$(OBJEXT) \ @HAVE_LIBC_MACHINE_AARCH64_TRUE@ libc/machine/aarch64/libc_a-strnlen.$(OBJEXT) \ @HAVE_LIBC_MACHINE_AARCH64_TRUE@ libc/machine/aarch64/libc_a-strrchr-stub.$(OBJEXT) \ @HAVE_LIBC_MACHINE_AARCH64_TRUE@ libc/machine/aarch64/libc_a-strrchr.$(OBJEXT) -@HAVE_LIBC_MACHINE_AMDGCN_TRUE@am__objects_77 = libc/machine/amdgcn/libc_a-abort.$(OBJEXT) \ +@HAVE_LIBC_MACHINE_AMDGCN_TRUE@am__objects_78 = libc/machine/amdgcn/libc_a-abort.$(OBJEXT) \ @HAVE_LIBC_MACHINE_AMDGCN_TRUE@ libc/machine/amdgcn/libc_a-exit.$(OBJEXT) \ @HAVE_LIBC_MACHINE_AMDGCN_TRUE@ libc/machine/amdgcn/libc_a-atexit.$(OBJEXT) \ @HAVE_LIBC_MACHINE_AMDGCN_TRUE@ libc/machine/amdgcn/libc_a-mlock.$(OBJEXT) \ @HAVE_LIBC_MACHINE_AMDGCN_TRUE@ libc/machine/amdgcn/libc_a-getreent.$(OBJEXT) \ @HAVE_LIBC_MACHINE_AMDGCN_TRUE@ libc/machine/amdgcn/libc_a-signal.$(OBJEXT) -@HAVE_LIBC_MACHINE_ARC_TRUE@am__objects_78 = libc/machine/arc/libc_a-memcmp.$(OBJEXT) \ +@HAVE_LIBC_MACHINE_ARC_TRUE@am__objects_79 = libc/machine/arc/libc_a-memcmp.$(OBJEXT) \ @HAVE_LIBC_MACHINE_ARC_TRUE@ libc/machine/arc/libc_a-memcmp-bs-norm.$(OBJEXT) \ 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+@HAVE_LIBM_MACHINE_XTENSA_TRUE@@XTENSA_XCHAL_HAVE_FP_SQRT_TRUE@am__objects_191 = libm/machine/xtensa/libm_a-ef_sqrt.$(OBJEXT) +@HAVE_LIBM_MACHINE_XTENSA_TRUE@am__objects_192 = libm/machine/xtensa/libm_a-feclearexcept.$(OBJEXT) \ +@HAVE_LIBM_MACHINE_XTENSA_TRUE@ libm/machine/xtensa/libm_a-fegetenv.$(OBJEXT) \ +@HAVE_LIBM_MACHINE_XTENSA_TRUE@ libm/machine/xtensa/libm_a-fegetexcept.$(OBJEXT) \ +@HAVE_LIBM_MACHINE_XTENSA_TRUE@ libm/machine/xtensa/libm_a-fegetexceptflag.$(OBJEXT) \ +@HAVE_LIBM_MACHINE_XTENSA_TRUE@ libm/machine/xtensa/libm_a-fegetround.$(OBJEXT) \ +@HAVE_LIBM_MACHINE_XTENSA_TRUE@ libm/machine/xtensa/libm_a-feholdexcept.$(OBJEXT) \ +@HAVE_LIBM_MACHINE_XTENSA_TRUE@ libm/machine/xtensa/libm_a-feraiseexcept.$(OBJEXT) \ +@HAVE_LIBM_MACHINE_XTENSA_TRUE@ libm/machine/xtensa/libm_a-fetestexcept.$(OBJEXT) \ +@HAVE_LIBM_MACHINE_XTENSA_TRUE@ libm/machine/xtensa/libm_a-feupdateenv.$(OBJEXT) \ +@HAVE_LIBM_MACHINE_XTENSA_TRUE@ $(am__objects_191) +@HAVE_LIBM_MACHINE_XTENSA_TRUE@am__objects_193 = $(am__objects_192) +am_libm_a_OBJECTS = $(am__objects_145) $(am__objects_149) \ + $(am__objects_150) $(am__objects_151) $(am__objects_153) \ + $(am__objects_155) $(am__objects_156) $(am__objects_157) \ + $(am__objects_158) $(am__objects_159) $(am__objects_161) \ + $(am__objects_163) $(am__objects_165) $(am__objects_167) \ + $(am__objects_169) $(am__objects_171) $(am__objects_173) \ + $(am__objects_177) $(am__objects_179) $(am__objects_181) \ + $(am__objects_183) $(am__objects_185) $(am__objects_187) \ + $(am__objects_189) $(am__objects_190) $(am__objects_193) libm_a_OBJECTS = $(am_libm_a_OBJECTS) am_libm_test_test_OBJECTS = libm/test/test.$(OBJEXT) \ libm/test/string.$(OBJEXT) libm/test/convert.$(OBJEXT) \ @@ -3951,7 +3985,7 @@ AM_CFLAGS = $(AM_CFLAGS_$(subst /,_,$(@D))) $(AM_CFLAGS_$(subst /,_,$(@D)_$(<F)) AM_CCASFLAGS = $(AM_CCASFLAGS_$(subst /,_,$(@D))) $(AM_CCASFLAGS_$(subst /,_,$(@D)_$(<F))) @HAVE_LIBC_MACHINE_ARM_FALSE@AM_CPPFLAGS = $(NEWLIB_CFLAGS) $(TARGET_CFLAGS) $(AM_CPPFLAGS_$(subst /,_,$(@D))) $(AM_CPPFLAGS_$(subst /,_,$(@D)_$(<F))) @HAVE_LIBC_MACHINE_ARM_TRUE@AM_CPPFLAGS = $(NEWLIB_CFLAGS) $(TARGET_CFLAGS) $(AM_CPPFLAGS_$(subst /,_,$(@D))) $(AM_CPPFLAGS_$(subst /,_,$(@D)_$(<F))) -idirafter $(srcroot)/include -toollib_LIBRARIES = libm.a libc.a $(am__append_72) +toollib_LIBRARIES = libm.a libc.a $(am__append_73) @HAVE_MULTISUBDIR_TRUE@BUILD_MULTISUBDIR = $(builddir)$(MULTISUBDIR) toollib_DATA = $(CRT0) $(CRT1) AWK_UNIQUE_OBJS = $(AWK) '{ \ @@ -4122,7 +4156,7 @@ libc_a_SOURCES = $(am__append_5) libc/stdlib/__adjust.c \ $(am__append_62) $(am__append_63) $(am__append_64) \ $(am__append_65) $(am__append_66) $(am__append_67) \ $(am__append_68) $(am__append_69) $(am__append_70) \ - $(am__append_71) $(am__append_73) $(am__append_74) \ + $(am__append_71) $(am__append_72) $(am__append_74) \ $(am__append_75) $(am__append_76) $(am__append_77) \ $(am__append_78) $(am__append_79) $(am__append_80) \ $(am__append_81) $(am__append_82) $(am__append_83) \ @@ -4141,20 +4175,21 @@ libc_a_SOURCES = $(am__append_5) libc/stdlib/__adjust.c \ $(am__append_120) $(am__append_121) $(am__append_122) \ $(am__append_123) $(am__append_124) $(am__append_125) \ $(am__append_126) $(am__append_127) $(am__append_128) \ - $(am__append_129) $(am__append_130) + $(am__append_129) $(am__append_130) $(am__append_131) \ + $(am__append_132) libc_a_CFLAGS = $(AM_CFLAGS) $(libc_a_CFLAGS_$(subst /,_,$(@D))) $(libc_a_CFLAGS_$(subst /,_,$(@D)_$(<F))) libc_a_CCASFLAGS = $(AM_CCASFLAGS) $(libc_a_CCASFLAGS_$(subst /,_,$(@D))) $(libc_a_CCASFLAGS_$(subst /,_,$(@D)_$(<F))) libc_a_CPPFLAGS = $(AM_CPPFLAGS) $(libc_a_CPPFLAGS_$(subst /,_,$(@D))) $(libc_a_CPPFLAGS_$(subst /,_,$(@D)_$(<F))) libc_a_DEPENDENCIES = stamp-libc-math-objects -libm_a_SOURCES = $(am__append_131) $(am__append_134) \ - $(libm_common_src) $(libm_common_fsrc) $(am__append_137) \ - $(am__append_138) $(libm_complex_src) $(libm_complex_fsrc) \ - $(libm_complex_lsrc) $(libm_fenv_src) $(am__append_141) \ - $(am__append_142) $(am__append_145) $(am__append_146) \ - $(am__append_147) $(am__append_148) $(am__append_151) \ - $(am__append_154) $(am__append_155) $(am__append_156) \ - $(am__append_157) $(am__append_158) $(am__append_159) \ - $(am__append_160) $(am__append_161) +libm_a_SOURCES = $(am__append_133) $(am__append_136) \ + $(libm_common_src) $(libm_common_fsrc) $(am__append_139) \ + $(am__append_140) $(libm_complex_src) $(libm_complex_fsrc) \ + $(libm_complex_lsrc) $(libm_fenv_src) $(am__append_143) \ + $(am__append_144) $(am__append_147) $(am__append_148) \ + $(am__append_149) $(am__append_150) $(am__append_153) \ + $(am__append_156) $(am__append_157) $(am__append_158) \ + $(am__append_159) $(am__append_160) $(am__append_161) \ + $(am__append_162) $(am__append_163) $(am__append_167) libm_a_CFLAGS = $(AM_CFLAGS) $(libm_a_CFLAGS_$(subst /,_,$(@D))) $(libm_a_CFLAGS_$(subst /,_,$(@D)_$(<F))) libm_a_CCASFLAGS = $(AM_CCASFLAGS) $(libm_a_CCASFLAGS_$(subst /,_,$(@D))) $(libm_a_CCASFLAGS_$(subst /,_,$(@D)_$(<F))) libm_a_CPPFLAGS = $(AM_CPPFLAGS) -I$(srcdir)/libm/common $(libm_a_CPPFLAGS_$(subst /,_,$(@D))) $(libm_a_CPPFLAGS_$(subst /,_,$(@D)_$(<F))) @@ -4583,8 +4618,11 @@ libc_ssp_ELIX_SOURCES = libc/ssp/chk_fail.c libc/ssp/stack_protector.c \ @HAVE_LIBC_MACHINE_MN10300_TRUE@libc_a_CCASFLAGS_libc_machine_mn10300 = -Wa,--gdwarf-2 @HAVE_LIBC_MACHINE_POWERPC_TRUE@libc_a_CPPFLAGS_libc_machine_powerpc = -I$(srcdir)/libc/stdio -I$(srcdir)/libc/stdlib +@HAVE_LIBC_MACHINE_XTENSA_TRUE@@XTENSA_ESP32_PSRAM_CACHE_FIX_TRUE@libc_a_CPPFLAGS_libc_machine_xtensa = \ +@HAVE_LIBC_MACHINE_XTENSA_TRUE@@XTENSA_ESP32_PSRAM_CACHE_FIX_TRUE@ -DXTENSA_ESP32_PSRAM_CACHE_FIX + libm_libm_TEXINFOS = libm/targetdep.tex $(LIBM_CHEWOUT_FILES) -LIBM_CHEWOUT_FILES = $(am__append_132) $(am__append_135) \ +LIBM_CHEWOUT_FILES = $(am__append_134) $(am__append_137) \ libm/common/s_cbrt.def libm/common/s_copysign.def \ libm/common/s_exp10.def libm/common/s_expm1.def \ libm/common/s_ilogb.def libm/common/s_infinity.def \ @@ -4599,7 +4637,7 @@ LIBM_CHEWOUT_FILES = $(am__append_132) $(am__append_135) \ libm/common/s_remquo.def libm/common/s_rint.def \ libm/common/s_round.def libm/common/s_signbit.def \ libm/common/s_trunc.def libm/common/isgreater.def \ - $(am__append_139) libm/complex/cabs.def libm/complex/cacos.def \ + $(am__append_141) libm/complex/cabs.def libm/complex/cacos.def \ libm/complex/cacosh.def libm/complex/carg.def \ libm/complex/casin.def libm/complex/casinh.def \ libm/complex/catan.def libm/complex/catanh.def \ @@ -4616,10 +4654,10 @@ LIBM_CHEWOUT_FILES = $(am__append_132) $(am__append_135) \ libm/fenv/feraiseexcept.def libm/fenv/fesetenv.def \ libm/fenv/fesetexceptflag.def libm/fenv/fesetround.def \ libm/fenv/fetestexcept.def libm/fenv/feupdateenv.def \ - $(am__append_143) $(am__append_149) $(am__append_162) -LIBM_CHAPTERS = $(am__append_133) $(am__append_136) $(am__append_140) \ - libm/complex/complex.tex libm/fenv/fenv.tex $(am__append_144) \ - $(am__append_150) $(am__append_163) + $(am__append_145) $(am__append_151) $(am__append_164) +LIBM_CHAPTERS = $(am__append_135) $(am__append_138) $(am__append_142) \ + libm/complex/complex.tex libm/fenv/fenv.tex $(am__append_146) \ + $(am__append_152) $(am__append_165) LIBM_DOCBOOK_OUT_FILES = $(LIBM_CHEWOUT_FILES:.def=.xml) @NEWLIB_HW_FP_TRUE@libm_mathfp_src = \ @NEWLIB_HW_FP_TRUE@ libm/mathfp/s_acos.c libm/mathfp/s_frexp.c libm/mathfp/s_mathcnst.c \ @@ -5147,8 +5185,8 @@ libm_test_test_LDADD = $(CRT0) libm.a libc.a # fenv.c cannot be compiled as mips16 since it uses the cfc1 instruction. @HAVE_LIBM_MACHINE_MIPS_TRUE@libm_a_CFLAGS_libm_machine_mips_fenv.c = -mno-mips16 @HAVE_LIBM_MACHINE_NDS32_TRUE@libm_machine_nds32_src = \ -@HAVE_LIBM_MACHINE_NDS32_TRUE@ $(am__append_152) \ -@HAVE_LIBM_MACHINE_NDS32_TRUE@ $(am__append_153) +@HAVE_LIBM_MACHINE_NDS32_TRUE@ $(am__append_154) \ +@HAVE_LIBM_MACHINE_NDS32_TRUE@ $(am__append_155) @HAVE_LIBM_MACHINE_POWERPC_TRUE@libm_machine_powerpc_src = \ @HAVE_LIBM_MACHINE_POWERPC_TRUE@ libm/machine/powerpc/feclearexcept.c libm/machine/powerpc/fegetenv.c libm/machine/powerpc/fegetexceptflag.c \ @HAVE_LIBM_MACHINE_POWERPC_TRUE@ libm/machine/powerpc/fegetround.c libm/machine/powerpc/feholdexcept.c libm/machine/powerpc/fenv.c libm/machine/powerpc/feraiseexcept.c libm/machine/powerpc/fesetenv.c \ @@ -5210,6 +5248,17 @@ libm_test_test_LDADD = $(CRT0) libm.a libc.a @HAVE_LIBM_MACHINE_X86_64_TRUE@ libm/machine/x86_64/feholdexcept.c libm/machine/x86_64/fenv.c libm/machine/x86_64/feraiseexcept.c libm/machine/x86_64/fesetenv.c libm/machine/x86_64/fesetexceptflag.c \ @HAVE_LIBM_MACHINE_X86_64_TRUE@ libm/machine/x86_64/fesetround.c libm/machine/x86_64/fetestexcept.c libm/machine/x86_64/feupdateenv.c +@HAVE_LIBM_MACHINE_XTENSA_TRUE@libm_machine_xtensa_src = libm/machine/xtensa/feclearexcept.c \ +@HAVE_LIBM_MACHINE_XTENSA_TRUE@ libm/machine/xtensa/fegetenv.c \ +@HAVE_LIBM_MACHINE_XTENSA_TRUE@ libm/machine/xtensa/fegetexcept.c \ +@HAVE_LIBM_MACHINE_XTENSA_TRUE@ libm/machine/xtensa/fegetexceptflag.c \ +@HAVE_LIBM_MACHINE_XTENSA_TRUE@ libm/machine/xtensa/fegetround.c \ +@HAVE_LIBM_MACHINE_XTENSA_TRUE@ libm/machine/xtensa/feholdexcept.c \ +@HAVE_LIBM_MACHINE_XTENSA_TRUE@ libm/machine/xtensa/feraiseexcept.c \ +@HAVE_LIBM_MACHINE_XTENSA_TRUE@ libm/machine/xtensa/fetestexcept.c \ +@HAVE_LIBM_MACHINE_XTENSA_TRUE@ libm/machine/xtensa/feupdateenv.c \ +@HAVE_LIBM_MACHINE_XTENSA_TRUE@ $(am__append_166) +@HAVE_LIBM_MACHINE_XTENSA_TRUE@libm_a_CFLAGS_libm_machine_xtensa = -D_LIBM all: newlib.h _newlib_version.h $(MAKE) $(AM_MAKEFLAGS) all-am @@ -5217,7 +5266,7 @@ all: newlib.h _newlib_version.h .SUFFIXES: .def .xml .S .c .dvi .o .obj .ps .s am--refresh: Makefile @: -$(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am $(srcdir)/../multilib.am $(srcdir)/doc/Makefile.inc $(srcdir)/libc/Makefile.inc $(srcdir)/libc/argz/Makefile.inc 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$(srcdir)/libm/machine/i386/Makefile.inc $(srcdir)/libm/ld80/Makefile.inc $(srcdir)/libm/machine/mips/Makefile.inc $(srcdir)/libm/machine/nds32/Makefile.inc $(srcdir)/libm/machine/powerpc/Makefile.inc $(srcdir)/libm/machine/pru/Makefile.inc $(srcdir)/libm/machine/sparc/Makefile.inc $(srcdir)/libm/machine/spu/Makefile.inc $(srcdir)/libm/machine/riscv/Makefile.inc $(srcdir)/libm/machine/x86_64/Makefile.inc $(srcdir)/libm/ld80/Makefile.inc $(srcdir)/libm/machine/xtensa/Makefile.inc $(am__empty): $(top_builddir)/config.status: $(top_srcdir)/configure $(CONFIG_STATUS_DEPENDENCIES) $(SHELL) ./config.status --recheck @@ -7921,6 +7970,21 @@ libc/sys/w65/libc_a-syscalls.$(OBJEXT): libc/sys/w65/$(am__dirstamp) \ libc/sys/w65/$(DEPDIR)/$(am__dirstamp) libc/sys/w65/libc_a-trap.$(OBJEXT): libc/sys/w65/$(am__dirstamp) \ libc/sys/w65/$(DEPDIR)/$(am__dirstamp) +libc/sys/xtensa/$(am__dirstamp): + @$(MKDIR_P) libc/sys/xtensa + @: > libc/sys/xtensa/$(am__dirstamp) +libc/sys/xtensa/$(DEPDIR)/$(am__dirstamp): + @$(MKDIR_P) libc/sys/xtensa/$(DEPDIR) + @: > libc/sys/xtensa/$(DEPDIR)/$(am__dirstamp) +libc/sys/xtensa/libc_a-creat.$(OBJEXT): \ + libc/sys/xtensa/$(am__dirstamp) \ + libc/sys/xtensa/$(DEPDIR)/$(am__dirstamp) +libc/sys/xtensa/libc_a-isatty.$(OBJEXT): \ + libc/sys/xtensa/$(am__dirstamp) \ + libc/sys/xtensa/$(DEPDIR)/$(am__dirstamp) +libc/sys/xtensa/libc_a-clibrary_init.$(OBJEXT): \ + libc/sys/xtensa/$(am__dirstamp) \ + libc/sys/xtensa/$(DEPDIR)/$(am__dirstamp) libc/sys/z8ksim/$(am__dirstamp): @$(MKDIR_P) libc/sys/z8ksim @: > libc/sys/z8ksim/$(am__dirstamp) @@ -9643,6 +9707,33 @@ libc/machine/xstormy16/libc_a-reallocr.$(OBJEXT): \ libc/machine/xstormy16/libc_a-valloc.$(OBJEXT): \ libc/machine/xstormy16/$(am__dirstamp) \ libc/machine/xstormy16/$(DEPDIR)/$(am__dirstamp) +libc/machine/xtensa/$(am__dirstamp): + @$(MKDIR_P) libc/machine/xtensa + @: > libc/machine/xtensa/$(am__dirstamp) +libc/machine/xtensa/$(DEPDIR)/$(am__dirstamp): + @$(MKDIR_P) libc/machine/xtensa/$(DEPDIR) + @: > libc/machine/xtensa/$(DEPDIR)/$(am__dirstamp) +libc/machine/xtensa/libc_a-memcpy.$(OBJEXT): \ + libc/machine/xtensa/$(am__dirstamp) \ + libc/machine/xtensa/$(DEPDIR)/$(am__dirstamp) +libc/machine/xtensa/libc_a-memset.$(OBJEXT): \ + libc/machine/xtensa/$(am__dirstamp) \ + libc/machine/xtensa/$(DEPDIR)/$(am__dirstamp) +libc/machine/xtensa/libc_a-setjmp.$(OBJEXT): \ + libc/machine/xtensa/$(am__dirstamp) \ + libc/machine/xtensa/$(DEPDIR)/$(am__dirstamp) +libc/machine/xtensa/libc_a-strcmp.$(OBJEXT): \ + libc/machine/xtensa/$(am__dirstamp) \ + libc/machine/xtensa/$(DEPDIR)/$(am__dirstamp) +libc/machine/xtensa/libc_a-strcpy.$(OBJEXT): \ + libc/machine/xtensa/$(am__dirstamp) \ + libc/machine/xtensa/$(DEPDIR)/$(am__dirstamp) +libc/machine/xtensa/libc_a-strlen.$(OBJEXT): \ + libc/machine/xtensa/$(am__dirstamp) \ + libc/machine/xtensa/$(DEPDIR)/$(am__dirstamp) +libc/machine/xtensa/libc_a-strncpy.$(OBJEXT): \ + libc/machine/xtensa/$(am__dirstamp) \ + libc/machine/xtensa/$(DEPDIR)/$(am__dirstamp) libc/machine/z8k/$(am__dirstamp): @$(MKDIR_P) libc/machine/z8k @: > libc/machine/z8k/$(am__dirstamp) @@ -12134,6 +12225,42 @@ libm/machine/x86_64/libm_a-fetestexcept.$(OBJEXT): \ libm/machine/x86_64/libm_a-feupdateenv.$(OBJEXT): \ libm/machine/x86_64/$(am__dirstamp) \ libm/machine/x86_64/$(DEPDIR)/$(am__dirstamp) +libm/machine/xtensa/$(am__dirstamp): + @$(MKDIR_P) libm/machine/xtensa + @: > libm/machine/xtensa/$(am__dirstamp) +libm/machine/xtensa/$(DEPDIR)/$(am__dirstamp): + @$(MKDIR_P) libm/machine/xtensa/$(DEPDIR) + @: > libm/machine/xtensa/$(DEPDIR)/$(am__dirstamp) +libm/machine/xtensa/libm_a-feclearexcept.$(OBJEXT): \ + libm/machine/xtensa/$(am__dirstamp) \ + libm/machine/xtensa/$(DEPDIR)/$(am__dirstamp) +libm/machine/xtensa/libm_a-fegetenv.$(OBJEXT): \ + libm/machine/xtensa/$(am__dirstamp) \ + libm/machine/xtensa/$(DEPDIR)/$(am__dirstamp) +libm/machine/xtensa/libm_a-fegetexcept.$(OBJEXT): \ + libm/machine/xtensa/$(am__dirstamp) \ + libm/machine/xtensa/$(DEPDIR)/$(am__dirstamp) +libm/machine/xtensa/libm_a-fegetexceptflag.$(OBJEXT): \ + libm/machine/xtensa/$(am__dirstamp) \ + libm/machine/xtensa/$(DEPDIR)/$(am__dirstamp) +libm/machine/xtensa/libm_a-fegetround.$(OBJEXT): \ + libm/machine/xtensa/$(am__dirstamp) \ + libm/machine/xtensa/$(DEPDIR)/$(am__dirstamp) +libm/machine/xtensa/libm_a-feholdexcept.$(OBJEXT): \ + libm/machine/xtensa/$(am__dirstamp) \ + libm/machine/xtensa/$(DEPDIR)/$(am__dirstamp) +libm/machine/xtensa/libm_a-feraiseexcept.$(OBJEXT): \ + libm/machine/xtensa/$(am__dirstamp) \ + libm/machine/xtensa/$(DEPDIR)/$(am__dirstamp) +libm/machine/xtensa/libm_a-fetestexcept.$(OBJEXT): \ + libm/machine/xtensa/$(am__dirstamp) \ + libm/machine/xtensa/$(DEPDIR)/$(am__dirstamp) +libm/machine/xtensa/libm_a-feupdateenv.$(OBJEXT): \ + libm/machine/xtensa/$(am__dirstamp) \ + libm/machine/xtensa/$(DEPDIR)/$(am__dirstamp) +libm/machine/xtensa/libm_a-ef_sqrt.$(OBJEXT): \ + libm/machine/xtensa/$(am__dirstamp) \ + libm/machine/xtensa/$(DEPDIR)/$(am__dirstamp) clean-checkPROGRAMS: -test -z "$(check_PROGRAMS)" || rm -f $(check_PROGRAMS) @@ -12370,6 +12497,7 @@ mostlyclean-compile: -rm -f libc/machine/x86_64/*.$(OBJEXT) -rm -f libc/machine/xc16x/*.$(OBJEXT) -rm -f libc/machine/xstormy16/*.$(OBJEXT) + -rm -f libc/machine/xtensa/*.$(OBJEXT) -rm -f libc/machine/z8k/*.$(OBJEXT) -rm -f libc/misc/*.$(OBJEXT) -rm -f libc/posix/*.$(OBJEXT) @@ -12402,6 +12530,7 @@ mostlyclean-compile: -rm -f libc/sys/sysvnecv70/*.$(OBJEXT) -rm -f libc/sys/tirtos/*.$(OBJEXT) -rm -f libc/sys/w65/*.$(OBJEXT) + -rm -f libc/sys/xtensa/*.$(OBJEXT) -rm -f libc/sys/z8ksim/*.$(OBJEXT) -rm -f libc/syscalls/*.$(OBJEXT) -rm -f libc/time/*.$(OBJEXT) @@ -12425,6 +12554,7 @@ mostlyclean-compile: -rm -f libm/machine/sparc/*.$(OBJEXT) -rm -f libm/machine/spu/*.$(OBJEXT) -rm -f libm/machine/x86_64/*.$(OBJEXT) + -rm -f libm/machine/xtensa/*.$(OBJEXT) -rm -f libm/math/*.$(OBJEXT) -rm -f libm/mathfp/*.$(OBJEXT) -rm -f libm/test/*.$(OBJEXT) @@ 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@am__quote@libc/sys/z8ksim/$(DEPDIR)/libc_a-glue.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@libc/syscalls/$(DEPDIR)/libc_a-sysclose.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@libc/syscalls/$(DEPDIR)/libc_a-sysexecve.Po@am__quote@ @@ -14641,6 +14781,16 @@ distclean-compile: @AMDEP_TRUE@@am__include@ @am__quote@libm/machine/x86_64/$(DEPDIR)/libm_a-fesetround.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@libm/machine/x86_64/$(DEPDIR)/libm_a-fetestexcept.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@libm/machine/x86_64/$(DEPDIR)/libm_a-feupdateenv.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@libm/machine/xtensa/$(DEPDIR)/libm_a-ef_sqrt.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@libm/machine/xtensa/$(DEPDIR)/libm_a-feclearexcept.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@libm/machine/xtensa/$(DEPDIR)/libm_a-fegetenv.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@libm/machine/xtensa/$(DEPDIR)/libm_a-fegetexcept.Po@am__quote@ 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+@am__fastdepCC_TRUE@ $(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libm_a_CPPFLAGS) $(CPPFLAGS) $(libm_a_CFLAGS) $(CFLAGS) -MT libm/machine/xtensa/libm_a-fetestexcept.obj -MD -MP -MF libm/machine/xtensa/$(DEPDIR)/libm_a-fetestexcept.Tpo -c -o libm/machine/xtensa/libm_a-fetestexcept.obj `if test -f 'libm/machine/xtensa/fetestexcept.c'; then $(CYGPATH_W) 'libm/machine/xtensa/fetestexcept.c'; else $(CYGPATH_W) '$(srcdir)/libm/machine/xtensa/fetestexcept.c'; fi` +@am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) libm/machine/xtensa/$(DEPDIR)/libm_a-fetestexcept.Tpo libm/machine/xtensa/$(DEPDIR)/libm_a-fetestexcept.Po +@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(AM_V_CC)source='libm/machine/xtensa/fetestexcept.c' object='libm/machine/xtensa/libm_a-fetestexcept.obj' libtool=no @AMDEPBACKSLASH@ +@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ +@am__fastdepCC_FALSE@ $(AM_V_CC@am__nodep@)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libm_a_CPPFLAGS) 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'$(srcdir)/libm/machine/xtensa/feupdateenv.c'; fi` +@am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) libm/machine/xtensa/$(DEPDIR)/libm_a-feupdateenv.Tpo libm/machine/xtensa/$(DEPDIR)/libm_a-feupdateenv.Po +@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(AM_V_CC)source='libm/machine/xtensa/feupdateenv.c' object='libm/machine/xtensa/libm_a-feupdateenv.obj' libtool=no @AMDEPBACKSLASH@ +@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ +@am__fastdepCC_FALSE@ $(AM_V_CC@am__nodep@)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libm_a_CPPFLAGS) $(CPPFLAGS) $(libm_a_CFLAGS) $(CFLAGS) -c -o libm/machine/xtensa/libm_a-feupdateenv.obj `if test -f 'libm/machine/xtensa/feupdateenv.c'; then $(CYGPATH_W) 'libm/machine/xtensa/feupdateenv.c'; else $(CYGPATH_W) '$(srcdir)/libm/machine/xtensa/feupdateenv.c'; fi` + +libm/machine/xtensa/libm_a-ef_sqrt.o: libm/machine/xtensa/ef_sqrt.c +@am__fastdepCC_TRUE@ $(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libm_a_CPPFLAGS) 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libm/machine/xtensa/ef_sqrt.c +@am__fastdepCC_TRUE@ $(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libm_a_CPPFLAGS) $(CPPFLAGS) $(libm_a_CFLAGS) $(CFLAGS) -MT libm/machine/xtensa/libm_a-ef_sqrt.obj -MD -MP -MF libm/machine/xtensa/$(DEPDIR)/libm_a-ef_sqrt.Tpo -c -o libm/machine/xtensa/libm_a-ef_sqrt.obj `if test -f 'libm/machine/xtensa/ef_sqrt.c'; then $(CYGPATH_W) 'libm/machine/xtensa/ef_sqrt.c'; else $(CYGPATH_W) '$(srcdir)/libm/machine/xtensa/ef_sqrt.c'; fi` +@am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) libm/machine/xtensa/$(DEPDIR)/libm_a-ef_sqrt.Tpo libm/machine/xtensa/$(DEPDIR)/libm_a-ef_sqrt.Po +@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(AM_V_CC)source='libm/machine/xtensa/ef_sqrt.c' object='libm/machine/xtensa/libm_a-ef_sqrt.obj' libtool=no @AMDEPBACKSLASH@ +@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ +@am__fastdepCC_FALSE@ $(AM_V_CC@am__nodep@)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libm_a_CPPFLAGS) $(CPPFLAGS) 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libc/sys/z8ksim/$(DEPDIR)/$(am__dirstamp) -rm -f libc/sys/z8ksim/$(am__dirstamp) -rm -f libc/syscalls/$(DEPDIR)/$(am__dirstamp) @@ -49691,6 +50125,8 @@ distclean-generic: -rm -f libm/machine/spu/$(am__dirstamp) -rm -f libm/machine/x86_64/$(DEPDIR)/$(am__dirstamp) -rm -f libm/machine/x86_64/$(am__dirstamp) + -rm -f libm/machine/xtensa/$(DEPDIR)/$(am__dirstamp) + -rm -f libm/machine/xtensa/$(am__dirstamp) -rm -f libm/math/$(DEPDIR)/$(am__dirstamp) -rm -f libm/math/$(am__dirstamp) -rm -f libm/mathfp/$(DEPDIR)/$(am__dirstamp) @@ -49708,7 +50144,7 @@ clean-am: clean-aminfo clean-checkPROGRAMS clean-generic clean-local \ distclean: distclean-am -rm -f $(am__CONFIG_DISTCLEAN_FILES) - -rm -rf libc/argz/$(DEPDIR) libc/ctype/$(DEPDIR) libc/errno/$(DEPDIR) libc/iconv/ccs/$(DEPDIR) libc/iconv/ces/$(DEPDIR) libc/iconv/lib/$(DEPDIR) libc/locale/$(DEPDIR) libc/machine/aarch64/$(DEPDIR) libc/machine/amdgcn/$(DEPDIR) libc/machine/arc/$(DEPDIR) libc/machine/arm/$(DEPDIR) libc/machine/bfin/$(DEPDIR) libc/machine/cr16/$(DEPDIR) libc/machine/cris/$(DEPDIR) libc/machine/crx/$(DEPDIR) libc/machine/csky/$(DEPDIR) libc/machine/d10v/$(DEPDIR) libc/machine/d30v/$(DEPDIR) libc/machine/epiphany/$(DEPDIR) libc/machine/fr30/$(DEPDIR) libc/machine/frv/$(DEPDIR) libc/machine/ft32/$(DEPDIR) libc/machine/h8300/$(DEPDIR) libc/machine/h8500/$(DEPDIR) libc/machine/hppa/$(DEPDIR) libc/machine/i386/$(DEPDIR) libc/machine/i960/$(DEPDIR) libc/machine/iq2000/$(DEPDIR) libc/machine/lm32/$(DEPDIR) libc/machine/m32c/$(DEPDIR) libc/machine/m32r/$(DEPDIR) libc/machine/m68hc11/$(DEPDIR) libc/machine/m68k/$(DEPDIR) libc/machine/m88k/$(DEPDIR) libc/machine/mep/$(DEPDIR) libc/machine/microblaze/$(DEPDIR) libc/machine/mips/$(DEPDIR) libc/machine/mn10200/$(DEPDIR) libc/machine/mn10300/$(DEPDIR) libc/machine/moxie/$(DEPDIR) libc/machine/msp430/$(DEPDIR) libc/machine/mt/$(DEPDIR) libc/machine/nds32/$(DEPDIR) libc/machine/necv70/$(DEPDIR) libc/machine/nvptx/$(DEPDIR) libc/machine/or1k/$(DEPDIR) libc/machine/powerpc/$(DEPDIR) libc/machine/riscv/$(DEPDIR) libc/machine/rl78/$(DEPDIR) libc/machine/rx/$(DEPDIR) libc/machine/sh/$(DEPDIR) libc/machine/sparc/$(DEPDIR) libc/machine/spu/$(DEPDIR) libc/machine/tic4x/$(DEPDIR) libc/machine/tic6x/$(DEPDIR) libc/machine/tic80/$(DEPDIR) libc/machine/v850/$(DEPDIR) libc/machine/visium/$(DEPDIR) libc/machine/w65/$(DEPDIR) libc/machine/x86_64/$(DEPDIR) libc/machine/xc16x/$(DEPDIR) libc/machine/xstormy16/$(DEPDIR) libc/machine/z8k/$(DEPDIR) libc/misc/$(DEPDIR) libc/posix/$(DEPDIR) libc/reent/$(DEPDIR) libc/search/$(DEPDIR) libc/signal/$(DEPDIR) libc/ssp/$(DEPDIR) libc/stdio/$(DEPDIR) libc/stdio64/$(DEPDIR) libc/stdlib/$(DEPDIR) libc/string/$(DEPDIR) libc/sys/a29khif/$(DEPDIR) libc/sys/amdgcn/$(DEPDIR) libc/sys/arm/$(DEPDIR) libc/sys/d10v/$(DEPDIR) libc/sys/epiphany/$(DEPDIR) libc/sys/h8300hms/$(DEPDIR) libc/sys/h8500hms/$(DEPDIR) libc/sys/m88kbug/$(DEPDIR) libc/sys/mmixware/$(DEPDIR) libc/sys/netware/$(DEPDIR) libc/sys/or1k/$(DEPDIR) libc/sys/rdos/$(DEPDIR) libc/sys/rtems/$(DEPDIR) libc/sys/sh/$(DEPDIR) libc/sys/sysmec/$(DEPDIR) libc/sys/sysnec810/$(DEPDIR) libc/sys/sysnecv850/$(DEPDIR) libc/sys/sysvi386/$(DEPDIR) libc/sys/sysvnecv70/$(DEPDIR) libc/sys/tirtos/$(DEPDIR) libc/sys/w65/$(DEPDIR) libc/sys/z8ksim/$(DEPDIR) libc/syscalls/$(DEPDIR) libc/time/$(DEPDIR) libc/unix/$(DEPDIR) libc/xdr/$(DEPDIR) libm/common/$(DEPDIR) libm/complex/$(DEPDIR) libm/fenv/$(DEPDIR) libm/ld/$(DEPDIR) libm/ld128/$(DEPDIR) libm/ld80/$(DEPDIR) libm/machine/aarch64/$(DEPDIR) libm/machine/amdgcn/$(DEPDIR) libm/machine/arm/$(DEPDIR) libm/machine/i386/$(DEPDIR) libm/machine/mips/$(DEPDIR) libm/machine/nds32/$(DEPDIR) libm/machine/powerpc/$(DEPDIR) libm/machine/pru/$(DEPDIR) libm/machine/riscv/$(DEPDIR) libm/machine/sparc/$(DEPDIR) libm/machine/spu/$(DEPDIR) libm/machine/x86_64/$(DEPDIR) libm/math/$(DEPDIR) libm/mathfp/$(DEPDIR) libm/test/$(DEPDIR) + -rm -rf libc/argz/$(DEPDIR) libc/ctype/$(DEPDIR) libc/errno/$(DEPDIR) libc/iconv/ccs/$(DEPDIR) libc/iconv/ces/$(DEPDIR) libc/iconv/lib/$(DEPDIR) libc/locale/$(DEPDIR) libc/machine/aarch64/$(DEPDIR) libc/machine/amdgcn/$(DEPDIR) libc/machine/arc/$(DEPDIR) libc/machine/arm/$(DEPDIR) libc/machine/bfin/$(DEPDIR) libc/machine/cr16/$(DEPDIR) libc/machine/cris/$(DEPDIR) libc/machine/crx/$(DEPDIR) libc/machine/csky/$(DEPDIR) libc/machine/d10v/$(DEPDIR) libc/machine/d30v/$(DEPDIR) libc/machine/epiphany/$(DEPDIR) libc/machine/fr30/$(DEPDIR) libc/machine/frv/$(DEPDIR) libc/machine/ft32/$(DEPDIR) libc/machine/h8300/$(DEPDIR) libc/machine/h8500/$(DEPDIR) libc/machine/hppa/$(DEPDIR) libc/machine/i386/$(DEPDIR) libc/machine/i960/$(DEPDIR) libc/machine/iq2000/$(DEPDIR) libc/machine/lm32/$(DEPDIR) libc/machine/m32c/$(DEPDIR) libc/machine/m32r/$(DEPDIR) libc/machine/m68hc11/$(DEPDIR) libc/machine/m68k/$(DEPDIR) libc/machine/m88k/$(DEPDIR) libc/machine/mep/$(DEPDIR) libc/machine/microblaze/$(DEPDIR) libc/machine/mips/$(DEPDIR) libc/machine/mn10200/$(DEPDIR) libc/machine/mn10300/$(DEPDIR) libc/machine/moxie/$(DEPDIR) libc/machine/msp430/$(DEPDIR) libc/machine/mt/$(DEPDIR) libc/machine/nds32/$(DEPDIR) libc/machine/necv70/$(DEPDIR) libc/machine/nvptx/$(DEPDIR) libc/machine/or1k/$(DEPDIR) libc/machine/powerpc/$(DEPDIR) libc/machine/riscv/$(DEPDIR) libc/machine/rl78/$(DEPDIR) libc/machine/rx/$(DEPDIR) libc/machine/sh/$(DEPDIR) libc/machine/sparc/$(DEPDIR) libc/machine/spu/$(DEPDIR) libc/machine/tic4x/$(DEPDIR) libc/machine/tic6x/$(DEPDIR) libc/machine/tic80/$(DEPDIR) libc/machine/v850/$(DEPDIR) libc/machine/visium/$(DEPDIR) libc/machine/w65/$(DEPDIR) libc/machine/x86_64/$(DEPDIR) libc/machine/xc16x/$(DEPDIR) libc/machine/xstormy16/$(DEPDIR) libc/machine/xtensa/$(DEPDIR) libc/machine/z8k/$(DEPDIR) libc/misc/$(DEPDIR) libc/posix/$(DEPDIR) libc/reent/$(DEPDIR) libc/search/$(DEPDIR) libc/signal/$(DEPDIR) libc/ssp/$(DEPDIR) libc/stdio/$(DEPDIR) libc/stdio64/$(DEPDIR) libc/stdlib/$(DEPDIR) libc/string/$(DEPDIR) libc/sys/a29khif/$(DEPDIR) libc/sys/amdgcn/$(DEPDIR) libc/sys/arm/$(DEPDIR) libc/sys/d10v/$(DEPDIR) libc/sys/epiphany/$(DEPDIR) libc/sys/h8300hms/$(DEPDIR) libc/sys/h8500hms/$(DEPDIR) libc/sys/m88kbug/$(DEPDIR) libc/sys/mmixware/$(DEPDIR) libc/sys/netware/$(DEPDIR) libc/sys/or1k/$(DEPDIR) libc/sys/rdos/$(DEPDIR) libc/sys/rtems/$(DEPDIR) libc/sys/sh/$(DEPDIR) libc/sys/sysmec/$(DEPDIR) libc/sys/sysnec810/$(DEPDIR) libc/sys/sysnecv850/$(DEPDIR) libc/sys/sysvi386/$(DEPDIR) libc/sys/sysvnecv70/$(DEPDIR) libc/sys/tirtos/$(DEPDIR) libc/sys/w65/$(DEPDIR) libc/sys/xtensa/$(DEPDIR) libc/sys/z8ksim/$(DEPDIR) libc/syscalls/$(DEPDIR) libc/time/$(DEPDIR) libc/unix/$(DEPDIR) libc/xdr/$(DEPDIR) libm/common/$(DEPDIR) libm/complex/$(DEPDIR) libm/fenv/$(DEPDIR) libm/ld/$(DEPDIR) libm/ld128/$(DEPDIR) libm/ld80/$(DEPDIR) libm/machine/aarch64/$(DEPDIR) libm/machine/amdgcn/$(DEPDIR) libm/machine/arm/$(DEPDIR) libm/machine/i386/$(DEPDIR) libm/machine/mips/$(DEPDIR) libm/machine/nds32/$(DEPDIR) libm/machine/powerpc/$(DEPDIR) libm/machine/pru/$(DEPDIR) libm/machine/riscv/$(DEPDIR) libm/machine/sparc/$(DEPDIR) libm/machine/spu/$(DEPDIR) libm/machine/x86_64/$(DEPDIR) libm/machine/xtensa/$(DEPDIR) libm/math/$(DEPDIR) libm/mathfp/$(DEPDIR) libm/test/$(DEPDIR) -rm -f Makefile distclean-am: clean-am distclean-DEJAGNU distclean-compile \ distclean-generic distclean-hdr distclean-local distclean-tags @@ -49846,7 +50282,7 @@ installcheck-am: maintainer-clean: maintainer-clean-am -rm -f $(am__CONFIG_DISTCLEAN_FILES) -rm -rf $(top_srcdir)/autom4te.cache - -rm -rf libc/argz/$(DEPDIR) libc/ctype/$(DEPDIR) libc/errno/$(DEPDIR) libc/iconv/ccs/$(DEPDIR) libc/iconv/ces/$(DEPDIR) libc/iconv/lib/$(DEPDIR) libc/locale/$(DEPDIR) libc/machine/aarch64/$(DEPDIR) libc/machine/amdgcn/$(DEPDIR) libc/machine/arc/$(DEPDIR) libc/machine/arm/$(DEPDIR) libc/machine/bfin/$(DEPDIR) libc/machine/cr16/$(DEPDIR) libc/machine/cris/$(DEPDIR) libc/machine/crx/$(DEPDIR) libc/machine/csky/$(DEPDIR) libc/machine/d10v/$(DEPDIR) libc/machine/d30v/$(DEPDIR) libc/machine/epiphany/$(DEPDIR) libc/machine/fr30/$(DEPDIR) libc/machine/frv/$(DEPDIR) libc/machine/ft32/$(DEPDIR) libc/machine/h8300/$(DEPDIR) libc/machine/h8500/$(DEPDIR) libc/machine/hppa/$(DEPDIR) libc/machine/i386/$(DEPDIR) libc/machine/i960/$(DEPDIR) libc/machine/iq2000/$(DEPDIR) libc/machine/lm32/$(DEPDIR) libc/machine/m32c/$(DEPDIR) libc/machine/m32r/$(DEPDIR) libc/machine/m68hc11/$(DEPDIR) libc/machine/m68k/$(DEPDIR) libc/machine/m88k/$(DEPDIR) libc/machine/mep/$(DEPDIR) libc/machine/microblaze/$(DEPDIR) libc/machine/mips/$(DEPDIR) libc/machine/mn10200/$(DEPDIR) libc/machine/mn10300/$(DEPDIR) libc/machine/moxie/$(DEPDIR) libc/machine/msp430/$(DEPDIR) libc/machine/mt/$(DEPDIR) libc/machine/nds32/$(DEPDIR) libc/machine/necv70/$(DEPDIR) libc/machine/nvptx/$(DEPDIR) libc/machine/or1k/$(DEPDIR) libc/machine/powerpc/$(DEPDIR) libc/machine/riscv/$(DEPDIR) libc/machine/rl78/$(DEPDIR) libc/machine/rx/$(DEPDIR) libc/machine/sh/$(DEPDIR) libc/machine/sparc/$(DEPDIR) libc/machine/spu/$(DEPDIR) libc/machine/tic4x/$(DEPDIR) libc/machine/tic6x/$(DEPDIR) libc/machine/tic80/$(DEPDIR) libc/machine/v850/$(DEPDIR) libc/machine/visium/$(DEPDIR) libc/machine/w65/$(DEPDIR) libc/machine/x86_64/$(DEPDIR) libc/machine/xc16x/$(DEPDIR) libc/machine/xstormy16/$(DEPDIR) libc/machine/z8k/$(DEPDIR) libc/misc/$(DEPDIR) libc/posix/$(DEPDIR) libc/reent/$(DEPDIR) libc/search/$(DEPDIR) libc/signal/$(DEPDIR) libc/ssp/$(DEPDIR) libc/stdio/$(DEPDIR) libc/stdio64/$(DEPDIR) libc/stdlib/$(DEPDIR) libc/string/$(DEPDIR) libc/sys/a29khif/$(DEPDIR) libc/sys/amdgcn/$(DEPDIR) libc/sys/arm/$(DEPDIR) libc/sys/d10v/$(DEPDIR) libc/sys/epiphany/$(DEPDIR) libc/sys/h8300hms/$(DEPDIR) libc/sys/h8500hms/$(DEPDIR) libc/sys/m88kbug/$(DEPDIR) libc/sys/mmixware/$(DEPDIR) libc/sys/netware/$(DEPDIR) libc/sys/or1k/$(DEPDIR) libc/sys/rdos/$(DEPDIR) libc/sys/rtems/$(DEPDIR) libc/sys/sh/$(DEPDIR) libc/sys/sysmec/$(DEPDIR) libc/sys/sysnec810/$(DEPDIR) libc/sys/sysnecv850/$(DEPDIR) libc/sys/sysvi386/$(DEPDIR) libc/sys/sysvnecv70/$(DEPDIR) libc/sys/tirtos/$(DEPDIR) libc/sys/w65/$(DEPDIR) libc/sys/z8ksim/$(DEPDIR) libc/syscalls/$(DEPDIR) libc/time/$(DEPDIR) libc/unix/$(DEPDIR) libc/xdr/$(DEPDIR) libm/common/$(DEPDIR) libm/complex/$(DEPDIR) libm/fenv/$(DEPDIR) libm/ld/$(DEPDIR) libm/ld128/$(DEPDIR) libm/ld80/$(DEPDIR) libm/machine/aarch64/$(DEPDIR) libm/machine/amdgcn/$(DEPDIR) libm/machine/arm/$(DEPDIR) libm/machine/i386/$(DEPDIR) libm/machine/mips/$(DEPDIR) libm/machine/nds32/$(DEPDIR) libm/machine/powerpc/$(DEPDIR) libm/machine/pru/$(DEPDIR) libm/machine/riscv/$(DEPDIR) libm/machine/sparc/$(DEPDIR) libm/machine/spu/$(DEPDIR) libm/machine/x86_64/$(DEPDIR) libm/math/$(DEPDIR) libm/mathfp/$(DEPDIR) libm/test/$(DEPDIR) + -rm -rf libc/argz/$(DEPDIR) libc/ctype/$(DEPDIR) libc/errno/$(DEPDIR) libc/iconv/ccs/$(DEPDIR) libc/iconv/ces/$(DEPDIR) libc/iconv/lib/$(DEPDIR) libc/locale/$(DEPDIR) libc/machine/aarch64/$(DEPDIR) libc/machine/amdgcn/$(DEPDIR) libc/machine/arc/$(DEPDIR) libc/machine/arm/$(DEPDIR) libc/machine/bfin/$(DEPDIR) libc/machine/cr16/$(DEPDIR) libc/machine/cris/$(DEPDIR) libc/machine/crx/$(DEPDIR) libc/machine/csky/$(DEPDIR) libc/machine/d10v/$(DEPDIR) libc/machine/d30v/$(DEPDIR) libc/machine/epiphany/$(DEPDIR) libc/machine/fr30/$(DEPDIR) libc/machine/frv/$(DEPDIR) libc/machine/ft32/$(DEPDIR) libc/machine/h8300/$(DEPDIR) libc/machine/h8500/$(DEPDIR) libc/machine/hppa/$(DEPDIR) libc/machine/i386/$(DEPDIR) libc/machine/i960/$(DEPDIR) libc/machine/iq2000/$(DEPDIR) libc/machine/lm32/$(DEPDIR) libc/machine/m32c/$(DEPDIR) libc/machine/m32r/$(DEPDIR) libc/machine/m68hc11/$(DEPDIR) libc/machine/m68k/$(DEPDIR) libc/machine/m88k/$(DEPDIR) libc/machine/mep/$(DEPDIR) libc/machine/microblaze/$(DEPDIR) libc/machine/mips/$(DEPDIR) libc/machine/mn10200/$(DEPDIR) libc/machine/mn10300/$(DEPDIR) libc/machine/moxie/$(DEPDIR) libc/machine/msp430/$(DEPDIR) libc/machine/mt/$(DEPDIR) libc/machine/nds32/$(DEPDIR) libc/machine/necv70/$(DEPDIR) libc/machine/nvptx/$(DEPDIR) libc/machine/or1k/$(DEPDIR) libc/machine/powerpc/$(DEPDIR) libc/machine/riscv/$(DEPDIR) libc/machine/rl78/$(DEPDIR) libc/machine/rx/$(DEPDIR) libc/machine/sh/$(DEPDIR) libc/machine/sparc/$(DEPDIR) libc/machine/spu/$(DEPDIR) libc/machine/tic4x/$(DEPDIR) libc/machine/tic6x/$(DEPDIR) libc/machine/tic80/$(DEPDIR) libc/machine/v850/$(DEPDIR) libc/machine/visium/$(DEPDIR) libc/machine/w65/$(DEPDIR) libc/machine/x86_64/$(DEPDIR) libc/machine/xc16x/$(DEPDIR) libc/machine/xstormy16/$(DEPDIR) libc/machine/xtensa/$(DEPDIR) libc/machine/z8k/$(DEPDIR) libc/misc/$(DEPDIR) libc/posix/$(DEPDIR) libc/reent/$(DEPDIR) libc/search/$(DEPDIR) libc/signal/$(DEPDIR) libc/ssp/$(DEPDIR) libc/stdio/$(DEPDIR) libc/stdio64/$(DEPDIR) libc/stdlib/$(DEPDIR) libc/string/$(DEPDIR) libc/sys/a29khif/$(DEPDIR) libc/sys/amdgcn/$(DEPDIR) libc/sys/arm/$(DEPDIR) libc/sys/d10v/$(DEPDIR) libc/sys/epiphany/$(DEPDIR) libc/sys/h8300hms/$(DEPDIR) libc/sys/h8500hms/$(DEPDIR) libc/sys/m88kbug/$(DEPDIR) libc/sys/mmixware/$(DEPDIR) libc/sys/netware/$(DEPDIR) libc/sys/or1k/$(DEPDIR) libc/sys/rdos/$(DEPDIR) libc/sys/rtems/$(DEPDIR) libc/sys/sh/$(DEPDIR) libc/sys/sysmec/$(DEPDIR) libc/sys/sysnec810/$(DEPDIR) libc/sys/sysnecv850/$(DEPDIR) libc/sys/sysvi386/$(DEPDIR) libc/sys/sysvnecv70/$(DEPDIR) libc/sys/tirtos/$(DEPDIR) libc/sys/w65/$(DEPDIR) libc/sys/xtensa/$(DEPDIR) libc/sys/z8ksim/$(DEPDIR) libc/syscalls/$(DEPDIR) libc/time/$(DEPDIR) libc/unix/$(DEPDIR) libc/xdr/$(DEPDIR) libm/common/$(DEPDIR) libm/complex/$(DEPDIR) libm/fenv/$(DEPDIR) libm/ld/$(DEPDIR) libm/ld128/$(DEPDIR) libm/ld80/$(DEPDIR) libm/machine/aarch64/$(DEPDIR) libm/machine/amdgcn/$(DEPDIR) libm/machine/arm/$(DEPDIR) libm/machine/i386/$(DEPDIR) libm/machine/mips/$(DEPDIR) libm/machine/nds32/$(DEPDIR) libm/machine/powerpc/$(DEPDIR) libm/machine/pru/$(DEPDIR) libm/machine/riscv/$(DEPDIR) libm/machine/sparc/$(DEPDIR) libm/machine/spu/$(DEPDIR) libm/machine/x86_64/$(DEPDIR) libm/machine/xtensa/$(DEPDIR) libm/math/$(DEPDIR) libm/mathfp/$(DEPDIR) libm/test/$(DEPDIR) -rm -f Makefile maintainer-clean-am: distclean-am maintainer-clean-aminfo \ maintainer-clean-generic maintainer-clean-local diff --git a/newlib/configure b/newlib/configure index 77ab8ec..0585e0e 100755 --- a/newlib/configure +++ b/newlib/configure @@ -603,6 +603,8 @@ HAVE_MULTISUBDIR_FALSE HAVE_MULTISUBDIR_TRUE HAVE_DOC_FALSE HAVE_DOC_TRUE +HAVE_LIBM_MACHINE_XTENSA_FALSE +HAVE_LIBM_MACHINE_XTENSA_TRUE HAVE_LIBM_MACHINE_X86_64_FALSE HAVE_LIBM_MACHINE_X86_64_TRUE HAVE_LIBM_MACHINE_RISCV_FALSE @@ -627,6 +629,8 @@ HAVE_LIBM_MACHINE_AMDGCN_FALSE HAVE_LIBM_MACHINE_AMDGCN_TRUE HAVE_LIBM_MACHINE_AARCH64_FALSE HAVE_LIBM_MACHINE_AARCH64_TRUE +XTENSA_XCHAL_HAVE_FP_SQRT_FALSE +XTENSA_XCHAL_HAVE_FP_SQRT_TRUE HAS_NDS32_FPU_DP_FALSE HAS_NDS32_FPU_DP_TRUE HAS_NDS32_FPU_SP_FALSE @@ -637,6 +641,8 @@ HAVE_FPMATH_H_FALSE HAVE_FPMATH_H_TRUE HAVE_LIBC_MACHINE_Z8K_FALSE HAVE_LIBC_MACHINE_Z8K_TRUE +HAVE_LIBC_MACHINE_XTENSA_FALSE +HAVE_LIBC_MACHINE_XTENSA_TRUE HAVE_LIBC_MACHINE_XSTORMY16_FALSE HAVE_LIBC_MACHINE_XSTORMY16_TRUE HAVE_LIBC_MACHINE_XC16X_FALSE @@ -751,6 +757,8 @@ HAVE_LIBC_MACHINE_AMDGCN_FALSE HAVE_LIBC_MACHINE_AMDGCN_TRUE HAVE_LIBC_MACHINE_AARCH64_FALSE HAVE_LIBC_MACHINE_AARCH64_TRUE +XTENSA_ESP32_PSRAM_CACHE_FIX_FALSE +XTENSA_ESP32_PSRAM_CACHE_FIX_TRUE HAVE_SPU_EA_FALSE HAVE_SPU_EA_TRUE SH64_FALSE @@ -767,6 +775,8 @@ HAVE_LONG_DOUBLE_FALSE HAVE_LONG_DOUBLE_TRUE HAVE_LIBC_SYS_Z8KSIM_DIR_FALSE HAVE_LIBC_SYS_Z8KSIM_DIR_TRUE +HAVE_LIBC_SYS_XTENSA_DIR_FALSE +HAVE_LIBC_SYS_XTENSA_DIR_TRUE HAVE_LIBC_SYS_W65_DIR_FALSE HAVE_LIBC_SYS_W65_DIR_TRUE HAVE_LIBC_SYS_TIRTOS_DIR_FALSE @@ -5502,6 +5512,13 @@ else HAVE_LIBC_SYS_W65_DIR_TRUE='#' HAVE_LIBC_SYS_W65_DIR_FALSE= fi + if test "${sys_dir}" = xtensa; then + HAVE_LIBC_SYS_XTENSA_DIR_TRUE= + HAVE_LIBC_SYS_XTENSA_DIR_FALSE='#' +else + HAVE_LIBC_SYS_XTENSA_DIR_TRUE='#' + HAVE_LIBC_SYS_XTENSA_DIR_FALSE= +fi if test "${sys_dir}" = z8ksim; then HAVE_LIBC_SYS_Z8KSIM_DIR_TRUE= HAVE_LIBC_SYS_Z8KSIM_DIR_FALSE='#' @@ -5716,6 +5733,15 @@ else fi + if echo $CC | grep mfix-esp32-psram-cache-issue >/dev/null 2>&1; then + XTENSA_ESP32_PSRAM_CACHE_FIX_TRUE= + XTENSA_ESP32_PSRAM_CACHE_FIX_FALSE='#' +else + XTENSA_ESP32_PSRAM_CACHE_FIX_TRUE='#' + XTENSA_ESP32_PSRAM_CACHE_FIX_FALSE= +fi + + if test "${machine_dir}" = aarch64; then HAVE_LIBC_MACHINE_AARCH64_TRUE= @@ -6116,6 +6142,13 @@ else HAVE_LIBC_MACHINE_XSTORMY16_TRUE='#' HAVE_LIBC_MACHINE_XSTORMY16_FALSE= fi + if test "${machine_dir}" = xtensa; then + HAVE_LIBC_MACHINE_XTENSA_TRUE= + HAVE_LIBC_MACHINE_XTENSA_FALSE='#' +else + HAVE_LIBC_MACHINE_XTENSA_TRUE='#' + HAVE_LIBC_MACHINE_XTENSA_FALSE= +fi if test "${machine_dir}" = z8k; then HAVE_LIBC_MACHINE_Z8K_TRUE= HAVE_LIBC_MACHINE_Z8K_FALSE='#' @@ -6221,6 +6254,47 @@ else fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for XCHAL_HAVE_FP_SQRT" >&5 +$as_echo_n "checking for XCHAL_HAVE_FP_SQRT... " >&6; } +if ${newlib_cv_xchal_have_fp_sqrt+:} false; then : + $as_echo_n "(cached) " >&6 +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#define _LIBM +// targ-include does not exist yet, use relative path +#include "../sys/xtensa/include/xtensa/config/core-isa.h" +#if (!XCHAL_HAVE_FP_SQRT) +# error "Have not XCHAL_HAVE_FP_SQRT" +#endif + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_cpp "$LINENO"; then : + newlib_cv_xchal_have_fp_sqrt="yes" +else + newlib_cv_xchal_have_fp_sqrt="no" +fi +rm -f conftest.err conftest.i conftest.$ac_ext +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $newlib_cv_xchal_have_fp_sqrt" >&5 +$as_echo "$newlib_cv_xchal_have_fp_sqrt" >&6; } + + if test "$newlib_cv_xchal_have_fp_sqrt" = "yes"; then + XTENSA_XCHAL_HAVE_FP_SQRT_TRUE= + XTENSA_XCHAL_HAVE_FP_SQRT_FALSE='#' +else + XTENSA_XCHAL_HAVE_FP_SQRT_TRUE='#' + XTENSA_XCHAL_HAVE_FP_SQRT_FALSE= +fi + + if test "${libm_machine_dir}" = "aarch64"; then HAVE_LIBM_MACHINE_AARCH64_TRUE= @@ -6318,6 +6392,14 @@ else HAVE_LIBM_MACHINE_X86_64_FALSE= fi + if test "${libm_machine_dir}" = "xtensa"; then + HAVE_LIBM_MACHINE_XTENSA_TRUE= + HAVE_LIBM_MACHINE_XTENSA_FALSE='#' +else + HAVE_LIBM_MACHINE_XTENSA_TRUE='#' + HAVE_LIBM_MACHINE_XTENSA_FALSE= +fi + @@ -7617,6 +7699,10 @@ if test -z "${HAVE_LIBC_SYS_W65_DIR_TRUE}" && test -z "${HAVE_LIBC_SYS_W65_DIR_F as_fn_error $? "conditional \"HAVE_LIBC_SYS_W65_DIR\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi +if test -z "${HAVE_LIBC_SYS_XTENSA_DIR_TRUE}" && test -z "${HAVE_LIBC_SYS_XTENSA_DIR_FALSE}"; then + as_fn_error $? "conditional \"HAVE_LIBC_SYS_XTENSA_DIR\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi if test -z "${HAVE_LIBC_SYS_Z8KSIM_DIR_TRUE}" && test -z "${HAVE_LIBC_SYS_Z8KSIM_DIR_FALSE}"; then as_fn_error $? "conditional \"HAVE_LIBC_SYS_Z8KSIM_DIR\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 @@ -7649,6 +7735,10 @@ if test -z "${HAVE_SPU_EA_TRUE}" && test -z "${HAVE_SPU_EA_FALSE}"; then as_fn_error $? "conditional \"HAVE_SPU_EA\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi +if test -z "${XTENSA_ESP32_PSRAM_CACHE_FIX_TRUE}" && test -z "${XTENSA_ESP32_PSRAM_CACHE_FIX_FALSE}"; then + as_fn_error $? "conditional \"XTENSA_ESP32_PSRAM_CACHE_FIX\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi if test -z "${HAVE_LIBC_MACHINE_AARCH64_TRUE}" && test -z "${HAVE_LIBC_MACHINE_AARCH64_FALSE}"; then as_fn_error $? "conditional \"HAVE_LIBC_MACHINE_AARCH64\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 @@ -7877,6 +7967,10 @@ if test -z "${HAVE_LIBC_MACHINE_XSTORMY16_TRUE}" && test -z "${HAVE_LIBC_MACHINE as_fn_error $? "conditional \"HAVE_LIBC_MACHINE_XSTORMY16\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi +if test -z "${HAVE_LIBC_MACHINE_XTENSA_TRUE}" && test -z "${HAVE_LIBC_MACHINE_XTENSA_FALSE}"; then + as_fn_error $? "conditional \"HAVE_LIBC_MACHINE_XTENSA\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi if test -z "${HAVE_LIBC_MACHINE_Z8K_TRUE}" && test -z "${HAVE_LIBC_MACHINE_Z8K_FALSE}"; then as_fn_error $? "conditional \"HAVE_LIBC_MACHINE_Z8K\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 @@ -7897,6 +7991,10 @@ if test -z "${HAS_NDS32_FPU_DP_TRUE}" && test -z "${HAS_NDS32_FPU_DP_FALSE}"; th as_fn_error $? "conditional \"HAS_NDS32_FPU_DP\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi +if test -z "${XTENSA_XCHAL_HAVE_FP_SQRT_TRUE}" && test -z "${XTENSA_XCHAL_HAVE_FP_SQRT_FALSE}"; then + as_fn_error $? "conditional \"XTENSA_XCHAL_HAVE_FP_SQRT\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi if test -z "${HAVE_LIBM_MACHINE_AARCH64_TRUE}" && test -z "${HAVE_LIBM_MACHINE_AARCH64_FALSE}"; then as_fn_error $? "conditional \"HAVE_LIBM_MACHINE_AARCH64\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 @@ -7945,6 +8043,10 @@ if test -z "${HAVE_LIBM_MACHINE_X86_64_TRUE}" && test -z "${HAVE_LIBM_MACHINE_X8 as_fn_error $? "conditional \"HAVE_LIBM_MACHINE_X86_64\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi +if test -z "${HAVE_LIBM_MACHINE_XTENSA_TRUE}" && test -z "${HAVE_LIBM_MACHINE_XTENSA_FALSE}"; then + as_fn_error $? "conditional \"HAVE_LIBM_MACHINE_XTENSA\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi if test -z "${HAVE_DOC_TRUE}" && test -z "${HAVE_DOC_FALSE}"; then as_fn_error $? "conditional \"HAVE_DOC\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 diff --git a/newlib/configure.host b/newlib/configure.host index 5f42752..3861834 100644 --- a/newlib/configure.host +++ b/newlib/configure.host @@ -365,6 +365,13 @@ case "${host_cpu}" in newlib_cflags="${newlib_cflags} -DMALLOC_PROVIDED" newlib_cflags="${newlib_cflags} -DPREFER_SIZE_OVER_SPEED" ;; + xtensa) + libm_machine_dir=xtensa + machine_dir=xtensa + newlib_cflags="${newlib_cflags} -mlongcalls" + default_newlib_atexit_dynamic_alloc="no" + have_init_fini=no + ;; z8k) machine_dir=z8k ;; @@ -569,6 +576,9 @@ case "${host}" in w65-*-*) sys_dir=w65 ;; + xtensa*-*-*) + sys_dir=xtensa + ;; z8k-*-coff) sys_dir=z8ksim ;; @@ -861,6 +871,9 @@ newlib_cflags="${newlib_cflags} -DCLOCK_PROVIDED -DMALLOC_PROVIDED -DEXIT_PROVID xstormy16-*-*) syscall_dir=syscalls ;; + xtensa*-*-* | xtensa*-*) + syscall_dir=syscalls + ;; z8k-*-*) syscall_dir=syscalls ;; diff --git a/newlib/libc/acinclude.m4 b/newlib/libc/acinclude.m4 index 4266266..24148b1 100644 --- a/newlib/libc/acinclude.m4 +++ b/newlib/libc/acinclude.m4 @@ -23,6 +23,7 @@ m4_foreach_w([SYS_DIR], [ sh sysmec sysnec810 sysnecv850 sysvi386 sysvnecv70 tic80 tirtos w65 + xtensa z8ksim ], [AM_CONDITIONAL([HAVE_LIBC_SYS_]m4_toupper(SYS_DIR)[_DIR], test "${sys_dir}" = SYS_DIR)]) @@ -38,6 +39,7 @@ m4_include([libc/machine/nds32/acinclude.m4]) m4_include([libc/machine/powerpc/acinclude.m4]) m4_include([libc/machine/sh/acinclude.m4]) m4_include([libc/machine/spu/acinclude.m4]) +m4_include([libc/machine/xtensa/acinclude.m4]) m4_foreach_w([MACHINE], [ aarch64 amdgcn arc arm @@ -58,7 +60,7 @@ m4_foreach_w([MACHINE], [ tic4x tic6x tic80 v850 visium w65 - x86_64 xc16x xstormy16 + x86_64 xc16x xstormy16 xtensa z8k ], [AM_CONDITIONAL([HAVE_LIBC_MACHINE_]m4_toupper(MACHINE), test "${machine_dir}" = MACHINE)]) diff --git a/newlib/libc/include/machine/ieeefp.h b/newlib/libc/include/machine/ieeefp.h index abadf52..ede75e1 100644 --- a/newlib/libc/include/machine/ieeefp.h +++ b/newlib/libc/include/machine/ieeefp.h @@ -506,6 +506,10 @@ #define __IEEE_LITTLE_ENDIAN #endif +#ifdef __XTENSA_EB__ +#define __IEEE_BIG_ENDIAN +#endif + #ifdef __CYGWIN__ #define __OBSOLETE_MATH_DEFAULT 0 #endif diff --git a/newlib/libc/include/machine/setjmp.h b/newlib/libc/include/machine/setjmp.h index 29b76ce..e3534e1 100644 --- a/newlib/libc/include/machine/setjmp.h +++ b/newlib/libc/include/machine/setjmp.h @@ -304,6 +304,35 @@ _BEGIN_STD_C #define _JBLEN 8 #endif +#ifdef __XTENSA__ +#if __XTENSA_WINDOWED_ABI__ + +/* The jmp_buf structure for Xtensa windowed ABI holds the following + (where "proc" is the procedure that calls setjmp): 4-12 registers + from the window of proc, the 4 words from the save area at proc's $sp + (in case a subsequent alloca in proc moves $sp), and the return + address within proc. Everything else is saved on the stack in the + normal save areas. The jmp_buf structure is: + + struct jmp_buf { + int regs[12]; + int save[4]; + void *return_address; + } + + See the setjmp code for details. */ + +/* sizeof(struct jmp_buf) */ +#define _JBLEN 17 + +#else /* __XTENSA_CALL0_ABI__ */ + +/* a0, a1, a12, a13, a14, a15 */ +#define _JBLEN 6 + +#endif /* __XTENSA_CALL0_ABI__ */ +#endif /* __XTENSA__ */ + #ifdef __mep__ /* 16 GPRs, pc, hi, lo */ #define _JBLEN 19 diff --git a/newlib/libc/machine/Makefile.inc b/newlib/libc/machine/Makefile.inc index 8aae2c5..a53cf9c 100644 --- a/newlib/libc/machine/Makefile.inc +++ b/newlib/libc/machine/Makefile.inc @@ -169,6 +169,9 @@ endif if HAVE_LIBC_MACHINE_XSTORMY16 include %D%/xstormy16/Makefile.inc endif +if HAVE_LIBC_MACHINE_XTENSA +include %D%/xtensa/Makefile.inc +endif if HAVE_LIBC_MACHINE_Z8K include %D%/z8k/Makefile.inc endif diff --git a/newlib/libc/machine/xtensa/Makefile.inc b/newlib/libc/machine/xtensa/Makefile.inc new file mode 100644 index 0000000..158c2be --- /dev/null +++ b/newlib/libc/machine/xtensa/Makefile.inc @@ -0,0 +1,8 @@ +libc_a_SOURCES += \ + %D%/memcpy.S %D%/memset.S %D%/setjmp.S %D%/strcmp.S %D%/strcpy.S \ + %D%/strlen.S %D%/strncpy.S + +if XTENSA_ESP32_PSRAM_CACHE_FIX +libc_a_CPPFLAGS_%C% = \ + -DXTENSA_ESP32_PSRAM_CACHE_FIX +endif diff --git a/newlib/libc/machine/xtensa/acinclude.m4 b/newlib/libc/machine/xtensa/acinclude.m4 new file mode 100644 index 0000000..863d750 --- /dev/null +++ b/newlib/libc/machine/xtensa/acinclude.m4 @@ -0,0 +1 @@ +AM_CONDITIONAL([XTENSA_ESP32_PSRAM_CACHE_FIX], [echo $CC | grep mfix-esp32-psram-cache-issue >/dev/null 2>&1]) diff --git a/newlib/libc/machine/xtensa/memcpy.S b/newlib/libc/machine/xtensa/memcpy.S new file mode 100644 index 0000000..77b026a --- /dev/null +++ b/newlib/libc/machine/xtensa/memcpy.S @@ -0,0 +1,343 @@ +/* ANSI C standard library function memcpy. + + Copyright (c) 2002-2008 Tensilica Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +#include "xtensa-asm.h" + +/* If the Xtensa Unaligned Load Exception option is not used, this + code can run a few cycles faster by relying on the low address bits + being ignored. However, if the code is then run with an Xtensa ISS + client that checks for unaligned accesses, it will produce a lot of + warning messages. Set this flag to disable the use of unaligned + accesses and keep the ISS happy. */ + +/* #define UNALIGNED_ADDRESSES_CHECKED XCHAL_UNALIGNED_LOAD_EXCEPTION */ +#define UNALIGNED_ADDRESSES_CHECKED 1 + + +/* void *memcpy (void *dst, const void *src, size_t len) + + The algorithm is as follows: + + If the destination is unaligned, align it by conditionally + copying 1- and/or 2-byte pieces. + + If the source is aligned, copy 16 bytes with a loop, and then finish up + with 8, 4, 2, and 1-byte copies conditional on the length. + + Else (if source is unaligned), do the same, but use SRC to align the + source data. + + This code tries to use fall-through branches for the common + case of aligned source and destination and multiple of 4 (or 8) length. */ + + +/* Byte by byte copy. */ + + .text + .begin schedule + .align XCHAL_INST_FETCH_WIDTH + .literal_position +__memcpy_aux: + + /* Skip bytes to get proper alignment for three-byte loop */ +.skip XCHAL_INST_FETCH_WIDTH - 3 + +.Lbytecopy: +#if XCHAL_HAVE_LOOPS + loopnez a4, 2f +#else + beqz a4, 2f + add a7, a3, a4 // a7 = end address for source +#endif +1: l8ui a6, a3, 0 + addi a3, a3, 1 +#if XTENSA_ESP32_PSRAM_CACHE_FIX + nop + nop + nop +#endif + s8i a6, a5, 0 + addi a5, a5, 1 +#if XTENSA_ESP32_PSRAM_CACHE_FIX + memw +#endif +#if !XCHAL_HAVE_LOOPS + bltu a3, a7, 1b +#endif +2: leaf_return + + +/* Destination is unaligned. */ + + .align 4 +.Ldst1mod2: // dst is only byte aligned + + /* Do short copies byte-by-byte. */ + bltui a4, 7, .Lbytecopy + + /* Copy 1 byte. */ + l8ui a6, a3, 0 + addi a3, a3, 1 + addi a4, a4, -1 + s8i a6, a5, 0 +#if XTENSA_ESP32_PSRAM_CACHE_FIX + memw +#endif + addi a5, a5, 1 + + /* Return to main algorithm if dst is now aligned. */ + bbci.l a5, 1, .Ldstaligned + +.Ldst2mod4: // dst has 16-bit alignment + + /* Do short copies byte-by-byte. */ + bltui a4, 6, .Lbytecopy + + /* Copy 2 bytes. */ + l8ui a6, a3, 0 + l8ui a7, a3, 1 + addi a3, a3, 2 + addi a4, a4, -2 + s8i a6, a5, 0 + s8i a7, a5, 1 +#if XTENSA_ESP32_PSRAM_CACHE_FIX + memw +#endif + addi a5, a5, 2 + + /* dst is now aligned; return to main algorithm. */ + j .Ldstaligned + + + .align 4 + .global memcpy + .type memcpy, @function +memcpy: + leaf_entry sp, 16 + /* a2 = dst, a3 = src, a4 = len */ + + mov a5, a2 // copy dst so that a2 is return value + bbsi.l a2, 0, .Ldst1mod2 + bbsi.l a2, 1, .Ldst2mod4 +.Ldstaligned: + + /* Get number of loop iterations with 16B per iteration. */ + srli a7, a4, 4 + + /* Check if source is aligned. */ + slli a8, a3, 30 + bnez a8, .Lsrcunaligned + + /* Destination and source are word-aligned, use word copy. */ +#if XCHAL_HAVE_LOOPS + loopnez a7, 2f +#else + beqz a7, 2f + slli a8, a7, 4 + add a8, a8, a3 // a8 = end of last 16B source chunk +#endif + +#if XTENSA_ESP32_PSRAM_CACHE_FIX + +1: l32i a6, a3, 0 + l32i a7, a3, 4 + s32i a6, a5, 0 + s32i a7, a5, 4 + memw + l32i a6, a3, 8 + l32i a7, a3, 12 + s32i a6, a5, 8 + s32i a7, a5, 12 + memw + + addi a3, a3, 16 + addi a5, a5, 16 + +#else + +1: l32i a6, a3, 0 + l32i a7, a3, 4 + s32i a6, a5, 0 + l32i a6, a3, 8 + s32i a7, a5, 4 + l32i a7, a3, 12 + s32i a6, a5, 8 + addi a3, a3, 16 + s32i a7, a5, 12 + addi a5, a5, 16 + +#endif + + +#if !XCHAL_HAVE_LOOPS + bltu a3, a8, 1b +#endif + + /* Copy any leftover pieces smaller than 16B. */ +2: bbci.l a4, 3, 3f + + /* Copy 8 bytes. */ + l32i a6, a3, 0 + l32i a7, a3, 4 + addi a3, a3, 8 + s32i a6, a5, 0 + s32i a7, a5, 4 + addi a5, a5, 8 + +3: bbsi.l a4, 2, 4f + bbsi.l a4, 1, 5f + bbsi.l a4, 0, 6f +#if XTENSA_ESP32_PSRAM_CACHE_FIX + memw +#endif + leaf_return + + .align 4 + /* Copy 4 bytes. */ +4: l32i a6, a3, 0 + addi a3, a3, 4 + s32i a6, a5, 0 + addi a5, a5, 4 + bbsi.l a4, 1, 5f + bbsi.l a4, 0, 6f +#if XTENSA_ESP32_PSRAM_CACHE_FIX + memw +#endif + leaf_return + + /* Copy 2 bytes. */ +5: l16ui a6, a3, 0 + addi a3, a3, 2 + s16i a6, a5, 0 + addi a5, a5, 2 + bbsi.l a4, 0, 6f +#if XTENSA_ESP32_PSRAM_CACHE_FIX + memw +#endif + leaf_return + + /* Copy 1 byte. */ +6: l8ui a6, a3, 0 + s8i a6, a5, 0 + +.Ldone: +#if XTENSA_ESP32_PSRAM_CACHE_FIX + memw +#endif + leaf_return + + +/* Destination is aligned; source is unaligned. */ + + .align 4 +.Lsrcunaligned: + /* Avoid loading anything for zero-length copies. */ + beqz a4, .Ldone + + /* Copy 16 bytes per iteration for word-aligned dst and + unaligned src. */ + ssa8 a3 // set shift amount from byte offset +#if UNALIGNED_ADDRESSES_CHECKED + srli a11, a8, 30 // save unalignment offset for below + sub a3, a3, a11 // align a3 +#endif + l32i a6, a3, 0 // load first word +#if XCHAL_HAVE_LOOPS + loopnez a7, 2f +#else + beqz a7, 2f + slli a10, a7, 4 + add a10, a10, a3 // a10 = end of last 16B source chunk +#endif +1: l32i a7, a3, 4 + l32i a8, a3, 8 + src_b a6, a6, a7 + s32i a6, a5, 0 + l32i a9, a3, 12 + src_b a7, a7, a8 + s32i a7, a5, 4 + l32i a6, a3, 16 + src_b a8, a8, a9 + s32i a8, a5, 8 + addi a3, a3, 16 + src_b a9, a9, a6 + s32i a9, a5, 12 + addi a5, a5, 16 +#if !XCHAL_HAVE_LOOPS + bltu a3, a10, 1b +#endif + +2: bbci.l a4, 3, 3f + + /* Copy 8 bytes. */ + l32i a7, a3, 4 + l32i a8, a3, 8 + src_b a6, a6, a7 + s32i a6, a5, 0 + addi a3, a3, 8 + src_b a7, a7, a8 + s32i a7, a5, 4 + addi a5, a5, 8 + mov a6, a8 + +3: bbci.l a4, 2, 4f + + /* Copy 4 bytes. */ + l32i a7, a3, 4 + addi a3, a3, 4 + src_b a6, a6, a7 + s32i a6, a5, 0 + addi a5, a5, 4 + mov a6, a7 +4: +#if UNALIGNED_ADDRESSES_CHECKED + add a3, a3, a11 // readjust a3 with correct misalignment +#endif + bbsi.l a4, 1, 5f + bbsi.l a4, 0, 6f + leaf_return + + /* Copy 2 bytes. */ +5: l8ui a6, a3, 0 + l8ui a7, a3, 1 + addi a3, a3, 2 + s8i a6, a5, 0 + s8i a7, a5, 1 + addi a5, a5, 2 + bbsi.l a4, 0, 6f +#if XTENSA_ESP32_PSRAM_CACHE_FIX + memw +#endif + leaf_return + + /* Copy 1 byte. */ +6: l8ui a6, a3, 0 + s8i a6, a5, 0 +#if XTENSA_ESP32_PSRAM_CACHE_FIX + memw +#endif + leaf_return + + .end schedule + + .size memcpy, . - memcpy diff --git a/newlib/libc/machine/xtensa/memset.S b/newlib/libc/machine/xtensa/memset.S new file mode 100644 index 0000000..48b5829 --- /dev/null +++ b/newlib/libc/machine/xtensa/memset.S @@ -0,0 +1,193 @@ +/* ANSI C standard library function memset. + + Copyright (c) 2001-2008 Tensilica Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +#include "xtensa-asm.h" + +/* void *memset (void *dst, int c, size_t length) + + The algorithm is as follows: + + Create a word with c in all byte positions. + + If the destination is aligned, set 16B chunks with a loop, and then + finish up with 8B, 4B, 2B, and 1B stores conditional on the length. + + If the destination is unaligned, align it by conditionally + setting 1B and/or 2B and then go to aligned case. + + This code tries to use fall-through branches for the common + case of an aligned destination (except for the branches to + the alignment labels). */ + + +/* Byte-by-byte set. */ + + .text + .begin schedule + .align XCHAL_INST_FETCH_WIDTH + .literal_position +__memset_aux: + + /* Skip bytes to get proper alignment for three-byte loop */ +.skip XCHAL_INST_FETCH_WIDTH - 3 + +.Lbyteset: +#if XCHAL_HAVE_LOOPS + loopnez a4, 2f +#else + beqz a4, 2f + add a6, a5, a4 // a6 = ending address +#endif +1: s8i a3, a5, 0 +#if XTENSA_ESP32_PSRAM_CACHE_FIX + memw +#endif + addi a5, a5, 1 +#if !XCHAL_HAVE_LOOPS + bltu a5, a6, 1b +#endif +2: leaf_return + + +/* Destination is unaligned. */ + + .align 4 + +.Ldst1mod2: // dst is only byte aligned + + /* Do short sizes byte-by-byte. */ + bltui a4, 8, .Lbyteset + + /* Set 1 byte. */ + s8i a3, a5, 0 + addi a5, a5, 1 + addi a4, a4, -1 +#if XTENSA_ESP32_PSRAM_CACHE_FIX + memw +#endif + + /* Now retest if dst is aligned. */ + _bbci.l a5, 1, .Ldstaligned + +.Ldst2mod4: // dst has 16-bit alignment + + /* Do short sizes byte-by-byte. */ + bltui a4, 8, .Lbyteset + + /* Set 2 bytes. */ + s16i a3, a5, 0 + addi a5, a5, 2 + addi a4, a4, -2 +#if XTENSA_ESP32_PSRAM_CACHE_FIX + memw +#endif + + /* dst is now aligned; return to main algorithm */ + j .Ldstaligned + + + .align 4 + .global memset + .type memset, @function +memset: + leaf_entry sp, 16 + /* a2 = dst, a3 = c, a4 = length */ + + /* Duplicate character into all bytes of word. */ + extui a3, a3, 0, 8 + slli a7, a3, 8 + or a3, a3, a7 + slli a7, a3, 16 + or a3, a3, a7 + + mov a5, a2 // copy dst so that a2 is return value + + /* Check if dst is unaligned. */ + _bbsi.l a2, 0, .Ldst1mod2 + _bbsi.l a2, 1, .Ldst2mod4 +.Ldstaligned: + + /* Get number of loop iterations with 16B per iteration. */ + srli a7, a4, 4 + +#if XTENSA_ESP32_PSRAM_CACHE_FIX + //do not do this if we have less than one iteration to do + beqz a7, 2f + //this seems to work to prefetch the cache line + s32i a3, a5, 0 + nop +#endif + + /* Destination is word-aligned. */ +#if XCHAL_HAVE_LOOPS + loopnez a7, 2f +#else + beqz a7, 2f + slli a6, a7, 4 + add a6, a6, a5 // a6 = end of last 16B chunk +#endif + /* Set 16 bytes per iteration. */ +1: s32i a3, a5, 0 + s32i a3, a5, 4 + s32i a3, a5, 8 + s32i a3, a5, 12 + addi a5, a5, 16 +#if !XCHAL_HAVE_LOOPS + bltu a5, a6, 1b +#endif + + /* Set any leftover pieces smaller than 16B. */ +2: bbci.l a4, 3, 3f + + /* Set 8 bytes. */ + s32i a3, a5, 0 + s32i a3, a5, 4 + addi a5, a5, 8 + +3: bbci.l a4, 2, 4f + + /* Set 4 bytes. */ + s32i a3, a5, 0 + addi a5, a5, 4 + +4: bbci.l a4, 1, 5f + + /* Set 2 bytes. */ + s16i a3, a5, 0 + addi a5, a5, 2 +#if XTENSA_ESP32_PSRAM_CACHE_FIX + memw +#endif + +5: bbci.l a4, 0, 6f + + /* Set 1 byte. */ + s8i a3, a5, 0 +#if XTENSA_ESP32_PSRAM_CACHE_FIX + memw +#endif +6: leaf_return + + .end schedule + + .size memset, . - memset diff --git a/newlib/libc/machine/xtensa/setjmp.S b/newlib/libc/machine/xtensa/setjmp.S new file mode 100644 index 0000000..c32d443 --- /dev/null +++ b/newlib/libc/machine/xtensa/setjmp.S @@ -0,0 +1,252 @@ +/* setjmp/longjmp functions for Xtensa. + + Copyright (c) 2001-2006 by Tensilica Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +/* Windowed ABI: + + This implementation relies heavily on the Xtensa register window + mechanism. Setjmp flushes all the windows except its own to the + stack and then copies registers from the save areas on the stack + into the jmp_buf structure, along with the return address of the call + to setjmp. Longjmp invalidates all the windows except its own, and + then sets things up so that it will return to the right place, + using a window underflow to automatically restore the registers. + + Note that it would probably be sufficient to only copy the + registers from setjmp's caller into jmp_buf. However, we also copy + the save area located at the stack pointer of setjmp's caller. + This save area will typically remain intact until the longjmp call. + The one exception is when there is an intervening alloca in + setjmp's caller. This is certainly an unusual situation and is + likely to cause problems in any case (the storage allocated on the + stack cannot be safely accessed following the longjmp). As bad as + it is, on most systems this situation would not necessarily lead to + a catastrophic failure. If we did not preserve the extra save area + on Xtensa, however, it would. When setjmp's caller returns after a + longjmp, there will be a window underflow; an invalid return + address or stack pointer in the save area will almost certainly + lead to a crash. Keeping a copy of the extra save area in the + jmp_buf avoids this with only a small additional cost. If setjmp + and longjmp are ever time-critical, this could be removed. + + + Call0 ABI: + + Much like other ABIs, this version just saves the necessary registers + to the stack and restores them later. Much less needs to be done. */ + +#include "xtensa-asm.h" + +#define SYS_nop 0 + + +#if XCHAL_HAVE_WINDOWED && !__XTENSA_CALL0_ABI__ + +/* int setjmp (jmp_buf env) */ + + .text + .align 4 + .literal_position + .global setjmp + .type setjmp, @function +setjmp: + entry sp, 16 + + /* Flush registers. */ + mov a4, a2 // save a2 (jmp_buf) + movi a2, SYS_nop + syscall + mov a2, a4 // restore a2 + + /* Copy the register save area at (sp - 16). */ + addi a5, a1, -16 + l32i a3, a5, 0 + l32i a4, a5, 4 + s32i a3, a2, 0 + s32i a4, a2, 4 + l32i a3, a5, 8 + l32i a4, a5, 12 + s32i a3, a2, 8 + s32i a4, a2, 12 + + /* Copy 0-8 words from the register overflow area. */ + extui a3, a0, 30, 2 + blti a3, 2, .Lendsj + l32i a7, a1, 4 + slli a4, a3, 4 + sub a5, a7, a4 + addi a6, a2, 16 + addi a7, a7, -16 // a7 = end of register overflow area +.Lsjloop: + l32i a3, a5, 0 + l32i a4, a5, 4 + s32i a3, a6, 0 + s32i a4, a6, 4 + l32i a3, a5, 8 + l32i a4, a5, 12 + s32i a3, a6, 8 + s32i a4, a6, 12 + addi a5, a5, 16 + addi a6, a6, 16 + blt a5, a7, .Lsjloop +.Lendsj: + + /* Copy the register save area at sp. */ + l32i a3, a1, 0 + l32i a4, a1, 4 + s32i a3, a2, 48 + s32i a4, a2, 52 + l32i a3, a1, 8 + l32i a4, a1, 12 + s32i a3, a2, 56 + s32i a4, a2, 60 + + /* Save the return address, including the window size bits. */ + s32i a0, a2, 64 + + movi a2, 0 + retw + .size setjmp, . - setjmp + + +/* void longjmp (jmp_buf env, int val) */ + + .align 4 + .literal_position + .global longjmp + .type longjmp, @function +longjmp: + entry sp, 16 + /* a2 == &env, a3 == val */ + + /* Invalidate all but the current window; + set WindowStart to (1 << WindowBase). */ + rsr a5, WINDOWBASE + movi a4, 1 + ssl a5 + sll a4, a4 + wsr a4, WINDOWSTART + rsync + + /* Return to the return address of the setjmp, using the + window size bits from the setjmp call so that the caller + will be able to find the return value that we put in a2. */ + + l32i a0, a2, 64 + + /* Copy the first 4 saved registers from jmp_buf into the save area + at the current sp so that the values will be restored to registers + when longjmp returns. */ + + addi a7, a1, -16 + l32i a4, a2, 0 + l32i a5, a2, 4 + s32i a4, a7, 0 + s32i a5, a7, 4 + l32i a4, a2, 8 + l32i a5, a2, 12 + s32i a4, a7, 8 + s32i a5, a7, 12 + + /* Copy the remaining 0-8 saved registers. */ + extui a7, a0, 30, 2 + blti a7, 2, .Lendlj + l32i a8, a2, 52 + slli a4, a7, 4 + sub a6, a8, a4 + addi a5, a2, 16 + addi a8, a8, -16 // a8 = end of register overflow area +.Lljloop: + l32i a7, a5, 0 + l32i a4, a5, 4 + s32i a7, a6, 0 + s32i a4, a6, 4 + l32i a7, a5, 8 + l32i a4, a5, 12 + s32i a7, a6, 8 + s32i a4, a6, 12 + addi a5, a5, 16 + addi a6, a6, 16 + blt a6, a8, .Lljloop +.Lendlj: + + /* The 4 words saved from the register save area at the target's + sp are copied back to the target procedure's save area. The + only point of this is to prevent a catastrophic failure in + case the contents were moved by an alloca after calling + setjmp. This is a bit paranoid but it doesn't cost much. */ + + l32i a7, a2, 4 // load the target stack pointer + addi a7, a7, -16 // find the destination save area + l32i a4, a2, 48 + l32i a5, a2, 52 + s32i a4, a7, 0 + s32i a5, a7, 4 + l32i a4, a2, 56 + l32i a5, a2, 60 + s32i a4, a7, 8 + s32i a5, a7, 12 + + /* Return val ? val : 1. */ + movi a2, 1 + movnez a2, a3, a3 + + retw + .size longjmp, . - longjmp + +#else /* CALL0 ABI */ + + .text + .align 4 + .literal_position + .global setjmp + .type setjmp, @function +setjmp: + s32i a0, a2, 0 + s32i a1, a2, 4 + s32i a12, a2, 8 + s32i a13, a2, 12 + s32i a14, a2, 16 + s32i a15, a2, 20 + movi a2, 0 + ret + .size setjmp, . - setjmp + + .align 4 + .literal_position + .global longjmp + .type longjmp, @function +longjmp: + l32i a0, a2, 0 + l32i a12, a2, 8 + l32i a13, a2, 12 + l32i a14, a2, 16 + l32i a15, a2, 20 + l32i a1, a2, 4 + /* Return val ? val : 1. */ + movi a2, 1 + movnez a2, a3, a3 + + ret + .size longjmp, .-longjmp + +#endif /* CALL0 ABI */ diff --git a/newlib/libc/machine/xtensa/strcmp.S b/newlib/libc/machine/xtensa/strcmp.S new file mode 100644 index 0000000..49cb805 --- /dev/null +++ b/newlib/libc/machine/xtensa/strcmp.S @@ -0,0 +1,353 @@ +/* ANSI C standard library function strcmp. + + Copyright (c) 2001-20012 Tensilica Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +#include "xtensa-asm.h" + +#define MASK4 0x40404040 + + +#if XCHAL_HAVE_L32R + .literal .Lmask0, MASK0 + .literal .Lmask1, MASK1 + .literal .Lmask2, MASK2 + .literal .Lmask3, MASK3 + .literal .Lmask4, MASK4 +#endif /* XCHAL_HAVE_L32R */ + + .text + .align 4 + .literal_position + .global strcmp + .type strcmp, @function +strcmp: + + leaf_entry sp, 16 + /* a2 = s1, a3 = s2 */ + + l8ui a8, a2, 0 // byte 0 from s1 + l8ui a9, a3, 0 // byte 0 from s2 + movi a10, 3 // mask + bne a8, a9, .Lretdiff + + or a11, a2, a3 + bnone a11, a10, .Laligned + + xor a11, a2, a3 // compare low two bits of s1 and s2 + bany a11, a10, .Lunaligned // if they have different alignment + + /* s1/s2 are not word-aligned. */ + addi a2, a2, 1 // advance s1 + beqz a8, .Leq // bytes equal, if zero, strings are equal + addi a3, a3, 1 // advance s2 + bnone a2, a10, .Laligned // if s1/s2 now aligned + l8ui a8, a2, 0 // byte 1 from s1 + l8ui a9, a3, 0 // byte 1 from s2 + addi a2, a2, 1 // advance s1 + bne a8, a9, .Lretdiff // if different, return difference + beqz a8, .Leq // bytes equal, if zero, strings are equal + addi a3, a3, 1 // advance s2 + bnone a2, a10, .Laligned // if s1/s2 now aligned + l8ui a8, a2, 0 // byte 2 from s1 + l8ui a9, a3, 0 // byte 2 from s2 + addi a2, a2, 1 // advance s1 + bne a8, a9, .Lretdiff // if different, return difference + beqz a8, .Leq // bytes equal, if zero, strings are equal + addi a3, a3, 1 // advance s2 + j .Laligned + +/* s1 and s2 have different alignment. + + If the zero-overhead loop option is available, use an (almost) + infinite zero-overhead loop with conditional exits so we only pay + for taken branches when exiting the loop. + + Note: It is important for this unaligned case to come before the + code for aligned strings, because otherwise some of the branches + above cannot reach and have to be transformed to branches around + jumps. The unaligned code is smaller and the branches can reach + over it. */ + + .align 4 +#if XCHAL_HAVE_LOOPS +#if XCHAL_HAVE_DENSITY + /* (2 mod 4) alignment for loop instruction */ +#else + /* (1 mod 4) alignment for loop instruction */ + .byte 0 + .byte 0 +#endif +#endif +.Lunaligned: +#if XCHAL_HAVE_LOOPS +#if XCHAL_HAVE_DENSITY + _movi.n a8, 0 // set up for the maximum loop count +#else + _movi a8, 0 // set up for the maximum loop count +#endif + loop a8, .Lretdiff // loop forever (almost anyway) +#endif +.Lnextbyte: + l8ui a8, a2, 0 + l8ui a9, a3, 0 + addi a2, a2, 1 + bne a8, a9, .Lretdiff + addi a3, a3, 1 +#if XCHAL_HAVE_LOOPS + beqz a8, .Lretdiff +#else + bnez a8, .Lnextbyte +#endif +.Lretdiff: + sub a2, a8, a9 + leaf_return + +/* s1 is word-aligned; s2 is word-aligned. + + If the zero-overhead loop option is available, use an (almost) + infinite zero-overhead loop with conditional exits so we only pay + for taken branches when exiting the loop. */ + +/* New algorithm, relying on the fact that all normal ASCII is between + 32 and 127. + + Rather than check all bytes for zero: + Take one word (4 bytes). Call it w1. + Shift w1 left by one into w1'. + Or w1 and w1'. For all normal ASCII bit 6 will be 1; for zero it won't. + Check that all 4 bit 6's (one for each byte) are one: + If they are, we are definitely not done. + If they are not, we are probably done, but need to check for zero. */ + + .align 4 +#if XCHAL_HAVE_LOOPS +#if !XCHAL_HAVE_L32R + /* (2 mod 4) alignment for loop instruction */ + .byte 0 + .byte 0 +#endif +.Laligned: +#if XCHAL_HAVE_L32R + l32r a4, .Lmask0 // mask for byte 0 + l32r a7, .Lmask4 +#else + const16 a4, MASK0@h + const16 a4, MASK0@l + const16 a7, MASK4@h + const16 a7, MASK4@l +#endif + /* Loop forever */ +1: + loop a0, .Laligned_done + + /* First unrolled loop body. */ + l32i a8, a2, 0 // get word from s1 + l32i a9, a3, 0 // get word from s2 + slli a5, a8, 1 + bne a8, a9, .Lwne2 + or a9, a8, a5 + bnall a9, a7, .Lprobeq + + /* Second unrolled loop body. */ + l32i a8, a2, 4 // get word from s1+4 + l32i a9, a3, 4 // get word from s2+4 + slli a5, a8, 1 + bne a8, a9, .Lwne2 + or a9, a8, a5 + bnall a9, a7, .Lprobeq2 + + addi a2, a2, 8 // advance s1 pointer + addi a3, a3, 8 // advance s2 pointer +.Laligned_done: + j 1b + +.Lprobeq2: + /* Adjust pointers to account for the loop unrolling. */ + addi a2, a2, 4 + addi a3, a3, 4 + +#else /* !XCHAL_HAVE_LOOPS */ + +.Laligned: + movi a4, MASK0 // mask for byte 0 + movi a7, MASK4 + j .Lfirstword +.Lnextword: + addi a2, a2, 4 // advance s1 pointer + addi a3, a3, 4 // advance s2 pointer +.Lfirstword: + l32i a8, a2, 0 // get word from s1 + l32i a9, a3, 0 // get word from s2 + slli a5, a8, 1 + bne a8, a9, .Lwne2 + or a9, a8, a5 + ball a9, a7, .Lnextword +#endif /* !XCHAL_HAVE_LOOPS */ + + /* align (0 mod 4) */ +.Lprobeq: + /* Words are probably equal, but check for sure. + If not, loop over the rest of string using normal algorithm. */ + + bnone a8, a4, .Leq // if byte 0 is zero +#if XCHAL_HAVE_L32R + l32r a5, .Lmask1 // mask for byte 1 + l32r a6, .Lmask2 // mask for byte 2 + bnone a8, a5, .Leq // if byte 1 is zero + l32r a7, .Lmask3 // mask for byte 3 + bnone a8, a6, .Leq // if byte 2 is zero + bnone a8, a7, .Leq // if byte 3 is zero + /* align (1 mod 4) */ +#else + const16 a5, MASK1@h // mask for byte 1 + const16 a5, MASK1@l + bnone a8, a5, .Leq // if byte 1 is zero + const16 a6, MASK2@h // mask for byte 2 + const16 a6, MASK2@l + bnone a8, a6, .Leq // if byte 2 is zero + const16 a7, MASK3@h // mask for byte 3 + const16 a7, MASK3@l + bnone a8, a7, .Leq // if byte 3 is zero + /* align (2 mod 4) */ +#endif /* XCHAL_HAVE_L32R */ +#if XCHAL_HAVE_DENSITY + addi.n a2, a2, 4 // advance s1 pointer + addi.n a3, a3, 4 // advance s2 pointer + /* align (1 mod 4) or (2 mod 4) */ +#else + addi a2, a2, 4 // advance s1 pointer + addi a3, a3, 4 // advance s2 pointer + or a1, a1, a1 // nop +#if !XCHAL_HAVE_L32R + or a1, a1, a1 // nop +#endif + /* align (2 mod 4) */ +#endif /* XCHAL_HAVE_DENSITY */ +#if XCHAL_HAVE_LOOPS +1: + loop a0, .Leq // loop forever (a4 is bigger than max iters) + l32i a8, a2, 0 // get word from s1 + l32i a9, a3, 0 // get word from s2 + addi a2, a2, 4 // advance s1 pointer + bne a8, a9, .Lwne + bnone a8, a4, .Leq // if byte 0 is zero + bnone a8, a5, .Leq // if byte 1 is zero + bnone a8, a6, .Leq // if byte 2 is zero + bnone a8, a7, .Leq // if byte 3 is zero + addi a3, a3, 4 // advance s2 pointer + j 1b +#else /* !XCHAL_HAVE_LOOPS */ + + j .Lfirstword2 +.Lnextword2: + addi a3, a3, 4 // advance s2 pointer +.Lfirstword2: + l32i a8, a2, 0 // get word from s1 + l32i a9, a3, 0 // get word from s2 + addi a2, a2, 4 // advance s1 pointer + bne a8, a9, .Lwne + bnone a8, a4, .Leq // if byte 0 is zero + bnone a8, a5, .Leq // if byte 1 is zero + bnone a8, a6, .Leq // if byte 2 is zero + bany a8, a7, .Lnextword2 // if byte 3 is zero +#endif /* !XCHAL_HAVE_LOOPS */ + + /* Words are equal; some byte is zero. */ +.Leq: movi a2, 0 // return equal + leaf_return + +.Lwne2: /* Words are not equal. On big-endian processors, if none of the + bytes are zero, the return value can be determined by a simple + comparison. */ +#ifdef __XTENSA_EB__ + or a10, a8, a5 + bnall a10, a7, .Lsomezero + bgeu a8, a9, .Lposreturn + movi a2, -1 + leaf_return +.Lposreturn: + movi a2, 1 + leaf_return +.Lsomezero: // There is probably some zero byte. +#endif /* __XTENSA_EB__ */ +.Lwne: /* Words are not equal. */ + xor a2, a8, a9 // get word with nonzero in byte that differs + bany a2, a4, .Ldiff0 // if byte 0 differs + movi a5, MASK1 // mask for byte 1 + bnone a8, a4, .Leq // if byte 0 is zero + bany a2, a5, .Ldiff1 // if byte 1 differs + movi a6, MASK2 // mask for byte 2 + bnone a8, a5, .Leq // if byte 1 is zero + bany a2, a6, .Ldiff2 // if byte 2 differs + bnone a8, a6, .Leq // if byte 2 is zero +#ifdef __XTENSA_EB__ +.Ldiff3: +.Ldiff2: +.Ldiff1: + /* Byte 0 is equal (at least) and there is a difference before a zero + byte. Just subtract words to get the return value. + The high order equal bytes cancel, leaving room for the sign. */ + sub a2, a8, a9 + leaf_return + +.Ldiff0: + /* Need to make room for the sign, so can't subtract whole words. */ + extui a10, a8, 24, 8 + extui a11, a9, 24, 8 + sub a2, a10, a11 + leaf_return + +#else /* !__XTENSA_EB__ */ + /* Little-endian is a little more difficult because can't subtract + whole words. */ +.Ldiff3: + /* Bytes 0-2 are equal; byte 3 is different. + For little-endian need to have a sign bit for the difference. */ + extui a10, a8, 24, 8 + extui a11, a9, 24, 8 + sub a2, a10, a11 + leaf_return + +.Ldiff0: + /* Byte 0 is different. */ + extui a10, a8, 0, 8 + extui a11, a9, 0, 8 + sub a2, a10, a11 + leaf_return + +.Ldiff1: + /* Byte 0 is equal; byte 1 is different. */ + extui a10, a8, 8, 8 + extui a11, a9, 8, 8 + sub a2, a10, a11 + leaf_return + +.Ldiff2: + /* Bytes 0-1 are equal; byte 2 is different. */ + extui a10, a8, 16, 8 + extui a11, a9, 16, 8 + sub a2, a10, a11 + leaf_return + +#endif /* !__XTENSA_EB */ + + .size strcmp, . - strcmp diff --git a/newlib/libc/machine/xtensa/strcpy.S b/newlib/libc/machine/xtensa/strcpy.S new file mode 100644 index 0000000..9ab624b --- /dev/null +++ b/newlib/libc/machine/xtensa/strcpy.S @@ -0,0 +1,274 @@ +/* ANSI C standard library function strcpy. + + Copyright (c) 2001-2008 Tensilica Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +#include "xtensa-asm.h" + + .text + .begin schedule + .align 4 + .literal_position + .global strcpy + .type strcpy, @function +strcpy: + leaf_entry sp, 16 + /* a2 = dst, a3 = src */ + + mov a10, a2 // leave dst in return value register + movi a4, MASK0 + movi a5, MASK1 + movi a6, MASK2 + movi a7, MASK3 + bbsi.l a3, 0, .Lsrc1mod2 + bbsi.l a3, 1, .Lsrc2mod4 +.Lsrcaligned: + + /* Check if the destination is aligned. */ + movi a8, 3 + bnone a10, a8, .Laligned + + j .Ldstunaligned + +.Lsrc1mod2: // src address is odd + l8ui a8, a3, 0 // get byte 0 + addi a3, a3, 1 // advance src pointer + s8i a8, a10, 0 // store byte 0 +#if XTENSA_ESP32_PSRAM_CACHE_FIX + memw +#endif + beqz a8, 1f // if byte 0 is zero + addi a10, a10, 1 // advance dst pointer + bbci.l a3, 1, .Lsrcaligned // if src is now word-aligned + +.Lsrc2mod4: // src address is 2 mod 4 + l8ui a8, a3, 0 // get byte 0 + /* 1-cycle interlock */ + s8i a8, a10, 0 // store byte 0 +#if XTENSA_ESP32_PSRAM_CACHE_FIX + memw +#endif + beqz a8, 1f // if byte 0 is zero + l8ui a8, a3, 1 // get byte 0 + addi a3, a3, 2 // advance src pointer + s8i a8, a10, 1 // store byte 0 + addi a10, a10, 2 // advance dst pointer +#if XTENSA_ESP32_PSRAM_CACHE_FIX + memw +#endif + bnez a8, .Lsrcaligned +1: leaf_return + + +/* dst is word-aligned; src is word-aligned. */ + + .align 4 +#if XCHAL_HAVE_LOOPS +#if XCHAL_HAVE_DENSITY + /* (2 mod 4) alignment for loop instruction */ +#else + /* (1 mod 4) alignment for loop instruction */ + .byte 0 + .byte 0 +#endif +.Laligned: +#if XCHAL_HAVE_DENSITY + _movi.n a8, 0 // set up for the maximum loop count +#else + _movi a8, 0 // set up for the maximum loop count +#endif + loop a8, .Lz3 // loop forever (almost anyway) + l32i a8, a3, 0 // get word from src + addi a3, a3, 4 // advance src pointer + bnone a8, a4, .Lz0 // if byte 0 is zero + bnone a8, a5, .Lz1 // if byte 1 is zero + bnone a8, a6, .Lz2 // if byte 2 is zero + s32i a8, a10, 0 // store word to dst +#if XTENSA_ESP32_PSRAM_CACHE_FIX + l32i a8, a10, 0 + s32i a8, a10, 0 +#endif + bnone a8, a7, .Lz3 // if byte 3 is zero + addi a10, a10, 4 // advance dst pointer + +#else /* !XCHAL_HAVE_LOOPS */ + +1: addi a10, a10, 4 // advance dst pointer +.Laligned: + l32i a8, a3, 0 // get word from src + addi a3, a3, 4 // advance src pointer + bnone a8, a4, .Lz0 // if byte 0 is zero + bnone a8, a5, .Lz1 // if byte 1 is zero + bnone a8, a6, .Lz2 // if byte 2 is zero + s32i a8, a10, 0 // store word to dst +#if XTENSA_ESP32_PSRAM_CACHE_FIX + l32i a8, a10, 0 + s32i a8, a10, 0 +#endif + + bany a8, a7, 1b // if byte 3 is zero +#endif /* !XCHAL_HAVE_LOOPS */ + +.Lz3: /* Byte 3 is zero. */ + leaf_return + +.Lz0: /* Byte 0 is zero. */ +#ifdef __XTENSA_EB__ + movi a8, 0 +#endif + s8i a8, a10, 0 +#if XTENSA_ESP32_PSRAM_CACHE_FIX + memw +#endif + leaf_return + +.Lz1: /* Byte 1 is zero. */ +#ifdef __XTENSA_EB__ + extui a8, a8, 16, 16 +#endif + s16i a8, a10, 0 +#if XTENSA_ESP32_PSRAM_CACHE_FIX + memw +#endif + leaf_return + +.Lz2: /* Byte 2 is zero. */ +#ifdef __XTENSA_EB__ + extui a8, a8, 16, 16 +#endif + s16i a8, a10, 0 + movi a8, 0 + s8i a8, a10, 2 +#if XTENSA_ESP32_PSRAM_CACHE_FIX + memw +#endif + leaf_return + +#if 1 +/* For now just use byte copy loop for the unaligned destination case. */ + + .align 4 +#if XCHAL_HAVE_LOOPS +#if XCHAL_HAVE_DENSITY + /* (2 mod 4) alignment for loop instruction */ +#else + /* (1 mod 4) alignment for loop instruction */ + .byte 0 + .byte 0 +#endif +#endif +.Ldstunaligned: + +#if XCHAL_HAVE_LOOPS +#if XCHAL_HAVE_DENSITY + _movi.n a8, 0 // set up for the maximum loop count +#else + _movi a8, 0 // set up for the maximum loop count +#endif + loop a8, 2f // loop forever (almost anyway) +#endif +1: l8ui a8, a3, 0 + addi a3, a3, 1 + s8i a8, a10, 0 + addi a10, a10, 1 +#if XTENSA_ESP32_PSRAM_CACHE_FIX + memw +#endif +#if XCHAL_HAVE_LOOPS + beqz a8, 2f +#else + bnez a8, 1b +#endif +2: leaf_return + +#else /* 0 */ + +/* This code is not functional yet. */ + +.Ldstunaligned: + l32i a9, a2, 0 // load word from dst +#ifdef __XTENSA_EB__ + ssa8b a9 // rotate by dst alignment so that + src a9, a9, a9 // shift in loop will put back in place + ssa8l a9 // shift left by byte*8 +#else + ssa8l a9 // rotate by dst alignment so that + src a9, a9, a9 // shift in loop will put back in place + ssa8b a9 // shift left by 32-byte*8 +#endif + +/* dst is word-aligned; src is unaligned. */ + +.Ldstunalignedloop: + l32i a8, a3, 0 // get word from src + /* 1-cycle interlock */ + bnone a8, a4, .Lu0 // if byte 0 is zero + bnone a8, a5, .Lu1 // if byte 1 is zero + bnone a8, a6, .Lu2 // if byte 2 is zero + src a9, a8, a9 // combine last word and this word + s32i a9, a10, 0 // store word to dst + bnone a8, a7, .Lu3 // if byte 3 is nonzero, iterate + l32i a9, a3, 4 // get word from src + addi a3, a3, 8 // advance src pointer + bnone a9, a4, .Lu4 // if byte 0 is zero + bnone a9, a5, .Lu5 // if byte 1 is zero + bnone a9, a6, .Lu6 // if byte 2 is zero + src a8, a9, a8 // combine last word and this word + s32i a8, a10, 4 // store word to dst + addi a10, a10, 8 // advance dst pointer + bany a8, a7, .Ldstunalignedloop // if byte 3 is nonzero, iterate + + /* Byte 7 is zero. */ +.Lu7: leaf_return + +.Lu0: /* Byte 0 is zero. */ +#ifdef __XTENSA_EB__ + movi a8, 0 +#endif + s8i a8, a10, 0 +#if XTENSA_ESP32_PSRAM_CACHE_FIX + memw +#endif + leaf_return + +.Lu1: /* Byte 1 is zero. */ +#ifdef __XTENSA_EB__ + extui a8, a8, 16, 16 +#endif + s16i a8, a10, 0 +#if XTENSA_ESP32_PSRAM_CACHE_FIX + memw +#endif + leaf_return + +.Lu2: /* Byte 2 is zero. */ + s16i a8, a10, 0 + movi a8, 0 + s8i a8, a10, 2 +#if XTENSA_ESP32_PSRAM_CACHE_FIX + memw +#endif + leaf_return + +#endif /* 0 */ + .end schedule + + .size strcpy, . - strcpy diff --git a/newlib/libc/machine/xtensa/strlen.S b/newlib/libc/machine/xtensa/strlen.S new file mode 100644 index 0000000..6560a31 --- /dev/null +++ b/newlib/libc/machine/xtensa/strlen.S @@ -0,0 +1,115 @@ +/* ANSI C standard library function strlen. + + Copyright (c) 2001-2008 Tensilica Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +#include "xtensa-asm.h" + + .text + .begin schedule + .align 4 + .literal_position + .global strlen + .type strlen, @function +strlen: + leaf_entry sp, 16 + /* a2 = s */ + + addi a3, a2, -4 // because we overincrement at the end + movi a4, MASK0 + movi a5, MASK1 + movi a6, MASK2 + movi a7, MASK3 + bbsi.l a2, 0, .L1mod2 + bbsi.l a2, 1, .L2mod4 + j .Laligned + +.L1mod2: // address is odd + l8ui a8, a3, 4 // get byte 0 + addi a3, a3, 1 // advance string pointer + beqz a8, .Lz3 // if byte 0 is zero + bbci.l a3, 1, .Laligned // if string pointer is now word-aligned + +.L2mod4: // address is 2 mod 4 + addi a3, a3, 2 // advance ptr for aligned access + l32i a8, a3, 0 // get word with first two bytes of string + bnone a8, a6, .Lz2 // if byte 2 (of word, not string) is zero + bany a8, a7, .Laligned // if byte 3 (of word, not string) is nonzero + + /* Byte 3 is zero. */ + addi a3, a3, 3 // point to zero byte + sub a2, a3, a2 // subtract to get length + leaf_return + + +/* String is word-aligned. */ + + .align 4 +#if XCHAL_HAVE_LOOPS +#if XCHAL_HAVE_DENSITY + /* (2 mod 4) alignment for loop instruction */ +#else + /* (1 mod 4) alignment for loop instruction */ + .byte 0 + .byte 0 +#endif +#endif +.Laligned: +#if XCHAL_HAVE_LOOPS +#if XCHAL_HAVE_DENSITY + _movi.n a8, 0 // set up for the maximum loop count +#else + _movi a8, 0 // set up for the maximum loop count +#endif + loop a8, .Lz3 // loop forever (almost anyway) +#endif +1: l32i a8, a3, 4 // get next word of string + addi a3, a3, 4 // advance string pointer + bnone a8, a4, .Lz0 // if byte 0 is zero + bnone a8, a5, .Lz1 // if byte 1 is zero + bnone a8, a6, .Lz2 // if byte 2 is zero +#if XCHAL_HAVE_LOOPS + bnone a8, a7, .Lz3 // if byte 3 is zero +#else + bany a8, a7, 1b // repeat if byte 3 is non-zero +#endif + +.Lz3: /* Byte 3 is zero. */ + addi a3, a3, 3 // point to zero byte + /* Fall through.... */ + +.Lz0: /* Byte 0 is zero. */ + sub a2, a3, a2 // subtract to get length + leaf_return + +.Lz1: /* Byte 1 is zero. */ + addi a3, a3, 1 // point to zero byte + sub a2, a3, a2 // subtract to get length + leaf_return + +.Lz2: /* Byte 2 is zero. */ + addi a3, a3, 2 // point to zero byte + sub a2, a3, a2 // subtract to get length + leaf_return + + .end schedule + + .size strlen, . - strlen diff --git a/newlib/libc/machine/xtensa/strncpy.S b/newlib/libc/machine/xtensa/strncpy.S new file mode 100644 index 0000000..faa7c7b --- /dev/null +++ b/newlib/libc/machine/xtensa/strncpy.S @@ -0,0 +1,274 @@ +/* ANSI C standard library function strncpy. + + Copyright (c) 2001-2008 Tensilica Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +#include "xtensa-asm.h" + + .text +.begin schedule + .align 4 + .literal_position +__strncpy_aux: + +.Lsrc1mod2: // src address is odd + l8ui a8, a3, 0 // get byte 0 + addi a3, a3, 1 // advance src pointer + s8i a8, a10, 0 // store byte 0 + addi a4, a4, -1 // decrement n + beqz a4, .Lret // if n is zero + addi a10, a10, 1 // advance dst pointer + beqz a8, .Lfill // if byte 0 is zero + bbci.l a3, 1, .Lsrcaligned // if src is now word-aligned + +.Lsrc2mod4: // src address is 2 mod 4 + l8ui a8, a3, 0 // get byte 0 + addi a4, a4, -1 // decrement n + s8i a8, a10, 0 // store byte 0 + beqz a4, .Lret // if n is zero + addi a10, a10, 1 // advance dst pointer + beqz a8, .Lfill // if byte 0 is zero + l8ui a8, a3, 1 // get byte 0 + addi a3, a3, 2 // advance src pointer + s8i a8, a10, 0 // store byte 0 + addi a4, a4, -1 // decrement n + beqz a4, .Lret // if n is zero + addi a10, a10, 1 // advance dst pointer + bnez a8, .Lsrcaligned + j .Lfill + +.Lret: +#if XTENSA_ESP32_PSRAM_CACHE_FIX + memw +#endif + leaf_return + + + .align 4 + .global strncpy + .type strncpy, @function +strncpy: + leaf_entry sp, 16 + /* a2 = dst, a3 = src */ + + mov a10, a2 // leave dst in return value register + beqz a4, .Lret // if n is zero + + movi a11, MASK0 + movi a5, MASK1 + movi a6, MASK2 + movi a7, MASK3 + bbsi.l a3, 0, .Lsrc1mod2 + bbsi.l a3, 1, .Lsrc2mod4 +.Lsrcaligned: + + /* Check if the destination is aligned. */ + movi a8, 3 + bnone a10, a8, .Laligned + + j .Ldstunaligned + + +/* Fill the dst with zeros -- n is at least 1. */ + +.Lfill: + movi a9, 0 + bbsi.l a10, 0, .Lfill1mod2 + bbsi.l a10, 1, .Lfill2mod4 +.Lfillaligned: + blti a4, 4, .Lfillcleanup + + /* Loop filling complete words with zero. */ +#if XCHAL_HAVE_LOOPS + + srai a8, a4, 2 + loop a8, 1f + s32i a9, a10, 0 + addi a10, a10, 4 + +1: slli a8, a8, 2 + sub a4, a4, a8 + +#else /* !XCHAL_HAVE_LOOPS */ + +1: s32i a9, a10, 0 + addi a10, a10, 4 + addi a4, a4, -4 + bgei a4, 4, 1b + +#endif /* !XCHAL_HAVE_LOOPS */ + + beqz a4, 2f + +.Lfillcleanup: + /* Fill leftover (1 to 3) bytes with zero. */ + s8i a9, a10, 0 // store byte 0 + addi a4, a4, -1 // decrement n + addi a10, a10, 1 + bnez a4, .Lfillcleanup + +2: +#if XTENSA_ESP32_PSRAM_CACHE_FIX + memw +#endif + leaf_return + +.Lfill1mod2: // dst address is odd + s8i a9, a10, 0 // store byte 0 + addi a4, a4, -1 // decrement n + beqz a4, 2b // if n is zero + addi a10, a10, 1 // advance dst pointer + bbci.l a10, 1, .Lfillaligned // if dst is now word-aligned + +.Lfill2mod4: // dst address is 2 mod 4 + s8i a9, a10, 0 // store byte 0 + addi a4, a4, -1 // decrement n + beqz a4, 2b // if n is zero + s8i a9, a10, 1 // store byte 1 + addi a4, a4, -1 // decrement n + beqz a4, 2b // if n is zero + addi a10, a10, 2 // advance dst pointer + j .Lfillaligned + + +/* dst is word-aligned; src is word-aligned; n is at least 1. */ + + .align 4 +#if XCHAL_HAVE_LOOPS +#if XCHAL_HAVE_DENSITY + /* (2 mod 4) alignment for loop instruction */ +#else + /* (1 mod 4) alignment for loop instruction */ + .byte 0 + .byte 0 +#endif +#endif +.Laligned: +#if XCHAL_HAVE_LOOPS +#if XCHAL_HAVE_DENSITY + _movi.n a8, 0 // set up for the maximum loop count +#else + _movi a8, 0 // set up for the maximum loop count +#endif + loop a8, 1f // loop forever (almost anyway) + blti a4, 5, .Ldstunaligned // n is near limit; do one at a time + l32i a8, a3, 0 // get word from src + addi a3, a3, 4 // advance src pointer + bnone a8, a11, .Lz0 // if byte 0 is zero + bnone a8, a5, .Lz1 // if byte 1 is zero + bnone a8, a6, .Lz2 // if byte 2 is zero + s32i a8, a10, 0 // store word to dst + addi a4, a4, -4 // decrement n + addi a10, a10, 4 // advance dst pointer + bnone a8, a7, .Lfill // if byte 3 is zero +1: + +#else /* !XCHAL_HAVE_LOOPS */ + +1: blti a4, 5, .Ldstunaligned // n is near limit; do one at a time + l32i a8, a3, 0 // get word from src + addi a3, a3, 4 // advance src pointer + bnone a8, a11, .Lz0 // if byte 0 is zero + bnone a8, a5, .Lz1 // if byte 1 is zero + bnone a8, a6, .Lz2 // if byte 2 is zero + s32i a8, a10, 0 // store word to dst + addi a4, a4, -4 // decrement n + addi a10, a10, 4 // advance dst pointer + bany a8, a7, 1b // no zeroes +#endif /* !XCHAL_HAVE_LOOPS */ + + j .Lfill + +.Lz0: /* Byte 0 is zero. */ +#ifdef __XTENSA_EB__ + movi a8, 0 +#endif + s8i a8, a10, 0 + addi a4, a4, -1 // decrement n + addi a10, a10, 1 // advance dst pointer + j .Lfill + +.Lz1: /* Byte 1 is zero. */ +#ifdef __XTENSA_EB__ + extui a8, a8, 16, 16 +#endif + s16i a8, a10, 0 + addi a4, a4, -2 // decrement n + addi a10, a10, 2 // advance dst pointer + j .Lfill + +.Lz2: /* Byte 2 is zero. */ +#ifdef __XTENSA_EB__ + extui a8, a8, 16, 16 +#endif + s16i a8, a10, 0 + movi a8, 0 + s8i a8, a10, 2 + addi a4, a4, -3 // decrement n + addi a10, a10, 3 // advance dst pointer + j .Lfill + + .align 4 +#if XCHAL_HAVE_LOOPS +#if XCHAL_HAVE_DENSITY + /* (2 mod 4) alignment for loop instruction */ +#else + /* (1 mod 4) alignment for loop instruction */ + .byte 0 + .byte 0 +#endif +#endif +.Ldstunaligned: + +#if XCHAL_HAVE_LOOPS +#if XCHAL_HAVE_DENSITY + _movi.n a8, 0 // set up for the maximum loop count +#else + _movi a8, 0 // set up for the maximum loop count +#endif + loop a8, 2f // loop forever (almost anyway) +#endif +1: l8ui a8, a3, 0 + addi a3, a3, 1 +#if XTENSA_ESP32_PSRAM_CACHE_FIX + nop + nop + nop +#endif + s8i a8, a10, 0 + addi a4, a4, -1 + beqz a4, 3f + addi a10, a10, 1 +#if XCHAL_HAVE_LOOPS + beqz a8, 2f +#else + bnez a8, 1b +#endif +2: j .Lfill + +3: +#if XTENSA_ESP32_PSRAM_CACHE_FIX + memw +#endif + leaf_return +.end schedule + + .size strncpy, . - strncpy diff --git a/newlib/libc/machine/xtensa/xtensa-asm.h b/newlib/libc/machine/xtensa/xtensa-asm.h new file mode 100644 index 0000000..926f3e4 --- /dev/null +++ b/newlib/libc/machine/xtensa/xtensa-asm.h @@ -0,0 +1,72 @@ +/* Copyright (c) 2006 Tensilica Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +/* Define macros for leaf function entry and return, supporting either the + * standard register windowed ABI or the non-windowed call0 ABI. These + * macros do not allocate any extra stack space, so they only work for + * leaf functions that do not need to spill anything to the stack. */ + +#include <xtensa/config/core-isa.h> + + .macro leaf_entry reg, size +#if XCHAL_HAVE_WINDOWED && !__XTENSA_CALL0_ABI__ + entry \reg, \size +#else + /* do nothing */ +#endif + .endm + + .macro leaf_return +#if XCHAL_HAVE_WINDOWED && !__XTENSA_CALL0_ABI__ + retw +#else + ret +#endif + .endm + + .macro src_b r, w0, w1 +#ifdef __XTENSA_EB__ + src \r, \w0, \w1 +#else + src \r, \w1, \w0 +#endif + .endm + + .macro ssa8 r +#ifdef __XTENSA_EB__ + ssa8b \r +#else + ssa8l \r +#endif + .endm + +#if XCHAL_HAVE_BE +#define MASK0 0xff000000 +#define MASK1 0x00ff0000 +#define MASK2 0x0000ff00 +#define MASK3 0x000000ff +#else +#define MASK0 0x000000ff +#define MASK1 0x0000ff00 +#define MASK2 0x00ff0000 +#define MASK3 0xff000000 +#endif + diff --git a/newlib/libc/machine/xtensa/xtensa.tex b/newlib/libc/machine/xtensa/xtensa.tex new file mode 100644 index 0000000..1a5bf65 --- /dev/null +++ b/newlib/libc/machine/xtensa/xtensa.tex @@ -0,0 +1,72 @@ +@node Xtensa +@chapter Functions for Xtensa Processors + +This chapter describes machine-dependent functions that are included +in the C library when it is built for Xtensa processors. + +@menu +* setjmp:: Save stack environment +* longjmp:: Non-local goto +@end menu + +@page +@node setjmp +@section @code{setjmp}---save stack environment +@findex setjmp +@strong{Synopsis} +@example +#include <setjmp.h> +int setjmp(jmp_buf env); + +@end example +@strong{Description}@* +@code{setjmp} and @code{longjmp} are useful for dealing with errors +and interrupts encountered in a low-level subroutine of a program. +@code{setjmp} saves the stack context/environment in @code{env} for +later use by @code{longjmp}. The stack context will be invalidated if +the function which called @code{setjmp} returns. + +@* +@strong{Returns}@* +@code{setjmp} returns 0 if returning directly, and non-zero when +returning from @code{longjmp} using the saved context. + +@* +@strong{Portability}@* +@code{setjmp} is ANSI C and POSIX.1. + +setjmp requires no supporting OS subroutines. + +@* +@page +@node longjmp +@section @code{longjmp}---non-local goto +@findex longjmp +@strong{Synopsis} +@example +#include <setjmp.h> +void longjmp(jmp_buf env, int val); + +@end example +@strong{Description}@* +@code{longjmp} and @code{setjmp} are useful for dealing with errors +and interrupts encountered in a low-level subroutine of a program. +@code{longjmp} restores the environment saved by the last call of +@code{setjmp} with the corresponding @code{env} argument. After +@code{longjmp} is completed, program execution continues as if the +corresponding call of @code{setjmp} had just returned the value +@code{val}. @code{longjmp} cannot cause 0 to be returned. If +@code{longjmp} is invoked with a second argument of 0, 1 will be +returned instead. + +@* +@strong{Returns}@* +This function never returns. + +@* +@strong{Portability}@* +@code{longjmp} is ANSI C and POSIX.1. + +longjmp requires no supporting OS subroutines. + +@* diff --git a/newlib/libc/sys/Makefile.inc b/newlib/libc/sys/Makefile.inc index 9f87589..24d8407 100644 --- a/newlib/libc/sys/Makefile.inc +++ b/newlib/libc/sys/Makefile.inc @@ -64,6 +64,9 @@ endif if HAVE_LIBC_SYS_W65_DIR include %D%/w65/Makefile.inc endif +if HAVE_LIBC_SYS_XTENSA_DIR +include %D%/xtensa/Makefile.inc +endif if HAVE_LIBC_SYS_Z8KSIM_DIR include %D%/z8ksim/Makefile.inc endif diff --git a/newlib/libc/sys/xtensa/Makefile.inc b/newlib/libc/sys/xtensa/Makefile.inc new file mode 100644 index 0000000..ddee58a --- /dev/null +++ b/newlib/libc/sys/xtensa/Makefile.inc @@ -0,0 +1 @@ +libc_a_SOURCES += %D%/creat.c %D%/isatty.c %D%/clibrary_init.c diff --git a/newlib/libc/sys/xtensa/clibrary_init.c b/newlib/libc/sys/xtensa/clibrary_init.c new file mode 100644 index 0000000..24d4cf9 --- /dev/null +++ b/newlib/libc/sys/xtensa/clibrary_init.c @@ -0,0 +1,42 @@ +/* Copyright (c) 2003-2006 Tensilica Inc. ALL RIGHTS RESERVED. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL TENSILICA + INCORPORATED BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ + +#include <stdlib.h> +#include <unistd.h> + +const char * __progname = 0; + +void +__clibrary_init (int argc, char **argv, char **envp, + void (*init)(void), + void (*fini)(void)) +{ + if (argv != 0) + __progname = *argv; + environ = envp; + if (init) + init (); + if (fini) + atexit (fini); +} diff --git a/newlib/libc/sys/xtensa/creat.c b/newlib/libc/sys/xtensa/creat.c new file mode 100644 index 0000000..21e6a18 --- /dev/null +++ b/newlib/libc/sys/xtensa/creat.c @@ -0,0 +1,9 @@ +/* creat() "system call" (copied from libc/posix/creat.c) */ + +#include <fcntl.h> + +int +creat (const char *path, mode_t mode) +{ + return open (path, O_WRONLY | O_CREAT | O_TRUNC, mode); +} diff --git a/newlib/libc/sys/xtensa/crt0.c b/newlib/libc/sys/xtensa/crt0.c new file mode 100644 index 0000000..11725dc --- /dev/null +++ b/newlib/libc/sys/xtensa/crt0.c @@ -0,0 +1,16 @@ +/* Dummy crt0 code. */ + +/* Copyright (c) 2003 by Tensilica Inc. ALL RIGHTS RESERVED. + These coded instructions, statements, and computer programs are the + copyrighted works and confidential proprietary information of Tensilica Inc. + They may not be modified, copied, reproduced, distributed, or disclosed to + third parties in any manner, medium, or form, in whole or in part, without + the prior written consent of Tensilica Inc. */ + +/* Xtensa systems normally use a crt1 file associated with a particular + linker support package (LSP). There is no need for this crt0 file, + except that the newlib makefiles require it to exist if there is a + sys/xtensa directory. The directory exists only to hold the header + files for the Xtensa ISS semihosting "platform". */ + +void crt0_unused (void) {} diff --git a/newlib/libc/sys/xtensa/include/fenv.h b/newlib/libc/sys/xtensa/include/fenv.h new file mode 100644 index 0000000..2fa76f7 --- /dev/null +++ b/newlib/libc/sys/xtensa/include/fenv.h @@ -0,0 +1,88 @@ +/* Copyright (c) 2011 Tensilica Inc. ALL RIGHTS RESERVED. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + + 1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above + copyright notice, this list of conditions and the following + disclaimer in the documentation and/or other materials provided + with the distribution. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL + TENSILICA INCORPORATED BE LIABLE FOR ANY DIRECT, INDIRECT, + INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED + OF THE POSSIBILITY OF SUCH DAMAGE. */ + + +#ifndef _FENV_H +#define _FENV_H + +#ifdef __cplusplus +extern "C" { +#endif + +typedef unsigned long fenv_t; +typedef unsigned long fexcept_t; + +#define FE_DIVBYZERO 0x08 +#define FE_INEXACT 0x01 +#define FE_INVALID 0x10 +#define FE_OVERFLOW 0x04 +#define FE_UNDERFLOW 0x02 + +#define FE_ALL_EXCEPT \ + (FE_DIVBYZERO | \ + FE_INEXACT | \ + FE_INVALID | \ + FE_OVERFLOW | \ + FE_UNDERFLOW) + +#define FE_DOWNWARD 0x3 +#define FE_TONEAREST 0x0 +#define FE_TOWARDZERO 0x1 +#define FE_UPWARD 0x2 + +#define FE_DFL_ENV ((const fenv_t *) 0) + +int feclearexcept(int); +int fegetexceptflag(fexcept_t *, int); +int feraiseexcept(int); +int fesetexceptflag(const fexcept_t *, int); +int fetestexcept(int); +int fegetround(void); +int fesetround(int); +int fegetenv(fenv_t *); +int feholdexcept(fenv_t *); +int fesetenv(const fenv_t *); +int feupdateenv(const fenv_t *); + +/* glibc extensions */ +int feenableexcept(int excepts); +int fedisableexcept(int excepts); +int fegetexcept(void); + +#define _FE_EXCEPTION_FLAGS_OFFSET 7 +#define _FE_EXCEPTION_FLAG_MASK (FE_ALL_EXCEPT << _FE_EXCEPTION_FLAGS_OFFSET) +#define _FE_EXCEPTION_ENABLE_OFFSET 2 +#define _FE_EXCEPTION_ENABLE_MASK (FE_ALL_EXCEPT << _FE_EXCEPTION_ENABLE_OFFSET) +#define _FE_ROUND_MODE_OFFSET 0 +#define _FE_ROUND_MODE_MASK (0x3 << _FE_ROUND_MODE_OFFSET) +#define _FE_FLOATING_ENV_MASK (_FE_EXCEPTION_FLAG_MASK | _FE_EXCEPTION_ENABLE_MASK | _FE_ROUND_MODE_MASK) + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/newlib/libc/sys/xtensa/include/unistd.h b/newlib/libc/sys/xtensa/include/unistd.h new file mode 100644 index 0000000..4f6fd29 --- /dev/null +++ b/newlib/libc/sys/xtensa/include/unistd.h @@ -0,0 +1,13 @@ +#ifndef _UNISTD_H_ +#define _UNISTD_H_ + +# include <sys/unistd.h> + +#ifndef L_SET +/* Old BSD names for the same constants; just for compatibility. */ +#define L_SET SEEK_SET +#define L_INCR SEEK_CUR +#define L_XTND SEEK_END +#endif + +#endif /* _UNISTD_H_ */ diff --git a/newlib/libc/sys/xtensa/include/xtensa/config/core-isa.h b/newlib/libc/sys/xtensa/include/xtensa/config/core-isa.h new file mode 100644 index 0000000..2accd41 --- /dev/null +++ b/newlib/libc/sys/xtensa/include/xtensa/config/core-isa.h @@ -0,0 +1,115 @@ +/* + * xtensa/config/core-isa.h -- minimum required HAL definitions that are + * dependent on Xtensa processor CORE configuration + * + * See <xtensa/config/core.h>, which includes this file, for more details. + */ + +/* Xtensa processor core configuration information. + + Copyright (c) 1999-2023 Tensilica Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +#ifndef _XTENSA_CORE_CONFIGURATION_H +#define _XTENSA_CORE_CONFIGURATION_H + +#if defined(_LIBC) || defined(_LIBM) || defined(_LIBGLOSS) + +/* Macros used to build newlib and libgloss */ + +#undef XCHAL_HAVE_BE +#ifdef __XCHAL_HAVE_BE +#define XCHAL_HAVE_BE __XCHAL_HAVE_BE +#else +#define XCHAL_HAVE_BE 0 /* big-endian byte ordering */ +#endif + +#undef XCHAL_HAVE_WINDOWED +#ifdef __XCHAL_HAVE_WINDOWED +#define XCHAL_HAVE_WINDOWED __XCHAL_HAVE_WINDOWED +#else +#define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */ +#endif + +#undef XCHAL_NUM_AREGS +#ifdef __XCHAL_NUM_AREGS +#define XCHAL_NUM_AREGS __XCHAL_NUM_AREGS +#else +#define XCHAL_NUM_AREGS 64 /* num of physical addr regs */ +#endif + +#undef XCHAL_HAVE_DENSITY +#ifdef __XCHAL_HAVE_DENSITY +#define XCHAL_HAVE_DENSITY __XCHAL_HAVE_DENSITY +#else +#define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */ +#endif + +#undef XCHAL_HAVE_LOOPS +#ifdef __XCHAL_HAVE_LOOPS +#define XCHAL_HAVE_LOOPS __XCHAL_HAVE_LOOPS +#else +#define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */ +#endif + +#undef XCHAL_HAVE_L32R +#ifdef __XCHAL_HAVE_L32R +#define XCHAL_HAVE_L32R __XCHAL_HAVE_L32R +#else +#define XCHAL_HAVE_L32R 1 /* L32R instruction */ +#endif + +#undef XCHAL_HAVE_FP +#ifdef __XCHAL_HAVE_FP +#define XCHAL_HAVE_FP __XCHAL_HAVE_FP +#else +#define XCHAL_HAVE_FP 1 /* single prec floating point */ +#endif + +#undef XCHAL_HAVE_FP_SQRT +#ifdef __XCHAL_HAVE_FP_SQRT +#define XCHAL_HAVE_FP_SQRT __XCHAL_HAVE_FP_SQRT +#else +#define XCHAL_HAVE_FP_SQRT 1 /* FP with SQRT instructions */ +#endif + +#undef XCHAL_HAVE_DFP +#ifdef __XCHAL_HAVE_DFP +#define XCHAL_HAVE_DFP __XCHAL_HAVE_DFP +#else +#define XCHAL_HAVE_DFP 0 /* double precision FP pkg */ +#endif + +#undef XCHAL_INST_FETCH_WIDTH +#ifdef __XCHAL_INST_FETCH_WIDTH +#define XCHAL_INST_FETCH_WIDTH __XCHAL_INST_FETCH_WIDTH +#else +#define XCHAL_INST_FETCH_WIDTH 4 /* instr-fetch width in bytes */ +#endif + +#else /* defined(_LIBC) || defined(_LIBM) || defined(_LIBGLOSS) */ + +/* Expect that core-isa.h exists in OS/baremetal port */ +#include_next <xtensa/config/core-isa.h> + +#endif /* defined(_LIBC) || defined(_LIBM) || defined(_LIBGLOSS) */ + +#endif /* _XTENSA_CORE_CONFIGURATION_H */ diff --git a/newlib/libc/sys/xtensa/isatty.c b/newlib/libc/sys/xtensa/isatty.c new file mode 100644 index 0000000..fe64209 --- /dev/null +++ b/newlib/libc/sys/xtensa/isatty.c @@ -0,0 +1,18 @@ +/* isatty.c */ + +/* Dumb implementation so programs will at least run. */ + +#include <sys/stat.h> +#include <reent.h> + +int +_isatty_r (struct _reent *ptr, int fd) +{ + struct stat buf; + + if (_fstat_r (ptr, fd, &buf) < 0) + return 0; + if (S_ISCHR (buf.st_mode)) + return 1; + return 0; +} diff --git a/newlib/libc/sys/xtensa/sys/file.h b/newlib/libc/sys/xtensa/sys/file.h new file mode 100644 index 0000000..48a2ca0 --- /dev/null +++ b/newlib/libc/sys/xtensa/sys/file.h @@ -0,0 +1,33 @@ +/* Copyright (c) 2005-2006 Tensilica Inc. ALL RIGHTS RESERVED. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL TENSILICA + INCORPORATED BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ + +#include <sys/fcntl.h> + +/* Alternate names for values for the WHENCE argument to `lseek'. + These are the same as SEEK_SET, SEEK_CUR, and SEEK_END, respectively. */ +#ifndef L_SET +#define L_SET 0 /* Seek from beginning of file. */ +#define L_INCR 1 /* Seek from current position. */ +#define L_XTND 2 /* Seek from end of file. */ +#endif diff --git a/newlib/libm/Makefile.inc b/newlib/libm/Makefile.inc index 075693a..28b84bf 100644 --- a/newlib/libm/Makefile.inc +++ b/newlib/libm/Makefile.inc @@ -92,6 +92,9 @@ if HAVE_LIBM_MACHINE_X86_64 include %D%/machine/x86_64/Makefile.inc include %D%/ld80/Makefile.inc endif +if HAVE_LIBM_MACHINE_XTENSA +include %D%/machine/xtensa/Makefile.inc +endif CLEANFILES += \ %D%/targetdep.tex \ diff --git a/newlib/libm/acinclude.m4 b/newlib/libm/acinclude.m4 index f7f9f53..f6d88d4 100644 --- a/newlib/libm/acinclude.m4 +++ b/newlib/libm/acinclude.m4 @@ -1,10 +1,11 @@ dnl We have to include these unconditionally since machines might want to use dnl AM_CONDITIONAL in their subdirs. m4_include([libm/machine/nds32/acinclude.m4]) +m4_include([libm/machine/xtensa/acinclude.m4]) dnl Define HAVE_LIBM_MACHINE_<machine> automake conditionals. m4_foreach_w([MACHINE], [ - aarch64 amdgcn arm i386 mips nds32 powerpc pru sparc spu riscv x86_64 + aarch64 amdgcn arm i386 mips nds32 powerpc pru sparc spu riscv x86_64 xtensa ], [dnl AM_CONDITIONAL([HAVE_LIBM_MACHINE_]m4_toupper(MACHINE), test "${libm_machine_dir}" = "MACHINE") ]) diff --git a/newlib/libm/machine/xtensa/Makefile.inc b/newlib/libm/machine/xtensa/Makefile.inc new file mode 100644 index 0000000..3c95a56 --- /dev/null +++ b/newlib/libm/machine/xtensa/Makefile.inc @@ -0,0 +1,12 @@ +%C%_src = \ + %D%/feclearexcept.c %D%/fegetenv.c %D%/fegetexcept.c %D%/fegetexceptflag.c \ + %D%/fegetround.c %D%/feholdexcept.c %D%/feraiseexcept.c %D%/fetestexcept.c \ + %D%/feupdateenv.c + +if XTENSA_XCHAL_HAVE_FP_SQRT +%C%_src += \ + %D%/ef_sqrt.c +endif + +libm_a_CFLAGS_%C% = -D_LIBM +libm_a_SOURCES += $(%C%_src) diff --git a/newlib/libm/machine/xtensa/acinclude.m4 b/newlib/libm/machine/xtensa/acinclude.m4 new file mode 100644 index 0000000..4d242e0 --- /dev/null +++ b/newlib/libm/machine/xtensa/acinclude.m4 @@ -0,0 +1,11 @@ +AC_CACHE_CHECK([for XCHAL_HAVE_FP_SQRT], newlib_cv_xchal_have_fp_sqrt, [dnl + AC_PREPROC_IFELSE([AC_LANG_PROGRAM( +[[#define _LIBM +// targ-include does not exist yet, use relative path +#include "../sys/xtensa/include/xtensa/config/core-isa.h" +#if (!XCHAL_HAVE_FP_SQRT) +# error "Have not XCHAL_HAVE_FP_SQRT" +#endif +]])], [newlib_cv_xchal_have_fp_sqrt="yes"], [newlib_cv_xchal_have_fp_sqrt="no"])]) + +AM_CONDITIONAL(XTENSA_XCHAL_HAVE_FP_SQRT, test "$newlib_cv_xchal_have_fp_sqrt" = "yes") diff --git a/newlib/libm/machine/xtensa/ef_sqrt.c b/newlib/libm/machine/xtensa/ef_sqrt.c new file mode 100644 index 0000000..39e8d75 --- /dev/null +++ b/newlib/libm/machine/xtensa/ef_sqrt.c @@ -0,0 +1,7 @@ +#include <xtensa/config/core-isa.h> + +#if !XCHAL_HAVE_FP_SQRT +#error "__ieee754_sqrtf from common libm must be used" +#else +/* Built-in GCC __ieee754_sqrtf must be used */ +#endif diff --git a/newlib/libm/machine/xtensa/feclearexcept.c b/newlib/libm/machine/xtensa/feclearexcept.c new file mode 100644 index 0000000..f1bd84f --- /dev/null +++ b/newlib/libm/machine/xtensa/feclearexcept.c @@ -0,0 +1,48 @@ +/* Copyright (c) 2011 Tensilica Inc. ALL RIGHTS RESERVED. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + + 1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above + copyright notice, this list of conditions and the following + disclaimer in the documentation and/or other materials provided + with the distribution. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL + TENSILICA INCORPORATED BE LIABLE FOR ANY DIRECT, INDIRECT, + INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED + OF THE POSSIBILITY OF SUCH DAMAGE. */ + +#include <xtensa/config/core-isa.h> + +#if XCHAL_HAVE_FP || XCHAL_HAVE_DFP + +#include <fenv.h> + + +int feclearexcept(int except) +{ + unsigned int fsr; + + if (except & ~FE_ALL_EXCEPT) + return -1; + except <<= _FE_EXCEPTION_FLAGS_OFFSET; + asm ("rur.fsr %0" : "=a"(fsr)); + fsr = fsr & ~except; + asm ("wur.fsr %0" : : "a"(fsr)); + return 0; +} + +#endif diff --git a/newlib/libm/machine/xtensa/fegetenv.c b/newlib/libm/machine/xtensa/fegetenv.c new file mode 100644 index 0000000..b3984ee --- /dev/null +++ b/newlib/libm/machine/xtensa/fegetenv.c @@ -0,0 +1,55 @@ +/* Copyright (c) 2011 Tensilica Inc. ALL RIGHTS RESERVED. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + + 1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above + copyright notice, this list of conditions and the following + disclaimer in the documentation and/or other materials provided + with the distribution. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL + TENSILICA INCORPORATED BE LIABLE FOR ANY DIRECT, INDIRECT, + INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED + OF THE POSSIBILITY OF SUCH DAMAGE. */ + +#include <xtensa/config/core-isa.h> + +#if XCHAL_HAVE_FP || XCHAL_HAVE_DFP + +#include <fenv.h> + +int fegetenv(fenv_t * env_ptr) +{ + unsigned int fsr; + unsigned int fcr; + asm ("rur.fsr %0" : "=a"(fsr)); + asm ("rur.fcr %0" : "=a"(fcr)); + *env_ptr = fsr | fcr; + return 0; +} + + +int fesetenv(const fenv_t * env_ptr) +{ + fenv_t env = *env_ptr; + if (env & ~(_FE_FLOATING_ENV_MASK)) + return -1; + asm ("wur.fsr %0" : : "a"(*env_ptr)); + asm ("wur.fcr %0" : : "a"(*env_ptr)); + return 0; +} + +#endif diff --git a/newlib/libm/machine/xtensa/fegetexcept.c b/newlib/libm/machine/xtensa/fegetexcept.c new file mode 100644 index 0000000..250917c --- /dev/null +++ b/newlib/libm/machine/xtensa/fegetexcept.c @@ -0,0 +1,67 @@ +/* Copyright (c) 2011 Tensilica Inc. ALL RIGHTS RESERVED. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + + 1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above + copyright notice, this list of conditions and the following + disclaimer in the documentation and/or other materials provided + with the distribution. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL + TENSILICA INCORPORATED BE LIABLE FOR ANY DIRECT, INDIRECT, + INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED + OF THE POSSIBILITY OF SUCH DAMAGE. */ + +#include <xtensa/config/core-isa.h> + +#if XCHAL_HAVE_FP || XCHAL_HAVE_DFP + +/* These functions are glibc extensions. */ + +#include <fenv.h> + +int fegetexcept(void) +{ + fexcept_t current; + asm ("rur.fsr %0" : "=a"(current)); + return (current >> _FE_EXCEPTION_ENABLE_OFFSET) & FE_ALL_EXCEPT; +} + + +int feenableexcept(int excepts) +{ + fexcept_t current; + if (excepts & ~FE_ALL_EXCEPT) + return -1; + asm ("rur.fcr %0" : "=a"(current)); + current |= excepts << _FE_EXCEPTION_ENABLE_OFFSET; + asm ("wur.fcr %0" : "=a"(current)); + return 0; +} + + +int fedisableexcept(int excepts) +{ + fexcept_t current; + if (excepts & ~FE_ALL_EXCEPT) + return -1; + asm ("rur.fcr %0" : "=a"(current)); + current &= ~(excepts << _FE_EXCEPTION_ENABLE_OFFSET); + asm ("wur.fcr %0" : "=a"(current)); + return 0; +} + +#endif diff --git a/newlib/libm/machine/xtensa/fegetexceptflag.c b/newlib/libm/machine/xtensa/fegetexceptflag.c new file mode 100644 index 0000000..6d9e7e6 --- /dev/null +++ b/newlib/libm/machine/xtensa/fegetexceptflag.c @@ -0,0 +1,63 @@ +/* Copyright (c) 2011 Tensilica Inc. ALL RIGHTS RESERVED. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + + 1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above + copyright notice, this list of conditions and the following + disclaimer in the documentation and/or other materials provided + with the distribution. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL + TENSILICA INCORPORATED BE LIABLE FOR ANY DIRECT, INDIRECT, + INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED + OF THE POSSIBILITY OF SUCH DAMAGE. */ + +#include <xtensa/config/core-isa.h> + +#if XCHAL_HAVE_FP || XCHAL_HAVE_DFP + +#include <fenv.h> + +int fegetexceptflag(fexcept_t *flagp, int excepts) +{ + unsigned int fsr; + if (excepts & ~FE_ALL_EXCEPT) + return -1; + asm ("rur.fsr %0" : "=a"(fsr)); + fsr >>= _FE_EXCEPTION_FLAGS_OFFSET; + excepts &= fsr; + *flagp = excepts; + + return 0; +} + + +int fesetexceptflag(const fexcept_t *flagp, int excepts) +{ + if (excepts & ~FE_ALL_EXCEPT) + return -1; + + unsigned int fsr; + + asm ("rur.fsr %0" : "=a"(fsr)); + + fsr &= ~(excepts << _FE_EXCEPTION_FLAGS_OFFSET); + fsr |= ((*flagp & excepts) << _FE_EXCEPTION_FLAGS_OFFSET); + asm ("wur.fsr %0" : : "a"(fsr)); + return 0; +} + +#endif diff --git a/newlib/libm/machine/xtensa/fegetround.c b/newlib/libm/machine/xtensa/fegetround.c new file mode 100644 index 0000000..f17be6d --- /dev/null +++ b/newlib/libm/machine/xtensa/fegetround.c @@ -0,0 +1,50 @@ +/* Copyright (c) 2011 Tensilica Inc. ALL RIGHTS RESERVED. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + + 1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above + copyright notice, this list of conditions and the following + disclaimer in the documentation and/or other materials provided + with the distribution. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL + TENSILICA INCORPORATED BE LIABLE FOR ANY DIRECT, INDIRECT, + INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED + OF THE POSSIBILITY OF SUCH DAMAGE. */ + +#include <xtensa/config/core-isa.h> + +#if XCHAL_HAVE_FP || XCHAL_HAVE_DFP + +#include <fenv.h> + +int fegetround(void) +{ + fexcept_t current; + asm ("rur.fcr %0" : "=a"(current)); + return (current & _FE_ROUND_MODE_MASK) >> _FE_ROUND_MODE_OFFSET; +} + + +int fesetround(int round) +{ + if (round & ~_FE_ROUND_MODE_MASK) + return -1; + asm ("wur.fcr %0" : : "a"(round)); + return 0; +} + +#endif diff --git a/newlib/libm/machine/xtensa/feholdexcept.c b/newlib/libm/machine/xtensa/feholdexcept.c new file mode 100644 index 0000000..32e5e0b --- /dev/null +++ b/newlib/libm/machine/xtensa/feholdexcept.c @@ -0,0 +1,54 @@ +/* Copyright (c) 2011 Tensilica Inc. ALL RIGHTS RESERVED. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + + 1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above + copyright notice, this list of conditions and the following + disclaimer in the documentation and/or other materials provided + with the distribution. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL + TENSILICA INCORPORATED BE LIABLE FOR ANY DIRECT, INDIRECT, + INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED + OF THE POSSIBILITY OF SUCH DAMAGE. */ + +#include <xtensa/config/core-isa.h> + +#if XCHAL_HAVE_FP || XCHAL_HAVE_DFP + +#include <fenv.h> + +int feholdexcept(fenv_t * envp) +{ + fexcept_t fsr; + fenv_t fcr; + /* Get the environment. */ + asm ("rur.fcr %0" : "=a"(fcr)); + asm ("rur.fsr %0" : "=a"(fsr)); + *envp = fsr | fcr; + + /* Clear the exception enable flags. */ + fcr &= _FE_ROUND_MODE_MASK; + asm ("wur.fcr %0" : :"a"(fcr)); + + /* Clear the exception happened flags. */ + fsr = 0; + asm ("wur.fsr %0" : :"a"(fsr)); + + return 0; +} + +#endif diff --git a/newlib/libm/machine/xtensa/feraiseexcept.c b/newlib/libm/machine/xtensa/feraiseexcept.c new file mode 100644 index 0000000..8d418f0 --- /dev/null +++ b/newlib/libm/machine/xtensa/feraiseexcept.c @@ -0,0 +1,49 @@ +/* Copyright (c) 2011 Tensilica Inc. ALL RIGHTS RESERVED. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + + 1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above + copyright notice, this list of conditions and the following + disclaimer in the documentation and/or other materials provided + with the distribution. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL + TENSILICA INCORPORATED BE LIABLE FOR ANY DIRECT, INDIRECT, + INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED + OF THE POSSIBILITY OF SUCH DAMAGE. */ + +#include <xtensa/config/core-isa.h> + +#if XCHAL_HAVE_FP || XCHAL_HAVE_DFP + +/* Xtensa doesn't trap, so setting the flags is the best we can + do. */ + +#include <fenv.h> + +int feraiseexcept(int excepts) +{ + fexcept_t current; + + if (excepts & ~FE_ALL_EXCEPT) + return -1; + asm ("rur.fsr %0" : "=a"(current)); + current |= excepts << _FE_EXCEPTION_FLAGS_OFFSET; + asm ("wur.fsr %0" : : "a"(current)); + return 0; +} + +#endif diff --git a/newlib/libm/machine/xtensa/fetestexcept.c b/newlib/libm/machine/xtensa/fetestexcept.c new file mode 100644 index 0000000..2950859 --- /dev/null +++ b/newlib/libm/machine/xtensa/fetestexcept.c @@ -0,0 +1,41 @@ +/* Copyright (c) 2011 Tensilica Inc. ALL RIGHTS RESERVED. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + + 1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above + copyright notice, this list of conditions and the following + disclaimer in the documentation and/or other materials provided + with the distribution. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL + TENSILICA INCORPORATED BE LIABLE FOR ANY DIRECT, INDIRECT, + INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED + OF THE POSSIBILITY OF SUCH DAMAGE. */ + +#include <xtensa/config/core-isa.h> + +#if XCHAL_HAVE_FP || XCHAL_HAVE_DFP + +#include <fenv.h> + +int fetestexcept(int excepts) +{ + fexcept_t current; + asm ("rur.fsr %0" : "=a"(current)); + return (current >> _FE_EXCEPTION_FLAGS_OFFSET) & excepts; +} + +#endif diff --git a/newlib/libm/machine/xtensa/feupdateenv.c b/newlib/libm/machine/xtensa/feupdateenv.c new file mode 100644 index 0000000..cbb1ffa --- /dev/null +++ b/newlib/libm/machine/xtensa/feupdateenv.c @@ -0,0 +1,46 @@ +/* Copyright (c) 2011 Tensilica Inc. ALL RIGHTS RESERVED. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + + 1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above + copyright notice, this list of conditions and the following + disclaimer in the documentation and/or other materials provided + with the distribution. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL + TENSILICA INCORPORATED BE LIABLE FOR ANY DIRECT, INDIRECT, + INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED + OF THE POSSIBILITY OF SUCH DAMAGE. */ + +#include <xtensa/config/core-isa.h> + +#if XCHAL_HAVE_FP || XCHAL_HAVE_DFP + +#include <fenv.h> + +int feupdateenv(const fenv_t * envp) +{ + fenv_t current; + int err = fegetenv (¤t); + if (err != 0) + return err; + err = fesetenv (envp); + if (err != 0) + return err; + return feraiseexcept (current); +} + +#endif |