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authorJoern Rennecke <joern.rennecke@embecosm.com>2000-02-17 00:33:35 +0000
committerJoern Rennecke <joern.rennecke@embecosm.com>2000-02-17 00:33:35 +0000
commit4415a7ef3e26c669f5f7c5c7efbf7b6ea9b7e2f4 (patch)
tree228df75d1c1eb1e88a1948b9ea986bb3915ebac1
parent483b47749b7fd6341d066d8d4d879a9b4732117f (diff)
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bfd:
Reinstate bits of sh4 support that got accidentally deleted. Add sh-dsp support. bfd: * archures.c (bfd_mach_sh2, bfd_mach_sh_dsp): New macros. (bfd_mach_sh3_dsp): Likewise. (bfd_mach_sh4): Reinstate. (bfd_default_scan): Recognize 7410, 7708, 7729 and 7750. * bfd-in2.h: Regenerate. * coff-sh.c (struct sh_opcode): flags is no longer short. (USESAS, USESAS_REG, USESR8, SETSAS, SETSAS_REG): New macros. (sh_opcode41, sh_opcode42): Integrate as sh_opcode41. (sh_opcode01, sh_opcode02, sh_opcode40): Add sh-dsp opcodes. (sh_opcode41, sh_opcode4, sh_opcode80): Likewise. (sh_opcodes): No longer const. (sh_dsp_opcodef0, sh_dsp_opcodef): New arrays. (sh_insn_uses_reg): Check for USESAS and USESR8. (sh_insn_sets_reg, sh_insns_conflict): Check for SETSAS. (_bfd_sh_align_load_span): Return early for SH4. Modify sh_opcodes lookup table for sh-dsp / sh3-dsp. Take into account that field b of a parallel processing insn could be mistaken for a separate insn. * cpu-sh.c (arch_info_struct): New array elements for sh2, sh-dsp and sh3-dsp. Reinstate element for sh4. (SH2_NEXT, SH_DSP_NEXT, SH3_DSP_NEXT): New macros. (SH4_NEXT): Reinstate. (SH3_NEXT, SH3E_NEXT): Adjust. * elf-bfd.h (_sh_elf_set_mach_from_flags): Declare. * elf32-sh.c (sh_elf_set_private_flags): New function. (sh_elf_copy_private_data, sh_elf_set_mach_from_flags): Likewise. (sh_elf_merge_private_data): New function. (elf_backend_object_p, bfd_elf32_bfd_set_private_bfd_flags): Define. (bfd_elf32_bfd_copy_private_bfd_data): Define. (bfd_elf32_bfd_merge_private_bfd_data): Change to sh_elf_merge_private_data. gas: * config/tc-sh.c ("elf/sh.h"): Include. (sh_dsp, valid_arch, reg_x, reg_y, reg_efg): New static variables. (md.begin): Initialize target_arch. Only include opcodes in has table that match selected architecture. (parse_reg): Recognize register names for sh-dsp. (parse_at): Recognize post-modify addressing. (get_operands): The leading space is now optional. (get_specific): Remove FDREG_N support. Add support for sh-dsp arguments. Update valid_arch. (build_Mytes): Add support for SDT_REG_N. (find_cooked_opcode): New function, broken out of md_assemble. (assemble_ppi, sh_elf_final_processing): New functions. (md_assemble): Use find_cooked_opcode and assemble_ppi. (md_longopts, md_parse_option): New option: -dsp. * config/tc-sh.h (elf_tc_final_processing): Define. (sh_elf_final_processing): Declare. include/elf: * sh.h: (EF_SH_MACH_MASK, EF_SH_UNKNOWN, EF_SH1, EF_SH2): New macros. (EF_SH3, EF_SH_HAS_DSP, EF_SH_DSP, EF_SH3_DSP): Likewise. (EF_SH_HAS_FP, EF_SH3E, EF_SH4, EF_SH_MERGE_MACH): Likewise. opcodes: * sh-dis.c (print_movxy, print_insn_ddt, print_dsp_reg): New functions. (print_insn_ppi): Likewise. (print_insn_shx): Use info->mach to select appropriate insn set. Add support for sh-dsp. Remove FD_REG_N support. * sh-opc.h (sh_nibble_type): Add new values for sh-dsp support. (sh_arg_type): Likewise. Remove FD_REG_N. (sh_dsp_reg_nums): New enum. (arch_sh1, arch_sh2, arch_sh3, arch_sh3e, arch_sh4): New macros. (arch_sh_dsp, arch_sh3_dsp, arch_sh1_up, arch_sh2_up): Likewise. (arch_sh3_up, arch_sh3e_up, arch_sh4_up, arch_sh_dsp_up): Likewise. (arch_sh3_dsp_up): Likewise. (sh_opcode_info): New field: arch. (sh_table): Split up insn with FD_REG_N into ones with F_REG_N and D_REG_N. Fill in arch field. Add sh-dsp insns.
-rw-r--r--include/elf/ChangeLog6
-rw-r--r--include/elf/sh.h27
2 files changed, 33 insertions, 0 deletions
diff --git a/include/elf/ChangeLog b/include/elf/ChangeLog
index bac124d..84c11b0 100644
--- a/include/elf/ChangeLog
+++ b/include/elf/ChangeLog
@@ -1,3 +1,9 @@
+Thu Feb 17 00:18:33 2000 J"orn Rennecke <amylaar@cygnus.co.uk>
+
+ * sh.h: (EF_SH_MACH_MASK, EF_SH_UNKNOWN, EF_SH1, EF_SH2): New macros.
+ (EF_SH3, EF_SH_HAS_DSP, EF_SH_DSP, EF_SH3_DSP): Likewise.
+ (EF_SH_HAS_FP, EF_SH3E, EF_SH4, EF_SH_MERGE_MACH): Likewise.
+
2000-02-03 H.J. Lu <hjl@gnu.org>
* arm-oabi.h: Duplicate changes made to arm.h on Jan. 27,
diff --git a/include/elf/sh.h b/include/elf/sh.h
index 4a47667..faee509 100644
--- a/include/elf/sh.h
+++ b/include/elf/sh.h
@@ -20,6 +20,33 @@
#ifndef _ELF_SH_H
#define _ELF_SH_H
+/* Processor specific flags for the ELF header e_flags field. */
+
+#define EF_SH_MACH_MASK 0x1f
+#define EF_SH_UNKNOWN 0 /* For backwards compatibility. */
+#define EF_SH1 1
+#define EF_SH2 2
+#define EF_SH3 3
+#define EF_SH_HAS_DSP(flags) ((flags) & 4)
+#define EF_SH_DSP 4
+#define EF_SH3_DSP 5
+#define EF_SH_HAS_FP(flags) ((flags) & 8)
+#define EF_SH3E 8
+#define EF_SH4 9
+
+#define EF_SH_MERGE_MACH(mach1, mach2) \
+ (((((mach1) == EF_SH3 || (mach1) == EF_SH_UNKNOWN) && (mach2) == EF_SH_DSP) \
+ || ((mach1) == EF_SH_DSP \
+ && ((mach2) == EF_SH3 || (mach2) == EF_SH_UNKNOWN))) \
+ ? EF_SH3_DSP \
+ : (((mach1) < EF_SH3 && (mach2) == EF_SH_UNKNOWN) \
+ || ((mach2) < EF_SH3 && (mach1) == EF_SH_UNKNOWN)) \
+ ? EF_SH3 \
+ : (((mach1) == EF_SH3E && (mach2) == EF_SH_UNKNOWN) \
+ || ((mach2) == EF_SH3E && (mach1) == EF_SH_UNKNOWN)) \
+ ? EF_SH4 \
+ : ((mach1) > (mach2) ? (mach1) : (mach2)))
+
#include "elf/reloc-macros.h"
/* Relocations. */