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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
; RUN: opt -S --passes=slp-vectorizer -mtriple=x86_64-unknown-linux-gnu -mcpu=znver2 < %s | FileCheck %s
define i32 @test(i32 %arg) {
; CHECK-LABEL: define i32 @test(
; CHECK-SAME: i32 [[ARG:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: [[BB:.*]]:
; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> <i32 0, i32 poison, i32 0, i32 0>, i32 [[ARG]], i32 1
; CHECK-NEXT: br label %[[BB1:.*]]
; CHECK: [[BB1]]:
; CHECK-NEXT: [[PHI:%.*]] = phi i32 [ 0, %[[BB]] ], [ [[OP_RDX:%.*]], %[[BB1]] ]
; CHECK-NEXT: [[TMP5:%.*]] = or <4 x i32> [[TMP0]], zeroinitializer
; CHECK-NEXT: [[TMP6:%.*]] = or <4 x i32> [[TMP5]], zeroinitializer
; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <4 x i32> [[TMP6]], <4 x i32> poison, <8 x i32> <i32 0, i32 0, i32 1, i32 1, i32 2, i32 2, i32 3, i32 3>
; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <4 x i32> [[TMP6]], <4 x i32> poison, <2 x i32> <i32 0, i32 3>
; CHECK-NEXT: [[TMP9:%.*]] = mul <2 x i32> zeroinitializer, [[TMP8]]
; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <2 x i32> [[TMP9]], <2 x i32> poison, <4 x i32> <i32 0, i32 0, i32 1, i32 1>
; CHECK-NEXT: [[TMP11:%.*]] = shufflevector <8 x i32> [[TMP7]], <8 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: [[RDX_OP:%.*]] = mul <4 x i32> [[TMP11]], [[TMP10]]
; CHECK-NEXT: [[TMP14:%.*]] = shufflevector <4 x i32> [[RDX_OP]], <4 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP12:%.*]] = shufflevector <8 x i32> [[TMP7]], <8 x i32> [[TMP14]], <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 4, i32 5, i32 6, i32 7>
; CHECK-NEXT: [[TMP13:%.*]] = call i32 @llvm.vector.reduce.mul.v8i32(<8 x i32> [[TMP12]])
; CHECK-NEXT: [[OP_RDX]] = mul i32 0, [[TMP13]]
; CHECK-NEXT: br label %[[BB1]]
;
bb:
br label %bb1
bb1:
%phi = phi i32 [ 0, %bb ], [ %mul37, %bb1 ]
%mul = mul i64 0, 0
%trunc = trunc i64 %mul to i32
%or = or i32 0, %trunc
%or2 = or i32 0, %or
%or3 = or i32 %or2, 0
%mul4 = mul i32 0, %or3
%mul5 = mul i32 %or3, 0
%mul6 = mul i32 %mul5, %mul4
%mul7 = mul i32 %mul6, %mul4
%mul8 = mul i32 %mul7, %or3
%mul9 = mul i64 0, 0
%trunc10 = trunc i64 %mul9 to i32
%or11 = or i32 0, %trunc10
%or12 = or i32 %arg, %or11
%or13 = or i32 %or12, 0
%mul14 = mul i32 %or13, %mul8
%mul15 = mul i32 %mul14, 0
%mul16 = mul i32 %mul15, 0
%mul17 = mul i32 %mul16, %or13
%shl = shl i64 0, 0
%mul18 = mul i64 %shl, 0
%trunc19 = trunc i64 %mul18 to i32
%or20 = or i32 0, %trunc19
%or21 = or i32 0, %or20
%or22 = or i32 %or21, 0
%mul23 = mul i32 %or22, %mul17
%mul24 = mul i32 %mul23, 0
%mul25 = mul i32 %mul24, 0
%mul26 = mul i32 %mul25, %or22
%shl27 = shl i64 0, 0
%mul28 = mul i64 %shl27, 0
%trunc29 = trunc i64 %mul28 to i32
%or30 = or i32 0, %trunc29
%or31 = or i32 0, %or30
%or32 = or i32 %or31, 0
%mul33 = mul i32 0, %or32
%mul34 = mul i32 %or32, %mul26
%mul35 = mul i32 %mul34, %mul33
%mul36 = mul i32 %mul35, %mul33
%mul37 = mul i32 %mul36, %or32
br label %bb1
}
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