llvm/test/CodeGen/AMDGPU/siloadstoreopt-misaligned-regsequence.ll


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 < %s | FileCheck %s

define amdgpu_kernel void @foo(ptr %0) {
; CHECK-LABEL: foo:
; CHECK:       ; %bb.0: ; %entry
; CHECK-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
; CHECK-NEXT:    v_mov_b32_e32 v2, 0
; CHECK-NEXT:    v_mov_b32_e32 v3, v2
; CHECK-NEXT:    v_mov_b32_e32 v4, v3
; CHECK-NEXT:    v_mov_b32_e32 v3, v2
; CHECK-NEXT:    s_waitcnt lgkmcnt(0)
; CHECK-NEXT:    v_mov_b64_e32 v[0:1], s[0:1]
; CHECK-NEXT:    flat_store_dwordx3 v[0:1], v[2:4]
; CHECK-NEXT:    s_endpgm
entry:
  %1 = getelementptr inbounds i8, ptr %0, i64 4
  store i32 0, ptr %0, align 4
  store i64 0, ptr %1, align 4
  ret void
}