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|
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck %s
define void @main(i1 %arg) #0 {
; CHECK-LABEL: main:
; CHECK: ; %bb.0: ; %bb
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: s_xor_saveexec_b64 s[4:5], -1
; CHECK-NEXT: buffer_store_dword v6, off, s[0:3], s32 ; 4-byte Folded Spill
; CHECK-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; CHECK-NEXT: s_mov_b64 exec, s[4:5]
; CHECK-NEXT: v_writelane_b32 v6, s30, 0
; CHECK-NEXT: v_writelane_b32 v6, s31, 1
; CHECK-NEXT: v_writelane_b32 v6, s36, 2
; CHECK-NEXT: v_writelane_b32 v6, s37, 3
; CHECK-NEXT: v_writelane_b32 v6, s38, 4
; CHECK-NEXT: v_writelane_b32 v6, s39, 5
; CHECK-NEXT: v_writelane_b32 v6, s48, 6
; CHECK-NEXT: v_writelane_b32 v6, s49, 7
; CHECK-NEXT: v_writelane_b32 v6, s50, 8
; CHECK-NEXT: v_writelane_b32 v6, s51, 9
; CHECK-NEXT: v_writelane_b32 v6, s52, 10
; CHECK-NEXT: v_writelane_b32 v6, s53, 11
; CHECK-NEXT: v_writelane_b32 v6, s54, 12
; CHECK-NEXT: v_writelane_b32 v6, s55, 13
; CHECK-NEXT: v_writelane_b32 v6, s64, 14
; CHECK-NEXT: v_writelane_b32 v6, s65, 15
; CHECK-NEXT: v_writelane_b32 v6, s66, 16
; CHECK-NEXT: v_writelane_b32 v6, s67, 17
; CHECK-NEXT: v_writelane_b32 v6, s68, 18
; CHECK-NEXT: s_getpc_b64 s[4:5]
; CHECK-NEXT: s_mov_b64 s[8:9], 0
; CHECK-NEXT: v_writelane_b32 v6, s69, 19
; CHECK-NEXT: s_mov_b32 s68, 0
; CHECK-NEXT: s_mov_b32 s69, s4
; CHECK-NEXT: s_load_dwordx4 s[4:7], s[8:9], 0x0
; CHECK-NEXT: s_load_dwordx8 s[24:31], s[68:69], 0x30
; CHECK-NEXT: s_load_dwordx16 s[52:67], s[68:69], 0xf0
; CHECK-NEXT: ; kill: killed $sgpr8_sgpr9
; CHECK-NEXT: s_nop 0
; CHECK-NEXT: s_load_dwordx16 s[8:23], s[68:69], 0x130
; CHECK-NEXT: ; implicit-def: $vgpr7 : SGPR spill to VGPR lane
; CHECK-NEXT: v_writelane_b32 v6, s70, 20
; CHECK-NEXT: v_writelane_b32 v6, s71, 21
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-NEXT: v_mov_b32_e32 v1, s4
; CHECK-NEXT: v_mov_b32_e32 v2, 0
; CHECK-NEXT: v_writelane_b32 v7, s8, 0
; CHECK-NEXT: v_writelane_b32 v7, s9, 1
; CHECK-NEXT: v_writelane_b32 v7, s10, 2
; CHECK-NEXT: v_writelane_b32 v7, s11, 3
; CHECK-NEXT: v_writelane_b32 v7, s12, 4
; CHECK-NEXT: v_writelane_b32 v7, s13, 5
; CHECK-NEXT: v_writelane_b32 v7, s14, 6
; CHECK-NEXT: v_writelane_b32 v7, s15, 7
; CHECK-NEXT: v_writelane_b32 v7, s16, 8
; CHECK-NEXT: v_writelane_b32 v7, s17, 9
; CHECK-NEXT: v_writelane_b32 v7, s18, 10
; CHECK-NEXT: v_writelane_b32 v7, s19, 11
; CHECK-NEXT: v_writelane_b32 v7, s20, 12
; CHECK-NEXT: v_writelane_b32 v7, s21, 13
; CHECK-NEXT: v_writelane_b32 v7, s22, 14
; CHECK-NEXT: v_writelane_b32 v7, s23, 15
; CHECK-NEXT: v_writelane_b32 v7, s52, 16
; CHECK-NEXT: v_writelane_b32 v7, s53, 17
; CHECK-NEXT: v_writelane_b32 v7, s54, 18
; CHECK-NEXT: v_writelane_b32 v7, s55, 19
; CHECK-NEXT: v_writelane_b32 v7, s56, 20
; CHECK-NEXT: v_writelane_b32 v7, s57, 21
; CHECK-NEXT: v_writelane_b32 v7, s58, 22
; CHECK-NEXT: v_writelane_b32 v7, s59, 23
; CHECK-NEXT: v_writelane_b32 v7, s60, 24
; CHECK-NEXT: v_writelane_b32 v7, s61, 25
; CHECK-NEXT: v_writelane_b32 v7, s62, 26
; CHECK-NEXT: v_writelane_b32 v7, s63, 27
; CHECK-NEXT: v_writelane_b32 v7, s64, 28
; CHECK-NEXT: v_writelane_b32 v7, s65, 29
; CHECK-NEXT: v_writelane_b32 v7, s66, 30
; CHECK-NEXT: s_load_dwordx16 s[8:23], s[68:69], 0x1f0
; CHECK-NEXT: s_load_dwordx16 s[36:51], s[68:69], 0x2f0
; CHECK-NEXT: s_mov_b32 s69, s68
; CHECK-NEXT: s_mov_b32 s70, s68
; CHECK-NEXT: s_mov_b32 s71, s68
; CHECK-NEXT: v_writelane_b32 v7, s67, 31
; CHECK-NEXT: image_sample_lz v3, v[1:2], s[60:67], s[68:71] dmask:0x1
; CHECK-NEXT: v_readlane_b32 s52, v7, 0
; CHECK-NEXT: v_mov_b32_e32 v1, v2
; CHECK-NEXT: v_readlane_b32 s53, v7, 1
; CHECK-NEXT: v_readlane_b32 s54, v7, 2
; CHECK-NEXT: v_readlane_b32 s55, v7, 3
; CHECK-NEXT: v_readlane_b32 s56, v7, 4
; CHECK-NEXT: v_readlane_b32 s57, v7, 5
; CHECK-NEXT: v_readlane_b32 s58, v7, 6
; CHECK-NEXT: v_readlane_b32 s59, v7, 7
; CHECK-NEXT: v_and_b32_e32 v5, 1, v0
; CHECK-NEXT: v_cmp_ne_u32_e64 s[4:5], 1, v5
; CHECK-NEXT: v_readlane_b32 s60, v7, 8
; CHECK-NEXT: v_readlane_b32 s61, v7, 9
; CHECK-NEXT: v_readlane_b32 s62, v7, 10
; CHECK-NEXT: image_sample_lz v4, v[1:2], s[52:59], s[68:71] dmask:0x1
; CHECK-NEXT: v_readlane_b32 s63, v7, 11
; CHECK-NEXT: v_readlane_b32 s64, v7, 12
; CHECK-NEXT: v_readlane_b32 s65, v7, 13
; CHECK-NEXT: v_readlane_b32 s66, v7, 14
; CHECK-NEXT: v_readlane_b32 s67, v7, 15
; CHECK-NEXT: s_waitcnt vmcnt(0)
; CHECK-NEXT: v_mul_f32_e32 v0, v4, v3
; CHECK-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
; CHECK-NEXT: s_xor_b64 s[6:7], exec, s[6:7]
; CHECK-NEXT: s_cbranch_execz .LBB0_3
; CHECK-NEXT: ; %bb.1: ; %bb48
; CHECK-NEXT: v_readlane_b32 s52, v7, 16
; CHECK-NEXT: v_readlane_b32 s60, v7, 24
; CHECK-NEXT: v_readlane_b32 s61, v7, 25
; CHECK-NEXT: v_readlane_b32 s62, v7, 26
; CHECK-NEXT: v_readlane_b32 s63, v7, 27
; CHECK-NEXT: v_readlane_b32 s64, v7, 28
; CHECK-NEXT: v_readlane_b32 s65, v7, 29
; CHECK-NEXT: v_readlane_b32 s66, v7, 30
; CHECK-NEXT: v_readlane_b32 s67, v7, 31
; CHECK-NEXT: s_and_b64 vcc, exec, -1
; CHECK-NEXT: v_readlane_b32 s53, v7, 17
; CHECK-NEXT: v_readlane_b32 s54, v7, 18
; CHECK-NEXT: v_readlane_b32 s55, v7, 19
; CHECK-NEXT: v_readlane_b32 s56, v7, 20
; CHECK-NEXT: image_sample_lz v3, v[1:2], s[60:67], s[68:71] dmask:0x1
; CHECK-NEXT: v_mov_b32_e32 v1, v2
; CHECK-NEXT: v_readlane_b32 s57, v7, 21
; CHECK-NEXT: v_readlane_b32 s58, v7, 22
; CHECK-NEXT: v_readlane_b32 s59, v7, 23
; CHECK-NEXT: .LBB0_2: ; %bb50
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-NEXT: image_sample_lz v4, v[1:2], s[16:23], s[28:31] dmask:0x1
; CHECK-NEXT: s_nop 0
; CHECK-NEXT: image_sample_lz v1, v[1:2], s[44:51], s[68:71] dmask:0x1
; CHECK-NEXT: s_waitcnt vmcnt(0)
; CHECK-NEXT: v_sub_f32_e32 v1, v1, v4
; CHECK-NEXT: v_mul_f32_e32 v1, v1, v0
; CHECK-NEXT: v_mul_f32_e32 v1, v1, v3
; CHECK-NEXT: s_mov_b64 vcc, vcc
; CHECK-NEXT: s_cbranch_vccnz .LBB0_2
; CHECK-NEXT: .LBB0_3: ; %Flow14
; CHECK-NEXT: s_andn2_saveexec_b64 s[6:7], s[6:7]
; CHECK-NEXT: s_cbranch_execz .LBB0_10
; CHECK-NEXT: ; %bb.4: ; %bb32
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-NEXT: s_and_saveexec_b64 s[16:17], s[4:5]
; CHECK-NEXT: s_xor_b64 s[4:5], exec, s[16:17]
; CHECK-NEXT: s_cbranch_execz .LBB0_6
; CHECK-NEXT: ; %bb.5: ; %bb43
; CHECK-NEXT: s_mov_b32 s16, 0
; CHECK-NEXT: s_mov_b32 s17, s16
; CHECK-NEXT: v_mov_b32_e32 v0, s16
; CHECK-NEXT: v_readlane_b32 s44, v7, 16
; CHECK-NEXT: v_mov_b32_e32 v1, s17
; CHECK-NEXT: s_mov_b32 s18, s16
; CHECK-NEXT: s_mov_b32 s19, s16
; CHECK-NEXT: v_readlane_b32 s45, v7, 17
; CHECK-NEXT: v_readlane_b32 s46, v7, 18
; CHECK-NEXT: v_readlane_b32 s47, v7, 19
; CHECK-NEXT: v_readlane_b32 s48, v7, 20
; CHECK-NEXT: v_readlane_b32 s49, v7, 21
; CHECK-NEXT: v_readlane_b32 s50, v7, 22
; CHECK-NEXT: v_readlane_b32 s51, v7, 23
; CHECK-NEXT: v_readlane_b32 s52, v7, 24
; CHECK-NEXT: v_readlane_b32 s53, v7, 25
; CHECK-NEXT: v_readlane_b32 s54, v7, 26
; CHECK-NEXT: v_readlane_b32 s55, v7, 27
; CHECK-NEXT: v_readlane_b32 s56, v7, 28
; CHECK-NEXT: v_readlane_b32 s57, v7, 29
; CHECK-NEXT: v_readlane_b32 s58, v7, 30
; CHECK-NEXT: v_readlane_b32 s59, v7, 31
; CHECK-NEXT: image_sample_lz v2, v[0:1], s[44:51], s[16:19] dmask:0x1
; CHECK-NEXT: v_readlane_b32 s44, v7, 0
; CHECK-NEXT: v_readlane_b32 s52, v7, 8
; CHECK-NEXT: v_readlane_b32 s53, v7, 9
; CHECK-NEXT: v_readlane_b32 s54, v7, 10
; CHECK-NEXT: v_readlane_b32 s55, v7, 11
; CHECK-NEXT: v_readlane_b32 s56, v7, 12
; CHECK-NEXT: v_readlane_b32 s57, v7, 13
; CHECK-NEXT: v_readlane_b32 s58, v7, 14
; CHECK-NEXT: v_readlane_b32 s59, v7, 15
; CHECK-NEXT: v_mov_b32_e32 v3, 0
; CHECK-NEXT: v_mov_b32_e32 v4, v3
; CHECK-NEXT: v_readlane_b32 s45, v7, 1
; CHECK-NEXT: v_readlane_b32 s46, v7, 2
; CHECK-NEXT: v_readlane_b32 s47, v7, 3
; CHECK-NEXT: image_sample_lz v0, v[0:1], s[52:59], s[24:27] dmask:0x1
; CHECK-NEXT: v_readlane_b32 s48, v7, 4
; CHECK-NEXT: v_readlane_b32 s49, v7, 5
; CHECK-NEXT: v_readlane_b32 s50, v7, 6
; CHECK-NEXT: v_readlane_b32 s51, v7, 7
; CHECK-NEXT: s_waitcnt vmcnt(1)
; CHECK-NEXT: buffer_store_dwordx3 v[2:4], off, s[16:19], 0
; CHECK-NEXT: s_waitcnt vmcnt(1)
; CHECK-NEXT: buffer_store_dwordx4 v[0:3], off, s[16:19], 0
; CHECK-NEXT: ; implicit-def: $vgpr0
; CHECK-NEXT: .LBB0_6: ; %Flow12
; CHECK-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; CHECK-NEXT: s_cbranch_execz .LBB0_9
; CHECK-NEXT: ; %bb.7: ; %bb33.preheader
; CHECK-NEXT: s_mov_b32 s16, 0
; CHECK-NEXT: s_mov_b32 s20, s16
; CHECK-NEXT: s_mov_b32 s21, s16
; CHECK-NEXT: v_mov_b32_e32 v1, s20
; CHECK-NEXT: s_mov_b32 s17, s16
; CHECK-NEXT: s_mov_b32 s18, s16
; CHECK-NEXT: s_mov_b32 s19, s16
; CHECK-NEXT: v_mov_b32_e32 v2, s21
; CHECK-NEXT: image_sample_lz v3, v[1:2], s[8:15], s[16:19] dmask:0x1
; CHECK-NEXT: image_sample_lz v4, v[1:2], s[36:43], s[16:19] dmask:0x1
; CHECK-NEXT: s_and_b64 vcc, exec, 0
; CHECK-NEXT: s_waitcnt vmcnt(0)
; CHECK-NEXT: v_sub_f32_e32 v1, v4, v3
; CHECK-NEXT: v_mul_f32_e32 v0, v1, v0
; CHECK-NEXT: v_mov_b32_e32 v1, 0
; CHECK-NEXT: .LBB0_8: ; %bb33
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-NEXT: v_add_f32_e32 v2, v1, v0
; CHECK-NEXT: v_sub_f32_e32 v1, v1, v2
; CHECK-NEXT: s_mov_b64 vcc, vcc
; CHECK-NEXT: s_cbranch_vccz .LBB0_8
; CHECK-NEXT: .LBB0_9: ; %Flow13
; CHECK-NEXT: s_or_b64 exec, exec, s[4:5]
; CHECK-NEXT: .LBB0_10: ; %UnifiedReturnBlock
; CHECK-NEXT: s_or_b64 exec, exec, s[6:7]
; CHECK-NEXT: v_readlane_b32 s71, v6, 21
; CHECK-NEXT: v_readlane_b32 s70, v6, 20
; CHECK-NEXT: v_readlane_b32 s69, v6, 19
; CHECK-NEXT: v_readlane_b32 s68, v6, 18
; CHECK-NEXT: v_readlane_b32 s67, v6, 17
; CHECK-NEXT: v_readlane_b32 s66, v6, 16
; CHECK-NEXT: v_readlane_b32 s65, v6, 15
; CHECK-NEXT: v_readlane_b32 s64, v6, 14
; CHECK-NEXT: v_readlane_b32 s55, v6, 13
; CHECK-NEXT: v_readlane_b32 s54, v6, 12
; CHECK-NEXT: v_readlane_b32 s53, v6, 11
; CHECK-NEXT: v_readlane_b32 s52, v6, 10
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-NEXT: v_readlane_b32 s51, v6, 9
; CHECK-NEXT: v_readlane_b32 s50, v6, 8
; CHECK-NEXT: v_readlane_b32 s49, v6, 7
; CHECK-NEXT: v_readlane_b32 s48, v6, 6
; CHECK-NEXT: v_readlane_b32 s39, v6, 5
; CHECK-NEXT: v_readlane_b32 s38, v6, 4
; CHECK-NEXT: v_readlane_b32 s37, v6, 3
; CHECK-NEXT: v_readlane_b32 s36, v6, 2
; CHECK-NEXT: v_readlane_b32 s31, v6, 1
; CHECK-NEXT: v_readlane_b32 s30, v6, 0
; CHECK-NEXT: s_xor_saveexec_b64 s[4:5], -1
; CHECK-NEXT: buffer_load_dword v6, off, s[0:3], s32 ; 4-byte Folded Reload
; CHECK-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
; CHECK-NEXT: s_mov_b64 exec, s[4:5]
; CHECK-NEXT: s_waitcnt vmcnt(0)
; CHECK-NEXT: s_setpc_b64 s[30:31]
bb:
%i = call i64 @llvm.amdgcn.s.getpc()
%i1 = trunc i64 %i to i32
%i2 = insertelement <2 x i32> zeroinitializer, i32 %i1, i64 1
%i3 = bitcast <2 x i32> %i2 to i64
%i4 = inttoptr i64 %i3 to ptr addrspace(4)
%i5 = getelementptr i8, ptr addrspace(4) %i4, i64 48
%i6 = load <4 x i32>, ptr addrspace(4) %i5, align 16
%i7 = getelementptr i8, ptr addrspace(4) %i4, i64 64
%i8 = load <4 x i32>, ptr addrspace(4) %i7, align 16
%i9 = getelementptr i8, ptr addrspace(4) %i4, i64 240
%i10 = load <8 x i32>, ptr addrspace(4) %i9, align 32
%i11 = getelementptr i8, ptr addrspace(4) %i4, i64 272
%i12 = load <8 x i32>, ptr addrspace(4) %i11, align 32
%i13 = getelementptr i8, ptr addrspace(4) %i4, i64 304
%i14 = load <8 x i32>, ptr addrspace(4) %i13, align 32
%i15 = getelementptr i8, ptr addrspace(4) %i4, i64 336
%i16 = load <8 x i32>, ptr addrspace(4) %i15, align 32
%i17 = getelementptr i8, ptr addrspace(4) %i4, i64 496
%i18 = load <8 x i32>, ptr addrspace(4) %i17, align 32
%i19 = getelementptr i8, ptr addrspace(4) %i4, i64 528
%i20 = load <8 x i32>, ptr addrspace(4) %i19, align 32
%i21 = getelementptr i8, ptr addrspace(4) %i4, i64 752
%i22 = load <8 x i32>, ptr addrspace(4) %i21, align 32
%i23 = getelementptr i8, ptr addrspace(4) %i4, i64 784
%i24 = load <8 x i32>, ptr addrspace(4) %i23, align 32
%i25 = load <4 x float>, ptr addrspace(4) null, align 16
%i26 = extractelement <4 x float> %i25, i64 0
%i27 = call float @llvm.amdgcn.image.sample.lz.2d.f32.f32(i32 1, float %i26, float 0.000000e+00, <8 x i32> %i12, <4 x i32> zeroinitializer, i1 false, i32 0, i32 0)
%i28 = call <4 x float> @llvm.amdgcn.image.sample.lz.2d.v4f32.f32(i32 1, float 0.000000e+00, float 0.000000e+00, <8 x i32> %i14, <4 x i32> zeroinitializer, i1 false, i32 0, i32 0)
%i29 = extractelement <4 x float> %i28, i64 0
%i30 = fmul float %i29, %i27
%i31 = call <4 x float> @llvm.amdgcn.image.sample.lz.2d.v4f32.f32(i32 1, float 0.000000e+00, float 0.000000e+00, <8 x i32> %i16, <4 x i32> %i6, i1 false, i32 0, i32 0)
br i1 %arg, label %bb32, label %bb48
bb32: ; preds = %bb
br i1 %arg, label %bb33, label %bb43
bb33: ; preds = %bb33, %bb32
%i34 = phi float [ %i42, %bb33 ], [ 0.000000e+00, %bb32 ]
%i35 = call <2 x float> @llvm.amdgcn.image.sample.lz.2d.v2f32.f32(i32 1, float 0.000000e+00, float 0.000000e+00, <8 x i32> %i18, <4 x i32> zeroinitializer, i1 false, i32 0, i32 0)
%i36 = extractelement <2 x float> %i35, i64 0
%i37 = call <2 x float> @llvm.amdgcn.image.sample.lz.2d.v2f32.f32(i32 1, float 0.000000e+00, float 0.000000e+00, <8 x i32> %i22, <4 x i32> zeroinitializer, i1 false, i32 0, i32 0)
%i38 = extractelement <2 x float> %i37, i64 0
%i39 = fsub float %i38, %i36
%i40 = fmul float %i39, %i30
%i41 = fadd float %i34, %i40
%i42 = fsub float %i34, %i41
br label %bb33
bb43: ; preds = %bb32
%i44 = call float @llvm.amdgcn.image.sample.lz.2d.f32.f32(i32 1, float 0.000000e+00, float 0.000000e+00, <8 x i32> %i10, <4 x i32> zeroinitializer, i1 false, i32 0, i32 0)
%i45 = bitcast float %i44 to i32
%i46 = insertelement <3 x i32> zeroinitializer, i32 %i45, i64 0
call void @llvm.amdgcn.raw.buffer.store.v3i32(<3 x i32> %i46, <4 x i32> zeroinitializer, i32 0, i32 0, i32 0)
%i47 = bitcast <4 x float> %i31 to <4 x i32>
call void @llvm.amdgcn.raw.buffer.store.v4i32(<4 x i32> %i47, <4 x i32> zeroinitializer, i32 0, i32 0, i32 0)
ret void
bb48: ; preds = %bb
%i49 = call float @llvm.amdgcn.image.sample.lz.2d.f32.f32(i32 1, float 0.000000e+00, float 0.000000e+00, <8 x i32> %i12, <4 x i32> zeroinitializer, i1 false, i32 0, i32 0)
br label %bb50
bb50: ; preds = %bb50, %bb48
%i51 = phi float [ 0.000000e+00, %bb48 ], [ %i58, %bb50 ]
%i52 = call <2 x float> @llvm.amdgcn.image.sample.lz.2d.v2f32.f32(i32 1, float %i51, float 0.000000e+00, <8 x i32> %i20, <4 x i32> %i8, i1 false, i32 0, i32 0)
%i53 = extractelement <2 x float> %i52, i64 0
%i54 = call <2 x float> @llvm.amdgcn.image.sample.lz.2d.v2f32.f32(i32 1, float %i51, float 0.000000e+00, <8 x i32> %i24, <4 x i32> zeroinitializer, i1 false, i32 0, i32 0)
%i55 = extractelement <2 x float> %i54, i64 0
%i56 = fsub float %i55, %i53
%i57 = fmul float %i56, %i30
%i58 = fmul float %i57, %i49
br label %bb50
}
declare i64 @llvm.amdgcn.s.getpc() #1
declare <4 x float> @llvm.amdgcn.image.sample.lz.2d.v4f32.f32(i32 immarg, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #2
declare float @llvm.amdgcn.image.sample.lz.2d.f32.f32(i32 immarg, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #2
declare <2 x float> @llvm.amdgcn.image.sample.lz.2d.v2f32.f32(i32 immarg, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #2
declare void @llvm.amdgcn.raw.buffer.store.v3i32(<3 x i32>, <4 x i32>, i32, i32, i32 immarg) #3
declare void @llvm.amdgcn.raw.buffer.store.v4i32(<4 x i32>, <4 x i32>, i32, i32, i32 immarg) #3
attributes #0 = { "amdgpu-waves-per-eu"="10,10" }
attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
attributes #2 = { nocallback nofree nosync nounwind willreturn memory(read) }
attributes #3 = { nocallback nofree nosync nounwind willreturn memory(write) }
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