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path: root/llvm/utils/TableGen/X86RecognizableInstr.h
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2014-12-24[X86] Remove the single AdSize indicator and replace it with separate AdSize1...Craig Topper1-2/+2
2014-08-13Canonicalize header guards into a common format.Benjamin Kramer1-2/+2
2014-07-17[X86] AVX512: Add disassembler support for compressed displacementAdam Nemet1-0/+5
2014-02-20[x86] Switch PAUSE instruction to use XS prefix instead of HasREPPrefix. Remo...Craig Topper1-2/+0
2014-02-13Remove unused method declaration.Craig Topper1-3/+0
2014-02-13Remove filtering concept from X86 disassembler table generation. It's no long...Craig Topper1-19/+0
2014-02-12Remove special case filtering for instructions with lock prefix as they are a...Craig Topper1-2/+0
2014-02-02TableGen/X86RecognizableInstr.h: Prune out-of-date "@param isSSE". [-Wdocumen...NAKAMURA Takumi1-4/+0
2014-02-02Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 ...Craig Topper1-30/+25
2014-02-02Merge HasVEXPrefix/HasEVEXPrefix/HasXOPPrefix into a 2-bit 'encoding' field i...Craig Topper1-8/+6
2014-01-31Separate x86 opcode maps and 0x66/0xf2/0xf3 prefixes from each other in the T...Craig Topper1-2/+4
2014-01-31Move REP out of the Prefix field of the X86 format. Give it its own bit. It h...Craig Topper1-0/+2
2014-01-15Simplify x86 disassembler table handling of when to use TYPE_Rv/TYPE_R16/TYPE...Craig Topper1-3/+3
2014-01-06The rest of r198588. Remove SegOvrBits from X86 TSFlags since they weren't be...Craig Topper1-2/+0
2014-01-05Add a new x86 specific instruction flag to force some isCodeGenOnly instructi...Craig Topper1-1/+3
2014-01-02Remove unused HasFROperands field from disassembler.Craig Topper1-3/+0
2014-01-02Remove unused function argument.Craig Topper1-3/+1
2013-11-03AVX-512: added VPCONFLICT instruction and intrinsics,Elena Demikhovsky1-0/+2
2013-07-28Added encoding prefixes for KNL instructions (EVEX).Elena Demikhovsky1-0/+10
2012-12-04Sort the #include lines for utils/...Chandler Carruth1-5/+3
2012-09-19Remove code for setting the VEX L-bit as a function of operand size from the ...Craig Topper1-4/+1
2012-09-13Fix Doxygen issues:Dmitri Gribenko1-8/+8
2012-08-23Fix a bunch of -Wdocumentation warnings.Dmitri Gribenko1-1/+1
2012-07-12Update GATHER instructions to support 2 read-write operands. Patch from mysel...Craig Topper1-1/+1
2012-02-27X86 disassembler support for jcxz, jecxz, and jrcxz. Fixes PR11643. Patch by ...Craig Topper1-0/+2
2011-12-30Add FMA4 instructions to disassembler.Craig Topper1-1/+3
2011-10-16Add X86 BZHI instruction as well as BMI2 feature detection.Craig Topper1-2/+2
2011-10-16Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand 3...Craig Topper1-1/+3
2011-10-04Add support in the disassembler for ignoring the L-bit on certain VEX instruc...Craig Topper1-0/+2
2011-10-01Move TableGen's parser and entry point into a libraryPeter Collingbourne1-1/+1
2011-09-23Don't allow 32-bit only instructions to be disassembled in 64-bit mode. Fixes...Craig Topper1-1/+3
2011-07-16Make the disassembler able to disassemble a bunch of instructions with names ...Eli Friedman1-0/+2
2011-03-15X86 table-generator and disassembler support for the AVXSean Callanan1-1/+15
2010-11-29I swear I did a make clean and make before committing all this...Michael J. Spencer1-1/+1
2010-11-01factor the operand list (and related fields/operations) out of Chris Lattner1-1/+2
2010-06-08Reapply r105521, this time appending "LLU" to 64 bitBruno Cardoso Lopes1-0/+2
2010-06-05revert r105521, which is breaking the buildbots with stuff like this:Chris Lattner1-2/+0
2010-06-05Initial AVX support for some instructions. No patterns matchedBruno Cardoso Lopes1-0/+2
2009-12-19Table-driven disassembler for the X86 architecture (16-, 32-, and 64-bit Sean Callanan1-0/+237
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