aboutsummaryrefslogtreecommitdiff
path: root/llvm/utils/TableGen/X86RecognizableInstr.cpp
AgeCommit message (Expand)AuthorFilesLines
2015-01-08[X86] Don't print 'dword ptr' or 'qword ptr' on the operand to some of the LE...Craig Topper1-1/+2
2015-01-07[X86] Remove some unused TYPE enums from the disassembler.Craig Topper1-1/+0
2015-01-06[X86] Add OpSize32 to XBEGIN_4. Add XBEGIN_2 with OpSize16.Craig Topper1-2/+4
2015-01-05[X86] Remove unused operand type from disassembler handling. NFCCraig Topper1-1/+0
2015-01-03[X86] Disassembler support for move to/from %rax with a 32-bit memory offset ...Craig Topper1-0/+4
2015-01-02[X86] Make the instructions that use AdSize16/32/64 co-exist together without...Craig Topper1-11/+30
2014-12-31[X86] Fix disassembly of absolute moves to work correctly in 16 and 32-bit mo...Craig Topper1-0/+4
2014-12-24[X86] Remove the single AdSize indicator and replace it with separate AdSize1...Craig Topper1-3/+7
2014-10-08[AVX512] Support mask register in MRMDestReg formatAdam Nemet1-0/+2
2014-10-01[X86 disasm tblegen backend] Clean up numPhysicalOperands assertsAdam Nemet1-42/+35
2014-09-06[x86] Fix a pretty horrible bug and inconsistency in the x86 asmChandler Carruth1-2/+0
2014-08-25[SKX] avx512_icmp_packed multiclass extensionRobert Khasanov1-0/+2
2014-07-31Add support for the X86 secure guard extensions instructions in assembler (SGX).Kevin Enderby1-56/+59
2014-07-28[SKX] Enabling mask logic instructions: encoding, loweringRobert Khasanov1-0/+2
2014-07-23[SKX] Enabling mask instructions: encoding, loweringRobert Khasanov1-0/+4
2014-07-21[SKX] Enabling SKX target and AVX512BW, AVX512DQ, AVX512VL features.Robert Khasanov1-0/+14
2014-07-17[X86] AVX512: Add disassembler support for compressed displacementAdam Nemet1-2/+15
2014-04-15[C++11] More 'nullptr' conversion. In some cases just using a boolean check i...Craig Topper1-1/+1
2014-02-26[x86] Simplify disassembler code slightly.Craig Topper1-4/+4
2014-02-20[x86] Switch PAUSE instruction to use XS prefix instead of HasREPPrefix. Remo...Craig Topper1-2/+1
2014-02-19Remove special FP opcode maps and instead add enough MRM_XX formats to handle...Craig Topper1-47/+46
2014-02-19Put some of the X86 formats in a more logical order.Craig Topper1-20/+20
2014-02-19Remove A6/A7 opcode maps. They can all be handled with a TB map, opcode of 0x...Craig Topper1-7/+6
2014-02-18Add an x86 prefix encoding for instructions that would decode to a different ...Craig Topper1-10/+38
2014-02-13Remove filtering concept from X86 disassembler table generation. It's no long...Craig Topper1-47/+14
2014-02-12Remove special case filtering for instructions with lock prefix as they are a...Craig Topper1-6/+0
2014-02-12Mark XACQUIRE_PREFIX/XRELEASE_PREFIX as isAsmParserOnly so they'll disappear ...Craig Topper1-6/+0
2014-02-10Recommit r201059 and r201060 with hopefully a fix for its original failure.Craig Topper1-299/+40
2014-02-10Revert r201059 and r201060.Bob Wilson1-40/+299
2014-02-10Simplify a bunch of code by removing the need for the x86 disassembler table ...Craig Topper1-301/+36
2014-02-10Add MRMXr/MRMXm form to X86 for use by instructions which treat the 'reg' fie...Craig Topper1-0/+6
2014-02-02Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 ...Craig Topper1-47/+46
2014-02-02Simplify some code since VEX and EVEX instructions never have HasOpSizePrefix.Craig Topper1-10/+10
2014-02-02Merge HasVEXPrefix/HasEVEXPrefix/HasXOPPrefix into a 2-bit 'encoding' field i...Craig Topper1-20/+23
2014-01-31Separate x86 opcode maps and 0x66/0xf2/0xf3 prefixes from each other in the T...Craig Topper1-121/+69
2014-01-31Move REP out of the Prefix field of the X86 format. Give it its own bit. It h...Craig Topper1-3/+2
2014-01-22]x86] Allow segment and address-size overrides for CMPS[BWLQ] (PR9385)David Woodhouse1-0/+5
2014-01-22[x86] Allow address-size overrides for STOS[BWLQ] (PR9385)David Woodhouse1-0/+12
2014-01-22[x86] Allow segment and address-size overrides for LODS[BWLQ] (PR9385)David Woodhouse1-0/+12
2014-01-20[x86] Fix disassembly of MOV16ao16 et al.David Woodhouse1-2/+0
2014-01-16Allow x86 mov instructions to/from memory with absolute address to be encoded...Craig Topper1-2/+30
2014-01-15Simplify x86 disassembler table handling of when to use TYPE_Rv/TYPE_R16/TYPE...Craig Topper1-22/+17
2014-01-14Remove stray comma in enum to satisfy -Wpedantic.Craig Topper1-1/+1
2014-01-14Separate the concept of 16-bit/32-bit operand size controlled by 0x66 prefix ...Craig Topper1-17/+36
2014-01-08[x86] Fix MOV8ao8 et al for 16-bit mode, fix up disassembler to understandDavid Woodhouse1-0/+2
2014-01-06The rest of r198588. Remove SegOvrBits from X86 TSFlags since they weren't be...Craig Topper1-7/+0
2014-01-05Use patterns to remove some duplicate instructions.Craig Topper1-3/+1
2014-01-05Fix encoding for PUSH64i16. Add In64BitMode Predicate. Remove disassembler hack.Craig Topper1-2/+1
2014-01-05Remove no longer needed x86 disassembler hack.Craig Topper1-6/+0
2014-01-05Mark x86 _alt instructions as AsmParserOnly so they will be omitted from disa...Craig Topper1-2/+1
generated by cgit v1.1 at 2025-10-17 11:08:35 +0000