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path: root/llvm/utils/TableGen/X86DisassemblerTables.cpp
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2025-07-07[TableGen] Remove an unnecessary cast (NFC) (#147454)Kazu Hirata1-2/+1
parent is already of InstructionContext.
2025-06-15[TableGen] Use range-based for loops (NFC) (#144283)Kazu Hirata1-3/+3
2025-03-30[TableGen] Use llvm::append_range (NFC) (#133649)Kazu Hirata1-2/+1
2025-01-16[TableGen] Use std::pair instead of std::make_pair. NFC. (#123174)Jay Foad1-2/+2
Also use brace initialization and emplace to avoid explicitly constructing std::pair, and the same for std::tuple.
2024-08-29[X86, MC] Recognize OSIZE=64b when EVEX.W = 1, EVEX.pp = 01 (#103816)Freddy Ye1-0/+2
In the legacy space, if both the 66 prefix and REX.W=1 are present, the REX.W=1 takes precedence and makes OSIZE=64b. EVEX map 4 inherits this convention, with EVEX.pp=01 and EVEX.W playing the roles of the 66 prefix and REX.W. So if EVEX.pp=00, the OSIZE can only be 64b or 32b, depending on whether EVEX.W=1 or not. But if EVEX.pp=01, then OSIZE is either 64b or 16b depending on whether EVEX.W=1 or not.
2024-08-04[X86][AVX10.2] Support YMM rounding new instructions (#101825)Phoebe Wang1-4/+4
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/828965
2024-08-03Reland "[X86][AVX10.2] Support AVX10.2 option and VMPSADBW/VADDP[D,H,S] new ↵Phoebe Wang1-1/+31
instructions (#101452)" (#101616) Ref.: https://cdrdv2.intel.com/v1/dl/getContent/828965
2024-08-02Revert "[X86][AVX10.2] Support AVX10.2 option and VMPSADBW/VADDP[D,H,S] new ↵Phoebe Wang1-31/+1
instructions" (#101612) Reverts llvm/llvm-project#101452 There are several buildbot failed. Revert first.
2024-08-02[X86][AVX10.2] Support AVX10.2 option and VMPSADBW/VADDP[D,H,S] new ↵Phoebe Wang1-1/+31
instructions (#101452) Ref.: https://cdrdv2.intel.com/v1/dl/getContent/828965
2024-07-05[llvm] Avoid 'raw_string_ostream::str' (NFC)Youngsuk Kim1-2/+2
Since `raw_string_ostream` doesn't own the string buffer, it is desirable (in terms of memory safety) for users to directly reference the string buffer rather than use `raw_string_ostream::str()`. Work towards TODO item to remove `raw_string_ostream::str()`.
2024-02-29[X86][MC] Teach disassembler to recognize apx instructions which ignores W ↵XinWang101-0/+2
bit (#82747) Extended VMX instructions and 8 bit apx extended instructions don't need W bit, they are marked as W ignored in spec. RFC: https://discourse.llvm.org/t/rfc-design-for-apx-feature-egpr-and-ndd-support/73031/4
2024-02-14[TableGen] Stop using make_pair and make_tuple. NFC. (#81730)Jay Foad1-2/+2
These are unnecessary since C++17.
2024-02-09[NFC] clang-format utils/TableGen (#80973)Pierre van Houtryve1-8/+13
``` find llvm/utils/TableGen -iname "*.h" -o -iname "*.cpp" | xargs clang-format-16 -i ``` Split from #80847
2024-01-26[X86] Support promoted ENQCMD, KEYLOCKER and USERMSR (#77293)XinWang101-1/+7
R16-R31 was added into GPRs in https://github.com/llvm/llvm-project/pull/70958, This patch supports the promoted ENQCMD, KEYLOCKER and USER-MSR instructions in EVEX space. RFC: https://discourse.llvm.org/t/rfc-design-for-apx-feature-egpr-and-ndd-support/73031/4
2023-12-28[X86][MC] Support encoding/decoding for APX variant ↵Shengchen Kan1-1/+20
ADD/SUB/ADC/SBB/OR/XOR/NEG/NOT instructions (#76319) Four variants: promoted legacy, ND (new data destination), NF (no flags update) and NF_ND (NF + ND). The syntax of NF instructions is aligned with GNU binutils. https://sourceware.org/pipermail/binutils/2023-September/129545.html
2023-12-15[X86][MC] Support Enc/Dec for EGPR for promoted MOVDIR instruction (#74713)XinWang101-2/+6
R16-R31 was added into GPRs in https://github.com/llvm/llvm-project/pull/70958, This patch supports the encoding/decoding for promoted MOVDIR instruction in EVEX space. RFC: https://discourse.llvm.org/t/rfc-design-for-apx-feature-egpr-and-ndd-support/73031/4
2023-12-07[X86][NFC] Clang-format X86DisassemblerTables.cpp for #74713Shengchen Kan1-136/+135
2023-11-24[X86][MC] Support encoding/decoding for PUSH2[P]/POP2[P] (#73233)Shengchen Kan1-3/+4
PUSH2 and POP2 are two new instructions for (respectively) pushing/popping 2 GPRs at a time to/from the stack. The opcodes of PUSH2 and POP2 are those of “PUSH r/m” and “POP r/m” from legacy map 0, but we require ModRM.Mod = 3 in order to disallow memory operand. The 1-bit Push-Pop Acceleration hint described in #73092 applies to PUSH2/POP2 too, then we have PUSH2P/POP2P. For AT&T syntax, PUSH2[P] pushes the registers from right to left onto the stack. POP2[P] pops the stack to registers from right to left. Intel syntax has the opposite order - from left to right. The assembly syntax is aligned with GCC & binutils https://gcc.gnu.org/pipermail/gcc-patches/2023-November/637718.html
2023-11-22[X86][MC] Support encoding/decoding for JMPABS (#72835)Shengchen Kan1-0/+3
JMPABS is a 64-bit only ISA extension, and acts as a near-direct branch with an absolute target. The 64-bit immediate operand is treated an as absolute effective address, which is subject to canonicality checks. It is in legacy map 0 and requires REX2 prefix with `REX2.M0=0` and `REX2.W=0`. All other REX2 payload bits are ignored. blog: https://kanrobert.github.io/rfc/All-about-APX-JMPABS/ This patch 1. Extends `ExplicitVEXPrefix` to `ExplicitOpPrefix` for instrcutions requires explicit `REX2` or `EVEX` 2. Adds `ATTR_REX2` and `IC_64BIT_REX2` to put `JMPABS` , `MOV EAX, moffs32` in different tables to avoid opcode conflict NOTE: 1. `ExplicitREX2Prefix` can be reused by the following PUSHP/POPP instructions. 2. `ExplicitEVEXPrefix` will be used by the instructions promoted to EVEX space for EGPR.
2023-10-16[X86] Add USER_MSR instructions. (#68944)Freddy Ye1-0/+1
For more details about this instruction, please refer to the latest ISE document: https://www.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html
2023-04-20[X86][Tablgen] Rename IgnoresVEX_W to IgnoresW, VEX_WIG to WIG, NFCIShengchen Kan1-135/+135
We no longer distinguish REX.W from VEX.W in .td.
2022-09-09[llvm] Remove includes of `llvm/Support/STLArrayExtras.h`Joe Loser1-1/+0
`llvm` and downstream internal callers no longer use `array_lengthof`, so drop the include everywhere. Differential Revision: https://reviews.llvm.org/D133600
2022-09-08[llvm] Use std::size instead of llvm::array_lengthofJoe Loser1-1/+1
LLVM contains a helpful function for getting the size of a C-style array: `llvm::array_lengthof`. This is useful prior to C++17, but not as helpful for C++17 or later: `std::size` already has support for C-style arrays. Change call sites to use `std::size` instead. Differential Revision: https://reviews.llvm.org/D133429
2022-09-03Drop empty string literals from static_assert (NFC)Kazu Hirata1-1/+1
Identified with modernize-unary-static-assert.
2022-04-12[X86] Fix handling of maskmovdqu in x32 differentlyHarald van Dijk1-22/+9
This reverts the functional changes of D103427 but keeps its tests, and and reimplements the functionality by reusing the existing 32-bit MASKMOVDQU and VMASKMOVDQU instructions as suggested by skan in review. These instructions were previously predicated on Not64BitMode. This reimplementation restores the disassembly of a class of instructions, which will see a test added in followup patch D122449. These instructions are in 64-bit mode special cased in X86MCInstLower::Lower, because we use flags with one meaning for subtly different things: we have an AdSize32 class which indicates both that the instruction needs a 0x67 prefix and that the text form of the instruction implies a 0x67 prefix. These instructions are special in needing a 0x67 prefix but having a text form that does *not* imply a 0x67 prefix, so we encode this in MCInst as an instruction that has an explicit address size override. Note that originally VMASKMOVDQU64 was special cased to be excluded from disassembly, as we cannot distinguish between VMASKMOVDQU and VMASKMOVDQU64 and rely on the fact that these are indistinguishable, or close enough to it, at the MCInst level that it does not matter which we use. Because VMASKMOVDQU now receives special casing, even though it does not make a difference in the current implementation, as a precaution VMASKMOVDQU is excluded from disassembly rather than VMASKMOVDQU64. Reviewed By: RKSimon, skan Differential Revision: https://reviews.llvm.org/D122540
2022-03-24[NFCI] Fix set-but-unused warning in X86DisassemblerTables.cppDávid Bolvanský1-3/+0
2022-01-31Cleanup llvm/utils/TableGen headersserge-sans-paille1-1/+4
Based on the output of include-what-you-use. It's an utility directory, so no much impact on other code areas. clang++ -E -Iinclude -I../llvm/include ../llvm/utils/TableGen/*.cpp -std=c++14 -fno-rtti -fno-exceptions | wc -l before: 4327274 after: 4316190 Related discourse thread: https://llvm.discourse.group/t/include-what-you-use-include-cleanup Differential Revision: https://reviews.llvm.org/D118466
2022-01-26Revert "Rename llvm::array_lengthof into llvm::size to match std::size from ↵Benjamin Kramer1-1/+1
C++17" This reverts commit ef8206320769ad31422a803a0d6de6077fd231d2. - It conflicts with the existing llvm::size in STLExtras, which will now never be called. - Calling it without llvm:: breaks C++17 compat
2022-01-26Fix ambiguous call to llvm::size introduced in ef8206320769ad31422serge-sans-paille1-1/+1
2022-01-26Rename llvm::array_lengthof into llvm::size to match std::size from C++17serge-sans-paille1-1/+1
As a conquence move llvm::array_lengthof from STLExtras.h to STLForwardCompat.h (which is included by STLExtras.h so no build breakage expected).
2021-08-10[X86] AVX512FP16 instructions enabling 1/6Wang, Pengfei1-0/+2
1. Enable FP16 type support and basic declarations used by following patches. 2. Enable new instructions VMOVW and VMOVSH. Ref.: https://software.intel.com/content/www/us/en/develop/download/intel-avx512-fp16-architecture-specification.html Reviewed By: LuoYuanke Differential Revision: https://reviews.llvm.org/D105263
2021-07-15[X86] Fix handling of maskmovdqu in X32Harald van Dijk1-9/+22
The maskmovdqu instruction is an odd one: it has a 32-bit and a 64-bit variant, the former using EDI, the latter RDI, but the use of the register is implicit. In 64-bit mode, a 0x67 prefix can be used to get the version using EDI, but there is no way to express this in assembly in a single instruction, the only way is with an explicit addr32. This change adds support for the instruction. When generating assembly text, that explicit addr32 will be added. When not generating assembly text, it will be kept as a single instruction and will be emitted with that 0x67 prefix. When parsing assembly text, it will be re-parsed as ADDR32 followed by MASKMOVDQU64, which still results in the correct bytes when converted to machine code. The same applies to vmaskmovdqu as well. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D103427
2021-06-04Fix some -Wunused-but-set-variable in -DLLVM_ENABLE_ASSERTIONS=off buildFangrui Song1-0/+1
2021-05-07[TableGen] Use range-based for loops (NFC)Coelacanthus1-18/+11
Use range-based for loops in TableGen. Reviewed By: Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D101994
2021-01-22[llvm] Use static_assert instead of assert (NFC)Kazu Hirata1-1/+1
Identified with misc-static-assert.
2020-07-03[X86] Remove MODRM_SPLITREGM from the disassembler tables.Craig Topper1-15/+0
This offers a very minor table size reduction due to only being used for one AMX opcode.
2020-07-02[X86-64] Support Intel AMX instructionsXiang1 Zhang1-0/+15
Summary: INTEL ADVANCED MATRIX EXTENSIONS (AMX). AMX is a new programming paradigm, it has a set of 2-dimensional registers (TILES) representing sub-arrays from a larger 2-dimensional memory image and operate on TILES. Spec can be found in Chapter 3 here https://software.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html Reviewers: LuoYuanke, annita.zhang, pengfei, RKSimon, xiangzhangllvm Reviewed By: xiangzhangllvm Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D82705
2020-04-25[X86] Shrink lib/Target/X86/X86GenDisassemblerTables.incFangrui Song1-21/+12
6330853 bytes -> 5207842 bytes
2020-01-11[X86][Disassembler] Shrink X86GenDisassemblerTables.inc from 36M to 6.1MFangrui Song1-46/+42
In x86Disassembler{OneByte,TwoByte,...}Codes, "/* EmptyTable */" is very common. Omitting it saves lots of space. Also, there is no need to display a table entry in multiple lines. It is also common that the whole OpcodeDecision is { MODRM_ONEENTRY, 0}. Make use of zero-initialization.
2019-08-15[llvm] Migrate llvm::make_unique to std::make_uniqueJonas Devlieghere1-1/+1
Now that we've moved to C++14, we no longer need the llvm::make_unique implementation from STLExtras.h. This patch is a mechanical replacement of (hopefully) all the llvm::make_unique instances across the monorepo. llvm-svn: 369013
2019-06-13[X86Disassembler] Unify the EVEX and VEX code in emitContextTable. Merge the ↵Craig Topper1-51/+23
ATTR_VEXL/ATTR_EVEXL bits. NFCI Merging the two bits shrinks the context table from 16384 bytes to 8192 bytes. Remove the ATTRIBUTE_BITS macro and just create an enum directly. Then fix the ATTR_max define to be 8192 to reflect the table size so we stop hardcoding it separately. llvm-svn: 363330
2019-01-19Update the file headers across all of the LLVM projects in the monorepoChandler Carruth1-4/+3
to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
2018-04-22[X86] Remove DATA32_PREFIX. Hack the printing for DATA16_PREFIX to print ↵Craig Topper1-4/+0
'data32' in 16-bit mode. Hack the asm parser to convert 'data32' to 'data16' in 16-bit mode. Improve the error messages to match GNU assembler. This also allows us to remove the hack from the disassembler table building. llvm-svn: 330531
2018-04-19[X86] Remove non-existant instruction name from X86DisassemblerTables.cpp.Craig Topper1-1/+0
This instruction was removed a long time so we don't need to check for it here. llvm-svn: 330363
2018-04-05[X86] Disassembler support for having an ADSIZE prefix affect instructions ↵Craig Topper1-2/+19
with 0xf2 and 0xf3 prefixes. Needed to support umonitor from D45253. llvm-svn: 329327
2018-03-24[X86] Add a new disassembler opcode map for 3DNow. Stop treating 3DNow as an ↵Craig Topper1-6/+3
attribute. This reduces the size of llvm-mc by at least 150k since we no longer have to multiply the attribute across 7 tables. llvm-svn: 328416
2018-03-24[X86] Use unique_ptr to simplify memory management. NFCCraig Topper1-10/+2
llvm-svn: 328413
2018-02-15[X86][3DNOW] Teach decoder about AMD 3DNow! instrsRafael Auler1-2/+6
Summary: This patch makes the decoder understand old AMD 3DNow! instructions that have never been properly supported in the X86 disassembler, despite being supported in other subsystems. Hopefully this should make the X86 decoder more complete with respect to binaries containing legacy code. Reviewers: craig.topper Reviewed By: craig.topper Subscribers: llvm-commits, maksfb, bruno Differential Revision: https://reviews.llvm.org/D43311 llvm-svn: 325295
2017-10-23[X86] Fix disassembler table generation to prevent instructions tagged with ↵Craig Topper1-14/+15
'PS' being inherited into PD/XS/XD attribute entries. llvm-svn: 316345
2017-10-23[X86] Fix disassembly of EVEX rounding control and SAE instructions.Craig Topper1-41/+146
Fixes PR31955. llvm-svn: 316308
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