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path: root/llvm/utils/TableGen/X86DisassemblerTables.cpp
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2016-06-20test commit: remove trailing whitespaceThomas Jablin1-1/+1
llvm-svn: 273197
2015-07-13AVX-512: Added all AVX-512 forms of Vector Convert for Float/Double/Int/Long ↵Elena Demikhovsky1-2/+24
types. In this patch I have only encoding. Intrinsics and DAG lowering will be in the next patch. I temporary removed the old intrinsics test (just to split this patch). Half types are not covered here. Differential Revision: http://reviews.llvm.org/D11134 llvm-svn: 242023
2015-04-21AVX-512: Added VPTESTM and VPTESTNM instructions for SKXElena Demikhovsky1-0/+7
llvm-svn: 235383
2015-04-09Use SmallVector instead of std::vector for uniquing X86 disassembler operand ↵Craig Topper1-1/+2
sets. The number of operands is a small fixed size. llvm-svn: 234465
2015-04-09Simplify some printing code by combining new lines onto previous strings. ↵Craig Topper1-9/+3
Don't work so hard not to print a comma on the last entry of an array. llvm-svn: 234464
2015-04-09Don't convert enum to strings just to put them in the uniquing map. Use the ↵Craig Topper1-15/+12
enum directly. Only convert to a string for printing. llvm-svn: 234463
2015-03-01AVX-512: Added mask and rounding mode for scalar arithmeticsElena Demikhovsky1-0/+12
Added more tests for scalar instructions to destinguish between AVX and AVX-512 forms. llvm-svn: 230891
2015-01-03[X86] Disassembler support for move to/from %rax with a 32-bit memory offset ↵Craig Topper1-2/+8
is REX.W and AdSize prefix are both present. llvm-svn: 225099
2015-01-02[X86] Make the instructions that use AdSize16/32/64 co-exist together ↵Craig Topper1-7/+11
without using mode predicates. This is necessary to allow the disassembler to be able to handle AdSize32 instructions in 64-bit mode when address size prefix is used. Eventually we should probably also support 'addr32' and 'addr16' in the assembler to override the address size on some of these instructions. But for now we'll just use special operand types that will lookup the current mode size to select the right instruction. llvm-svn: 225075
2014-12-31[X86] Fix disassembly of absolute moves to work correctly in 16 and 32-bit ↵Craig Topper1-14/+14
modes with all 4 combinations of OpSize and AdSize prefixes being present or not. llvm-svn: 225036
2014-12-24[X86] Remove the single AdSize indicator and replace it with separate ↵Craig Topper1-0/+3
AdSize16/32/64 flags. This removes a hardcoded list of instructions in the CodeEmitter. Eventually I intend to remove the predicates on the affected instructions since in any given mode two of them are valid if we supported addr32/addr16 prefixes in the assembler. llvm-svn: 224809
2014-10-28[AVX512] Extended avx512_sqrt_packed (sqrt instructions) to VL subset.Robert Khasanov1-0/+5
Refactored through AVX512_maskable llvm-svn: 220806
2014-10-09[AVX512] Extended avx512_binop_rm for AVX512VL subsets.Robert Khasanov1-0/+4
Added avx512_binop_rm_vl multiclass for VL subset Added encoding tests llvm-svn: 219390
2014-08-25[SKX] avx512_icmp_packed multiclass extensionRobert Khasanov1-0/+6
Extended avx512_icmp_packed multiclass by masking versions. Added avx512_icmp_packed_rmb multiclass for embedded broadcast versions. Added corresponding _vl multiclasses. Added encoding tests for CPCMP{EQ|GT}* instructions. Add more fields for X86VectorVTInfo. Added AVX512VLVectorVTInfo that include X86VectorVTInfo for 512/256/128-bit versions Differential Revision: http://reviews.llvm.org/D5024 llvm-svn: 216383
2014-08-04[SKX] Enabling load/store instructions: encodingRobert Khasanov1-0/+11
Instructions: VMOVAPD, VMOVAPS, VMOVDQA8, VMOVDQA16, VMOVDQA32,VMOVDQA64, VMOVDQU8, VMOVDQU16, VMOVDQU32,VMOVDQU64, VMOVUPD, VMOVUPS, Reviewed by Elena Demikhovsky <elena.demikhovsky@intel.com> llvm-svn: 214719
2014-03-06AVX-512: Added rrk, rrkz, rmk, rmkz, rmbk, rmbkz versions of AVX512 FP ↵Elena Demikhovsky1-0/+2
packed instructions, added encoding tests for them. By Robert Khazanov. llvm-svn: 203098
2014-02-19Remove A6/A7 opcode maps. They can all be handled with a TB map, opcode of ↵Craig Topper1-5/+3
0xa6/0xa7, and adding MRM_C0/MRM_E0 forms. Removes 376K from the disassembler tables. llvm-svn: 201641
2014-02-13Remove filtering concept from X86 disassembler table generation. It's no ↵Craig Topper1-5/+1
longer necessary. llvm-svn: 201299
2014-02-09Remove unnecessary include.Craig Topper1-1/+0
llvm-svn: 201041
2014-01-20[x86] Fix disassembly of MOV16ao16 et al.David Woodhouse1-4/+10
The addition of IC_OPSIZE_ADSIZE in r198759 wasn't quite complete. It also turns out to have been unnecessary. The disassembler handles the AdSize prefix for itself, and doesn't care about the difference between (e.g.) MOV8ao8 and MOB8ao8_16 definitions. So just let them coexist and don't worry about it. llvm-svn: 199654
2014-01-13AVX-512: Embedded Rounding Control - encoding and printingElena Demikhovsky1-2/+3
Changed intrinsics for vrcp14/vrcp28 vrsqrt14/vrsqrt28 - aligned with GCC. llvm-svn: 199102
2014-01-08[x86] Fix MOV8ao8 et al for 16-bit mode, fix up disassembler to understandDavid Woodhouse1-1/+4
It seems there is no separate instruction class for having AdSize *and* OpSize bits set, which is required in order to disambiguate between all these instructions. So add that to the disassembler. Hm, perhaps we do need an AdSize16 bit after all? llvm-svn: 198759
2014-01-01Remove modifierType/Base from X86 disassembler tables as they are no longer ↵Craig Topper1-24/+0
used. Removes ~11.5K from static tables. llvm-svn: 198284
2014-01-01AVX-512: Added intrinsics for vcvt, vcvtt, vrndscale, vcmpElena Demikhovsky1-43/+48
Printing rounding control. Enncoding for EVEX_RC (rounding control). llvm-svn: 198277
2013-12-25AVX-512: decoder for AVX-512, made by Alexey Bader.Elena Demikhovsky1-4/+26
llvm-svn: 198013
2013-11-03AVX-512: added VPCONFLICT instruction and intrinsics,Elena Demikhovsky1-3/+32
added EVEX_KZ to tablegen llvm-svn: 193959
2013-10-03Add XOP disassembler support. Fixes PR13933.Craig Topper1-0/+3
llvm-svn: 191874
2013-09-30Filter out repeated sections from the X86 disassembler modRMTable. Saves ↵Craig Topper1-52/+47
about ~43K from a released build. Unfortunately the disassembler tables are still upwards of 800K. llvm-svn: 191652
2013-09-30Various x86 disassembler fixes.Craig Topper1-6/+18
Add VEX_LIG to scalar FMA4 instructions. Use VEX_LIG in some of the inheriting checks in disassembler table generator. Make use of VEX_L_W, VEX_L_W_XS, VEX_L_W_XD contexts. Don't let VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE inherit from their non-L forms unless VEX_LIG is set. Let VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE inherit from all of their non-L or non-W cases. Increase ranking on VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE so they get chosen over non-L/non-W forms. llvm-svn: 191649
2013-07-28Added encoding prefixes for KNL instructions (EVEX).Elena Demikhovsky1-6/+95
Added 512-bit operands printing. Added instruction formats for KNL instructions. llvm-svn: 187324
2012-12-04Sort the #include lines for utils/...Chandler Carruth1-3/+2
I've tried to find main moudle headers where possible, but the TableGen stuff may warrant someone else looking at it. llvm-svn: 169251
2012-09-13Add a new compression type to ModRM table that detects when the memory modRM ↵Craig Topper1-2/+15
byte represent 8 instructions and the reg modRM byte represents up to 64 instructions. Reduces modRM table from 43k entreis to 25k entries. Based on a patch from Manman Ren. llvm-svn: 163774
2012-09-11Change unsigned to a uint16_t in static disassembler tables to reduce the ↵Craig Topper1-0/+4
table size. llvm-svn: 163594
2012-08-01Add more indirection to the disassembler tables to reduce amount of space ↵Craig Topper1-29/+53
used to store the operand types and encodings. Store only the unique combinations in a separate table and store indices in the instruction table. Saves about 32K of static data. llvm-svn: 161101
2012-07-31Use uint8_t to store the InstructionContext table. Saves 768 bytes of static ↵Craig Topper1-1/+1
data. llvm-svn: 161034
2012-07-31Tidy up. Move for loop index declarations into for statements. Use unsigned ↵Craig Topper1-39/+26
instead of uint16_t for loop indices. Use unsigned instead of uint32_t for arguments to raw_ostream.indent. llvm-svn: 161033
2012-07-31Tidy up function argument formatting.Craig Topper1-35/+17
llvm-svn: 161032
2012-07-31Remove trailing whitespaceCraig Topper1-31/+31
llvm-svn: 161030
2012-03-04Use uint8_t instead of enums to store values in X86 disassembler table. ↵Craig Topper1-8/+8
Shaves 150k off the size of X86DisassemblerDecoder.o llvm-svn: 151995
2012-02-27X86 disassembler support for jcxz, jecxz, and jrcxz. Fixes PR11643. Patch by ↵Craig Topper1-0/+9
Kay Tiong Khoo. llvm-svn: 151510
2012-02-19Remove dead code. Improve llvm_unreachable text. Simplify some control flow.Ahmed Charles1-2/+0
llvm-svn: 150918
2012-02-11Reuse the enum names from X86Desc in the X86Disassembler.Benjamin Kramer1-1/+1
This requires some gymnastics to make it available for C code. Remove the names from the disassembler tables, making them relocation free. llvm-svn: 150303
2012-02-09More tweaks to get the size of the X86 disassembler tables down.Craig Topper1-7/+28
llvm-svn: 150167
2012-02-09Flatten some of the arrays in the X86 disassembler tables to reduce space ↵Craig Topper1-38/+38
needed to store pointers on 64-bit hosts and reduce relocations needed at startup. Part of PR11953. llvm-svn: 150161
2012-01-17Remove unreachable code. (replace with llvm_unreachable to help GCC where ↵David Blaikie1-1/+0
necessary) llvm-svn: 148284
2011-11-06More AVX2 instructions and their intrinsics.Craig Topper1-1/+6
llvm-svn: 143895
2011-10-11Fix disassembling of popcntw. Also remove some code that says it accounts ↵Craig Topper1-0/+7
for 64BIT_REXW_XD not existing, but it does exist. llvm-svn: 141642
2011-10-07Revert part of r141274. Only need to change encoding for xchg %eax, %eax in ↵Craig Topper1-0/+1
64-bit mode. This is because in 64-bit mode xchg %eax, %eax implies zeroing the upper 32-bits of RAX which makes it not a NOP. In 32-bit mode using NOP encoding is fine. llvm-svn: 141353
2011-10-04Add support in the disassembler for ignoring the L-bit on certain VEX ↵Craig Topper1-15/+13
instructions. Mark instructions that have this behavior. Fixes PR10676. llvm-svn: 141065
2011-10-02Fix typo in r140954.Craig Topper1-1/+0
llvm-svn: 140962
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