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path: root/llvm/utils/TableGen/SubtargetEmitter.cpp
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2014-11-19Update SetVector to rely on the underlying set's insert to return a ↵David Blaikie1-2/+2
pair<iterator, bool> This is to be consistent with StringSet and ultimately with the standard library's associative container insert function. This lead to updating SmallSet::insert to return pair<iterator, bool>, and then to update SmallPtrSet::insert to return pair<iterator, bool>, and then to update all the existing users of those functions... llvm-svn: 222334
2014-09-02Tablegen scheduling models don't reference empty itineraries as of r216919, ↵Pete Cooper1-4/+5
so don't emit the unused itinerary variables llvm-svn: 216993
2014-09-02Change MCSchedModel to be a struct of statically initialized data.Pete Cooper1-4/+4
This removes static initializers from the backends which generate this data, and also makes this struct match the other Tablegen generated structs in behaviour Reviewed by Andy Trick and Chandler C llvm-svn: 216919
2014-07-15Move Post RA Scheduling flag bit into SchedMachineModelSanjay Patel1-0/+4
Refactoring; no functional changes intended Removed PostRAScheduler bits from subtargets (X86, ARM). Added PostRAScheduler bit to MCSchedModel class. This bit is set by a CPU's scheduling model (if it exists). Removed enablePostRAScheduler() function from TargetSubtargetInfo and subclasses. Fixed the existing enablePostMachineScheduler() method to use the MCSchedModel (was just returning false!). Added methods to TargetSubtargetInfo to allow overrides for AntiDepBreakMode, CriticalPathRCs, and OptLevel for PostRAScheduling. Added enablePostRAScheduler() function to PostRAScheduler class which queries the subtarget for the above values. Preserved existing scheduler behavior for ARM, MIPS, PPC, and X86: a. ARM overrides the CPU's postRA settings by enabling postRA for any non-Thumb or Thumb2 subtarget. b. MIPS overrides the CPU's postRA settings by enabling postRA for everything. c. PPC overrides the CPU's postRA settings by enabling postRA for everything. d. X86 is the only target that actually has postRA specified via sched model info. Differential Revision: http://reviews.llvm.org/D4217 llvm-svn: 213101
2014-05-08Move late partial-unrolling thresholds into the processor definitionsHal Finkel1-0/+1
The old method used by X86TTI to determine partial-unrolling thresholds was messy (because it worked by testing target features), and also would not correctly identify the target CPU if certain target features were disabled. After some discussions on IRC with Chandler et al., it was decided that the processor scheduling models were the right containers for this information (because it is often tied to special uop dispatch-buffer sizes). This does represent a small functionality change: - For generic x86-64 (which uses the SB model and, thus, will get some unrolling). - For AMD cores (because they still currently use the SB scheduling model) - For Haswell (based on benchmarking by Louis Gerbarg, it was decided to bump the default threshold to 50; we're working on a test case for this). Otherwise, nothing has changed for any other targets. The logic, however, has been moved into BasicTTI, so other targets may now also opt-in to this functionality simply by setting LoopMicroOpBufferSize in their processor model definitions. llvm-svn: 208289
2014-05-07Debug.h already includes raw_ostream.h, no need to include it again.Eric Christopher1-1/+0
llvm-svn: 208235
2014-05-06ArrayRef-ize the Feature and Processor tables for SubtargetFeatures.Eric Christopher1-12/+12
This removes arguments passed everywhere and allows the use of standard iteration over lists. Should be no functional change. llvm-svn: 208127
2014-04-30[C++11] Use 'nullptr' in tablegen output files.Craig Topper1-1/+1
llvm-svn: 207611
2014-04-22[Modules] Fix potential ODR violations by sinking the DEBUG_TYPEChandler Carruth1-2/+2
definition below all of the header #include lines, TableGen edition. llvm-svn: 206846
2014-04-15[C++11] More 'nullptr' conversion. In some cases just using a boolean check ↵Craig Topper1-6/+6
instead of comparing to nullptr. llvm-svn: 206254
2014-03-09[C++11] Add 'override' keyword to virtual methods that override their base ↵Craig Topper1-1/+1
class. llvm-svn: 203378
2013-09-25Mark the x86 machine model as incomplete. PR17367.Andrew Trick1-0/+5
Ideally, the machinel model is added at the time the instructions are defined. But many instructions in X86InstrSSE.td still need a model. Without this workaround the scheduler asserts because x86 already has itinerary classes for these instructions, indicating they should be modeled by the scheduler. Since we use the new machine model for other instructions, it expects a new machine model for these too. llvm-svn: 191391
2013-06-15Support BufferSize on ProcResGroup for unified MOp schedulers.Andrew Trick1-5/+1
And add Sandybridge/Haswell resource buffers. llvm-svn: 184034
2013-06-15Machine Model: Add MicroOpBufferSize and resource BufferSize.Andrew Trick1-10/+7
Replace the ill-defined MinLatency and ILPWindow properties with with straightforward buffer sizes: MCSchedMode::MicroOpBufferSize MCProcResourceDesc::BufferSize These can be used to more precisely model instruction execution if desired. Disabled some misched tests temporarily. They'll be reenabled in a few commits. llvm-svn: 184032
2013-06-05SubtargetEmitter fixArnold Schwaighofer1-1/+1
Don't output data if we are supposed to ignore the record. Reapply of 183255, I don't think this was causing the tablegen segfault on linux testers. llvm-svn: 183311
2013-06-04Revert series of sched model patches until I figure out what is going on.Arnold Schwaighofer1-1/+1
llvm-svn: 183273
2013-06-04SubtargetEmitter fixArnold Schwaighofer1-1/+1
Don't output data if we are supposed to ignore the record. llvm-svn: 183255
2013-04-23Machine model: Generate table entries for super-resources.Andrew Trick1-14/+23
Super-resources and resource groups are two ways of expressing overlapping sets of processor resources. Now we generate table entries the same way for both so the scheduler never needs to explicitly check for super-resources. llvm-svn: 180162
2013-04-23Machine model: rewrite a tablegen loop to avoid comparing record pointers.Andrew Trick1-8/+4
llvm-svn: 180160
2013-03-26TableGen SubtargetEmitter fix to allow A9 and Swift to coexist.Andrew Trick1-1/+16
Allow variants to be defined only for some processors on a target. llvm-svn: 178074
2013-03-16Machine model. Allow mixed itinerary classes and SchedRW lists.Andrew Trick1-43/+35
We always supported a mixture of the old itinerary model and new per-operand model, but it required a level of indirection to map itinerary classes to SchedRW lists. This was done for ARM A9. Now we want to define x86 SchedRW lists, with the goal of removing its itinerary classes, but still support the itineraries in the mean time. When I original developed the model, Atom did not have itineraries, so there was no reason to expect this requirement. llvm-svn: 177226
2013-03-14Fix r177112: Add ProcResGroup.Andrew Trick1-1/+3
This is the other half of r177122 that I meant to commit at the same time. llvm-svn: 177123
2013-03-14MachineModel: Add a ProcResGroup class.Andrew Trick1-12/+75
This allows abitrary groups of processor resources. Using something in a subset automatically counts againts the superset. Currently, this only works if the superset is also a ProcResGroup as opposed to a SuperUnit. This allows SandyBridge to be expressed naturally, which will be checked in shortly. def SBPort01 : ProcResGroup<[SBPort0, SBPort1]>; def SBPort15 : ProcResGroup<[SBPort1, SBPort5]>; def SBPort23 : ProcResGroup<[SBPort2, SBPort3]>; def SBPort015 : ProcResGroup<[SBPort0, SBPort1, SBPort5]>; llvm-svn: 177112
2013-03-01MIsched machine model: tablegen subtarget emitter improvement.Andrew Trick1-1/+14
Fix the way resources are counted. I'm taking some time to cleanup the way MachineScheduler handles in-order machine resources. Eventually we'll need more PPC/Atom test cases in tree. llvm-svn: 176390
2013-01-09MIsched: add an ILP window property to machine model.Andrew Trick1-0/+1
This was an experimental option, but needs to be defined per-target. e.g. PPC A2 needs to aggressively hide latency. I converted some in-order scheduling tests to A2. Hal is working on more test cases. llvm-svn: 171946
2012-12-04Sort the #include lines for utils/...Chandler Carruth1-3/+3
I've tried to find main moudle headers where possible, but the TableGen stuff may warrant someone else looking at it. llvm-svn: 169251
2012-11-02Fix a build problem with xlc. The error message wasRafael Espindola1-1/+1
"../llvm-git/utils/TableGen/CodeGenSchedule.cpp", line 1594.12: 1540-0218 (S) The call does not match any parameter list for "operator+". "../llvm-git/include/llvm/ADT/STLExtras.h", line 130.1: 1540-1283 (I) "template <class _Iterator, class Func> llvm::operator+(mapped_iterator<_Iterator,Func>::difference_type, const mapped_iterator<_Iterator,Func> &)" is not a viable candidate. Patch by Kai. llvm-svn: 167311
2012-10-25Remove exception handling usage from tblgen.Joerg Sonnenberger1-7/+7
Most places can use PrintFatalError as the unwinding mechanism was not used for anything other than printing the error. The single exception was CodeGenDAGPatterns.cpp, where intermediate errors during type resolution were ignored to simplify incremental platform development. This use is replaced by an error flag in TreePattern and bailout earlier in various places if it is set. llvm-svn: 166712
2012-10-10misched: Generate IsBuffered flag for machine resources.Andrew Trick1-4/+4
llvm-svn: 165602
2012-10-03TableGen subtarget emitter, nearly first class support for SchedAlias.Andrew Trick1-8/+14
A processor can now arbitrarily alias one SchedWrite onto another. Only the SchedAlias definition need be within the processor model. The aliased SchedWrite may be a SchedVariant, WriteSequence, or transitively refer to another alias. llvm-svn: 165179
2012-10-03Cleanup TableGen subtarget emitter.Andrew Trick1-2/+6
llvm-svn: 165178
2012-09-22Machine Model (-schedmodel only). Added SchedAliases.Andrew Trick1-22/+82
Allow subtargets to tie SchedReadWrite types to processor specific sequences or variants. llvm-svn: 164451
2012-09-19SchedMachineModel: compress the CPU's WriteLatencyTable.Andrew Trick1-7/+26
llvm-svn: 164199
2012-09-18Replaced ReInitMCSubtargetInfo with InitMCProcessor.Andrew Trick1-1/+2
Now where we used to call ReInitMCSubtargetInfo, we actually recompute the same information as InitMCSubtargetInfo instead of only setting the feature bits. llvm-svn: 164105
2012-09-18TableGen subtarget emitter. Generate resolveSchedClass generated hook for ↵Andrew Trick1-0/+84
resolving instruction variants. llvm-svn: 164095
2012-09-18TableGen subtarget emitter. Remove unnecessary header dependence.Andrew Trick1-0/+1
llvm-svn: 164094
2012-09-18TableGen subtarget emitter. Initialize MCSubtargetInfo with the new machine ↵Andrew Trick1-6/+25
model. llvm-svn: 164092
2012-09-17Backout the wrong subtarget emitter fixAndrew Trick1-1/+1
llvm-svn: 164078
2012-09-17Fix release build after revertingAndrew Trick1-2/+1
llvm-svn: 164075
2012-09-17Revert r164061-r164067. Most of the new subtarget emitter.Andrew Trick1-111/+8
I have to work out the Target/CodeGen header dependencies before putting this back. llvm-svn: 164072
2012-09-17InitMCProcessorAndrew Trick1-1/+2
llvm-svn: 164066
2012-09-17TableGen subtarget emitter. Generate resolveSchedClass generated hook for ↵Andrew Trick1-0/+84
resolving instruction variants. llvm-svn: 164062
2012-09-17TableGen subtarget emitter. Initialize MCSubtargetInfo with the new machine ↵Andrew Trick1-7/+25
model. llvm-svn: 164061
2012-09-17TableGen subtarget emitter. Format and emit data tables for the new machine ↵Andrew Trick1-6/+117
model. llvm-svn: 164060
2012-09-17TableGen subtarget emitter. Generate data tables for the new machine model.Andrew Trick1-2/+291
Map the CodeGenSchedule object model onto data tables. The structure of the data tables is defined in MC, so for convenience we include MCSchedule.h. The alternative is maintaining a redundant copy of the table structure definitions. Mapping the object model onto data tables is sufficiently complicated that it should not be interleaved with emitting source code. This avoids major problem with the backend for itinerary generation. llvm-svn: 164059
2012-09-17TableGen subtarget emitter. Emit processor resources for the new machine model.Andrew Trick1-10/+63
llvm-svn: 164058
2012-09-15TableGen subtarget parser. Handle new machine model.Andrew Trick1-3/+3
Collect SchedClasses and SchedRW types from the subtarget defs. llvm-svn: 163951
2012-09-05Constify subtarget info properly so that we dont cast away the const inRoman Divacky1-1/+1
the SubtargetInfoKV tables. Found by gcc48 -Wcast-qual. llvm-svn: 163251
2012-08-08Added MispredictPenalty to SchedMachineModel.Andrew Trick1-0/+1
This replaces an existing subtarget hook on ARM and allows standard CodeGen passes to potentially use the property. llvm-svn: 161471
2012-07-23Fix a typo (the the => the)Sylvestre Ledru1-1/+1
llvm-svn: 160621
generated by cgit v1.1 at 2025-10-18 23:25:24 +0000