aboutsummaryrefslogtreecommitdiff
path: root/llvm/utils/TableGen/SubtargetEmitter.cpp
diff options
context:
space:
mode:
authorAndrew Trick <atrick@apple.com>2013-04-23 23:45:16 +0000
committerAndrew Trick <atrick@apple.com>2013-04-23 23:45:16 +0000
commita3801a39de6baeb7f2a61cbeed611dd8ac9b3747 (patch)
treed51968e7bdccf6ca607ab0db2c4817acc4db89e5 /llvm/utils/TableGen/SubtargetEmitter.cpp
parentcf398b220d051e1a04a5e7b5065cbcfb000f1397 (diff)
downloadllvm-a3801a39de6baeb7f2a61cbeed611dd8ac9b3747.zip
llvm-a3801a39de6baeb7f2a61cbeed611dd8ac9b3747.tar.gz
llvm-a3801a39de6baeb7f2a61cbeed611dd8ac9b3747.tar.bz2
Machine model: Generate table entries for super-resources.
Super-resources and resource groups are two ways of expressing overlapping sets of processor resources. Now we generate table entries the same way for both so the scheduler never needs to explicitly check for super-resources. llvm-svn: 180162
Diffstat (limited to 'llvm/utils/TableGen/SubtargetEmitter.cpp')
-rw-r--r--llvm/utils/TableGen/SubtargetEmitter.cpp37
1 files changed, 23 insertions, 14 deletions
diff --git a/llvm/utils/TableGen/SubtargetEmitter.cpp b/llvm/utils/TableGen/SubtargetEmitter.cpp
index 0d36c4f..4918b1b 100644
--- a/llvm/utils/TableGen/SubtargetEmitter.cpp
+++ b/llvm/utils/TableGen/SubtargetEmitter.cpp
@@ -782,29 +782,38 @@ Record *SubtargetEmitter::FindReadAdvance(const CodeGenSchedRW &SchedRead,
}
// Expand an explicit list of processor resources into a full list of implied
-// resource groups that cover them.
-//
-// FIXME: Effectively consider a super-resource a group that include all of its
-// subresources to allow mixing and matching super-resources and groups.
-//
-// FIXME: Warn if two overlapping groups don't have a common supergroup.
+// resource groups and super resources that cover them.
void SubtargetEmitter::ExpandProcResources(RecVec &PRVec,
std::vector<int64_t> &Cycles,
- const CodeGenProcModel &ProcModel) {
+ const CodeGenProcModel &PM) {
// Default to 1 resource cycle.
Cycles.resize(PRVec.size(), 1);
for (unsigned i = 0, e = PRVec.size(); i != e; ++i) {
+ Record *PRDef = PRVec[i];
RecVec SubResources;
- if (PRVec[i]->isSubClassOf("ProcResGroup")) {
- SubResources = PRVec[i]->getValueAsListOfDefs("Resources");
- }
+ if (PRDef->isSubClassOf("ProcResGroup"))
+ SubResources = PRDef->getValueAsListOfDefs("Resources");
else {
- SubResources.push_back(PRVec[i]);
+ SubResources.push_back(PRDef);
+ PRDef = SchedModels.findProcResUnits(PRVec[i], PM);
+ for (Record *SubDef = PRDef;
+ SubDef->getValueInit("Super")->isComplete();) {
+ if (SubDef->isSubClassOf("ProcResGroup")) {
+ // Disallow this for simplicitly.
+ PrintFatalError(SubDef->getLoc(), "Processor resource group "
+ " cannot be a super resources.");
+ }
+ Record *SuperDef =
+ SchedModels.findProcResUnits(SubDef->getValueAsDef("Super"), PM);
+ PRVec.push_back(SuperDef);
+ Cycles.push_back(Cycles[i]);
+ SubDef = SuperDef;
+ }
}
- for (RecIter PRI = ProcModel.ProcResourceDefs.begin(),
- PRE = ProcModel.ProcResourceDefs.end();
+ for (RecIter PRI = PM.ProcResourceDefs.begin(),
+ PRE = PM.ProcResourceDefs.end();
PRI != PRE; ++PRI) {
- if (*PRI == PRVec[i] || !(*PRI)->isSubClassOf("ProcResGroup"))
+ if (*PRI == PRDef || !(*PRI)->isSubClassOf("ProcResGroup"))
continue;
RecVec SuperResources = (*PRI)->getValueAsListOfDefs("Resources");
RecIter SubI = SubResources.begin(), SubE = SubResources.end();