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path: root/llvm/utils/TableGen/CodeGenDAGPatterns.cpp
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2022-07-08[GlobalISel][SelectionDAG] Implement the HasNoUse builtin predicateAbinav Puthan Purayil1-1/+7
This change introduces the HasNoUse builtin predicate in PatFrags that checks for the absence of use of the first result operand. GlobalISelEmitter will allow source PatFrags with this predicate to be matched with destination instructions with empty outs. This predicate is required for selecting the no-return variant of atomic instructions in AMDGPU. Differential Revision: https://reviews.llvm.org/D125212
2022-07-07[TableGen] Rewrite type set intersection in type inferenceKrzysztof Parzyszek1-36/+62
The previous code had a bug when dealing with matching iPTR against a set of integer types. It was trying to handle it all in a compact way, but that implementation couldn't be modified to correct the problem in a simple way. The code wasn't long, and it was easier to rewrite it. The actual issue was that non-scalar-integer types were considered when matching against iPTR. For example {iPTR} intersected with {i32 f32} was {iPTR} (due to multiple types in the other set), but should be just {i32}, because i32 is the only integer scalar in the other set.
2022-07-07[TableGen] Move printing to stream directly to MachineValueTypeSetKrzysztof Parzyszek1-12/+16
2022-05-11[TableGen] Remove the use of global Record stateRiver Riddle1-6/+7
This commits removes TableGens reliance on managed static global record state by moving the RecordContext into the RecordKeeper. The RecordKeeper is now treated similarly to a (LLVM|MLIR|etc)Context object and is passed to static construction functions. This is an important step forward in removing TableGens reliance on global state, and in a followup will allow for users that parse tablegen to parse multiple tablegen files without worrying about Record lifetime. Differential Revision: https://reviews.llvm.org/D125276
2022-03-11Cleanup include: TableGenserge-sans-paille1-0/+1
This also includes a few cleanup from Support. Discourse thread: https://discourse.llvm.org/t/include-what-you-use-include-cleanup Differential Revision: https://reviews.llvm.org/D121331
2022-02-01[TableGen][RISCV] Relax a restriction in generating patterns for commutable ↵Craig Topper1-23/+17
SDNodes. Previously, all children would be checked to see if any were an explicit Register. If anywhere no commutable patterns would be generated. This patch loosens the restriction to only check the children that are being commuted. Digging back through history, this code predates the existence of commutable intrinsics and commutable SDNodes with more than 2 operands. At that time the loop would count the number of children that weren't registers and if that was equal to 2 it would allow commuting. I don't think this loop was re-considered when commutable intrinsics were added or when we allowed SDNodes with more than 2 operands. This important for RISCV were our isel patterns have a V0 mask operand after the commutable operands on some RISCVISD opcodes. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D117955
2021-12-10utils: Remove some no-op raw_string_ostream flush calls, NFCDuncan P. N. Exon Smith1-1/+1
Since 65b13610a5226b84889b923bae884ba395ad084d, raw_string_ostream has been unbuffered by default. Based on an audit of llvm/utils/, this commit removes every call to `raw_string_ostream::flush()` and any call to `raw_string_ostream::str()` whose result is ignored or that doesn't help with clarity. I left behind a few calls to `str()`. In these cases, the underlying std::string was declared pretty far away and never used again, whereas stream recently had its last write. The code is easier to read as-is; the no-op call to `flush()` inside `str()` isn't harmful, and when https://reviews.llvm.org/D115421 lands it'll be gone anyway.
2021-12-03[TableGen][SelectionDAG] Use ComplexPattern type for non-leaf nodesJessica Clarke1-1/+19
When used as a non-leaf node, TableGen does not currently use the type of a ComplexPattern for type inference, which also means it does not check it doesn't conflict with the use. This differs from when used as a leaf value, where the type is used for inference. This addresses that discrepancy. The test case is not representative of most real-world uses but is sufficient to demonstrate inference is working. Some of these uses also make use of ValueTypeByHwMode rather than SimpleValueType and so the existing type inference is extended to support that alongside the new type inference. There are also currently various cases of using ComplexPatterns with an untyped type, but only for non-leaf nodes. For compatibility this is permitted, and uses the old behaviour of not inferring for non-leaf nodes, but the existing logic is still used for leaf values. This remaining discrepancy should eventually be eliminated, either by removing all such uses of untyped so the special case goes away (I imagine Any, or a more specific type in certain cases, would be perfectly sufficient), or by copying it to the leaf value case so they're consistent with one another if this is something that does need to keep being supported. All non-experimental targets have been verified to produce bit-for-bit identical TableGen output with this change applied. Reviewed By: kparzysz Differential Revision: https://reviews.llvm.org/D109035
2021-10-16[TableGen] Replace static_cast with llvm's cast. NFCCraig Topper1-3/+3
These all appear next to an isa<> and cast<> is much more common in these cases.
2021-10-12[TableGen] Fix both sides of '&&' are sameCraig Topper1-4/+15
The operand of the second any_of in EnforceSmallerThan should be B not S like the FP code in the if below. Unfortunately, fixing that causes an infinite loop in the build of RISCV. So I've added a workaround for that as well. Fixes PR44768. Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D111502
2021-10-03Fixed warnings in LLVM produced by -Wbitwise-instead-of-logicalDávid Bolvanský1-2/+4
2021-06-01Convert TableGen assert to errorStephen Neuendorffer1-1/+2
This gives a nice message about the location of errors in a large tablegen file, which is much more useful for users Differential Revision: https://reviews.llvm.org/D102740
2021-05-28[AArch64][RISCV] Make sure isel correctly honors failure orderings.Eli Friedman1-9/+9
If a cmpxchg specifies acquire or seq_cst on failure, make sure we generate code consistent with that ordering even if the success ordering is not acquire/seq_cst. At one point, it was ambiguous whether this sort of construct was valid, but the C++ standad and LLVM now accept arbitrary combinations of success/failure orderings. This doesn't address the corresponding issue in AtomicExpand. (This was reported as https://bugs.llvm.org/show_bug.cgi?id=33332 .) Fixes https://bugs.llvm.org/show_bug.cgi?id=50512. Differential Revision: https://reviews.llvm.org/D103284
2021-05-15Revert rG632668c1c0e7dcf97154d2e377491cdc8cb6963c : "[TableGen] ↵Simon Pilgrim1-3/+1
TreePatternNode::isIsomorphicTo - early out for matching leafs. NFCI." Revert premature (and very broken....) experimental commit.
2021-05-15[TableGen] TreePatternNode::isIsomorphicTo - early out for matching leafs. NFCI.Simon Pilgrim1-1/+3
If the leafs are the same then no need to perform DefInit matching.
2021-05-12[ValueTypes] Rename MVT::getVectorNumElements() to ↵Craig Topper1-6/+10
MVT::getVectorMinNumElements(). Fix some misuses of getVectorNumElements() getVectorNumElements() returns a value for scalable vectors without any warning so it is effectively getVectorMinNumElements(). By renaming it and making getVectorNumElements() forward to it, we can insert a check for scalable vectors into getVectorNumElements() similar to EVT. I didn't do that in this patch because there are still more fixes needed, but I was able to temporarily do it and passed the RISCV lit tests with these changes. The changes to isPow2VectorType and getPow2VectorType are copied from EVT. The change to TypeInfer::EnforceSameNumElts reduces the size of AArch64's isel table. We're now considering SameNumElts to require the scalable property to match which removes some unneeded type checks. This was motivated by the bug I fixed yesterday in 80b9510806cf11c57f2dd87191d3989fc45defa8 Reviewed By: frasercrmck, sdesmalen Differential Revision: https://reviews.llvm.org/D102262
2021-04-28[TableGen] Remove predicate filtering from GenerateVariants.Craig Topper1-52/+7
After D100691, predicates should be cheap to compare again so we don't need to filter anymore. This is mostly just a revert of several patches going back to 2018. Reviewed By: kparzysz Differential Revision: https://reviews.llvm.org/D100695
2021-04-28[TableGen] Store predicates in PatternToMatch as ListInit *. Add string for ↵Craig Topper1-41/+56
HwModeFeatures This uses to be how predicates were handled prior to HwMode being added. When the Predicates were converted to a std::vector it significantly increased the cost of a compare in GenerateVariants. Since ListInit's are uniquified by tablegen, we can use a simple pointer comparison to check for identical lists. In order to store the HwMode, we now add a separate string to PatternToMatch. This will be appended separately to the predicate string in getPredicateCheck. A new getPredicateRecords is added to allow GlobalISel and getPredicateCheck to both get the sorted list of Records. GlobalISel was ignoring any HwMode predicates before and still is. There is one slight change here, ListInits with different predicate orders aren't sorted so the filtering in GenerateVariants might fail to detect two isomorphic patterns with different predicate orders. This doesn't seem to be happening in tree today. My hope is this will allow us to remove all the BitVector tracking in GenerateVariants that was making up for predicates beeing expensive to compare. There's a decent amount of heap allocations there on large targets like X86, AMDGPU, and RISCV. Differential Revision: https://reviews.llvm.org/D100691
2021-04-27[TableGen] Add predicate checks to isel patterns for default HwMode.Craig Topper1-16/+7
As discussed in D100691 and based on D100889. I removed the ModeChecks cache which provides little value. Reduced from three loops to two. Used ArrayRef to pass the Predicate to AppendPattern to avoid needing to construct a vector for single mode. Used SmallVector to avoid heap allocation constructing DefaultCheck for the in tree targets the use it. Reviewed By: kparzysz Differential Revision: https://reviews.llvm.org/D101240
2021-04-18[TableGen] Pass SmallVector to union_modes instead of returning a std::vector.Craig Topper1-5/+14
The number of modes is small so this should avoid a heap allocation. Also replace std::set with SmallSet.
2021-04-18[TableGen] Use MachineValueTypeSet in place of SmallSet.Craig Topper1-1/+1
MachineValueTypeSet is effectively a std::bitset<256>. This allows us quickly insert into the set and check if a type is in the set.
2021-04-17[TableGen] Remove local SmallSet from TypeSetByHwMode::insert.Craig Topper1-3/+1
This keeps track of which modes are in VVT so we can find out if a mode is missing later. But we can just ask VVT whether it has a particular mode.
2021-04-16[TableGen] Replace two SmallDenseSets with SmallSets.Craig Topper1-2/+2
The key here is HwMode indices. They're going to be small numbers, contiguous, and only a few different values. I don't think we need to go through the SmallDenseSet hashing. A BitVector would be even better, but we don't have the upper bound here.
2021-04-16[TableGen] Run GenerateVariants before ExpandHwModeBasedTypes.Craig Topper1-4/+4
A large portion of the patterns are duplicated for HwMode on RISCV. If we expand HwMode first, we need to check nearly twice as many patterns for variants. HwModes shouldn't affect whether a variant is valid so we should be able to expand after. This also reduces the RISCV isel table by 539 bytes due to factoring working better on this pattern order. Unfortunately it increases Hexagon table size by ~50 bytes. But I think this is a reasonable trade.
2021-04-16[TableGen] Fix -WparenthesesFangrui Song1-7/+7
2021-04-16[tblgen] Fold loop into assert to avoid unused variable warnings. NFCI.Benjamin Kramer1-4/+7
2021-04-16[TableGen] CodeGenDAGPatterns - use const references on for-range loops to ↵Simon Pilgrim1-7/+7
avoid unnecessary copies. NFCI.
2021-04-16[TableGen] CodeGenDAGPatterns - (style) remove if-else chain when if block ↵Simon Pilgrim1-1/+1
always returns. NFCI.
2021-03-31[TableGen] Emit more helpful error messages on empty type setAlex Richardson1-1/+5
I have seen this error quite frequently in our out-of-tree CHERI backends and the lack of location information sometimes makes it quite difficult to track down the actual source of the error. This patch changes the llvm_unreachable() to a PrintFatalError() so that tablegen prints a stack of source locations. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D99468
2021-03-09[RISCV] Add support for VECTOR_REVERSE for scalable vector types.Craig Topper1-2/+13
I've left mask registers to a future patch as we'll need to convert them to full vectors, shuffle, and then truncate. Reviewed By: frasercrmck Differential Revision: https://reviews.llvm.org/D97609
2021-02-26[TableGen] Use ListSeparator (NFC)Kazu Hirata1-10/+7
2021-02-11[TableGen] Use ListSeparator (NFC)Kazu Hirata1-8/+7
2021-02-08[RISCV] Use SplatPat/SplatPat_simm5 to handle PseudoVMV_V_X_/PseudoVMV_V_I_ ↵Craig Topper1-0/+3
selection as well. This ensures that we'll match immediates consistently regardless of whether we match them as a standalone splat or as part of another operation. While I was there I added complexities to the simm5/uimm5 patterns so we didn't have to assume that the 1 on the non-immediate was lower than what tablegen inferred. I had to make a minor tweak to tablegen to fix one place that didn't expect to see a ComplexPattern that wasn't a "leaf". Reviewed By: frasercrmck Differential Revision: https://reviews.llvm.org/D96199
2021-02-06[TableGen] Make all the fields in PatternToMatch private. NFCICraig Topper1-7/+7
Add the few missing accessor methods. Use accessor methdods everywhere.
2021-02-01[TableGen] Use range-based for loops (NFC)Kazu Hirata1-2/+1
2021-01-31[TableGen] Don't commute isel patterns if it would put an immAllOnesV or ↵Craig Topper1-0/+2
immAllZerosV on the left hand side. This primarily occurs with isel patterns using vnot. This reduces the number of variants in the isel tables. We generally canonicalize build_vectors of constants to the RHS. I think we might fail if there is a bitcast on the build_vector, but that should be easy to fix if we can find a case. Usually the bitcast is introduced by type legalization or lowering. It's likely canonicalization would have already occured.
2021-01-30[TableGen] Use emplace_back to add to PatternsToMatch in GenerateVariants. ↵Craig Topper1-3/+3
Use std::move when adding to PatternsToMatch in AddPatternToMatch. We already used emplace_back in at least one other place so be consistent. AddPatternToMatch already took PTM as an rvalue reference, but we need to use std::move again to move it into the PatternToMatch vector.
2021-01-30[TableGen] Avoid a couple vector copies in ExpandHwModeBasedTypes.Craig Topper1-4/+5
Use vector::swap instead of copying to a local vector and clearing the original. We can just swap into the just created local vector instead which will move the pointers and not the data. Use std::move in another place to avoid a copy.
2021-01-12[llvm] Remove redundant string initialization (NFC)Kazu Hirata1-1/+1
Identified with readability-redundant-string-init.
2021-01-08[Tablegen] Use llvm::find_if (NFC)Kazu Hirata1-4/+5
2021-01-07[TableGen] Make CodeGenDAGPatterns::getSDNodeNamed take a StringRef instead ↵Craig Topper1-1/+1
of const std::string &. All callers use a string literal and the getDef method the string is passed to already takes a StringRef.
2021-01-02[TableGen] Use llvm::append_range (NFC)Kazu Hirata1-1/+1
2020-10-19[SVE] Replace TypeSize comparison operators in llvm/utils/TableGenDavid Sherwood1-7/+9
In CodeGenDAGPatterns.cpp we were relying upon TypeSize comparison operators for ordering types, when we can actually just use the known minimum size since the scalable property is already being taken into account. Also, in TypeInfer::EnforceSameSize I fixed some implicit TypeSize->uint64_t casts by changing the code to test the equality of TypeSize objects instead. In other places I have replaced calls to getSizeInBits() with getFixedSizeInBits() because we are only ever expecting integer values. Differential Revision: https://reviews.llvm.org/D88947
2020-07-22[ARM] Extra MVE select(binop) patternsDavid Green1-0/+3
This is very similar to 243970d03cace2, but handling a slightly different form of predicated operations. When starting with a pattern of the form select(p, BinOp(x, y), x), Instcombine will often transform this to BinOp(x, select(p, y, 0)), where 0 is the identity value of the binop (0 for adds/subs, 1 for muls, -1 for ands etc). This adds the patterns that transforms those back into predicated binary operations. There is also a very minor adjustment to tablegen null_frag in here, to allow it to also be recognized as a PatLeaf node, so that it can be used in MVE_TwoOpPattern to easily exclude the cases where we do not need the alternate transform. Differential Revision: https://reviews.llvm.org/D84091
2020-03-31[Alignment][NFC] Transitionning more getMachineMemOperand call sitesGuillaume Chatelet1-2/+2
Summary: This is patch is part of a series to introduce an Alignment type. See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html See this patch for the introduction of the type: https://reviews.llvm.org/D64790 Reviewers: courbet Subscribers: arsenm, dylanmckay, sdardis, nemanjai, jvesely, nhaehnle, hiraditya, kbarton, jrtc27, atanasyan, Jim, kerbowa, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D77121
2020-03-13TableGen: Fix typoMatt Arsenault1-1/+1
2020-02-19TableGen: Fix logic for default operandsMatt Arsenault1-5/+9
This was checking for default operands in the current DAG instruction, rather than the correct result operand list. I'm not entirly sure how this managed to work before, but was failing for me when multiple default operands were overridden.
2020-02-17[TableGen] Don't elide bitconverts in PatFrag fragments.Simon Tatham1-0/+7
Summary: In the DAG pattern backend, `SimplifyTree` simplifies a pattern by removing bitconverts between two identical types. But that function is also run on the fragments list in instances of `PatFrags`, in which the types haven't been specified yet. So the input and output of the bitconvert always evaluate to the empty set of types, which makes them compare equal. So the test always passes, and bitconverts are unconditionally removed from the PatFrag RHS. Fixed by spotting the empty type set and using it to inhibit the optimization. Reviewers: nhaehnle, hfinkel Reviewed By: nhaehnle Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D74627
2020-01-29Fix a couple more implicit conversions that Clang doesn't diagnose.Benjamin Kramer1-1/+2
2020-01-28Make llvm::StringRef to std::string conversions explicit.Benjamin Kramer1-6/+9
This is how it should've been and brings it more in line with std::string_view. There should be no functional change here. This is mostly mechanical from a custom clang-tidy check, with a lot of manual fixups. It uncovers a lot of minor inefficiencies. This doesn't actually modify StringRef yet, I'll do that in a follow-up.
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