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path: root/llvm/unittests/IR/VPIntrinsicTest.cpp
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2025-08-05[VP][RISCV] Add a vp.load.ff intrinsic for fault only first load. (#128593)Craig Topper1-0/+3
There's been some interest in supporting early-exit loops recently. https://discourse.llvm.org/t/rfc-supporting-more-early-exit-loops/84690 This patch was extracted from our downstream where we've been using it in our vectorizer.
2024-10-11[NFC] Rename `Intrinsic::getDeclaration` to `getOrInsertDeclaration` (#111752)Rahul Joshi1-2/+2
Rename the function to reflect its correct behavior and to be consistent with `Module::getOrInsertFunction`. This is also in preparation of adding a new `Intrinsic::getDeclaration` that will have behavior similar to `Module::getFunction` (i.e, just lookup, no creation).
2024-08-29[VP] Kill VP_PROPERTY_(MEMOP,CASTOP) and simplify _CONSTRAINEDFP [nfc] (#105574)Philip Reames1-16/+0
These lists are quite static. Heavy use of macros is undesirable, and not idiomatic in LLVM, so let's just use the naive switch cases. Note that the first two fields in the CONSTRAINEDFP property were utterly unused (aside from a C++ test). In the same vien as https://github.com/llvm/llvm-project/pull/105551. Once both changes have landed, we'll be left with _BINARYOP which needs a bit of additional untangling, and the actual opcode mappings.
2024-07-25[VP] Refactor VectorBuilder to avoid layering violation. NFC (#99276)Mel Chen1-0/+53
This patch refactors the handling of reduction to eliminate layering violations. * Introduced `getReductionIntrinsicID` in LoopUtils.h for mapping recurrence kinds to llvm.vector.reduce.* intrinsic IDs. * Updated `VectorBuilder::createSimpleTargetReduction` to accept llvm.vector.reduce.* intrinsic directly. * New function `VPIntrinsic::getForIntrinsic` for mapping intrinsic ID to the same functional VP intrinsic ID.
2024-07-17[VP][RISCV] Introduce vp.splat and RISC-V. (#98731)Yeting Kuo1-0/+2
This patch introduces a vp intrinsic for splat. It's helpful for IR-level passes to create a splat with specific vector length.
2024-06-21Revert "Intrinsic: introduce minimumnum and maximumnum (#93841)"Nikita Popov1-6/+5
As far as I can tell, this pull request was not approved, and did not go through an RFC on discourse. This reverts commit 89881480030f48f83af668175b70a9798edca2fb. This reverts commit 225d8fc8eb24fb797154c1ef6dcbe5ba033142da.
2024-06-21Intrinsic: introduce minimumnum and maximumnum (#93841)YunQiang Su1-5/+6
Currently, on different platform, the behaivor of llvm.minnum is different if one operand is sNaN: When we compare sNaN vs NUM: ARM/AArch64/PowerPC: follow the IEEE754-2008's minNUM: return qNaN. RISC-V/Hexagon follow the IEEE754-2019's minimumNumber: return NUM. X86: Returns NUM but not same with IEEE754-2019's minimumNumber as +0.0 is not always greater than -0.0. MIPS/LoongArch/Generic: return NUM. LIBCALL: returns qNaN. So, let's introduce llvm.minmumnum/llvm.maximumnum, which always follow IEEE754-2019's minimumNumber/maximumNumber. Half-fix: #93033
2024-05-10[VP][RISCV] Add vp.reduce.fmaximum/fminimum and its RISC-V codegen (#91782)Min-Yih Hsu1-1/+2
`vp.reduce.fmaximum/fminimum` are the VP version of `vector.reduce.fmaximum/fminimum`.
2024-04-30[VP] Fix unit test failures caused by #90502Min Hsu1-0/+2
Forgot to add vp.cttz.elts into the unittest. Also, I didn't specify the positions of overloaded type parameters.
2024-02-26[VP][RISCV] Introduce vp.lrint/llrint and RISC-V support. (#82627)Yeting Kuo1-0/+4
RISC-V implements vector lrint/llrint by vfcvt.x.f.v.
2024-02-23[RISCV][VP] Introduce vp saturating addition/subtraction and RISC-V support. ↵Yeting Kuo1-0/+8
(#82370) This patch also pick the MatchContext framework from DAGCombiner to an indiviual header file to make the framework be used from other files in llvm/lib/CodeGen/SelectionDAG/.
2024-01-22[VP][RISCV] Introduce llvm.vp.minimum/maximum intrinsics (#74840)Simeon K1-2/+3
Although there are predicated versions of minnum/maxnum, the ones for minimum/maximum are currently missing. This patch introduces these intrinsics and implements their lowering to RISC-V.
2023-11-05[VP][RISCV] Add llvm.experimental.vp.reverse. (#70405)Craig Topper1-0/+2
This is similar to vector.reverse, but only reverses the first EVL elements. I extracted this code from our downstream. Some of it may have come from https://repo.hca.bsc.es/gitlab/rferrer/llvm-epi/ originally.
2023-08-25[VP][RISCV] Add vp.is.fpclass and RISC-V supportLiaoChunyu1-0/+2
There is no vp.fpclass after FCLASS_VL(D151176), try to support vp.fpclass. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D152993
2023-02-23[VP] Reorder is_int_min_poison/is_zero_poison operand before mask for ↵Yeting Kuo1-3/+3
vp.abs/ctlz/cttz. The patch ensures last two operands of vp.abs/ctlz/cttz are mask and evl. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D144536
2023-01-06[VP][RISCV] Add vp.abs and RISC-V support.Yeting Kuo1-0/+2
RISC-V uses ISD::ABS lower method (abs x) -> (smax_vl x (sub_vl 0, x)) for ISD::VP_ABS. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D141033
2023-01-04[VP][RISCV] Add vp.ctlz/cttz and RISC-V support.Yeting Kuo1-0/+4
The patch also adds expandVPCTLZ and expandVPCTTZ to expand vp.ctlz/cttz nodes and the cost model of vp.ctlz/cttz. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D140370
2022-12-20[llvm] Use std::optional instead of OptionalKazu Hirata1-2/+2
This is part of an effort to migrate from llvm::Optional to std::optional: https://discourse.llvm.org/t/deprecating-llvm-optional-x-hasvalue-getvalue-getvalueor/63716
2022-12-17[llvm] llvm::Optional::value => operator*/operator->Fangrui Song1-2/+2
std::optional::value() has undesired exception checking semantics and is unavailable in some older Xcode. The call sites block std::optional migration.
2022-12-17std::optional::value => operator*/operator->Fangrui Song1-2/+2
value() has undesired exception checking semantics and calls __throw_bad_optional_access in libc++. Moreover, the API is unavailable without _LIBCPP_NO_EXCEPTIONS on older Mach-O platforms (see _LIBCPP_AVAILABILITY_BAD_OPTIONAL_ACCESS). This fixes check-llvm.
2022-12-14[VP][RISCV] Add vp.ctpop and RISC-V support.Yeting Kuo1-0/+2
The patch also adds expandVPCTPOP in TargetLowering to expand VP_CTPOP nodes. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D139920
2022-12-12[VP][RISCV] Add vp.bitreverse and RISC-V support.Yeting Kuo1-0/+2
The patch also added function expandVPBITREVERSE to expand ISD::VP_BITREVERSE nodes. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D139697
2022-12-07[VP][RISCV] Recommit "Add vp.fshl/fshr and RISC-V support."Yeting Kuo1-0/+4
This reverts commit 7883e5b061bdbbe8bee5f479ebe911db5045b7e9. The original commit was reverted that it didn't update test files after D136263 landed. The recommit fixed those. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D139509
2022-12-06Revert "[VP][RISCV] Add vp.fshl/fshr and RISC-V support."Kazu Hirata1-4/+0
This reverts commit 70de0e014013b4d97febe6704881a9a8c893d078. I'm seeing: Failed Tests (2): LLVM :: CodeGen/RISCV/rvv/fixed-vectors-fshr-fshl-vp.ll LLVM :: CodeGen/RISCV/rvv/fshr-fshl-vp.ll Also reported at: https://lab.llvm.org/buildbot/#/builders/123/builds/14531
2022-12-07[VP][RISCV] Add vp.fshl/fshr and RISC-V support.Yeting Kuo1-0/+4
The patch made VectorLegalizer expand ISD::VP_FSHL and ISD::VP_FSHR to achieve the codegen. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D138379
2022-12-04[IR] Use std::nullopt instead of None (NFC)Kazu Hirata1-2/+2
This is part of an effort to migrate from llvm::Optional to std::optional: https://discourse.llvm.org/t/deprecating-llvm-optional-x-hasvalue-getvalue-getvalueor/63716
2022-12-04Instructions: convert Optional to std::optionalKrzysztof Parzyszek1-4/+5
2022-11-16[VP][RISCV] Add vp.nearbyint and RISC-V support.Yeting Kuo1-0/+3
nearbyint has the property to execute without exception. For not modifying fflags, the patch added new machine opcode PseudoVFROUND_NOEXCEPT_V that expands vfcvt.x.f.v and vfcvt.f.x.v between a pair of frflags and fsflags. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D137685
2022-11-16[VP][RISCV] Add vp.bswap and RISC-V support.Yeting Kuo1-0/+3
The patch also added function expandVPBSWAP to expand ISD::VP_BSWAP nodes. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D137928
2022-11-01[VP][RISCV] Add vp.rint and RISC-V support.Yeting Kuo1-0/+2
FRINT uses dynamic rounding mode instead of static rounding mode. The patch rename VFCVT_X_F_VL to VFCVT_RM_X_F_VL for static rounding mode uses and added new ISDNode VFCVT_X_F_VL directly selected to PseudoVFCVT_X_F_V. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D136662
2022-10-07[VP][RISCV] Add vp.smax/smin/umax/umin intrinsicsCraig Topper1-1/+2
Differential Revision: https://reviews.llvm.org/D135418
2022-10-07[VP][RISCV] Add vp.roundtozero and its RISC-V supporteopXD1-0/+3
The scalar instruction of this is `llvm.trunc`. However the naming of ISD::VP_TRUNC is already taken by `trunc` of the LLVM IR. Naming this as `vp.ftrunc` would likely cause confusion with `vp.fptrunc`. So adding `vp.roundtozero` that will look similar to `vp.roundeven`. Reviewed By: frasercrmck Differential Revision: https://reviews.llvm.org/D135233
2022-10-01[VP][RISCV] Add vp.copysign and RISC-V support.Yeting Kuo1-2/+2
Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D134935
2022-09-27[VP][RISCV] Add vp.floor, vp.round, vp.roundeven and their RISC-V supporteopXD1-0/+7
Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D134759
2022-09-27[VP][RISCV] Add vp.ceil and RISC-V supporteopXD1-0/+2
Previous commit 8b00b24f8505 missed to add `int_ceil` anchor for the llvm.ceil.* section under LangRef.rst Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D134586
2022-09-27Revert "[VP][RISCV] Add vp.ceil and RISC-V support"eopXD1-2/+0
This reverts commit 8b00b24f8505970f54eab85aad8db5845a635850.
2022-09-27[VP][RISCV] Add vp.ceil and RISC-V supporteopXD1-0/+2
Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D134586
2022-09-27[VP][RISCV] Add vp.fmuladd.Craig Topper1-0/+2
Expanded in SelectionDAGBuilder similar to llvm.fmuladd. Reviewed By: frasercrmck, simoll Differential Revision: https://reviews.llvm.org/D134474
2022-09-27[VP][RISCV] Add vp.maxnum and vp.minnum intrinsics and RISC-V support.Yeting Kuo1-1/+2
Add vp.maxnum and vp.minnum which are vector predicted intrinsics of llvm.maxnum and llvm.minnum. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D134639
2022-09-26[VP][RISCV] Add vp.sqrt intrinsic and RISC-V support.Yeting Kuo1-0/+2
The patch modeled vp.fabs patch D132793. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D133690
2022-08-29[VP][RISCV] Add vp.fabs intrinsic and RISC-V support.Craig Topper1-0/+2
Mostly just modeled after vp.fneg except there is a "functional instruction" for fneg while fabs is always an intrinsic. Reviewed By: fakepaper56 Differential Revision: https://reviews.llvm.org/D132793
2022-07-13[llvm] Use value instead of getValue (NFC)Kazu Hirata1-4/+4
2022-07-12[llvm] Use has_value instead of hasValue (NFC)Kazu Hirata1-10/+10
2022-06-25[llvm] Don't use Optional::hasValue (NFC)Kazu Hirata1-2/+2
This patch replaces Optional::hasValue with the implicit cast to bool in conditionals only.
2022-06-25Revert "Don't use Optional::hasValue (NFC)"Kazu Hirata1-16/+16
This reverts commit aa8feeefd3ac6c78ee8f67bf033976fc7d68bc6d.
2022-06-25Don't use Optional::hasValue (NFC)Kazu Hirata1-16/+16
2022-04-01[VP] Add more cast VPintrinsic and docs.yanming1-0/+18
Add vp.fptoui, vp.uitofp, vp.fptrunc, vp.fpext, vp.trunc, vp.zext, vp.sext, vp.ptrtoint, vp.inttoptr intrinsic and docs. Reviewed By: frasercrmck, craig.topper Differential Revision: https://reviews.llvm.org/D122291
2022-03-30[VP] Add vp.icmp comparison intrinsic and docsFraser Cormack1-0/+2
This patch mostly follows up on D121292 which introduced the vp.fcmp intrinsic. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D122729
2022-03-30[VP] Add vp.fcmp comparison intrinsic and docsFraser Cormack1-2/+6
This patch adds the first support for vector-predicated comparison intrinsics, starting with vp.fcmp. It uses metadata to encode its condition code, like the llvm.experimental.constrained.fcmp intrinsic. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D121292
2022-03-22[VP] Preserve address space of pointer for strided load/store intrinsics.Craig Topper1-0/+6
This adds LLVMAnyPointerToElt to use instead of LLVMPointerToElt. This allows us to preserve the address space as part of the type overload for the intrinsic, but still require the vector element type to match the pointer type. Reviewed By: nikic Differential Revision: https://reviews.llvm.org/D122042
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