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2025-09-03Revert "[llvm-exegesis] Exclude loads/stores from aliasing instruction set" ↵Sjoerd Meijer1-2/+0
(#156735) Reverts llvm/llvm-project#156300 Need to look at the X86 test failures.
2025-09-03[llvm-exegesis] Exclude loads/stores from aliasing instruction set (#156300)Sjoerd Meijer1-0/+2
In the serial snippet generator and function that computes the aliasing instructions, we don't want to include load/store instructions to create a chain as that could make the results more unreliable. There is a hasMemoryOperands() check, but currently that looks like a X86 way for checking for loads/stores. For AArch64 and other architectures, we should check mayLoad() and mayStore().
2025-06-26[llvm] Use llvm::interleaved (NFC) (#145839)Kazu Hirata1-9/+3
Note that llvm::interleaved constructs a string with the elements from a given range with a given separator.
2025-02-28[Exegesis][RISCV] Add initial RVV support (#128767)Min-Yih Hsu1-0/+4
This patch adds initial vector extension support to RISC-V's exegesis. The strategy here is to enumerate all RVV _pseudo_ opcodes as their MC opcode counterparts are kind of useless under this circumstance. We also enumerate all possible VTYPE operands in each CodeTemplate configuration. Various of MachineFunction Passes are used for post processing the snippets, like inserting VSETVLI instructions. See https://llvm.org/devmtg/2024-10/slides/techtalk/Hsu-RVV-Exegesis.pdf for more technical details.
2025-01-16[llvm-exegesis] Begin replacing unsigned with MCRegister. NFC (#123109)Craig Topper1-2/+2
Some of this was needed to fix implicit conversions from MCRegister to unsigned when calling getReg() on MCOperand for example. The majority was done by reviewing parts of the code that dealt with registers, converting them to MCRegister and then seeing what new implicit conversions were created and fixing those. There were a few places where I used MCPhysReg instead of MCRegiser for static arrays since its uint16_t instead of unsigned.
2024-12-19[Exegesis][RISCV] Add RISCV support for llvm-exegesis (#120467)Bushev Dmitry1-3/+15
This patch also makes following amendments to core exegesis: * Added distinction between regular registers aliasing check and registers used as memory address in instruction. * Added scratch memory space pointer register. * General exegesis options were amended: * mattr - new option to pass a list of enabled target features Llvm-exegesis RISCV port is a result of team effort. Below everyone involved listed. Co-authored-by: Konstantin Vladimirov <konstantin.vladimirov@syntacore.com> Co-authored-by: Dmitrii Petrov <dmitrii.petrov@syntacore.com> Co-authored-by: Dmitry Bushev <dmitry.bushev@syntacore.com> Co-authored-by: Mark Goncharov <mark.goncharov@syntacore.com> Co-authored-by: Anastasiya Chernikova <anastasiya.chernikova@syntacore.com> Original pr: #89047 --------- Co-authored-by: Kazu Hirata <kazu@google.com>
2024-12-18Revert "[Exegesis][RISCV] Add RISCV support for llvm-exegesis (#120419)"Thurston Dang1-15/+3
This reverts commit 6993d32c77a78ac0e6eee0e4bffd714a455e776b. Reason: buildbot breakage (https://lab.llvm.org/buildbot/#/builders/51/builds/7908) CCACHE_CPP2=yes CCACHE_HASHDIR=yes /usr/bin/ccache /home/b/sanitizer-aarch64-linux/build/llvm_build0/bin/clang++ -DGTEST_HAS_RTTI=0 -DLLVM_BUILD_STATIC -D_DEBUG -D_GLIBCXX_ASSERTIONS -D_GNU_SOURCE -D__STDC_CONSTANT_MACROS -D__STDC_FORMAT_MACROS -D__STDC_LIMIT_MACROS -I/home/b/sanitizer-aarch64-linux/build/build_default/tools/llvm-exegesis/lib/RISCV -I/home/b/sanitizer-aarch64-linux/build/llvm-project/llvm/tools/llvm-exegesis/lib/RISCV -I/home/b/sanitizer-aarch64-linux/build/build_default/include -I/home/b/sanitizer-aarch64-linux/build/llvm-project/llvm/include -I/home/b/sanitizer-aarch64-linux/build/llvm-project/llvm/lib/Target/RISCV -I/home/b/sanitizer-aarch64-linux/build/build_default/lib/Target/RISCV -fPIC -fno-semantic-interposition -fvisibility-inlines-hidden -Werror -Werror=date-time -Werror=unguarded-availability-new -Wall -Wextra -Wno-unused-parameter -Wwrite-strings -Wcast-qual -Wmissing-field-initializers -pedantic -Wno-long-long -Wc++98-compat-extra-semi -Wimplicit-fallthrough -Wcovered-switch-default -Wno-noexcept-type -Wnon-virtual-dtor -Wdelete-non-virtual-dtor -Wsuggest-override -Wstring-conversion -Wmisleading-indentation -Wctad-maybe-unsupported -fdiagnostics-color -ffunction-sections -fdata-sections -O3 -DNDEBUG -std=c++17 -fno-exceptions -funwind-tables -fno-rtti -UNDEBUG -MD -MT tools/llvm-exegesis/lib/RISCV/CMakeFiles/LLVMExegesisRISCV.dir/Target.cpp.o -MF tools/llvm-exegesis/lib/RISCV/CMakeFiles/LLVMExegesisRISCV.dir/Target.cpp.o.d -o tools/llvm-exegesis/lib/RISCV/CMakeFiles/LLVMExegesisRISCV.dir/Target.cpp.o -c /home/b/sanitizer-aarch64-linux/build/llvm-project/llvm/tools/llvm-exegesis/lib/RISCV/Target.cpp In file included from /home/b/sanitizer-aarch64-linux/build/llvm-project/llvm/tools/llvm-exegesis/lib/RISCV/Target.cpp:139: /home/b/sanitizer-aarch64-linux/build/build_default/lib/Target/RISCV/RISCVGenAsmMatcher.inc:239:19: error: unused function 'MatchRegisterName' [-Werror,-Wunused-function] 239 | static MCRegister MatchRegisterName(StringRef Name) { | ^~~~~~~~~~~~~~~~~ /home/b/sanitizer-aarch64-linux/build/build_default/lib/Target/RISCV/RISCVGenAsmMatcher.inc:568:19: error: unused function 'MatchRegisterAltName' [-Werror,-Wunused-function] 568 | static MCRegister MatchRegisterAltName(StringRef Name) { | ^~~~~~~~~~~~~~~~~~~~
2024-12-18[Exegesis][RISCV] Add RISCV support for llvm-exegesis (#120419)Bushev Dmitry1-3/+15
This patch also makes following amendments to core exegesis: * Added distinction between regular registers aliasing check and registers used as memory address in instruction. * Added scratch memory space pointer register. * General exegesis options were amended: * mattr - new option to pass a list of enabled target features Llvm-exegesis RISCV port is a result of team effort. Below everyone involved listed. Co-authored-by: Konstantin Vladimirov <konstantin.vladimirov@syntacore.com> Co-authored-by: Dmitrii Petrov <dmitrii.petrov@syntacore.com> Co-authored-by: Dmitry Bushev <dmitry.bushev@syntacore.com> Co-authored-by: Mark Goncharov <mark.goncharov@syntacore.com> Co-authored-by: Anastasiya Chernikova <anastasiya.chernikova@syntacore.com> --------- Co-authored-by: Anastasiya Chernikova <anastasiya.chernikova@syntacore.com>
2024-12-18Revert "[Exegesis][RISCV] Add RISCV support for llvm-exegesis (#89047)"Wang Pengcheng1-15/+3
This reverts commit bc3eee11ea6f771bf007c4921a34c1dfee040471. These tests are failing because of no `REQUIRES`.
2024-12-18[Exegesis][RISCV] Add RISCV support for llvm-exegesis (#89047)AnastasiyaChernikova1-3/+15
This patch also makes following amendments to core exegesis: * Added distinction between regular registers aliasing check and registers used as memory address in instruction. * Added scratch memory space pointer register. * General exegesis options were amended: * mattr - new option to pass a list of enabled target features Llvm-exegesis RISCV port is a result of team effort. Below everyone involved listed. Co-authored-by: Konstantin Vladimirov <konstantin.vladimirov@syntacore.com> Co-authored-by: Dmitrii Petrov <dmitrii.petrov@syntacore.com> Co-authored-by: Dmitry Bushev <dmitry.bushev@syntacore.com> Co-authored-by: Mark Goncharov <mark.goncharov@syntacore.com> Co-authored-by: Anastasiya Chernikova <anastasiya.chernikova@syntacore.com> --------- Co-authored-by: Dmitry Bushev <dmitry.bushev@syntacore.com>
2024-01-29[llvm-exegesis] Remove llvm prefix where unnecessary (#79802)Aiden Grossman1-1/+1
This patch removes the llvm:: prefix within llvm-exegesis where it is not necessary. This is most occurrences of the prefix within exegesis as exegesis is within the llvm namespace. This patch makes things more consistent as the vast majority of the code did not use the llvm:: prefix for anything.
2023-12-03[llvm] Stop including map (NFC)Kazu Hirata1-1/+0
Identified with clangd.
2023-01-23[MC] Define and use MCInstrDesc implicit_uses and implicit_defs. NFC.Jay Foad1-9/+7
The new methods return a range for easier iteration. Use them everywhere instead of getImplicitUses, getNumImplicitUses, getImplicitDefs and getNumImplicitDefs. A future patch will remove the old methods. In some use cases the new methods are less efficient because they always have to scan the whole uses/defs array to count its length, but that will be fixed in a future patch by storing the number of implicit uses/defs explicitly in MCInstrDesc. At that point there will be no need to 0-terminate the arrays. Differential Revision: https://reviews.llvm.org/D142215
2023-01-23[MC] Make more use of MCInstrDesc::operands. NFC.Jay Foad1-1/+1
Change MCInstrDesc::operands to return an ArrayRef so we can easily use it everywhere instead of the (IMHO ugly) opInfo_begin and opInfo_end. A future patch will remove opInfo_begin and opInfo_end. Also use it instead of raw access to the OpInfo pointer. A future patch will remove this pointer. Differential Revision: https://reviews.llvm.org/D142213
2022-12-21[llvm-exegesis] `AliasingConfigurations`: pay attention to forbidden registersRoman Lebedev1-4/+6
When trying to measure latency of certain opcodes, e.g. `./bin/llvm-exegesis --opcode-name=BT32ri8 --mode=latency --repetition-mode=loop --benchmarks-file=- --max-configs-per-opcode=65536`, we'd pick such an aliasing instruction, and such an aliasing registers, that would alias with forbidden registers. And in particular with loop counter in `loop` repetition mode, which made the measurements never finish. This does not address all such cases, only the most obvious one. The added test case fails without the patch. Fixes https://github.com/llvm/llvm-project/issues/59441
2022-06-26[llvm] Use Optional::has_value instead of Optional::hasValue (NFC)Kazu Hirata1-2/+2
This patch replaces x.hasValue() with x.has_value() where x is not contextually convertible to bool.
2022-06-25Revert "Don't use Optional::hasValue (NFC)"Kazu Hirata1-2/+2
This reverts commit aa8feeefd3ac6c78ee8f67bf033976fc7d68bc6d.
2022-06-25Don't use Optional::hasValue (NFC)Kazu Hirata1-2/+2
2021-02-04[WebAssembly] Support single-floating-point immediate valueDan Gohman1-2/+4
As mentioned in TODO comment, casting double to float causes NaNs to change bits. To avoid the change, this patch adds support for single-floating-point immediate value on MachineCode. Patch by Yuta Saito. Differential Revision: https://reviews.llvm.org/D77384
2020-02-04Fix "expression is redundant [misc-redundant-expression]" warning (PR44768)Simon Pilgrim1-2/+4
Be more specific that getOperandConstraint should return -1 or a uint8_t value
2020-01-13[llvm-exegesis] Initialize const bitvector memberJonas Devlieghere1-1/+1
This causes an error with older versions of clang: constructor for 'llvm::exegesis::InstructionsCache' must explicitly initialize the const member 'BVC'
2019-12-18[llvm-exegesis][NFC] internal changesGuillaume Chatelet1-33/+55
Summary: BitVectors are now cached to lower memory utilization. Instructions have reference semantics. Reviewers: courbet Subscribers: sdardis, tschuett, jrtc27, atanasyan, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D71653
2019-10-09[llvm-exegesis][NFC] Remove extra `llvm::` qualifications.Clement Courbet1-24/+25
Summary: Second patch: in the lib. Reviewers: gchatelet Subscribers: nemanjai, tschuett, MaskRay, mgrang, jsji, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D68692 llvm-svn: 374158
2019-09-27[llvm-exegesis] Refactor how forbidden registers are computed.Clement Courbet1-6/+28
Summary: Right now latency generation can incorrectly select the scratch register as a dependency-carrying register. - Move the logic for preventing register selection from Uops implementation to common SnippetGenerator class. - Aliasing detection now takes a set of forbidden registers just like random register assignment does. Reviewers: gchatelet Subscribers: tschuett, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D68084 llvm-svn: 373048
2019-09-26[llvm-exegesis][NFC] Remove dead code.Clement Courbet1-6/+0
Summary: `hasAliasingImplicitRegistersThrough()` is no longer used. Reviewers: gchatelet Subscribers: tschuett, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D68078 llvm-svn: 372968
2019-01-19Update the file headers across all of the LLVM projects in the monorepoChandler Carruth1-4/+3
to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
2018-10-24[llvm-exegesis] Implements a cache of Instruction objects.Guillaume Chatelet1-4/+15
llvm-svn: 345130
2018-10-22[llvm-exegesis] Move namespace exegesis inside llvm::Fangrui Song1-0/+2
Summary: This allows simplifying references of llvm::foo with foo when the needs come in the future. Reviewers: courbet, gchatelet Reviewed By: gchatelet Subscribers: javed.absar, tschuett, llvm-commits Differential Revision: https://reviews.llvm.org/D53455 llvm-svn: 344922
2018-10-19Use llvm::{all,any,none}_of instead std::{all,any,none}_of. NFCFangrui Song1-1/+1
llvm-svn: 344774
2018-10-17[llvm-exegeis] Computing Latency configuration upfront so we can generate ↵Guillaume Chatelet1-3/+13
many CodeTemplates at once. Summary: LatencyGenerator now computes all possible mode of serial execution for an Instruction upfront and generates CodeTemplate for the ones that give the best results (e.g. no need to generate a two instructions snippet when repeating a single one would do). The next step is to generate even more configurations for cases (e.g. for XOR we should generate "XOR EAX, EAX, EAX" and "XOR EAX, EAX, EBX") Reviewers: courbet Reviewed By: courbet Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53320 llvm-svn: 344689
2018-10-10[llvm-exegesis][NFC] Pass Instruction instead of bare OpcodeGuillaume Chatelet1-4/+11
llvm-svn: 344145
2018-10-10[llvm-exegesis][NFC] Code simplificationGuillaume Chatelet1-9/+9
Summary: Simplify code by having LLVMState hold the RegisterAliasingTrackerCache. Reviewers: courbet Subscribers: tschuett, llvm-commits Differential Revision: https://reviews.llvm.org/D53078 llvm-svn: 344143
2018-10-10[llvm-exegesis] Remove unused variable, add more semantic to Instruction.Guillaume Chatelet1-1/+15
Reviewers: courbet Subscribers: tschuett, llvm-commits Differential Revision: https://reviews.llvm.org/D53062 llvm-svn: 344127
2018-10-09Fix function case.Guillaume Chatelet1-1/+1
llvm-svn: 344051
2018-10-09[llvm-exegesis] Fix invalid return type and add a Dump function.Guillaume Chatelet1-5/+55
Reviewers: courbet Subscribers: tschuett, llvm-commits Differential Revision: https://reviews.llvm.org/D53020 llvm-svn: 344050
2018-10-09[llvm-exegesis] Fix wrong index type.Guillaume Chatelet1-1/+2
llvm-svn: 344032
2018-10-09[llvm-exegesis] Fix unused lambda capture.Guillaume Chatelet1-1/+1
llvm-svn: 344029
2018-10-09[llvm-exegesis][NFC] Use accessors for Operand.Guillaume Chatelet1-22/+111
Summary: This moves checking logic into the accessors and makes the structure smaller. It will also help when/if Operand are generated from the TD files. Subscribers: tschuett, courbet, llvm-commits Differential Revision: https://reviews.llvm.org/D52982 llvm-svn: 344028
2018-09-27[llvm-exegesis][NFC] moving code around.Guillaume Chatelet1-146/+0
Summary: Renaming InstructionBuilder into InstructionTemplate and moving code generation tools from MCInstrDescView to CodeTemplate. Reviewers: courbet Subscribers: tschuett, llvm-commits Differential Revision: https://reviews.llvm.org/D52592 llvm-svn: 343188
2018-09-26[llvm-exegesis][NFC] Move CodeTemplate to it's own file.Guillaume Chatelet1-4/+0
Summary: This is is preparation of exploring value ranges. Reviewers: courbet Reviewed By: courbet Subscribers: mgorny, tschuett, llvm-commits Differential Revision: https://reviews.llvm.org/D52542 llvm-svn: 343098
2018-08-03[llvm-exegesis] Renaming classes and functions.Guillaume Chatelet1-2/+2
Summary: Functional No Op. Reviewers: gchatelet Subscribers: tschuett, courbet, llvm-commits Differential Revision: https://reviews.llvm.org/D50231 llvm-svn: 338836
2018-08-02[llvm-exegesis] Rename InstructionInstance into InstructionBuilder.Guillaume Chatelet1-20/+20
Summary: Non functional change. Subscribers: tschuett, courbet, llvm-commits Differential Revision: https://reviews.llvm.org/D50176 llvm-svn: 338701
2018-08-01[llvm-exegesis] Provide a way to handle memory instructions.Guillaume Chatelet1-6/+23
Summary: And implement memory instructions on X86. This fixes PR36906. Reviewers: gchatelet Reviewed By: gchatelet Subscribers: lebedev.ri, filcab, mgorny, tschuett, RKSimon, llvm-commits Differential Revision: https://reviews.llvm.org/D48935 llvm-svn: 338567
2018-06-25[llvm-exegesis] Generate snippet setup code.Clement Courbet1-1/+15
Summary: This ensures that the snippet always sees the same values for registers, making measurements reproducible. This will also allow exploring different values. Reviewers: gchatelet Subscribers: tschuett, llvm-commits Differential Revision: https://reviews.llvm.org/D48542 llvm-svn: 335465
2018-06-25[llvm-exegesis][NFC] clang-formatClement Courbet1-4/+2
llvm-svn: 335452
2018-06-20[llvm-exegesis] Remove noexcept in r335105.Clement Courbet1-3/+4
gcc checks for transitivity (https://gcc.gnu.org/bugzilla/show_bug.cgi?id=53903) llvm-svn: 335109
2018-06-20[llvm-exegesis] Use a Prototype to defer picking a value for free vars.Guillaume Chatelet1-8/+33
Summary: Introducing a Prototype object to capture Variables that must be set but keeps degrees of freedom as Invalid. This allows exploring non constraint variables later on. Reviewers: courbet Subscribers: tschuett, llvm-commits Differential Revision: https://reviews.llvm.org/D48316 llvm-svn: 335105
2018-06-13[llvm-exegesis] Fix failing assert when creating Snippet for LAHF.Guillaume Chatelet1-6/+10
Reviewers: courbet Subscribers: tschuett, llvm-commits Differential Revision: https://reviews.llvm.org/D48123 llvm-svn: 334599
2018-06-13[llvm-exegesis] Cleaner design without mutable data.Guillaume Chatelet1-64/+61
Summary: Previous design was relying on the 'mutate' keyword and was quite confusing. This version separate mutable from immutable data and makes it clearer what changes and what doesn't. Reviewers: courbet Subscribers: tschuett, llvm-commits Differential Revision: https://reviews.llvm.org/D48020 llvm-svn: 334596
2018-05-17reland r332579: [llvm-exegesis] Update to cover latency through another opcode.Clement Courbet1-0/+268
Restructuring the code to measure latency and uops. The end goal is to have this program spawn another process to deal with SIGILL and other malformed programs. It is not yet the case in this redesign, it is still the main program that runs the code (and may crash). It now uses BitVector instead of Graph for performance reasons. https://reviews.llvm.org/D46821 (with fixed ARM tests) Authored by Guillaume Chatelet llvm-svn: 332592
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