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path: root/llvm/lib/Target/R600/R600MachineScheduler.cpp
AgeCommit message (Expand)AuthorFilesLines
2014-09-17Fix float division-by-zero in R600 scheduler.Alexey Samsonov1-14/+18
2014-08-04R600: Remove unused includeMatt Arsenault1-1/+0
2014-06-13R600: Move AMDGPUInstrInfo from AMDGPUTargetMachine into AMDGPUSubtargetTom Stellard1-0/+1
2014-04-25[C++] Use 'nullptr'. Target edition.Craig Topper1-5/+5
2014-04-22[Modules] Fix potential ODR violations by sinking the DEBUG_TYPEChandler Carruth1-2/+2
2013-12-28Factor MI-Sched in preparation for post-ra scheduling support.Andrew Trick1-4/+3
2013-11-15R600: Fix scheduling of instructions that use the LDS output queueTom Stellard1-32/+0
2013-09-12R600: Don't use trans slot for instructions that read LDS source registersTom Stellard1-0/+4
2013-09-04R600: Non vector only instruction can be scheduled on trans unitVincent Lejeune1-12/+21
2013-07-31Revert "R600: Non vector only instruction can be scheduled on trans unit"Tom Stellard1-21/+12
2013-07-31R600: Non vector only instruction can be scheduled on trans unitVincent Lejeune1-12/+21
2013-06-29R600: Support schedule and packetization of trans-only instVincent Lejeune1-7/+18
2013-06-28R600: Add local memory support via LDSTom Stellard1-2/+10
2013-06-28R600: Add support for GROUP_BARRIER instructionTom Stellard1-1/+5
2013-06-07R600: Use a refined heuristic to choose when switching clauseVincent Lejeune1-9/+43
2013-06-07R600: Rework subtarget info and remove AMDILDevice classesTom Stellard1-0/+1
2013-06-06R600: Remove leftover code in R600MachineScheduler.cppVincent Lejeune1-16/+0
2013-06-05R600: Schedule copy from phys register at beginning of blockVincent Lejeune1-1/+31
2013-06-05R600: Make sure to schedule AR register uses and defs in the same clauseTom Stellard1-2/+34
2013-05-23Move passes from namespace llvm into anonymous namespaces. Sort includes whil...Benjamin Kramer1-1/+1
2013-05-17R600: Use bottom up scheduling algorithmVincent Lejeune1-23/+28
2013-05-17R600: Use depth first scheduling algorithmVincent Lejeune1-52/+26
2013-05-17R600: Replace big texture opcode switch in scheduler by usesTC/usesVCVincent Lejeune1-23/+3
2013-05-17R600: Relax some vector constraints on Dot4.Vincent Lejeune1-2/+2
2013-05-17R600: Factorize Fetch size limit inside AMDGPUSubTargetVincent Lejeune1-8/+4
2013-04-03R600: Factorize maximum alu per clause in a single locationVincent Lejeune1-1/+1
2013-03-14R600: Factorize code handling Const Read Port limitationVincent Lejeune1-68/+7
2013-03-11R600MachineScheduler.cpp: Fix use cases of dbgs(). Don't include <iostream> h...NAKAMURA Takumi1-1/+2
2013-03-05R600: initial scheduler codeVincent Lejeune1-0/+487
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