aboutsummaryrefslogtreecommitdiff
path: root/llvm/lib/Target/R600/AMDGPUInstrInfo.cpp
AgeCommit message (Expand)AuthorFilesLines
2014-12-07R600/SI: Add VI instructionsMarek Olsak1-1/+1
2014-10-07R600: Remove dead codeMatt Arsenault1-16/+1
2014-08-06R600: Increase nearby load scheduling threshold.Matt Arsenault1-9/+20
2014-08-04Remove the TargetMachine forwards for TargetSubtargetInfo basedEric Christopher1-1/+4
2014-07-29Remove line with no effectMatt Arsenault1-1/+0
2014-07-24R600: Implement enableClusterLoads()Matt Arsenault1-0/+4
2014-06-13R600: Remove AMDIL instruction and register definitionsTom Stellard1-22/+0
2014-06-13R600: Move AMDGPUInstrInfo from AMDGPUTargetMachine into AMDGPUSubtargetTom Stellard1-2/+2
2014-06-13R600: Drop use of cached TargetMachine in AMDGPUInstrInfo.cppTom Stellard1-1/+1
2014-05-16R600/SI: Refactor the VOP3_32 tablegen classTom Stellard1-0/+11
2014-04-25[C++] Use 'nullptr'. Target edition.Craig Topper1-3/+3
2014-04-22[cleanup] Lift using directives, DEBUG_TYPE definitions, and even someChandler Carruth1-3/+2
2014-03-11Fix indentationMatt Arsenault1-9/+8
2013-12-10Use llvm_unreachable instead of assert(0)Matt Arsenault1-2/+2
2013-11-19[weak vtables] Remove a bunch of weak vtablesJuergen Ributzka1-1/+5
2013-11-18Revert r194865 and r194874.Alexey Samsonov1-5/+1
2013-11-15[weak vtables] Remove a bunch of weak vtablesJuergen Ributzka1-1/+5
2013-11-13R600/SI: Add support for private address space load/storeTom Stellard1-12/+75
2013-10-29Removing a switch statement that contains only a default label. This resolve...Aaron Ballman1-28/+25
2013-10-22R600: Simplify handling of private address spaceTom Stellard1-0/+40
2013-10-10R600/SI: Define a separate MIMG instruction for each possible output value typeTom Stellard1-0/+9
2013-10-01R600: Enable -verify-machineinstrs in some tests.Vincent Lejeune1-1/+1
2013-06-25R600: Use new getNamedOperandIdx function generated by TableGenTom Stellard1-0/+1
2013-06-07R600: Rework subtarget info and remove AMDILDevice classesTom Stellard1-1/+0
2013-06-07Don't cache the instruction and register info from the TargetMachine, becauseBill Wendling1-1/+1
2013-05-23R600: Hide symbols of implementation details.Benjamin Kramer1-21/+0
2013-02-26R600/SI: add VOP mapping functionsChristian Konig1-0/+1
2013-02-06R600: Support for indirect addressing v4Tom Stellard1-1/+10
2012-12-11Add R600 backendTom Stellard1-0/+257