aboutsummaryrefslogtreecommitdiff
path: root/llvm/lib/Target/R600/AMDGPUISelLowering.cpp
AgeCommit message (Expand)AuthorFilesLines
2015-01-08[SelectionDAG] Allow targets to specify legality of extloads' resultAhmed Bougacha1-13/+16
2015-01-06R600/SI: Add class intrinsicMatt Arsenault1-0/+5
2014-12-19R600: Remove outdated commentMatt Arsenault1-4/+0
2014-12-19R600/SI: Only form min/max with 1 use.Matt Arsenault1-1/+1
2014-12-12R600: Fix min/max matching problems with unordered comparesMatt Arsenault1-42/+43
2014-12-12Add target hook for whether it is profitable to reduce load widthsMatt Arsenault1-0/+23
2014-12-07R600/SI: Update instruction conversions for VIMarek Olsak1-1/+19
2014-11-26R600/SI: Use ZeroOrNegativeOneBooleanContentMatt Arsenault1-0/+3
2014-11-23R600: Fix assert on copy of an i1 on pre-SIMatt Arsenault1-1/+2
2014-11-15R600: Permute operands when selecting legacy min/maxMatt Arsenault1-6/+9
2014-11-15R600: Fix 64-bit integer divisionTom Stellard1-2/+2
2014-11-15R600: Factor i64 UDIVREM lowering into its own fuctionTom Stellard1-0/+81
2014-11-14R600/SI: Combine min3/max3 instructionsMatt Arsenault1-0/+6
2014-11-14R600/SI: Match integer min / max instructionsMatt Arsenault1-21/+69
2014-11-13R600/SI: Fix fmin_legacy / fmax_legacy matching for SIMatt Arsenault1-19/+50
2014-11-13We can get the TLOF from the TargetMachine - so constructor no longer require...Aditya Nandakumar1-1/+1
2014-11-13R600: Error on initializer for LDS.Matt Arsenault1-2/+21
2014-11-13This patch changes the ownership of TLOF from TargetLoweringBase to TargetMac...Aditya Nandakumar1-1/+1
2014-10-21Add minnum / maxnum codegenMatt Arsenault1-0/+2
2014-10-21R600/SI: Add missing parameter to div_fmas intrinsicMatt Arsenault1-0/+2
2014-10-16R600: Fix nonsensical implementation of computeKnownBits for BFEMatt Arsenault1-5/+1
2014-10-16R600: Remove dead functionMatt Arsenault1-12/+0
2014-10-15R600: Remove unnecessary part of computeKnownBitsForTargetNodeMatt Arsenault1-5/+0
2014-10-15Move variable down to useMatt Arsenault1-4/+4
2014-10-15R600: Fix miscompiles when BFE has multiple usesMatt Arsenault1-7/+10
2014-10-15R600: Use existing variableMatt Arsenault1-1/+1
2014-10-15R600: Remove outdated commentMatt Arsenault1-3/+0
2014-10-03R600/SI: Custom lower f64 -> i64 conversionsMatt Arsenault1-0/+53
2014-10-03R600: Custom lower [s|u]int_to_fp for i64 -> f64Matt Arsenault1-2/+43
2014-10-03R600/SI: Fix ftrunc f64 conformance failures.Matt Arsenault1-1/+1
2014-09-26R600/SI: Add a note about the order of the operands to div_scaleMatt Arsenault1-0/+6
2014-09-22R600: Don't set BypassSlowDiv for 64-bit divisionTom Stellard1-3/+0
2014-09-22R600/SI: Use ISD::MUL instead of ISD::UMULO when lowering divisionTom Stellard1-3/+3
2014-09-19R600: Better fix for bug 20982Matt Arsenault1-6/+3
2014-09-18R600: Bug 20982 - Avoid undefined left shift of negative valueMatt Arsenault1-3/+10
2014-09-10R600: Custom lower fremMatt Arsenault1-0/+19
2014-08-29R600/SI: Use mad for fsub + fmulMatt Arsenault1-0/+1
2014-08-21name change: isPow2DivCheap -> isPow2SDivCheapSanjay Patel1-1/+1
2014-08-15R600/SI: Use source modifiers for f64 fnegMatt Arsenault1-1/+1
2014-08-15R600/SI: Use source modifier for f64 fabsMatt Arsenault1-1/+1
2014-08-15R600/SI: Add intrinsic for ldexpMatt Arsenault1-0/+5
2014-08-12R600: Use optimized 24bit path in udivremJan Vesely1-17/+38
2014-08-12R600: Remove unused code.Jan Vesely1-168/+0
2014-08-12R600: Use i24 optimized path for SREMJan Vesely1-7/+27
2014-08-09R600: Disable FP exceptions.Matt Arsenault1-0/+5
2014-08-05R600/SI: Avoid generating REGISTER_LOAD instructions.Tom Stellard1-1/+2
2014-08-04Remove the TargetMachine forwards for TargetSubtargetInfo basedEric Christopher1-4/+4
2014-08-04Use the known address space constant rather than checking itMatt Arsenault1-1/+1
2014-08-01Revert "R600: Move code for generating REGISTER_LOAD into R600ISelLowering.cpp"Tom Stellard1-1/+37
2014-08-01R600: Move code for generating REGISTER_LOAD into R600ISelLowering.cppTom Stellard1-37/+1
generated by cgit v1.1 at 2025-10-17 17:48:46 +0000