| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2016-08-19 | [Hexagon] Improvements to handling and generation of FP instructions | Krzysztof Parzyszek | 1 | -0/+1 |
| 2016-08-16 | [Hexagon] Standardize next batch of pseudo instructions | Krzysztof Parzyszek | 1 | -2/+2 |
| 2016-06-12 | Run clang-tidy's performance-unnecessary-copy-initialization over LLVM. | Benjamin Kramer | 1 | -1/+1 |
| 2016-05-16 | [Hexagon] Make getCallerSavedRegs specific to a register class | Krzysztof Parzyszek | 1 | -14/+42 |
| 2016-04-18 | [NFC] Header cleanup | Mehdi Amini | 1 | -1/+0 |
| 2016-03-21 | [Hexagon] Fix reserving emergency spill slots for register scavenger | Krzysztof Parzyszek | 1 | -2/+0 |
| 2016-02-18 | [Hexagon] Implement TLS support | Krzysztof Parzyszek | 1 | -0/+1 |
| 2016-02-18 | [Hexagon] Update the callee-saved register set for EH-aware functions | Krzysztof Parzyszek | 1 | -3/+15 |
| 2016-02-12 | [Hexagon] Eliminate pseudo instructions for circ/brev loads and stores | Krzysztof Parzyszek | 1 | -1/+4 |
| 2016-02-12 | [Hexagon] Handle out-of-range offsets in eliminateFrameIndex | Krzysztof Parzyszek | 1 | -12/+15 |
| 2016-01-11 | [Hexagon] Mark D14 and GP as reserved registers | Krzysztof Parzyszek | 1 | -0/+2 |
| 2015-12-18 | [Hexagon] Add PIC support | Krzysztof Parzyszek | 1 | -1/+1 |
| 2015-10-19 | [Hexagon] Fix debug information for local objects | Krzysztof Parzyszek | 1 | -68/+13 |
| 2015-10-17 | [Hexagon] Adding skeleton of HVX extension instructions. | Colin LeMahieu | 1 | -0/+4 |
| 2015-07-20 | Targets: commonize some stack realignment code | JF Bastien | 1 | -7/+0 |
| 2015-07-10 | Target RegisterInfo: devirtualize TargetFrameLowering | JF Bastien | 1 | -2/+3 |
| 2015-04-22 | [Hexagon] Overhaul of stack object allocation | Krzysztof Parzyszek | 1 | -129/+142 |
| 2015-03-12 | Remove unused complex patterns for addressing modes on Hexagon. | Krzysztof Parzyszek | 1 | -1/+3 |
| 2015-03-10 | Remove subtarget dependence from HexagonRegisterInfo. | Eric Christopher | 1 | -7/+4 |
| 2015-02-09 | [Hexagon] Removing more V4 predicates since V4 is the required minimum. | Colin LeMahieu | 1 | -50/+5 |
| 2015-02-05 | [Hexagon] Renaming A2_addi and formatting. | Colin LeMahieu | 1 | -6/+6 |
| 2015-01-15 | [Hexagon] Replacing old versions of stores and loads. | Colin LeMahieu | 1 | -5/+2 |
| 2015-01-14 | [Hexagon] Replacing old version of convert and load f64. | Colin LeMahieu | 1 | -2/+1 |
| 2014-12-29 | [Hexagon] Adding post-increment register form stores and register-immediate f... | Colin LeMahieu | 1 | -5/+4 |
| 2014-12-23 | [Hexagon] Adding doubleword load. | Colin LeMahieu | 1 | -2/+2 |
| 2014-12-23 | [Hexagon] Reapplying 224775 load words. | Colin LeMahieu | 1 | -1/+1 |
| 2014-12-23 | Reverting 224775 until mayLoad flag is addressed. | Colin LeMahieu | 1 | -1/+1 |
| 2014-12-23 | [Hexagon] Adding word loads. | Colin LeMahieu | 1 | -1/+1 |
| 2014-12-23 | [Hexagon] Adding signed halfword loads. | Colin LeMahieu | 1 | -1/+1 |
| 2014-12-23 | [Hexagon] Adding unsigned halfword load. | Colin LeMahieu | 1 | -1/+1 |
| 2014-12-22 | [Hexagon] Adding memb instruction. Fixing whitespace in test from 224730. | Colin LeMahieu | 1 | -1/+1 |
| 2014-12-22 | [Hexagon] Adding classes and load unsigned byte instruction, updating usages. | Colin LeMahieu | 1 | -1/+1 |
| 2014-11-18 | [Hexagon] Converting from ADD_rr to A2_add which has encoding bits. | Colin LeMahieu | 1 | -4/+4 |
| 2014-08-05 | Have MachineFunction cache a pointer to the subtarget to make lookups | Eric Christopher | 1 | -6/+3 |
| 2014-08-04 | Remove the TargetMachine forwards for TargetSubtargetInfo based | Eric Christopher | 1 | -3/+6 |
| 2014-04-04 | Make consistent use of MCPhysReg instead of uint16_t throughout the tree. | Craig Topper | 1 | -5/+4 |
| 2014-01-07 | Re-sort all of the includes with ./utils/sort_includes.py so that | Chandler Carruth | 1 | -5/+5 |
| 2013-10-07 | Remove getEHExceptionRegister and getEHHandlerRegister. | Rafael Espindola | 1 | -8/+0 |
| 2013-06-07 | Don't cache the instruction and register info from the TargetMachine, because | Bill Wendling | 1 | -4/+4 |
| 2013-05-10 | Remove unused function. | Rafael Espindola | 1 | -10/+0 |
| 2013-03-22 | Hexagon: Add and enable memops setbit, clrbit, &,|,+,- for byte, short, and w... | Jyotsna Verma | 1 | -26/+40 |
| 2013-02-22 | Remove code copied from GenRegisterInfo.inc. | Andrew Trick | 1 | -52/+0 |
| 2013-02-21 | Move the eliminateCallFramePseudoInstr method from TargetRegisterInfo | Eli Bendersky | 1 | -15/+0 |
| 2013-01-31 | [PEI] Pass the frame index operand number to the eliminateFrameIndex function. | Chad Rosier | 1 | -27/+23 |
| 2013-01-02 | Move all of the header files which are involved in modelling the LLVM IR | Chandler Carruth | 1 | -2/+2 |
| 2012-12-03 | Use the new script to sort the includes of every file under lib. | Chandler Carruth | 1 | -7/+7 |
| 2012-09-04 | Porting Hexagon MI Scheduler to the new API. | Sergei Larin | 1 | -0/+52 |
| 2012-05-30 | Fix some uses of getSubRegisters() to use getSubReg() instead. | Jakob Stoklund Olesen | 1 | -1/+1 |
| 2012-05-10 | Hexagon V5 FP Support. | Sirish Pande | 1 | -7/+14 |
| 2012-04-23 | Revert r155365, r155366, and r155367. All three of these have regression | Chandler Carruth | 1 | -14/+7 |
