| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2016-08-25 | MachineFunctionProperties/MIRParser: Rename AllVRegsAllocated->NoVRegs, compu... | Matthias Braun | 1 | -1/+1 |
| 2016-07-12 | Hexagon: Avoid implicit iterator conversions, NFC | Duncan P. N. Exon Smith | 1 | -6/+6 |
| 2016-04-26 | Add optimization bisect opt-in calls for Hexagon passes | Andrew Kaylor | 1 | -0/+2 |
| 2016-04-04 | Add MachineFunctionProperty checks for AllVRegsAllocated for target passes | Derek Schuff | 1 | -1/+4 |
| 2016-02-27 | WIP: CodeGen: Use MachineInstr& in MachineInstrBundle.h, NFC | Duncan P. N. Exon Smith | 1 | -1/+1 |
| 2015-12-05 | Replace uint16_t with the MCPhysReg typedef in many places. A lot of physical... | Craig Topper | 1 | -2/+2 |
| 2015-07-20 | [Hexagon] Generate MUX from conditional transfers when dot-new not possible | Krzysztof Parzyszek | 1 | -0/+319 |
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index : riscv-gnu-toolchain/llvm.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
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