| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2015-03-12 | Remove the need to cache the subtarget in the ARM TargetRegisterInfo | Eric Christopher | 1 | -1/+1 |
| 2014-08-13 | Canonicalize header guards into a common format. | Benjamin Kramer | 1 | -2/+2 |
| 2014-03-22 | Prune includes in ARM target. | Craig Topper | 1 | -2/+0 |
| 2013-06-07 | Don't cache the instruction and register info from the TargetMachine, because | Bill Wendling | 1 | -3/+3 |
| 2012-03-17 | Reorder includes to match coding standards. Fix an issue or two exposed by that. | Craig Topper | 1 | -2/+1 |
| 2012-02-18 | Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430,... | Jia Liu | 1 | -1/+1 |
| 2011-12-20 | Unweaken vtables as per http://llvm.org/docs/CodingStandards.html#ll_virtual_... | David Blaikie | 1 | -0/+1 |
| 2010-05-24 | Switch ARMRegisterInfo.td to use SubRegIndex and eliminate the parallel enums | Jakob Stoklund Olesen | 1 | -13/+0 |
| 2010-05-14 | Teach two-address pass to do some coalescing while eliminating REG_SEQUENCE | Evan Cheng | 1 | -1/+2 |
| 2010-05-14 | Added a QQQQ register file to model 4-consecutive Q registers. | Evan Cheng | 1 | -3/+4 |
| 2010-05-06 | Re-apply 103156 and 103157. 103156 didn't break anything. 10315 exposed a coa... | Evan Cheng | 1 | -1/+2 |
| 2010-05-06 | Revert r103156 since it was breaking the build bots. | Eric Christopher | 1 | -2/+1 |
| 2010-05-06 | Adding pseudo 256-bit registers QQ0 . . . QQ7 to represent pairs of Q registe... | Evan Cheng | 1 | -1/+2 |
| 2009-10-06 | Add codegen support for NEON vld2 operations on quad registers. | Bob Wilson | 1 | -0/+10 |
| 2009-07-08 | Push methods into base class in preparation for sharing. | David Goodwin | 1 | -28/+2 |
| 2009-07-08 | Start breaking out common base functionality for register info. | David Goodwin | 1 | -86/+1 |
| 2009-06-27 | Simplify a bit | Anton Korobeynikov | 1 | -7/+16 |
| 2009-06-27 | ARM refactoring. Step 2: split RegisterInfo | Anton Korobeynikov | 1 | -31/+41 |
| 2009-06-18 | - Update register allocation hint after coalescing. This is done by the targe... | Evan Cheng | 1 | -1/+4 |
| 2009-06-15 | Part 1. | Evan Cheng | 1 | -7/+27 |
| 2009-04-07 | PR2985 / <rdar://problem/6584986> | Jim Grosbach | 1 | -0/+2 |
| 2009-02-13 | Remove refs to non-DebugLoc versions of BuildMI from ARM. | Dale Johannesen | 1 | -1/+2 |
| 2009-02-06 | Move getPointerRegClass from TargetInstrInfo to TargetRegisterInfo. | Evan Cheng | 1 | -0/+4 |
| 2008-11-12 | Fix encoding of single-precision VFP registers. | Evan Cheng | 1 | -0/+4 |
| 2008-03-31 | Move reMaterialize() from TargetRegisterInfo to TargetInstrInfo. | Evan Cheng | 1 | -3/+8 |
| 2008-02-10 | Rename MRegisterInfo to TargetRegisterInfo. | Dan Gohman | 1 | -2/+2 |
| 2008-01-07 | Move even more functionality from MRegisterInfo into TargetInstrInfo. | Owen Anderson | 1 | -13/+2 |
| 2008-01-04 | Move some more functionality from MRegisterInfo to TargetInstrInfo. | Owen Anderson | 1 | -8/+0 |
| 2008-01-01 | Move some more instruction creation methods from RegisterInfo into InstrInfo. | Owen Anderson | 1 | -25/+0 |
| 2007-12-29 | Remove attribution from file headers, per discussion on llvmdev. | Chris Lattner | 1 | -2/+1 |
| 2007-12-05 | Add a argument to storeRegToStackSlot and storeRegToAddr to specify whether | Evan Cheng | 1 | -2/+5 |
| 2007-12-02 | Remove redundant foldMemoryOperand variants and other code clean up. | Evan Cheng | 1 | -13/+3 |
| 2007-12-01 | Allow some reloads to be folded in multi-use cases. Specifically testl r, r -... | Evan Cheng | 1 | -0/+12 |
| 2007-11-13 | Add parameter to getDwarfRegNum to permit targets | Dale Johannesen | 1 | -1/+1 |
| 2007-11-11 | Use TableGen to emit information for dwarf register numbers. | Anton Korobeynikov | 1 | -0/+2 |
| 2007-10-18 | - Added getOpcodeAfterMemoryUnfold(). It doesn't unfold an instruction, but o... | Evan Cheng | 1 | -2/+2 |
| 2007-10-18 | Use SmallVectorImpl instead of SmallVector with hardcoded size in MRegister p... | Evan Cheng | 1 | -4/+4 |
| 2007-10-05 | - Added a few target hooks to generate load / store instructions from / to any | Evan Cheng | 1 | -0/+10 |
| 2007-09-26 | Allow copyRegToReg to emit cross register classes copies. | Evan Cheng | 1 | -1/+2 |
| 2007-08-30 | Add a variant of foldMemoryOperand to fold any load / store, not just load / ... | Evan Cheng | 1 | -0/+5 |
| 2007-07-19 | Change instruction description to split OperandList into OutOperandList and | Evan Cheng | 1 | -2/+2 |
| 2007-07-14 | Long live the exception handling! | Anton Korobeynikov | 1 | -2/+3 |
| 2007-05-01 | eliminateFrameIndex() change. | Evan Cheng | 1 | -1/+1 |
| 2007-05-01 | Under normal circumstances, when a frame pointer is not required, we reserve | Evan Cheng | 1 | -0/+2 |
| 2007-03-20 | Added MRegisterInfo hook to re-materialize an instruction. | Evan Cheng | 1 | -0/+3 |
| 2007-03-06 | Scavenge a register using the register scavenger when needed. | Evan Cheng | 1 | -6/+4 |
| 2007-02-28 | Make requiresRegisterScavenging determination on a per MachineFunction basis. | Evan Cheng | 1 | -1/+1 |
| 2007-02-28 | PEI now passes a RegScavenger ptr to eliminateFrameIndex. | Evan Cheng | 1 | -3/+4 |
| 2007-02-27 | Let MRegisterInfo now owns RegScavenger; eliminateFrameIndex must preserve re... | Evan Cheng | 1 | -3/+8 |
| 2007-02-23 | Add option to turn on register scavenger; By default, spills kills the regist... | Evan Cheng | 1 | -0/+2 |
