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path: root/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
AgeCommit message (Expand)AuthorFilesLines
2016-09-10AMDGPU: Implement is{LoadFrom|StoreTo}FrameIndexMatt Arsenault1-2/+2
2016-09-09AMDGPU] Assembler: better support for immediate literals in assembler.Sam Kolton1-2/+4
2016-09-06[AMDGPU] Wave and register controlsKonstantin Zhuravlyov1-123/+178
2016-09-03AMDGPU: Fix spilling of m0Matt Arsenault1-2/+26
2016-08-29AMDGPU/SI: Implement a custom MachineSchedStrategyTom Stellard1-0/+6
2016-08-26XXXTom Stellard1-1/+1
2016-08-26AMDGPU/SI: Use a better method for determining the largest pressure setsTom Stellard1-9/+28
2016-08-11AMDGPU: Remove custom getSubRegMatt Arsenault1-72/+10
2016-07-28MachineFunction: Return reference for getFrameInfo(); NFCMatthias Braun1-10/+10
2016-07-28AMDGPU/SI: Don't use reserved VGPRs for SGPR spillingTom Stellard1-3/+6
2016-07-22AMDGPU: Add HSA dispatch id intrinsicMatt Arsenault1-1/+2
2016-07-13AMDGPU/SI: Emit the number of SGPR and VGPR spillsMarek Olsak1-0/+2
2016-07-11AMDGPU: Enable trackLivenessAfterRegAllocMatt Arsenault1-0/+5
2016-07-11AMDGPU: fix local stack slot allocation bugsNicolai Haehnle1-2/+8
2016-06-30CodeGen: Use MachineInstr& in TargetInstrInfo, NFCDuncan P. N. Exon Smith1-1/+1
2016-06-24AMDGPU: Cleanup subtarget handling.Matt Arsenault1-26/+22
2016-06-16AMDGPU/SI: Propagate the Kill flag in storeRegToStackSlot and eliminateFrameI...Changpeng Fang1-12/+26
2016-06-09AMDGPU: Remove incorrect assertionMatt Arsenault1-4/+0
2016-05-24[AMDGPU][NFC] Rename ReserveTrapVGPRs -> ReserveRegsKonstantin Zhuravlyov1-3/+3
2016-05-18AMDGPU: Fix verifier error when spilling undef subregMatt Arsenault1-3/+11
2016-05-02AMDGPU/SI: Use v_readfirstlane_b32 when restoring SGPRs spilled to scratchTom Stellard1-2/+1
2016-05-02AMDGPU/SI: Set the kill flag on temp VGPRs used to restore SGPRs from scratchTom Stellard1-1/+1
2016-04-30AMDGPU/SI: Enable the post-ra schedulerTom Stellard1-16/+11
2016-04-26[AMDGPU] Move reserved vgpr count for trap handler usage to SIMachineFunction...Konstantin Zhuravlyov1-2/+3
2016-04-26[AMDGPU] Reserve VGPRs for trap handler usage if instructedKonstantin Zhuravlyov1-0/+11
2016-04-25AMDGPU: Add queue ptr intrinsicMatt Arsenault1-1/+2
2016-04-18Silence some "initialized but unused" warnings from MSVC -- the function bein...Aaron Ballman1-13/+2
2016-04-16AMDGPU: Enable LocalStackSlotAllocation passMatt Arsenault1-0/+138
2016-04-14AMDGPU: allow specifying a workgroup size that needs to fit in a compute unitTom Stellard1-52/+73
2016-04-13AMDGPU/SI: Add support for spilling VGPRs without having to scavenge registersTom Stellard1-10/+27
2016-04-13[AMDGPU][llvm-mc] Support of Trap Handler registers (TTMP0..11 and TBA/TMA)gi...Artem Tamazov1-1/+25
2016-04-07AMDGPU/SI: Add MachineBasicBlock parameter to SIInstrInfo::insertWaitStatesTom Stellard1-2/+2
2016-03-23AMDGPU: Cache information about register pressure setsTom Stellard1-24/+33
2016-03-10AMDGPU/SI: add llvm.amdgcn.buffer.load/store.format intrinsicsNicolai Haehnle1-3/+3
2016-03-04AMDGPU/SI: Add support for spiling SGPRs to scratch bufferTom Stellard1-17/+69
2016-03-04AMDGPU/SI: Enable frame index scavenging during PrologEpilogueInserterTom Stellard1-7/+13
2016-02-12AMDGPU/SI: Detect uniform branches and emit s_cbranch instructionsTom Stellard1-1/+4
2016-02-12AMDGPU: Set flat_scratch from flat_scratch_init regMatt Arsenault1-0/+5
2016-02-11AMDGPU/SI: Make sure MIMG descriptors and samplers stay in SGPRsTom Stellard1-0/+18
2016-02-10AMDGPU: Release the scavenged offset register during VGPR spillNicolai Haehnle1-1/+8
2016-01-13AMDGPU/SI: Add SI Machine SchedulerNicolai Haehnle1-1/+14
2016-01-07AMDGPU/SI: Fold operands with sub-registersNicolai Haehnle1-4/+30
2016-01-07AMDGPU/SI: xnack_mask is always reserved on VINicolai Haehnle1-31/+16
2016-01-04AMDGPU: add +xnack featureNicolai Haehnle1-6/+27
2016-01-04AMDGPU: Avoid assertions after SGPR spilling failedNicolai Haehnle1-10/+0
2015-12-17AMDGPU: Fix off-by-one in SIRegisterInfo::eliminateFrameIndexNicolai Haehnle1-6/+7
2015-12-01Squelch unused variable warning in SIRegisterInfo.cpp.Matt Arsenault1-1/+2
2015-11-30AMDGPU: Rework how private buffer passed for HSAMatt Arsenault1-18/+62
2015-11-30AMDGPU: Rename enums to be consistent with HSA code object terminologyMatt Arsenault1-14/+14
2015-11-30AMDGPU: Remove SIPrepareScratchRegsMatt Arsenault1-0/+19
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