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path: root/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
AgeCommit message (Expand)AuthorFilesLines
2016-09-16AMDGPU/SI: Add support for triples with the mesa3d operating systemTom Stellard1-1/+1
2016-09-06[AMDGPU] Wave and register controlsKonstantin Zhuravlyov1-14/+4
2016-08-11AMDGPU: Remove unused tracking of flat instructionsMatt Arsenault1-1/+0
2016-07-28MachineFunction: Return reference for getFrameInfo(); NFCMatthias Braun1-4/+4
2016-07-28AMDGPU/SI: Don't use reserved VGPRs for SGPR spillingTom Stellard1-1/+2
2016-07-26AMDGPU: Make AMDGPUMachineFunction fields privateMatt Arsenault1-3/+0
2016-07-22AMDGPU: Add HSA dispatch id intrinsicMatt Arsenault1-1/+11
2016-07-13AMDGPU/SI: Emit the number of SGPR and VGPR spillsMarek Olsak1-0/+2
2016-06-27SIMachineFunctionInfo.cpp: Appease msc18 to use std::array.NAKAMURA Takumi1-2/+2
2016-06-27Reformat.NAKAMURA Takumi1-1/+1
2016-06-27Reformat blank lines.NAKAMURA Takumi1-2/+0
2016-06-25[AMDGPU] Emit debugger prologue and emit the rest of the debugger fields in t...Konstantin Zhuravlyov1-4/+6
2016-06-24AMDGPU: Cleanup subtarget handling.Matt Arsenault1-5/+6
2016-06-23AMDGPU: Add option to disable spilling SGPRs to VGPRs.Matt Arsenault1-2/+9
2016-05-24[AMDGPU][NFC] Rename ReserveTrapVGPRs -> ReserveRegsKonstantin Zhuravlyov1-3/+3
2016-04-26[AMDGPU] Move reserved vgpr count for trap handler usage to SIMachineFunction...Konstantin Zhuravlyov1-0/+4
2016-04-25AMDGPU: Add queue ptr intrinsicMatt Arsenault1-0/+3
2016-04-14AMDGPU: allow specifying a workgroup size that needs to fit in a compute unitTom Stellard1-6/+7
2016-04-14AMDGPU/SI: Use the correct scratch wave offset register for shaders.Tom Stellard1-3/+6
2016-04-06AMDGPU: Add a shader calling conventionNicolai Haehnle1-3/+5
2016-03-04AMDGPU/SI: Add support for spiling SGPRs to scratch bufferTom Stellard1-10/+5
2016-02-12AMDGPU: Set flat_scratch from flat_scratch_init regMatt Arsenault1-4/+20
2016-01-13AMDGPU/SI: Add s_waitcnt at the end of non-void functionsMarek Olsak1-0/+1
2016-01-13AMDGPU/SI: Add new target attribute InitialPSInputAddrMarek Olsak1-1/+4
2016-01-04AMDGPU: Avoid assertions after SGPR spilling failedNicolai Haehnle1-0/+11
2015-11-30AMDGPU: Rework how private buffer passed for HSAMatt Arsenault1-9/+71
2015-11-30AMDGPU: Remove SIPrepareScratchRegsMatt Arsenault1-0/+8
2015-11-25AMDGPU: Check feature attributes in SIMachineFunctionInfoMatt Arsenault1-3/+36
2015-11-05AMDGPU: Also track whether SGPRs were spilledMatt Arsenault1-0/+1
2015-07-14MachineRegisterInfo: Remove UsedPhysReg infrastructureMatthias Braun1-1/+0
2015-06-13R600 -> AMDGPU renameTom Stellard1-0/+77
2012-07-16Revert "AMDGPU: Add core backend files for R600/SI codegen v6"Tom Stellard1-18/+0
2012-07-16AMDGPU: Add core backend files for R600/SI codegen v6Tom Stellard1-0/+18
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