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path: root/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
AgeCommit message (Expand)AuthorFilesLines
2016-08-27AMDGPU: Remove register operand from si_mask_branchMatt Arsenault1-4/+2
2016-08-22AMDGPU: Split SILowerControlFlow into two piecesMatt Arsenault1-343/+169
2016-08-11AMDGPU: Remove unused tracking of flat instructionsMatt Arsenault1-15/+0
2016-08-10AMDGPU: Change insertion point of si_mask_branchMatt Arsenault1-10/+17
2016-07-28AMDGPU: add execfix flag to SI_ELSENicolai Haehnle1-8/+4
2016-07-27Remove MCAsmInfo.h include from TargetOptions.hReid Kleckner1-0/+1
2016-07-26AMDGPU: Make AMDGPUMachineFunction fields privateMatt Arsenault1-1/+1
2016-07-25AMDGPU: Make skip threshold an optionMatt Arsenault1-3/+8
2016-07-19[AMDGPU] Remove spurious line (should've been removed in r276029).Davide Italiano1-3/+0
2016-07-19[AMDGPU] Remove dead code.Davide Italiano1-25/+0
2016-07-19AMDGPU: Expand register indexing pseudos in custom inserterMatt Arsenault1-286/+0
2016-07-15AMDGPU: Fix not expanding control flow after some kill blocksMatt Arsenault1-7/+2
2016-07-15AMDGPU: Fix trying to skip from a block with no successorsMatt Arsenault1-2/+3
2016-07-12AMDGPU: Follow up to r275203Matt Arsenault1-24/+27
2016-07-12AMDGPU: Fix verifier error with kill intrinsicMatt Arsenault1-65/+122
2016-07-09Revert "AMDGPU: Remove unused control flow intrinsic"Matt Arsenault1-0/+19
2016-07-09AMDGPU: Improve offset folding for register indexingMatt Arsenault1-22/+40
2016-07-08AMDGPU: Remove unused control flow intrinsicMatt Arsenault1-19/+0
2016-07-08AMDGPU: Minor adjustment to r274817Matt Arsenault1-1/+1
2016-07-08AMDGPU: Move si_mask_branch register operand to be a useMatt Arsenault1-4/+6
2016-07-08AMDGPU: Cleanup. Use definesRegister instead of manual loopMatt Arsenault1-6/+2
2016-07-06AMDGPU: Fix return of non-void-returning shadersNicolai Haehnle1-6/+4
2016-06-30AMDGPU: Add m0 vgpr load loop block as successorMatt Arsenault1-0/+1
2016-06-28AMDGPU: Fix out of bounds indirect indexing errorsMatt Arsenault1-8/+19
2016-06-27AMDGPU: Fix verifier errors with undef vector indicesMatt Arsenault1-27/+37
2016-06-24AMDGPU: Cleanup subtarget handling.Matt Arsenault1-3/+4
2016-06-22AMDGPU: Fix liveness when expanding m0 loopMatt Arsenault1-17/+60
2016-06-22AMDGPU: Fix verifier errors in SILowerControlFlowMatt Arsenault1-66/+127
2016-05-19AMDGPU: Also look for s_cbranch_vcczMatt Arsenault1-1/+2
2016-04-29AMDGPU: Fix crash with unreachable terminators.Matt Arsenault1-12/+27
2016-04-06AMDGPU: Add a shader calling conventionNicolai Haehnle1-6/+4
2016-03-21AMDGPU: Add SIWholeQuadMode passNicolai Haehnle1-12/+21
2016-03-21AMDGPU/SI: Fix threshold calculation for branching when exec is zeroTom Stellard1-3/+5
2016-03-18AMDGPU: add missing braces around multi-line if blockNicolai Haehnle1-1/+2
2016-03-16AMDGPU: Prevent uniform loops from becoming infiniteNicolai Haehnle1-0/+6
2016-03-14AMDGPU/SI: Incomplete shader binaries need to finish execution at the endMarek Olsak1-0/+24
2016-02-12AMDGPU: Set flat_scratch from flat_scratch_init regMatt Arsenault1-35/+3
2016-02-12AMDGPU: Initialize SILowerControlFlowMatt Arsenault1-28/+36
2016-02-12AMDGPU: Remove trailing whitespaceMatt Arsenault1-4/+4
2015-10-21AMDGPU: Fix adding redundant m0 usesMatt Arsenault1-2/+0
2015-10-20AMDGPU: Add MachineInstr overloads for instruction format testsMatt Arsenault1-2/+2
2015-10-07AMDGPU: Use explicit register size indirect pseudosMatt Arsenault1-1/+5
2015-09-25AMDGPU: Fix recomputing dominator tree unnecessarilyMatt Arsenault1-0/+4
2015-08-08AMDGPU/SI: Remove VCCRegMatt Arsenault1-4/+4
2015-08-05AMDGPU/SI: Remove EXECRegMatt Arsenault1-8/+4
2015-06-13R600 -> AMDGPU renameTom Stellard1-0/+605
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