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path: root/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
AgeCommit message (Expand)AuthorFilesLines
2016-09-12AMDGPU: Do not clobber SCC in SIWholeQuadModeNicolai Haehnle1-5/+13
2016-09-10AMDGPU: Implement is{LoadFrom|StoreTo}FrameIndexMatt Arsenault1-6/+56
2016-09-09AMDGPU: Fix immediate folding logic when shrinking instructionsMatt Arsenault1-7/+7
2016-09-09AMDGPU] Assembler: better support for immediate literals in assembler.Sam Kolton1-4/+6
2016-09-08AMDGPU: Sign extend constants when splitting themMatt Arsenault1-3/+2
2016-09-08AMDGPU: Support commuting with immediate in src0Matt Arsenault1-97/+71
2016-09-06[AMDGPU] Wave and register controlsKonstantin Zhuravlyov1-1/+1
2016-09-06AMDGPU/SI: Teach SIInstrInfo::FoldImmediate() to fold immediates into copiesTom Stellard1-2/+27
2016-09-03AMDGPU: Set sizes of spill pseudosMatt Arsenault1-3/+1
2016-09-03AMDGPU: Fix spilling of m0Matt Arsenault1-14/+13
2016-08-29AMDGPU/SI: Query AA, if available, in areMemAccessesTriviallyDisjoint()Tom Stellard1-0/+11
2016-08-27AMDGPU: Move cndmask pseudo to be isel pseudoMatt Arsenault1-23/+0
2016-08-17Replace "fallthrough" comments with LLVM_FALLTHROUGHJustin Bogner1-1/+1
2016-08-13AMDGPU: Fix not estimating MBB operand sizes correctlyMatt Arsenault1-2/+20
2016-08-10AMDGPU: Remove unnecessary castMatt Arsenault1-4/+2
2016-07-28MachineFunction: Return reference for getFrameInfo(); NFCMatthias Braun1-6/+6
2016-07-28AMDGPU/SI: Don't use reserved VGPRs for SGPR spillingTom Stellard1-1/+2
2016-07-26AMDGPU: Make AMDGPUMachineFunction fields privateMatt Arsenault1-1/+1
2016-07-19AMDGPU: Expand register indexing pseudos in custom inserterMatt Arsenault1-0/+51
2016-07-15AMDGPU: Fix verifier error from partially undef copyMatt Arsenault1-5/+3
2016-07-15Rename AnalyzeBranch* to analyzeBranch*.Jacques Pienaar1-2/+1
2016-07-12AMDGPU: Cleanup pseudoinstructionsMatt Arsenault1-5/+0
2016-07-09AMDGPU: Move R600 only pieces into R600 classesMatt Arsenault1-8/+0
2016-07-09AMDGPU: Improve offset folding for register indexingMatt Arsenault1-1/+2
2016-07-09AMDGPU: Simplify isSchedulingBoundaryMatt Arsenault1-5/+4
2016-07-08AMDGPU: Remove implicit iterator conversions, NFCDuncan P. N. Exon Smith1-6/+6
2016-07-05AMDGPU: Fix folding SGPRs into madak/madmk src0Matt Arsenault1-3/+11
2016-06-30CodeGen: Use MachineInstr& in TargetInstrInfo, NFCDuncan P. N. Exon Smith1-430/+420
2016-06-28AMDGPU: Remove unused functionMatt Arsenault1-27/+0
2016-06-24AMDGPU: Cleanup subtarget handling.Matt Arsenault1-18/+17
2016-06-23AMDGPU: readlane/writelane do not read execMatt Arsenault1-1/+24
2016-06-20Reformat blank lines.NAKAMURA Takumi1-7/+0
2016-06-20Untabify.NAKAMURA Takumi1-2/+2
2016-06-16AMDGPU/SI: Propagate the Kill flag in storeRegToStackSlot and eliminateFrameI...Changpeng Fang1-2/+2
2016-06-14AMDGPU/SI: Refactor fixup handling for constant addrspace variablesTom Stellard1-1/+1
2016-06-14Revert "AMDGPU/SI: Refactor fixup handling for constant addrspace variables"Tom Stellard1-1/+1
2016-06-14AMDGPU/SI: Refactor fixup handling for constant addrspace variablesTom Stellard1-1/+1
2016-06-13AMDGPU/SI: Set INDEX_STRIDE for scratch coalescingMarek Olsak1-1/+3
2016-06-13AMDGPU: Fix post-RA verifier errors with trackLivenessAfterRegAllocMatt Arsenault1-14/+16
2016-06-12Pass DebugLoc and SDLoc by const ref.Benjamin Kramer1-6/+5
2016-06-06AMDGPU: Add function for getting instruction sizeMatt Arsenault1-0/+49
2016-06-02AMDGPU: Handle flat in getMemOpBaseRegImmOfsMatt Arsenault1-0/+7
2016-06-02AMDGPU: Fix incorrectly setting kill flag when copying register tuplesMatt Arsenault1-1/+1
2016-05-21AMDGPU: Fix verifier error when spilling SGPRsMatt Arsenault1-0/+13
2016-05-21AMDGPU: Handle cbranch vccz/vccnzMatt Arsenault1-0/+16
2016-05-21AMDGPU: Implement ReverseBranchConditionMatt Arsenault1-0/+7
2016-05-21AMDGPU: Implement AnalyzeBranchMatt Arsenault1-0/+109
2016-05-13AMDGPU: Remove verifier check for scc live insMatt Arsenault1-10/+0
2016-05-02AMDGPU/SI: Fix bug in SIInstrInfo::insertWaitStates() uncovered by r268260Tom Stellard1-1/+2
2016-04-30AMDGPU/SI: Enable the post-ra schedulerTom Stellard1-2/+36
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