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path: root/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
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4 days[NFC][LLVM] Pass/return SMLoc by value instead of const reference (#160797)Rahul Joshi1-13/+11
SMLoc itself encapsulates just a pointer, so there is no need to pass or return it by reference.
5 daysAMDGPU: Ensure both wavesize features are not set (#159234)Matt Arsenault1-12/+21
Make sure we cannot be in a mode with both wavesizes. This prevents assertions in a future change. This should probably just be an error, but we do not have a good way to report errors from the MCSubtargetInfo constructor.
6 days[AMDGPU][AsmParser] Introduce MC representation for lit() and lit64(). (#160316)Ivan Kosarev1-19/+70
And rework the lit64() support to use it. The rules for when to add lit64() can be simplified and improved. In this change, however, we just follow the existing conventions on the assembler and disassembler sides. In codegen we do not (and normally should not need to) add explicit lit() and lit64() modifiers, so the codegen tests lose them. The change is an NFCI otherwise. Simplifies printing operands.
7 days[AMDGPU][AsmParser][NFC] Combine the Lit and Lit64 modifier flags. (#160315)Ivan Kosarev1-34/+37
They represent mutually exclusive values of the same attribute.
13 daysAMDGPU: Remove subtarget feature hacking in AsmParser (#159227)Matt Arsenault1-14/+0
The wavesize hacking part was already done in createAMDGPUMCSubtargetInfo, and we can move the default target hack there too.
2025-09-16[AMDGPU][MC] Keep MCOperands unencoded. (#158685)Ivan Kosarev1-69/+12
We have proper encoding facilities to encode operands and instructions; there's no need to pollute the MC representation with encoding details. Supposed to be an NFCI, but happens to fix some re-encoded instruction codes in disassembler tests. The 64-bit operands are to be addressed in following patches introducing MC-level representation for lit() and lit64() modifiers, to then be respected by both the assembler and disassembler.
2025-09-15[AMDGPU][AsmParser] Simplify getting source locations of operands. (#158323)Ivan Kosarev1-186/+102
Remember indexes of MCOperands in MCParsedAsmOperands as we add them to instructions. Then use the indexes to find locations by known MCOperands indexes. Happens to fix some reported locations in tests. NFCI otherwise. getImmLoc() is to be eliminated as well; there's enough work for another patch.
2025-09-10Revert "[AMDGPU][gfx1250] Add `cu-store` subtarget feature (#150588)" (#157639)Pierre van Houtryve1-6/+0
This reverts commit be17791f2624f22b3ed24a2539406164a379125d. This is not necessary for gfx1250 anymore.
2025-09-06AMDGPU: Check aligned vgpr feature in assembler (#156997)Matt Arsenault1-1/+1
Use the new feature instead of listing the two separate cases.
2025-09-04[AMDGPU] Ensure positive InstOffset for buffer operations (#145504)Aleksandar Spasojevic1-3/+7
GFX12+ buffer ops require positive InstOffset per AMD hardware spec. Modified assembler/disassembler to reject negative buffer offsets.
2025-09-04[AMDGPU] Fix source location for assembler warnings (#156621)Jay Foad1-1/+1
Call MCInst::setLoc earlier so it is available for warnings generated during MatchInstructionImpl.
2025-09-03[AMDGPU] Define 1024 VGPRs on gfx1250 (#156765)Stanislav Mekhanoshin1-1/+14
This is a baseline support, it is not useable yet.
2025-09-02[AMDGPU] Add s_set_vgpr_msb gfx1250 instruction (#156524)Stanislav Mekhanoshin1-0/+20
2025-08-26NFC: remove some instances of deprecated capture (#154884)Jeremy Kun1-1/+1
``` warning: implicit capture of 'this' with a capture default of '=' is deprecated [-Wdeprecated-this-capture] ``` Co-authored-by: Jeremy Kun <j2kun@users.noreply.github.com>
2025-08-22[AMDGPU] gfx1250 kernel descriptor update (#155008)Stanislav Mekhanoshin1-6/+18
2025-08-20[AMDGPU] report named barrier cnt part2 (#154588)Gang Chen1-0/+11
2025-08-14[AMDGPU] Don't allow wgp mode on gfx1250 (#153680)Stanislav Mekhanoshin1-2/+3
- gfx1250 only supports cu mode
2025-08-11[AMDGPU] Per-subtarget DPP instruction classification (#153096)Stanislav Mekhanoshin1-4/+6
This is NFCI at this point.
2025-08-07[AMDGPU] Restrict packed math FP32 instructions to read only one SGPR per ↵Stanislav Mekhanoshin1-0/+37
operand on gfx12+ (#152465) Sec. 4.6.7.1 of the gfx1250 SPG states that if an SGPR is used as an operand, only one SGPR will be read for both the low and high operations. As a result, the corresponding bits in `op_sel` and `op_sel_hi` must be the same when the operand is an SGPR. Co-authored-by: Tian, Shilei <Shilei.Tian@amd.com> Co-authored-by: Tian, Shilei <Shilei.Tian@amd.com>
2025-08-05[AMDGPU] Add MC support for new gfx1250 src_flat_scratch_base_lo/hi (#152203)Stanislav Mekhanoshin1-40/+49
2025-08-04[AMDGPU] gfx1250 v_wmma_ld_scale instructions (#152010)Stanislav Mekhanoshin1-0/+84
2025-07-31[AMDGPU] Add v_cvt_scale_pk8_* gfx1250 instructions (#151616)Stanislav Mekhanoshin1-0/+6
2025-07-31[AMDGPU] Add gfx1250 cvt_pk|sr_fp8|bf8_f32 instructions (#151595)Stanislav Mekhanoshin1-5/+10
2025-07-30[AMDGPU] Add v_cvt_sr|pk_bf8|fp8_f16 gfx1250 instructions (#151415)Stanislav Mekhanoshin1-1/+23
2025-07-29[AMDGPU][gfx1250] Add `cu-store` subtarget feature (#150588)Pierre van Houtryve1-0/+6
Determines whether we can use `SCOPE_CU` stores (on by default), or whether all stores must be done at `SCOPE_SE` minimum.
2025-07-21[AMDGPU] MC support for gfx1250 scale_offset modifier (#149881)Stanislav Mekhanoshin1-1/+27
2025-07-21[AMDGPU] Verify asm VGPR alignment on gfx1250 (#149880)Stanislav Mekhanoshin1-2/+34
Co-authored-by: Shilei Tian <Shilei.Tian@amd.com>
2025-07-21AMDGPU: Support v_wmma_f32_16x16x128_f8f6f4 on gfx1250 (#149684)Changpeng Fang1-0/+79
Co-authored-by: Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com>
2025-07-18[AMDGPU] Support nv memory instructions modifier on gfx1250 (#149582)Stanislav Mekhanoshin1-1/+25
2025-07-15[AMDGPU] Use a range-based for loop (NFC) (#148767)Kazu Hirata1-2/+2
2025-07-15AMDGPU: Implement MC layer support for gfx1250 wmma instructions. (#148570)Changpeng Fang1-3/+35
Regular wmma/swmmac plus matrix reuse only. --------- Co-authored-by: Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> Co-authored-by: Shilei Tian <Shilei.Tian@amd.com>
2025-07-11[AMDGPU] MC support for v_fmaak_f64/v_fmamk_f64 gfx1250 intructions (#148282)Stanislav Mekhanoshin1-4/+24
2025-07-10[AMDGPU] VOPD/VOPD3 changes for gfx1250 (#147602)Stanislav Mekhanoshin1-22/+185
2025-07-09[AMDGPU] gfx1250: MC support for 64-bit literals (#147861)Stanislav Mekhanoshin1-31/+95
2025-07-08[AMDGPU] Add support for `v_cvt_f32_fp8` on gfx1250 (#147579)Shilei Tian1-4/+4
Co-authored-by: Mekhanoshin, Stanislav <Stanislav.Mekhanoshin@amd.com>
2025-07-03AMDGPU: Implement tensor load and store instructions for gfx1250 (#146636)Changpeng Fang1-6/+21
Co-authored-by: Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com>
2025-06-28MCParsedAsmOperand::print: Add MCAsmInfo parameterFangrui Song1-2/+2
so that subclasses can provide the appropriate MCAsmInfo to print MCExpr objects. At present, llvm/utils/TableGen/AsmMatcherEmitter.cpp constucts a generic MCAsmInfo.
2025-06-28MC: Migrate away from operator<< MCExprFangrui Song1-1/+4
MCExpr::print has an optional MCAsmInfo argument, which is error-prone when omitted. MCExpr::print and the convenience helper operator<< are discouraged to use. Switch to MCAsmInfo::printExpr instead. Use the target-specific MCAsmInfo if available.
2025-06-27[AMDGPU] Use StringRef::consume_back (NFC) (#146194)Kazu Hirata1-10/+10
Note that StringRef::consume_back returns true while consuming the given prefix if present.
2025-06-17[llvm] annotate interfaces in llvm/Target for DLL export (#143615)Andrew Rogers1-1/+3
## Purpose This patch is one in a series of code-mods that annotate LLVM’s public interface for export. This patch annotates the `llvm/Target` library. These annotations currently have no meaningful impact on the LLVM build; however, they are a prerequisite to support an LLVM Windows DLL (shared library) build. ## Background This effort is tracked in #109483. Additional context is provided in [this discourse](https://discourse.llvm.org/t/psa-annotating-llvm-public-interface/85307), and documentation for `LLVM_ABI` and related annotations is found in the LLVM repo [here](https://github.com/llvm/llvm-project/blob/main/llvm/docs/InterfaceExportAnnotations.rst). A sub-set of these changes were generated automatically using the [Interface Definition Scanner (IDS)](https://github.com/compnerd/ids) tool, followed formatting with `git clang-format`. The bulk of this change is manual additions of `LLVM_ABI` to `LLVMInitializeX` functions defined in .cpp files under llvm/lib/Target. Adding `LLVM_ABI` to the function implementation is required here because they do not `#include "llvm/Support/TargetSelect.h"`, which contains the declarations for this functions and was already updated with `LLVM_ABI` in a previous patch. I considered patching these files with `#include "llvm/Support/TargetSelect.h"` instead, but since TargetSelect.h is a large file with a bunch of preprocessor x-macro stuff in it I was concerned it would unnecessarily impact compile times. In addition, a number of unit tests under llvm/unittests/Target required additional dependencies to make them build correctly against the LLVM DLL on Windows using MSVC. ## Validation Local builds and tests to validate cross-platform compatibility. This included llvm, clang, and lldb on the following configurations: - Windows with MSVC - Windows with Clang - Linux with GCC - Linux with Clang - Darwin with Clang
2025-06-13[AMDGPU][AsmParser] Support true16 register suffix for valid register range ↵Shilei Tian1-3/+16
(#143997)
2025-06-04[AMDGPU][True16][MC][CodeGen] true16 mode for v_cvt_pk_bf8/fp8_f32 (#141881)Brox Chen1-4/+8
Update true16/fake16 profile with v_cvt_pk_bf8/fp8_f32, keeping the vdst_in profile, and update codegen pattern. update mc test and codegen test.
2025-06-03[AMDGPU] Bugfix for scaled MFMA parsing FP literals (#142493)Vigneshwar Jayakumar1-8/+22
bugfix on parsing FP literals for scale values in the scaled MFMA. Due to the change in order of operands between MCinst and parsed operands, the FP literal imms for scale values were not parsed correctly. --------- Co-authored-by: Matt Arsenault <arsenm2@gmail.com>
2025-05-27MCSymbol: Remove the default argument of getVariableValueFangrui Song1-1/+1
It has been made ineffective by e015626f189dc76f8df9fdc25a47638c6a2f3feb. This change migrates the users.
2025-05-26MCParser: Error when .set reassigns a non-redefinable variableFangrui Song1-0/+1
The conditions in parseAssignmentExpression are conservative. We should also report an error when a non-redefiniable variable (e.g. .equiv followed by .set; .weakref followed by .set). Make MCAsmStreamer::emitLabel call setOffset to make the behavior similar to MCObjectStreamer. `isUndefined()` can now be replaced with `isUnset()`. Additionally, fix an AMDGPU API user (tested by a few tests including MC/AMDGPU/hsa-v4.s)
2025-05-26[AMDGPU] Use StringRef::consume_front (NFC) (#141442)Kazu Hirata1-2/+1
2025-05-25Replace #include MCAsmLexer.h with AsmLexer.hFangrui Song1-1/+1
MCAsmLexer.h has been made a forwarder header since #134207
2025-05-21[AMDGPU] Fix scale opsel flags for scaled MFMA operations (#140183)Vigneshwar Jayakumar1-7/+80
Fix for src scale opsel flags encoding and ASM parsing for gfx950 scaled MFMA.
2025-05-09[AMDGPU][NFC] Remove _DEFERRED operands. (#139123)Ivan Kosarev1-17/+5
All immediates are deferred now.
2025-05-08[AMDGPU][NFC] Remove unused operand types. (#139062)Ivan Kosarev1-34/+4