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path: root/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
AgeCommit message (Expand)AuthorFilesLines
2016-04-30AMDGPU/SI: Enable the post-ra schedulerTom Stellard1-0/+11
2016-04-29AMDGPU/SI: Move post regalloc run of SIShrinkInstructionsMatt Arsenault1-5/+1
2016-04-22[AMDGPU] Insert nop pass: take care of outstanding feedbackKonstantin Zhuravlyov1-5/+1
2016-04-18[AMDGPU] Add insert nops pass based on subtarget features instead of cl::optKonstantin Zhuravlyov1-7/+3
2016-04-14AMDGPU: Run SIFoldOperands after PeepholeOptimizerMatt Arsenault1-1/+15
2016-04-14AMDGPU: Add skeleton GlobalIsel implementationTom Stellard1-0/+16
2016-04-14AMDGPU: Remove SIFixSGPRLiveRanges passNicolai Haehnle1-7/+0
2016-03-21AMDGPU: Add SIWholeQuadMode passNicolai Haehnle1-0/+2
2016-03-11AMDGPU: R600 code splitting cleanupMatt Arsenault1-2/+2
2016-03-03AMDGPU: Insert two S_NOP instructions for every high level source statement.Tom Stellard1-0/+11
2016-02-12AMDGPU/SI: Detect uniform branches and emit s_cbranch instructionsTom Stellard1-5/+5
2016-02-12AMDGPU: Initialize SILowerControlFlowMatt Arsenault1-1/+2
2016-02-05AMDGPU: Fix ordering of CPU and FS parameters in TargetMachine constructorsTom Stellard1-4/+4
2016-02-05AMDGPU/SI: Correctly initialize SIInsertWaits passTom Stellard1-1/+2
2016-02-02AMDGPU: Skip promote alloca with no optimizationsMatt Arsenault1-1/+1
2016-01-30AMDGPU: Fix emitting invalid workitem intrinsics for HSAMatt Arsenault1-2/+4
2016-01-27AMDGPU: Fix default device handlingMatt Arsenault1-2/+16
2016-01-21AMDGPU/SI: Pass whether to use the SI scheduler via Target AttributeTom Stellard1-0/+2
2016-01-20Correctly initialize SIAnnotateControlFlowTom Stellard1-0/+1
2016-01-13AMDGPU/SI: Add SI Machine SchedulerNicolai Haehnle1-2/+6
2015-12-15AMDGPU/SI: Select constant loads with non-uniform addresses to MUBUF instruct...Tom Stellard1-0/+3
2015-12-10AMDGPU/SI: Emit constant arrays in the .text sectionTom Stellard1-2/+2
2015-11-30AMDGPU: Remove SIPrepareScratchRegsMatt Arsenault1-1/+0
2015-11-06AMDGPU: Add pass to detect used kernel featuresMatt Arsenault1-0/+8
2015-11-03AMDGPU: Initialize SIFixSGPRCopies so -print-after worksMatt Arsenault1-1/+2
2015-10-12AMDGPU: Register some more passes so -print-before worksMatt Arsenault1-0/+2
2015-10-08CodeGen: print and verify after TargetPassConfig::insertPass by defaultJustin Bogner1-1/+3
2015-10-07AMDGPU: Properly register passesMatt Arsenault1-2/+2
2015-10-01AMDGPU: Move SIFixSGPRLiveRanges to be a regalloc passMatt Arsenault1-1/+17
2015-09-25AMDGPU/SI: Use .hsatext section instead of .text for HSATom Stellard1-4/+10
2015-09-25AMDGPU: Disable some passes that are not meaningfulMatt Arsenault1-3/+15
2015-09-16constify the Function parameter to the TTI creation callback andEric Christopher1-1/+1
2015-08-22AMDGPU: Make sure to run verifier after SIFixSGPRLiveRangesMatt Arsenault1-1/+1
2015-08-07AMDGPU: Add pass to lower OpenCL image and sampler arguments.Tom Stellard1-0/+2
2015-07-14AMDGPU/SI: Fix read2 merging into a super register.Matt Arsenault1-0/+1
2015-07-09Make TargetTransformInfo keeping a reference to the Module DataLayoutMehdi Amini1-2/+4
2015-07-06AMDGPU: Run SIInsertWaits as pre-emit passMatt Arsenault1-1/+1
2015-06-13R600 -> AMDGPU renameTom Stellard1-0/+292
2012-07-16Revert "AMDGPU: Add core backend files for R600/SI codegen v6"Tom Stellard1-162/+0
2012-07-16AMDGPU: Add core backend files for R600/SI codegen v6Tom Stellard1-0/+162
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