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path: root/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
AgeCommit message (Expand)AuthorFilesLines
2016-09-06[AMDGPU] Wave and register controlsKonstantin Zhuravlyov1-0/+82
2016-08-29AMDGPU/SI: Implement a custom MachineSchedStrategyTom Stellard1-0/+45
2016-08-11AMDGPU: Fix crashes on memory functionsMatt Arsenault1-1/+2
2016-07-25AMDGPU: Delete dead codeMatt Arsenault1-26/+0
2016-07-01AMDGPU: Add feature for unaligned accessMatt Arsenault1-2/+3
2016-07-01Target: Remove unused arguments from overrideSchedPolicy, NFCDuncan P. N. Exon Smith1-2/+0
2016-06-28AMDGPU: Fix global isel crashesMatt Arsenault1-2/+2
2016-06-28AMDGPU: Fix global isel buildMatt Arsenault1-15/+3
2016-06-27AMDGPU: Implement per-function subtargetsMatt Arsenault1-11/+1
2016-06-27AMDGPU: Move subtarget feature checks into passesMatt Arsenault1-1/+0
2016-06-25[AMDGPU] Emit debugger prologue and emit the rest of the debugger fields in t...Konstantin Zhuravlyov1-0/+1
2016-06-24AMDGPU: Remove disable-irstructurizer subtarget featureMatt Arsenault1-1/+0
2016-06-24AMDGPU: Cleanup subtarget handling.Matt Arsenault1-100/+111
2016-06-22AMDGPU: Make FrameLowering stack alignment 16Matt Arsenault1-3/+4
2016-06-02AMDGPU: Fix crashes on unknown processor nameMatt Arsenault1-2/+4
2016-05-26AMDGPU/SI: Enable load-store-opt by default.Changpeng Fang1-1/+1
2016-05-24[AMDGPU][NFC] Rename ReserveTrapVGPRs -> ReserveRegsKonstantin Zhuravlyov1-1/+1
2016-05-16AMDGPU: Fix promote alloca pass creating huge arraysMatt Arsenault1-0/+58
2016-05-11AMDGPU: Change private_element_size to 4Matt Arsenault1-1/+1
2016-04-26[AMDGPU] Reserve VGPRs for trap handler usage if instructedKonstantin Zhuravlyov1-1/+1
2016-04-18[AMDGPU] Add insert nops pass based on subtarget features instead of cl::optKonstantin Zhuravlyov1-1/+3
2016-04-14AMDGPU: Add skeleton GlobalIsel implementationTom Stellard1-0/+27
2016-04-06AMDGPU: Add a shader calling conventionNicolai Haehnle1-3/+2
2016-03-30AMDGPU/SI: Enable lanemask tracking in mischedTom Stellard1-0/+4
2016-02-27AMDGPU: More bits of frame index are known to be zeroMatt Arsenault1-1/+1
2016-02-27AMDGPU: Split vi-insts subtarget featureMatt Arsenault1-1/+2
2016-02-27AMDGPU: Implement readcyclecounterMatt Arsenault1-1/+2
2016-02-12AMDGPU: Set element_size in private resource descriptorMatt Arsenault1-1/+6
2016-01-28AMDGPU: Match some med3 patternsMatt Arsenault1-3/+3
2016-01-27AMDGPU: Fix default device handlingMatt Arsenault1-4/+1
2016-01-23AMDGPU: Remove Feature64BitPtrMatt Arsenault1-1/+1
2016-01-21AMDGPU/SI: Pass whether to use the SI scheduler via Target AttributeTom Stellard1-1/+1
2016-01-18AMDGPU: Add subtarget feature for instruction ratesMatt Arsenault1-4/+7
2016-01-04AMDGPU: add +xnack featureNicolai Haehnle1-0/+1
2015-12-22 AMDGPU/SI: Use flat for global load/store when targeting HSAChangpeng Fang1-3/+5
2015-12-22Revert "AMDGPU/SI: Use flat for global load/store when targeting HSA"Rafael Espindola1-5/+3
2015-12-22AMDGPU/SI: Use flat for global load/store when targeting HSAChangpeng Fang1-3/+5
2015-11-06AMDGPU: Cleanup includesMatt Arsenault1-0/+1
2015-11-06AMDGPU: Create emergency stack slots during frame loweringMatt Arsenault1-3/+13
2015-09-15Revert r247692: Replace Triple with a new TargetTuple in MCTargetDesc/* and r...Daniel Sanders1-7/+7
2015-09-15Re-commit r247683: Replace Triple with a new TargetTuple in MCTargetDesc/* an...Daniel Sanders1-7/+7
2015-09-15Revert r247684 - Replace Triple with a new TargetTuple ...Daniel Sanders1-7/+7
2015-09-15Replace Triple with a new TargetTuple in MCTargetDesc/* and related. NFC.Daniel Sanders1-7/+7
2015-07-16AMDPGU/SI: Use AssertZext node to mask high bit for scratch offsetsTom Stellard1-1/+1
2015-07-06AMDGPU/SI: Add debugging subtarget feature for DS offsetsMatt Arsenault1-0/+1
2015-06-26AMDGPU/SI: Add hsa code object directivesTom Stellard1-0/+6
2015-06-13R600 -> AMDGPU renameTom Stellard1-0/+133
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