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path: root/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
AgeCommit message (Expand)AuthorFilesLines
2016-08-29AMDGPU/R600: Remove MergeVectorStores from legalizationJan Vesely1-3/+0
2016-08-27AMDGPU: Select mulhi 24-bit instructionsMatt Arsenault1-2/+9
2016-08-04[X86] Heuristic to selectively build Newton-Raphson SQRT estimationNikolai Bozhenov1-0/+3
2016-07-28AMDGPU : Add intrinsics for compare with the full wavefront resultWei Ding1-0/+3
2016-07-26AMDGPU: Add fp legacy instruction intrinsicsMatt Arsenault1-0/+2
2016-07-25AMDGPU: Delete dead codeMatt Arsenault1-1/+0
2016-07-23AMDGPU: Delete dead codeMatt Arsenault1-4/+0
2016-07-19AMDGPU: Only use legal inline immediates with kill pseudoMatt Arsenault1-0/+1
2016-07-18AMDGPU: Add intrinsic for s_flbit_i32/v_ffbh_i32Matt Arsenault1-0/+1
2016-07-14AMDGPU: Remove dead codeMatt Arsenault1-1/+0
2016-07-01AMDGPU: Expand unaligned accesses earlyMatt Arsenault1-1/+1
2016-07-01AMDGPU: Improve load/store of illegal types.Matt Arsenault1-1/+4
2016-06-24AMDGPU: Cleanup subtarget handling.Matt Arsenault1-1/+1
2016-06-22AMDGPU: Fix verifier errors in SILowerControlFlowMatt Arsenault1-1/+2
2016-06-21AMDGPU: Add implicitarg.ptr intrinsic.Jan Vesely1-2/+3
2016-06-14AMDGPU/SI: Refactor fixup handling for constant addrspace variablesTom Stellard1-0/+1
2016-06-14Revert "AMDGPU/SI: Refactor fixup handling for constant addrspace variables"Tom Stellard1-1/+0
2016-06-14AMDGPU/SI: Refactor fixup handling for constant addrspace variablesTom Stellard1-0/+1
2016-06-12Pass DebugLoc and SDLoc by const ref.Benjamin Kramer1-14/+8
2016-04-14AMDGPU: Remove custom load/store scalarizationMatt Arsenault1-6/+0
2016-04-12AMDGPU: Add atomic_inc + atomic_dec intrinsicsMatt Arsenault1-0/+2
2016-04-01AMDGPU: Implement {BUFFER,FLAT}_ATOMIC_CMPSWAP{,_X2}Tom Stellard1-0/+1
2016-03-11AMDGPU: R600 code splitting cleanupMatt Arsenault1-8/+3
2016-03-07AMDGPU: Move function only used by R600Matt Arsenault1-1/+0
2016-02-13AMDGPU: Rename intrinsic to better match instruction nameMatt Arsenault1-1/+1
2016-02-11AMDGPU: Split R600 and SI store loweringMatt Arsenault1-1/+0
2016-02-10AMDGPU: Split R600 and SI load loweringMatt Arsenault1-1/+0
2016-01-28AMDGPU: Match some med3 patternsMatt Arsenault1-0/+3
2016-01-23AMDGPU: Remove more unused intrinsicsMatt Arsenault1-1/+0
2016-01-20AMDGPU: Remove abs intrinsicMatt Arsenault1-1/+0
2016-01-18AMDGPU: Reduce 64-bit SRAsMatt Arsenault1-0/+2
2016-01-18AMDGPU: Split 64-bit and of constant upMatt Arsenault1-1/+7
2016-01-18AMDGPU: Reduce 64-bit lshr by constant to 32-bitMatt Arsenault1-0/+1
2016-01-13AMDGPU/SI: Add support for non-void functionsMarek Olsak1-0/+2
2016-01-11AMDGPU: Implement {{s|u}}int_to_fp i64 -> f32Matt Arsenault1-0/+1
2016-01-11AMDGPU: Pattern match ffbh pattern to instruction.Matt Arsenault1-0/+4
2016-01-11AMDGPU: Custom lower i64 ctlzMatt Arsenault1-0/+2
2015-12-14AMDGPU: Use generic bitreverse intrinsicMatt Arsenault1-1/+0
2015-10-12DAGCombiner: Combine extract_vector_elt from build_vectorMatt Arsenault1-0/+1
2015-08-26AMDGPU: Produce error on dynamic_stackallocMatt Arsenault1-0/+3
2015-08-13[AMDGPU] Use the general SMAX/SMIN/UMAX/UMIN pattern matching and remove the ...Simon Pilgrim1-8/+0
2015-07-28AMDGPU: Fix return type of getImplicitParameterOffset.Matt Arsenault1-1/+1
2015-07-14AMDGPU: Avoid using 64-bit shift for i64 (shl x, 32)Matt Arsenault1-0/+1
2015-07-09AMDGPU: Add helper function for implicit parameter offsets.Tom Stellard1-0/+10
2015-07-09Make TargetLowering::getPointerTy() taking DataLayout as an argumentMehdi Amini1-1/+1
2015-06-13R600 -> AMDGPU renameTom Stellard1-0/+307
2012-07-16Revert "AMDGPU: Add core backend files for R600/SI codegen v6"Tom Stellard1-77/+0
2012-07-16AMDGPU: Add core backend files for R600/SI codegen v6Tom Stellard1-0/+77
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