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path: root/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
AgeCommit message (Expand)AuthorFilesLines
2016-08-25MachineFunctionProperties/MIRParser: Rename AllVRegsAllocated->NoVRegs, compu...Matthias Braun1-1/+1
2016-08-12[AArch64LoadStoreOptimizer] Check aliasing correctly when creating paired loa...Eli Friedman1-1/+4
2016-08-12[AArch64LoadStoreOpt] Handle offsets correctly for post-indexed paired loads.Eli Friedman1-5/+5
2016-08-12[AArch64] Re-factor code shared by AArch64LoadStoreOpt and AArch64InstrInfo.Geoff Berry1-37/+3
2016-07-21[AArch64] Load/store opt: Don't count transient instructions towards search l...Geoff Berry1-15/+14
2016-07-20[AArch64] Register AArch64LoadStoreOptimizer so it can be run by llc -run-pas...Geoff Berry1-4/+0
2016-07-08AArch64: Avoid implicit iterator conversions, NFCDuncan P. N. Exon Smith1-155/+155
2016-06-30CodeGen: Use MachineInstr& in TargetInstrInfo, NFCDuncan P. N. Exon Smith1-21/+21
2016-06-20Untabify.NAKAMURA Takumi1-1/+1
2016-06-10[AArch64] Move comments closer to relevant check. NFC.Chad Rosier1-6/+4
2016-06-10[AArch64] Refactor a check earlier. NFC.Chad Rosier1-12/+18
2016-06-02AArch64: Do not test for CPUs, use SubtargetFeaturesMatthias Braun1-14/+2
2016-05-20[AArch64] Disable narrow load merge by defaultJun Bum Lim1-1/+1
2016-05-06[AArch64] Decouple zero store promotion from narrow ld merge. NFC.Jun Bum Lim1-28/+16
2016-04-25Add optimization bisect opt-in calls for AArch64 passesAndrew Kaylor1-0/+3
2016-04-04Add MachineFunctionProperty checks for AllVRegsAllocated for target passesDerek Schuff1-0/+5
2016-03-31[AArch64] Handle missing store pair opportunityJun Bum Lim1-22/+23
2016-03-30[AArch64] Fix warnings pointed out by Hal.Chad Rosier1-1/+5
2016-03-18[AArch64] Enable more load clustering in the MI Scheduler.Chad Rosier1-29/+2
2016-03-09[AArch64] Move helper functions into TII, so they can be reused elsewhere. NFC.Chad Rosier1-47/+21
2016-03-08[AArch64] Add MMOs to unscaled pairs.Chad Rosier1-3/+2
2016-02-12[AArch64] Add support for Qualcomm Kryo CPU.Chad Rosier1-1/+1
2016-02-12[AArch64] Merge two adjacent str WZR into str XZRJun Bum Lim1-15/+30
2016-02-11[AArch64] Refactoring findMatchingStore() in aarch64-ldst-opt; NFCJun Bum Lim1-11/+13
2016-02-11[AArch64] Improve load/store optimizer to handle LDUR + LDR.Chad Rosier1-11/+68
2016-02-10[AArch64] Refactor is logic into a helper function. NFC.Chad Rosier1-12/+22
2016-02-10[AArch64] Update comment to match reality. NFC.Chad Rosier1-2/+2
2016-02-10[AArch64] This bit of logic is specific to pairing. NFC.Chad Rosier1-8/+10
2016-02-09[AArch64] This check is specific to merging instructions. NFC.Chad Rosier1-4/+4
2016-02-09[AArch64] AArch64LoadStoreOptimizer: fix bug in pre-inc check iteratorGeoff Berry1-8/+9
2016-02-09[AArch64] Bail even earlier if the instructions modifieds the base register. ...Chad Rosier1-5/+6
2016-02-09[AArch64] Simplify. NFC.Chad Rosier1-3/+1
2016-02-09[AArch64] Add an assert to ensure we don't scale an offset that can't be scaled.Chad Rosier1-1/+3
2016-02-09[AArch64] Add a FIXME about invalid KILL markers after the ld/st opt pass.Chad Rosier1-0/+5
2016-02-09[AArch64] Remove redundant calls and clang format. NFC.Chad Rosier1-42/+40
2016-02-09[AArch64] Hoist now common logic. NFC.Chad Rosier1-13/+9
2016-02-09[AArch64] Rename variable to make it clear we're merging here, not pairing.Chad Rosier1-19/+19
2016-02-09[AArch64] Separage the codegen logic for widening vs. pairing. NFC.Chad Rosier1-38/+94
2016-02-09[AArch64] Cleanup to simplify logic when widening vs. pairing loads/stores. NFC.Chad Rosier1-13/+50
2016-02-09[AArch64] Rename variable to improve readability. NFC.Chad Rosier1-5/+5
2016-02-09[AArch64] Remove stale comment.Chad Rosier1-3/+0
2016-02-05[AArch64] Refactoring aarch64-ldst-opt. NCF.Jun Bum Lim1-25/+38
2016-02-05Revert "[AArch64] Improve load/store optimizer to handle LDUR + LDR (take 3)."Renato Golin1-76/+21
2016-02-04[AArch64] Bound the number of instructions we scan when searching for updates.Chad Rosier1-14/+26
2016-02-04[AArch64] Improve load/store optimizer to handle LDUR + LDR (take 3).Chad Rosier1-21/+76
2016-02-04Revert "[AArch64] Improve load/store optimizer to handle LDUR + LDR."Chad Rosier1-77/+22
2016-02-04[AArch64] Improve load/store optimizer to handle LDUR + LDR.Chad Rosier1-22/+77
2016-02-02[AArch64] Add a FIXME comment.Chad Rosier1-0/+2
2016-02-02[AArch64] Allocate the modified and used regs only once per function.Chad Rosier1-12/+17
2016-02-01Move comments a bit closer to associated code. NFC.Chad Rosier1-29/+25
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