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path: root/llvm/lib/CodeGen/VirtRegMap.cpp
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2014-04-22[Modules] Remove potential ODR violations by sinking the DEBUG_TYPEChandler Carruth1-1/+2
define below all header includes in the lib/CodeGen/... tree. While the current modules implementation doesn't check for this kind of ODR violation yet, it is likely to grow support for it in the future. It also removes one layer of macro pollution across all the included headers. Other sub-trees will follow. llvm-svn: 206837
2014-03-17Switch a number of loops in lib/CodeGen over to range-based for-loops, now thatOwen Anderson1-4/+2
the MachineRegisterInfo iterators are compatible with it. llvm-svn: 204075
2014-03-13Phase 2 of the great MachineRegisterInfo cleanup. This time, we're changingOwen Anderson1-3/+3
operator* on the by-operand iterators to return a MachineOperand& rather than a MachineInstr&. At this point they almost behave like normal iterators! Again, this requires making some existing loops more verbose, but should pave the way for the big range-based for-loop cleanups in the future. llvm-svn: 203865
2014-03-07[C++11] Add 'override' keyword to virtual methods that override their base ↵Craig Topper1-2/+2
class. llvm-svn: 203220
2014-03-04[cleanup] Re-sort all the includes with utils/sort_includes.py.Chandler Carruth1-1/+1
llvm-svn: 202811
2014-02-25Keep the link register for uwtable.Logan Chien1-3/+12
The function with uwtable attribute might be visited by the stack unwinder, thus the link register should be considered as clobbered after the execution of the branch and link instruction (i.e. the definition of the machine instruction can't be ignored) even when the callee function are marked with noreturn. llvm-svn: 202165
2014-02-06Yet another patch to reduce compile time for small programs:Puyan Lotfi1-4/+28
The aim in this patch is to reduce work that VirtRegRewriter needs to do when telling MachineRegisterInfo which physregs are in use. Up until now VirtRegRewriter::rewrite has been doing rewriting and populating def info and then proceeding to set whether a physreg is used based this info for every physreg that the target provides. This can be expensive when a target has an unusually high number of supported physregs, and is a noticeable chunk of compile time for small programs on such targets. So to reduce compile time, this patch simply adds the use of a SparseSet to the rewrite function that is used to flag each physreg that is encountered in a MachineFunction. Afterward, rather than iterating over the set of all physregs for a given target to set the physregs used in MachineRegisterInfo, the new way is to iterate over the set of physregs that were actually encountered and set in the SparseSet. This improves compile time because the existing rewrite function was iterating over all MachineOperands already, and because the iterations afterward to setPhysRegUsed is reduced by use of the SparseSet data. llvm-svn: 200919
2013-11-08[VirtRegMap] Fix for PR17825. Do not ignore noreturn definitions when settingQuentin Colombet1-1/+5
isPhysRegUsed if the unwind information is required. Indeed, the runtime may need a correct stack to be able to unwind the call. llvm-svn: 194271
2013-09-25[PR16882] Ignore noreturn definitions when setting isPhysRegUsed.Quentin Colombet1-3/+39
PEI inserts a save/restore sequence for the link register, according to the information it gets from the MachineRegisterInfo. MachineRegisterInfo is populated by the VirtRegMap pass. This pass was not aware of noreturn calls and was registering the definitions of these calls the same way as regular operations. Modify VirtRegPass so that it does not set the isPhysRegUsed information for registers only defined by noreturn calls. The rational is that a noreturn call is the "last instruction" of the program (if it returns the behavior is undefined), so everything that is defined by it cannot be used and will not interfere with anything else. Therefore, it is pointless to account for then. llvm-svn: 191349
2012-12-04Remove VirtRegMap::getRegAllocPref().Jakob Stoklund Olesen1-11/+0
Now that there can be multiple hint registers from targets, it doesn't make sense to have a function that returns 'the' preferred register. llvm-svn: 169190
2012-12-04Use MRI::getSimpleHint() instead of getRegAllocPref() in remaining cases.Jakob Stoklund Olesen1-0/+9
Targets can provide multiple hints now, so getRegAllocPref() doesn't make sense any longer because it only returns one preferred register. Replace it with getSimpleHint() in the remaining heuristics. This function only llvm-svn: 169188
2012-12-03Add VirtRegMap::hasKnownPreference().Jakob Stoklund Olesen1-0/+9
Virtual registers with a known preferred register are prioritized by RAGreedy. This function makes the condition explicit without depending on getRegAllocPref(). llvm-svn: 169179
2012-12-03Use the new script to sort the includes of every file under lib.Chandler Carruth1-5/+5
Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] llvm-svn: 169131
2012-11-28Make the LiveRegMatrix analysis available to targets.Jakob Stoklund Olesen1-1/+1
No functional change, just moved header files. Targets can inject custom passes between register allocation and rewriting. This makes it possible to tweak the register allocation before rewriting, using the full global interference checking available from LiveRegMatrix. llvm-svn: 168806
2012-10-15Switch most getReservedRegs() clients to the MRI equivalent.Jakob Stoklund Olesen1-4/+1
Using the cached bit vector in MRI avoids comstantly allocating and recomputing the reserved register bit vector. llvm-svn: 165983
2012-09-21Fix a significant recent(?) regression. StackSlotColoring no longer did anythingEvan Cheng1-0/+4
because LiveStackAnalysis was not preserved by VirtRegWriter. This caused big stack usage regression in some cases. rdar://12340383 llvm-svn: 164408
2012-09-11Release build: guard dump functions withManman Ren1-1/+1
"#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)" No functional change. Update r163339. llvm-svn: 163653
2012-09-06Release build: guard dump functions with "ifndef NDEBUG"Manman Ren1-0/+2
No functional change. llvm-svn: 163339
2012-09-06Handle overlapping regunit intervals in LiveIntervals::addKillFlags().Jakob Stoklund Olesen1-1/+1
We will soon allow virtual register live ranges to overlap regunit live ranges when the physreg is defined as a copy of the virtreg: %EAX = COPY %vreg5 FOO %vreg5 BAR %EAX<kill> There is no real interference since %vreg5 and %EAX have the same value where they overlap. This patch prevents addKillFlags from adding virtreg kill flags to FOO where the assigned physreg is overlapping the virtual register live range. llvm-svn: 163335
2012-08-22Add a getName function to MachineFunction. Use it in places that previously ↵Craig Topper1-2/+1
did getFunction()->getName(). Remove includes of Function.h that are no longer needed. llvm-svn: 162347
2012-06-09Also compute MBB live-in lists in the new rewriter pass.Jakob Stoklund Olesen1-0/+32
This deduplicates some code from the optimizing register allocators, and it means that it is now possible to change the register allocators' solutions simply by editing the VirtRegMap between the register allocator pass and the rewriter. llvm-svn: 158249
2012-06-08Reintroduce VirtRegRewriter.Jakob Stoklund Olesen1-33/+114
OK, not really. We don't want to reintroduce the old rewriter hacks. This patch extracts virtual register rewriting as a separate pass that runs after the register allocator. This is possible now that CodeGen/Passes.cpp can configure the full optimizing register allocator pipeline. The rewriter pass uses register assignments in VirtRegMap to rewrite virtual registers to physical registers, and it inserts kill flags based on live intervals. These finalization steps are the same for the optimizing register allocators: RABasic, RAGreedy, and PBQP. llvm-svn: 158244
2012-02-17Transfer regmasks to MRI.Jakob Stoklund Olesen1-0/+5
MRI keeps track of which physregs have been used. Make sure it gets updated with all the regmask-clobbered registers. Delete the closePhysRegsUsed() function which isn't necessary. llvm-svn: 150830
2012-01-19Rewriter should definitly rewrite instructions inside bundles.Evan Cheng1-2/+2
llvm-svn: 148464
2012-01-07Use the 'regalloc' debug tag for most register allocator tracing.Jakob Stoklund Olesen1-1/+1
llvm-svn: 147725
2012-01-03Assert when reserved registers have been assigned.Jakob Stoklund Olesen1-0/+4
This can only happen if the set of reserved registers changes during register allocation. <rdar://problem/10625436> llvm-svn: 147486
2011-11-13More dead code elimination in VirtRegMap.Jakob Stoklund Olesen1-12/+0
This thing is looking a lot like a virtual register map now. llvm-svn: 144486
2011-11-13Stop tracking spill slot uses in VirtRegMap.Jakob Stoklund Olesen1-45/+0
Nobody cared, StackSlotColoring scans the instructions to find used stack slots. llvm-svn: 144485
2011-11-13Remove dead code and data from VirtRegMap.Jakob Stoklund Olesen1-61/+0
Most of this stuff was supporting the old deferred spill code insertion mechanism. Modern spillers just edit machine code in place. llvm-svn: 144484
2011-11-13Stop tracking unused registers in VirtRegMap.Jakob Stoklund Olesen1-35/+0
The information was only used by the register allocator in StackSlotColoring. llvm-svn: 144482
2011-10-05Also add <imp-use,kill> flags for redefined super-registers.Jakob Stoklund Olesen1-8/+18
For example: %vreg10:dsub_0<def,undef> = COPY %vreg1 %vreg10:dsub_1<def> = COPY %vreg2 is rewritten as: %D2<def> = COPY %D0, %Q1<imp-def> %D3<def> = COPY %D1, %Q1<imp-use,kill>, %Q1<imp-def> The first COPY doesn't care about the previous value of %Q1, so it doesn't read that register. The second COPY is a partial redefinition of %Q1, so it implicitly kills and redefines that register. This makes it possible to recognize instructions that can harmlessly clobber the full super-register. The write and don't read the super-register. llvm-svn: 141139
2011-09-15VirtRegMap is counting spill slots, not register spills.Jakob Stoklund Olesen1-3/+3
Fix the stats counters to reflect that. llvm-svn: 139819
2011-05-06Also count identity copies.Jakob Stoklund Olesen1-0/+2
llvm-svn: 130996
2011-04-27Also add <imp-def> operands for defined and dead super-registers when rewriting.Jakob Stoklund Olesen1-6/+15
We cannot rely on the <imp-def> operands added by LiveIntervals in all cases as demonstrated by the test case. llvm-svn: 130313
2011-03-31Don't completely eliminate identity copies that also modify super register ↵Jakob Stoklund Olesen1-6/+12
liveness. Turn them into noop KILL instructions instead. This lets the scavenger know when super-registers are killed and defined. llvm-svn: 128645
2011-03-23Dump the register map before rewriting.Jakob Stoklund Olesen1-1/+1
llvm-svn: 128143
2011-02-18Add VirtRegMap::rewrite() and use it in the new register allocators.Jakob Stoklund Olesen1-0/+71
The rewriter works almost identically to -rewriter=trivial, except it also eliminates any identity copies. This makes the new register allocators independent of VirtRegRewriter.cpp which will be going away at the same time as RegAllocLinearScan. llvm-svn: 125967
2011-01-10Simplify a bunch of isVirtualRegister() and isPhysicalRegister() logic.Jakob Stoklund Olesen1-3/+2
These functions not longer assert when passed 0, but simply return false instead. No functional change intended. llvm-svn: 123155
2011-01-09Remove MachineRegisterInfo::getLastVirtReg(), it was giving wrong resultsJakob Stoklund Olesen1-8/+8
when no virtual registers have been allocated. It was only used to resize IndexedMaps, so provide an IndexedMap::resize() method such that Map.grow(MRI.getLastVirtReg()); can be replaced with the simpler Map.resize(MRI.getNumVirtRegs()); This works correctly when no virtuals are allocated, and it bypasses the to/from index conversions. llvm-svn: 123130
2011-01-09Replace TargetRegisterInfo::printReg with a PrintReg class that also works ↵Jakob Stoklund Olesen1-8/+4
without a TRI instance. Print virtual registers numbered from 0 instead of the arbitrary FirstVirtualRegister. The first virtual register is printed as %vreg0. TRI::NoRegister is printed as %noreg. llvm-svn: 123107
2011-01-08Fix VirtRegMap to use TRI::index2VirtReg and TRI::virtReg2Index instead ofJakob Stoklund Olesen1-17/+25
depending on TRI::FirstVirtualRegister. Also use TRI::printReg instead of printing virtual registers directly. llvm-svn: 123101
2010-11-16Remember to resize SpillSlotToUsesMap when allocating an emergency spill slot.Jakob Stoklund Olesen1-19/+16
Use amazing new function call technology instead of writing identical code in multiple places. This fixes PR8604. llvm-svn: 119306
2010-10-07Now with fewer extraneous semicolons!Owen Anderson1-1/+1
llvm-svn: 115996
2010-07-21Fix batch of converting RegisterPass<> to INTIALIZE_PASS().Owen Anderson1-2/+1
llvm-svn: 109045
2010-02-26Use the right floating point load/store instructions in ↵Jakob Stoklund Olesen1-2/+4
PPCInstrInfo::foldMemoryOperandImpl(). The PowerPC floating point registers can represent both f32 and f64 via the two register classes F4RC and F8RC. F8RC is considered a subclass of F4RC to allow cross-class coalescing. This coalescing only affects whether registers are spilled as f32 or f64. Spill slots must be accessed with load/store instructions corresponding to the class of the spilled register. PPCInstrInfo::foldMemoryOperandImpl was looking at the instruction opcode which is wrong. X86 has similar floating point register classes, but doesn't try to fold memory operands, so there is no problem there. llvm-svn: 97262
2010-02-10Fix "the the" and similar typos.Dan Gohman1-1/+1
llvm-svn: 95781
2010-01-05Change errs() to dbgs().David Greene1-1/+1
llvm-svn: 92587
2009-11-12Add a bool flag to StackObjects telling whether they reference spillDavid Greene1-4/+4
slots. The AsmPrinter will use this information to determine whether to print a spill/reload comment. Remove default argument values. It's too easy to pass a wrong argument value when multiple arguments have default values. Make everything explicit to trap bugs early. Update all targets to adhere to the new interfaces.. llvm-svn: 87022
2009-11-03The Indexes Patch.Lang Hames1-1/+1
This introduces a new pass, SlotIndexes, which is responsible for numbering instructions for register allocation (and other clients). SlotIndexes numbering is designed to match the existing scheme, so this patch should not cause any changes in the generated code. For consistency, and to avoid naming confusion, LiveIndex has been renamed SlotIndex. The processImplicitDefs method of the LiveIntervals analysis has been moved into its own pass so that it can be run prior to SlotIndexes. This was necessary to match the existing numbering scheme. llvm-svn: 85979
2009-10-17Distinquish stack slots from other stack objects. They (and fixed objects) ↵Evan Cheng1-2/+2
get FixedStack PseudoSourceValues. llvm-svn: 84326
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