| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2012-06-25 | Handle <undef> operands in TwoAddressInstructionPass. | Jakob Stoklund Olesen | 1 | -12/+31 |
| 2012-06-05 | misched: API for minimum vs. expected latency. | Andrew Trick | 1 | -1/+1 |
| 2012-05-20 | Properly constrain register classes in 2-addr. | Jakob Stoklund Olesen | 1 | -0/+6 |
| 2012-05-18 | Teach two-address pass to update the "source" map so it doesn't perform a | Evan Cheng | 1 | -1/+7 |
| 2012-05-07 | Add an MF argument to TRI::getPointerRegClass() and TII::getRegClass(). | Jakob Stoklund Olesen | 1 | -1/+1 |
| 2012-05-03 | Fix two-address pass's aggressive instruction commuting heuristics. It's meant | Evan Cheng | 1 | -15/+16 |
| 2012-05-03 | Added TargetRegisterInfo::getAllocatableClass. | Andrew Trick | 1 | -1/+2 |
| 2012-04-09 | Patch r153892 for PR11861 apparently broke an external project (see PR12493). | Lang Hames | 1 | -16/+17 |
| 2012-04-04 | REG_SEQUENCE expansion to COPY instructions wasn't taking account of sub regi... | Pete Cooper | 1 | -1/+2 |
| 2012-04-04 | Remove spurious debug output. | Jakob Stoklund Olesen | 1 | -1/+0 |
| 2012-04-02 | During two-address lowering, rescheduling an instruction does not untie | Lang Hames | 1 | -2/+2 |
| 2012-02-10 | RegAlloc superpass: includes phi elimination, coalescing, and scheduling. | Andrew Trick | 1 | -1/+0 |
| 2012-02-03 | whitespace | Andrew Trick | 1 | -8/+8 |
| 2012-01-24 | Set correct <def,undef> flags when lowering REG_SEQUENCE. | Jakob Stoklund Olesen | 1 | -0/+46 |
| 2012-01-24 | Preserve <def,undef> flags in CoalesceExtSubRegs. | Jakob Stoklund Olesen | 1 | -3/+7 |
| 2012-01-18 | Fix ISD::REG_SEQUENCE to accept physical registers and change TwoAddressInstr... | Pete Cooper | 1 | -9/+12 |
| 2011-12-07 | Add bundle aware API for querying instruction properties and switch the code | Evan Cheng | 1 | -18/+13 |
| 2011-12-03 | Simplify code. No functionality change. | Benjamin Kramer | 1 | -2/+1 |
| 2011-11-16 | Disable expensive two-address optimizations at -O0. rdar://10453055 | Evan Cheng | 1 | -0/+8 |
| 2011-11-16 | Disable the assertion again. Looks like fastisel is still generating bad kill... | Evan Cheng | 1 | -1/+2 |
| 2011-11-16 | Revert r144568 now that r144730 has fixed the fast-isel kill marker bug. | Evan Cheng | 1 | -2/+1 |
| 2011-11-16 | If the 2addr instruction has other kills, don't move it below any other uses ... | Evan Cheng | 1 | -2/+7 |
| 2011-11-16 | RescheduleKillAboveMI() must backtrack to before the rescheduled DBG_VALUE in... | Evan Cheng | 1 | -1/+1 |
| 2011-11-16 | Process all uses first before defs to accurately capture register liveness. r... | Evan Cheng | 1 | -7/+13 |
| 2011-11-15 | Set SeenStore to true to prevent loads from being moved; also eliminates a no... | Evan Cheng | 1 | -2/+2 |
| 2011-11-14 | Avoid dereferencing off the beginning of lists. | Evan Cheng | 1 | -7/+4 |
| 2011-11-14 | At -O0, multiple uses of a virtual registers in the same BB are being marked | Evan Cheng | 1 | -1/+2 |
| 2011-11-14 | Teach two-address pass to re-schedule two-address instructions (or the kill | Evan Cheng | 1 | -19/+356 |
| 2011-09-23 | PR10998: It is not legal to sink an instruction past the terminator of a bloc... | Eli Friedman | 1 | -1/+9 |
| 2011-07-29 | Add an isSSA() flag to MachineRegisterInfo. | Jakob Stoklund Olesen | 1 | -0/+3 |
| 2011-06-28 | - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and | Evan Cheng | 1 | -16/+17 |
| 2011-06-27 | More refactoring. Move getRegClass from TargetOperandInfo to TargetInstrInfo. | Evan Cheng | 1 | -1/+1 |
| 2011-06-18 | Simplify code. No change in functionality. | Benjamin Kramer | 1 | -6/+1 |
| 2011-06-07 | Fix an issue where the two-address conversion pass incorrectly rewrites untied | Cameron Zwarich | 1 | -9/+16 |
| 2011-03-02 | Catch more cases where 2-address pass should 3-addressify instructions. rdar:... | Evan Cheng | 1 | -49/+70 |
| 2011-02-10 | After 3-addressifying a two-address instruction, update the register maps; ad... | Evan Cheng | 1 | -4/+9 |
| 2011-01-10 | Simplify a bunch of isVirtualRegister() and isPhysicalRegister() logic. | Jakob Stoklund Olesen | 1 | -1/+1 |
| 2011-01-09 | Shrink a BitVector that didn't mean to store bits for all physical registers. | Jakob Stoklund Olesen | 1 | -6/+4 |
| 2011-01-07 | Do not model all INLINEASM instructions as having unmodelled side effects. | Evan Cheng | 1 | -1/+1 |
| 2010-12-19 | StrongPHIElimination will never run before TwoAddressInstructionPass. | Cameron Zwarich | 1 | -1/+0 |
| 2010-12-19 | Remove some checks for StrongPHIElim. These checks make it impossible to use an | Cameron Zwarich | 1 | -4/+2 |
| 2010-12-17 | Fix crash compiling a QQQQ REG_SEQUENCE for a Neon vld3_lane operation. | Bob Wilson | 1 | -2/+5 |
| 2010-12-14 | Fix a minor bug in two-address pass. It was missing a commute opportunity. | Evan Cheng | 1 | -1/+2 |
| 2010-10-21 | Remove some variables that are never really used | Duncan Sands | 1 | -1/+0 |
| 2010-10-19 | Get rid of static constructors for pass registration. Instead, every pass ex... | Owen Anderson | 1 | -1/+3 |
| 2010-10-12 | Begin adding static dependence information to passes, which will allow us to | Owen Anderson | 1 | -1/+4 |
| 2010-10-07 | Now with fewer extraneous semicolons! | Owen Anderson | 1 | -1/+1 |
| 2010-08-23 | Now that PassInfo and Pass::ID have been separated, move the rest of the pass... | Owen Anderson | 1 | -2/+2 |
| 2010-08-09 | A REG_SEQUENCE instruction may use the same register twice. | Jakob Stoklund Olesen | 1 | -1/+11 |
| 2010-08-06 | Reapply r110396, with fixes to appease the Linux buildbot gods. | Owen Anderson | 1 | -2/+2 |
