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path: root/llvm/lib/CodeGen/MachineScheduler.cpp
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2012-12-01misched: Fix RegisterPressureTracker handling of DebugVals.Andrew Trick1-0/+4
Assertion failed: (TopRPTracker.getPos() == RegionBegin && "bad initial Top tracker"). rdar://12790302. llvm-svn: 169072
2012-12-01misched: fix RegionBegin when DebugValues get shuffled to the top.Andrew Trick1-0/+2
assert (RemainingInstrs == 0 && "Instruction count mismatch!") rdar://12776937. llvm-svn: 169069
2012-11-29misched: Recompute priority queue when DFSResults are updated.Benjamin Kramer1-0/+2
This was found by MSVC10's STL debug mode on a test from the test suite. Sadly std::is_heap isn't standard so there is no way to assert this without writing our own heap verify, which looks like overkill to me. llvm-svn: 168885
2012-11-28misched: Analysis that partitions the DAG into subtrees.Andrew Trick1-15/+56
This is a simple, cheap infrastructure for analyzing the shape of a DAG. It recognizes uniform DAGs that take the shape of bottom-up subtrees, such as the included matrix multiplication example. This is useful for heuristics that balance register pressure with ILP. Two canonical expressions of the heuristic are implemented in scheduling modes: -misched-ilpmin and -misched-ilpmax. llvm-svn: 168773
2012-11-28misched: rename ScheduleDAGILP to ScheduleDFS to prepare for other heuristics.Andrew Trick1-1/+1
llvm-svn: 168772
2012-11-28misched: Debug output fix. Use an always valid iterator.Andrew Trick1-1/+1
llvm-svn: 168767
2012-11-13misched: Allow subtargets to enable misched and dependent options.Andrew Trick1-2/+2
This allows me to begin enabling (or backing out) misched by default for one subtarget at a time. To run misched we typically want to: - Disable SelectionDAG scheduling (use the source order scheduler) - Enable more aggressive coalescing (until we decide to always run the coalescer this way) - Enable MachineScheduler pass itself. Disabling PostRA sched may follow for some subtargets. llvm-svn: 167826
2012-11-12misched: rename interfaceto avoid gcc warningsAndrew Trick1-2/+1
llvm-svn: 167753
2012-11-12misched: Target-independent support for MacroFusion.Andrew Trick1-5/+61
Uses the infrastructure from r167742 to support clustering instructure that the target processor can "fuse". e.g. cmp+jmp. Next step: target hook implementations with test cases, and enable. llvm-svn: 167744
2012-11-12misched: Target-independent support for load/store clustering.Andrew Trick1-12/+176
This infrastructure is generally useful for any target that wants to strongly prefer two instructions to be adjacent after scheduling. A following checkin will add target-specific hooks with unit tests. Then this feature will be enabled by default with misched. llvm-svn: 167742
2012-11-12misched: Infrastructure for weak DAG edges.Andrew Trick1-8/+18
This adds support for weak DAG edges to the general scheduling infrastructure in preparation for MachineScheduler support for heuristics based on weak edges. llvm-svn: 167738
2012-11-09Silence GCC warning about falling off the end of a non-void function.Benjamin Kramer1-0/+1
llvm-svn: 167618
2012-11-07misched: Heuristics based on the machine model.Andrew Trick1-146/+762
misched is disabled by default. With -enable-misched, these heuristics balance the schedule to simultaneously avoid saturating processor resources, expose ILP, and minimize register pressure. I've been analyzing the performance of these heuristics on everything in the llvm test suite in addition to a few other benchmarks. I would like each heuristic check to be verified by a unit test, but I'm still trying to figure out the best way to do that. The heuristics are still in considerable flux, but as they are refined we should be rigorous about unit testing the improvements. llvm-svn: 167527
2012-11-06misched: Rename RemainingCount to avoid confusion with remaining resources.Andrew Trick1-6/+6
llvm-svn: 167443
2012-10-16misched: Added handleMove support for updating all kill flags, not just for ↵Andrew Trick1-1/+1
allocatable regs. This is a medium term workaround until we have a more robust solution in the form of a register liveness utility for postRA passes. llvm-svn: 166001
2012-10-15misched: ILP scheduler for experimental heuristics.Andrew Trick1-20/+104
llvm-svn: 165950
2012-10-10misched: Use the TargetSchedModel interface wherever possible.Andrew Trick1-10/+20
Allows the new machine model to be used for NumMicroOps and OutputLatency. Allows the HazardRecognizer to be disabled along with itineraries. llvm-svn: 165603
2012-10-08misched: avoid scheduling an instruction twice.Andrew Trick1-25/+29
llvm-svn: 165416
2012-09-14misched: add a hook for custom DAG postprocessing.Andrew Trick1-0/+9
llvm-svn: 163915
2012-09-11Release build: guard dump functions withManman Ren1-1/+1
"#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)" No functional change. Update r163339. llvm-svn: 163653
2012-09-11Reorganize MachineScheduler interfaces and publish them in the header.Andrew Trick1-256/+100
The Hexagon target decided to use a lot of functionality from the target-independent scheduler. That's fine, and other targets should be able to do the same. This reorg and API update makes that easy. For the record, ScheduleDAGMI was not meant to be subclassed. Instead, new scheduling algorithms should be able to implement MachineSchedStrategy and be done. But if need be, it's nice to be able to extend ScheduleDAGMI, so I also made that easier. The target scheduler is somewhat more apt to break that way though. llvm-svn: 163580
2012-09-06Release build: guard dump functions with "ifndef NDEBUG"Manman Ren1-0/+2
No functional change. llvm-svn: 163339
2012-08-23Simplify the computeOperandLatency API.Andrew Trick1-10/+8
The logic for recomputing latency based on a ScheduleDAG edge was shady. This bypasses the problem by requiring the client to provide operand indices. This ensures consistent use of the machine model's API. llvm-svn: 162420
2012-08-22Add a getName function to MachineFunction. Use it in places that previously ↵Craig Topper1-1/+1
did getFunction()->getName(). Remove includes of Function.h that are no longer needed. llvm-svn: 162347
2012-07-23Fix a typo (the the => the)Sylvestre Ledru1-1/+1
llvm-svn: 160621
2012-07-07I'm introducing a new machine model to simultaneously allow simpleAndrew Trick1-1/+2
subtarget CPU descriptions and support new features of MachineScheduler. MachineModel has three categories of data: 1) Basic properties for coarse grained instruction cost model. 2) Scheduler Read/Write resources for simple per-opcode and operand cost model (TBD). 3) Instruction itineraties for detailed per-cycle reservation tables. These will all live side-by-side. Any subtarget can use any combination of them. Instruction itineraries will not change in the near term. In the long run, I expect them to only be relevant for in-order VLIW machines that have complex contraints and require a precise scheduling/bundling model. Once itineraries are only actively used by VLIW-ish targets, they could be replaced by something more appropriate for those targets. This tablegen backend rewrite sets things up for introducing MachineModel type #2: per opcode/operand cost model. llvm-svn: 159891
2012-07-02misched: allow NULL InstrItineraries.Andrew Trick1-0/+1
llvm-svn: 159599
2012-06-29misched: avoid scheduling instructions that can't be dispatched.Andrew Trick1-6/+29
llvm-svn: 159408
2012-06-29misched: count micro-ops toward the issue limit.Andrew Trick1-10/+19
llvm-svn: 159407
2012-06-16Guard private fields that are unused in Release builds with #ifndef NDEBUG.Benjamin Kramer1-1/+7
llvm-svn: 158608
2012-06-06Move RegisterClassInfo.h.Andrew Trick1-1/+1
Allow targets to access this API. It's required for RegisterPressure. llvm-svn: 158102
2012-06-06Move RegisterPressure.h.Andrew Trick1-1/+1
Make it a general utility for use by Targets. llvm-svn: 158097
2012-06-05misched: API for minimum vs. expected latency.Andrew Trick1-31/+81
Minimum latency determines per-cycle scheduling groups. Expected latency determines critical path and cost. llvm-svn: 158021
2012-06-05misched: comments from code review.Andrew Trick1-3/+3
llvm-svn: 157975
2012-05-25misched: trace formattingAndrew Trick1-6/+5
llvm-svn: 157455
2012-05-24Silence unused variable warnings from when assertions are disabled.Kaelyn Uhrain1-0/+2
llvm-svn: 157438
2012-05-24misched: Use the same scheduling heuristics with -misched-topdown/bottomup.Andrew Trick1-2/+16
(except the part about choosing direction) llvm-svn: 157437
2012-05-24misched: Trace regpressure.Andrew Trick1-2/+4
llvm-svn: 157429
2012-05-24misched: Give each ReadyQ a unique IDAndrew Trick1-36/+45
llvm-svn: 157428
2012-05-24misched: Added ScoreboardHazardRecognizer.Andrew Trick1-49/+232
The Hazard checker implements in-order contraints, or interlocked resources. Ready instructions with hazards do not enter the available queue and are not visible to other heuristics. The major code change is the addition of SchedBoundary to encapsulate the state at the top or bottom of the schedule, including both a pending and available queue. The scheduler now counts cycles in sync with the hazard checker. These are minimum cycle counts based on known hazards. Targets with no itinerary (x86_64) currently remain at cycle 0. To fix this, we need to provide some maximum issue width for all targets. We also need to add the concept of expected latency vs. minimum latency. llvm-svn: 157427
2012-05-24misched: Release bottom roots in reverse order.Andrew Trick1-9/+23
llvm-svn: 157426
2012-05-24misched: rename ReadyQ classAndrew Trick1-8/+9
llvm-svn: 157425
2012-05-24misched: copy comments so compareRPDelta is readable by itself.Andrew Trick1-1/+4
llvm-svn: 157424
2012-05-17commentsAndrew Trick1-2/+3
llvm-svn: 157020
2012-05-17misched: trace ReadyQ.Andrew Trick1-0/+8
llvm-svn: 157007
2012-05-17misched: Added 3-level regpressure back-off.Andrew Trick1-36/+184
Introduce the basic strategy for register pressure scheduling. 1) Respect target limits at all times. 2) Indentify critical register classes (pressure sets). Track pressure within the scheduled region. Avoid increasing scheduled pressure for critical registers. 3) Avoid exceeding the max pressure of the region prior to scheduling. Added logic for picking between the top and bottom ready Q's based on regpressure heuristics. Status: functional but needs to be asjusted to achieve good results. llvm-svn: 157006
2012-05-17commentAndrew Trick1-2/+0
llvm-svn: 157005
2012-05-17misched: fix liveness iteratorsAndrew Trick1-10/+16
llvm-svn: 157003
2012-05-10misched: Print machineinstrs with -debug-only=mischedAndrew Trick1-0/+2
llvm-svn: 156576
2012-05-10misched: tracing register pressure heuristics.Andrew Trick1-6/+22
llvm-svn: 156575
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