riscv-gnu-toolchain/llvm.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2012-12-01	misched: Fix RegisterPressureTracker handling of DebugVals.	Andrew Trick	1	-0/+4
2012-12-01	misched: fix RegionBegin when DebugValues get shuffled to the top.	Andrew Trick	1	-0/+2
2012-11-29	misched: Recompute priority queue when DFSResults are updated.	Benjamin Kramer	1	-0/+2
2012-11-28	misched: Analysis that partitions the DAG into subtrees.	Andrew Trick	1	-15/+56
2012-11-28	misched: rename ScheduleDAGILP to ScheduleDFS to prepare for other heuristics.	Andrew Trick	1	-1/+1
2012-11-28	misched: Debug output fix. Use an always valid iterator.	Andrew Trick	1	-1/+1
2012-11-13	misched: Allow subtargets to enable misched and dependent options.	Andrew Trick	1	-2/+2
2012-11-12	misched: rename interfaceto avoid gcc warnings	Andrew Trick	1	-2/+1
2012-11-12	misched: Target-independent support for MacroFusion.	Andrew Trick	1	-5/+61
2012-11-12	misched: Target-independent support for load/store clustering.	Andrew Trick	1	-12/+176
2012-11-12	misched: Infrastructure for weak DAG edges.	Andrew Trick	1	-8/+18
2012-11-09	Silence GCC warning about falling off the end of a non-void function.	Benjamin Kramer	1	-0/+1
2012-11-07	misched: Heuristics based on the machine model.	Andrew Trick	1	-146/+762
2012-11-06	misched: Rename RemainingCount to avoid confusion with remaining resources.	Andrew Trick	1	-6/+6
2012-10-16	misched: Added handleMove support for updating all kill flags, not just for a...	Andrew Trick	1	-1/+1
2012-10-15	misched: ILP scheduler for experimental heuristics.	Andrew Trick	1	-20/+104
2012-10-10	misched: Use the TargetSchedModel interface wherever possible.	Andrew Trick	1	-10/+20
2012-10-08	misched: avoid scheduling an instruction twice.	Andrew Trick	1	-25/+29
2012-09-14	misched: add a hook for custom DAG postprocessing.	Andrew Trick	1	-0/+9
2012-09-11	Release build: guard dump functions with	Manman Ren	1	-1/+1
2012-09-11	Reorganize MachineScheduler interfaces and publish them in the header.	Andrew Trick	1	-256/+100
2012-09-06	Release build: guard dump functions with "ifndef NDEBUG"	Manman Ren	1	-0/+2
2012-08-23	Simplify the computeOperandLatency API.	Andrew Trick	1	-10/+8
2012-08-22	Add a getName function to MachineFunction. Use it in places that previously d...	Craig Topper	1	-1/+1
2012-07-23	Fix a typo (the the => the)	Sylvestre Ledru	1	-1/+1
2012-07-07	I'm introducing a new machine model to simultaneously allow simple	Andrew Trick	1	-1/+2
2012-07-02	misched: allow NULL InstrItineraries.	Andrew Trick	1	-0/+1
2012-06-29	misched: avoid scheduling instructions that can't be dispatched.	Andrew Trick	1	-6/+29
2012-06-29	misched: count micro-ops toward the issue limit.	Andrew Trick	1	-10/+19
2012-06-16	Guard private fields that are unused in Release builds with #ifndef NDEBUG.	Benjamin Kramer	1	-1/+7
2012-06-06	Move RegisterClassInfo.h.	Andrew Trick	1	-1/+1
2012-06-06	Move RegisterPressure.h.	Andrew Trick	1	-1/+1
2012-06-05	misched: API for minimum vs. expected latency.	Andrew Trick	1	-31/+81
2012-06-05	misched: comments from code review.	Andrew Trick	1	-3/+3
2012-05-25	misched: trace formatting	Andrew Trick	1	-6/+5
2012-05-24	Silence unused variable warnings from when assertions are disabled.	Kaelyn Uhrain	1	-0/+2
2012-05-24	misched: Use the same scheduling heuristics with -misched-topdown/bottomup.	Andrew Trick	1	-2/+16
2012-05-24	misched: Trace regpressure.	Andrew Trick	1	-2/+4
2012-05-24	misched: Give each ReadyQ a unique ID	Andrew Trick	1	-36/+45
2012-05-24	misched: Added ScoreboardHazardRecognizer.	Andrew Trick	1	-49/+232
2012-05-24	misched: Release bottom roots in reverse order.	Andrew Trick	1	-9/+23
2012-05-24	misched: rename ReadyQ class	Andrew Trick	1	-8/+9
2012-05-24	misched: copy comments so compareRPDelta is readable by itself.	Andrew Trick	1	-1/+4
2012-05-17	comments	Andrew Trick	1	-2/+3
2012-05-17	misched: trace ReadyQ.	Andrew Trick	1	-0/+8
2012-05-17	misched: Added 3-level regpressure back-off.	Andrew Trick	1	-36/+184
2012-05-17	comment	Andrew Trick	1	-2/+0
2012-05-17	misched: fix liveness iterators	Andrew Trick	1	-10/+16
2012-05-10	misched: Print machineinstrs with -debug-only=misched	Andrew Trick	1	-0/+2
2012-05-10	misched: tracing register pressure heuristics.	Andrew Trick	1	-6/+22