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path: root/llvm/lib/CodeGen/MIRParser/MILexer.cpp
AgeCommit message (Expand)AuthorFilesLines
2019-08-13GlobalISel: Change representation of shuffle masksMatt Arsenault1-0/+1
2019-06-05Allow target to handle STRICT floating-point nodesUlrich Weigand1-0/+1
2019-01-19Update the file headers across all of the LLVM projects in the monorepoChandler Carruth1-4/+3
2018-12-18[AArch64] - Return address signing dwarf supportLuke Cheeseman1-0/+1
2018-12-13[mir] Serialize DILocation inline when not possible to use a metadata referenceDaniel Sanders1-0/+1
2018-11-23Revert r347490 as it breaks address sanitizer buildsLuke Cheeseman1-1/+0
2018-11-23Revert r343341Luke Cheeseman1-0/+1
2018-09-28Revert r343317Luke Cheeseman1-1/+0
2018-09-28Reapply changes reverted by r343235Luke Cheeseman1-0/+1
2018-09-27Revert r343192 as an ubsan build is currently failingLuke Cheeseman1-1/+0
2018-09-27Reapply changes reverted in r343114, lldb patch to follow shortlyLuke Cheeseman1-0/+1
2018-09-26Revert r343112 as CallFrameString API change has broken lldb buildsLuke Cheeseman1-1/+0
2018-09-26[AArch64] - Return address signing dwarf supportLuke Cheeseman1-0/+1
2018-09-26Revert r343089 "[AArch64] - Return address signing dwarf support"Hans Wennborg1-1/+0
2018-09-26[AArch64] - Return address signing dwarf supportLuke Cheeseman1-0/+1
2018-09-11add IR flags to MIMichael Berg1-0/+3
2018-08-20Consistently use MemoryLocation::UnknownSize to indicate unknown access sizeKrzysztof Parzyszek1-0/+1
2018-08-16[x86/MIR] Implement support for pre- and post-instruction symbols, asChandler Carruth1-0/+51
2018-05-05[MIRParser] Allow register class names in the form of integer/scalarHeejin Ahn1-19/+0
2018-05-03MachineInst support mapping SDNode fast math flags for support in Back End co...Michael Berg1-0/+7
2018-03-30[MIR] Adding support for Named Virtual Registers in MIR.Puyan Lotfi1-1/+13
2018-01-31Followup on Proposal to move MIR physical register namespace to '$' sigil.Puyan Lotfi1-7/+16
2018-01-26[MIR] Add support for addrspace in MIRFrancis Visoiu Mistrih1-0/+1
2018-01-10[MIR] Repurposing '$' sigil used by external symbols. Replacing with '&'.Puyan Lotfi1-1/+1
2018-01-09[MIR] Add support for the frame-destroy MachineInstr flagFrancis Visoiu Mistrih1-0/+1
2017-12-15[MIR] Add support for missing CFI directivesFrancis Visoiu Mistrih1-0/+8
2017-12-12[MachineOperand][MIR] Add isRenamable to MachineOperand.Geoff Berry1-0/+1
2017-12-04[CodeGen] Unify MBB reference format in both MIR and debug outputFrancis Visoiu Mistrih1-0/+3
2017-11-02[AsmPrinterDwarf] Add support for .cfi_restore directiveFrancis Visoiu Mistrih1-0/+1
2017-09-27[CodeGen] Fix some Clang-tidy modernize-use-default-member-init and Include W...Eugene Zelenko1-6/+12
2017-08-23Parse and print DIExpressions inline to ease IR and MIR testingReid Kleckner1-0/+1
2017-07-11Enhance synchscope representationKonstantin Zhuravlyov1-0/+10
2016-10-12[MIRParser] Parse lane masks for register live-insKrzysztof Parzyszek1-14/+23
2016-09-11[CodeGen] Split out the notions of MI invariance and MI dereferenceability.Justin Lebar1-0/+1
2016-08-17GlobalISel: support irtranslation of icmp instructions.Tim Northover1-0/+2
2016-07-29CodeGen: add new "intrinsic" MachineOperand kind.Tim Northover1-0/+1
2016-07-26MIRParser: Use dot instead of colon to mark subregistersMatthias Braun1-2/+9
2016-07-26MIRParser: Use shorter cfi identifiersMatthias Braun1-5/+5
2016-07-22GlobalISel: implement alloca instructionTim Northover1-3/+7
2016-07-20GlobalISel: implement low-level type with just size & vector lanes.Tim Northover1-4/+6
2016-04-16Remove some unneeded headers and replace some headers with forward class decl...Mehdi Amini1-0/+1
2016-03-28MIRParser: Add %subreg.xxx syntax for subregister index operandsMatthias Braun1-0/+11
2016-03-18MILexer: Add ErrorCallbackType typedef; NFCMatthias Braun1-30/+22
2016-03-08[MIR] Change the token name for '<' and '>' to be consitent with the LLVM IR ...Quentin Colombet1-2/+2
2016-03-08[MIR] Teach the parser how to parse complex types of generic machine instruct...Quentin Colombet1-0/+4
2015-08-21MIR Serialization: Serialize the pointer IR expression values in the machineAlex Lorenz1-0/+26
2015-08-20MIR Serialization: Change syntax for the call entry pseudo source values.Alex Lorenz1-0/+1
2015-08-19MIR Serialization: Serialize unnamed local IR values in memory operands.Alex Lorenz1-0/+2
2015-08-19MIR Serialization: Serialize instruction's register ties.Alex Lorenz1-0/+1
2015-08-19MIR Serialization: Serialize defined registers that require 'def' register flag.Alex Lorenz1-0/+1
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