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path: root/llvm/lib/Analysis/TargetTransformInfo.cpp
AgeCommit message (Expand)AuthorFilesLines
2019-08-14InferAddressSpaces: Move target intrinsic handling to TTIMatt Arsenault1-0/+10
2019-07-17[AMDGPU] Tune inlining parameters for AMDGPU targetDaniil Fukalov1-0/+4
2019-07-09Revert "[HardwareLoops] NFC - move hardware loop checking code to isHardwareL...Jinsong Ji1-32/+1
2019-07-09[HardwareLoops] NFC - move hardware loop checking code to isHardwareLoopProfi...Chen Zheng1-1/+32
2019-07-03[PowerPC] exclude ICmpZero in LSR if icmp can be replaced in later hardware l...Chen Zheng1-0/+7
2019-06-26[HardwareLoops] NFC - move loop with irreducible control flow checking logic ...Chen Zheng1-7/+11
2019-06-26[HardwareLoops] NFC - move loop with irreducible control flow checking logic ...Chen Zheng1-1/+9
2019-06-25[ExpandMemCmp] Move all options to TargetTransformInfo.Clement Courbet1-3/+3
2019-06-19[NFC] move some hardware loop checking code to a common place for other using.Chen Zheng1-0/+85
2019-06-17[GlobalISel][Localizer] Rewrite localizer to run in 2 phases, inter & intra b...Amara Emerson1-0/+4
2019-06-17[LV] Suppress vectorization in some nontemporal casesWarren Ristow1-0/+10
2019-06-07[CodeGen] Generic Hardware Loop SupportSam Parker1-0/+6
2019-05-28[CostModel] Add really basic support for being able to query the cost of the ...Craig Topper1-0/+10
2019-04-30[ARM] Implement TTI::getMemcpyCostSjoerd Meijer1-0/+6
2019-03-21[ScalarizeMaskedMemIntrin] Add support for scalarizing expandload and compres...Craig Topper1-0/+8
2019-03-12[TTI] Enable analysis of clib functions in getIntrinsicCosts. NFCI.Sjoerd Meijer1-6/+9
2019-02-07[LSR] Generate cross iteration indexesSam Parker1-0/+4
2019-01-19Update the file headers across all of the LLVM projects in the monorepoChandler Carruth1-4/+3
2019-01-16Only promote args when function attributes are compatibleTom Stellard1-0/+6
2018-11-14[TTI] getOperandInfo - a broadcast shuffle means the result is OK_UniformValue Simon Pilgrim1-0/+7
2018-11-13[TTI] Make TargetTransformInfo::getOperandInfo static. NFCI.Simon Pilgrim1-2/+1
2018-11-09[TTI] Flip vector types in getShuffleCost SK_ExtractSubvector callSimon Pilgrim1-1/+1
2018-11-09[CostModel] Add SK_ExtractSubvector handling to getInstructionThroughput (PR3...Simon Pilgrim1-2/+8
2018-10-31[LV] Support vectorization of interleave-groups that require an epilog underDorit Nuzman1-3/+6
2018-10-14recommit 344472 after fixing build failure on ARM and PPC.Dorit Nuzman1-3/+7
2018-10-14revert 344472 due to failures.Dorit Nuzman1-7/+3
2018-10-14[IAI,LV] Add support for vectorizing predicated strided accesses using maskedDorit Nuzman1-3/+7
2018-10-05[LoopVectorizer] Use TTI.getOperandInfo()Jonas Paulsson1-43/+43
2018-07-30Remove trailing spaceFangrui Song1-9/+9
2018-07-11[TargetTransformInfo] Add pow2 analysis for scalar constantsSimon Pilgrim1-0/+6
2018-06-19[IR] move shuffle mask queries from TTI to ShuffleVectorInstSanjay Patel1-168/+18
2018-06-16Fix namespaces. No functionality change.Benjamin Kramer1-1/+1
2018-06-14[CostModel] Cleanup isSingleSourceVectorMask to match other shuffle matchers....Simon Pilgrim1-10/+12
2018-06-14[CostModel] Recognise REVERSE shuffle mask if the elements come from the seco...Simon Pilgrim1-4/+11
2018-06-13[CostModel] Recognise BROADCAST shuffle mask if the elements come from the se...Simon Pilgrim1-4/+11
2018-06-12[CostModel] Replace ShuffleKind::SK_Alternate with ShuffleKind::SK_Select (PR...Simon Pilgrim1-19/+15
2018-06-12Fix signed/unsigned warning. NFCI.Simon Pilgrim1-2/+2
2018-06-12[CostModel] Treat Identity shuffle masks as zero costSimon Pilgrim1-0/+20
2018-05-22[TTI] Add uniform/non-uniform constant Pow2 detection to TargetTransformInfo:...Simon Pilgrim1-13/+28
2018-05-01Remove \brief commands from doxygen comments.Adrian Prantl1-1/+1
2018-04-26[TTI, AArch64] Add transpose shuffle kindMatthew Simpson1-10/+74
2018-04-13[LV] Introduce TTI::getMinimumVFKrzysztof Parzyszek1-0/+4
2018-03-28Plumb useAA through TargetTransformInfo to remove Transforms->CodeGen header ...David Blaikie1-0/+2
2018-03-27[LV] Add TTI::shouldMaximizeVectorBandwidth to allow enabling it per targetKrzysztof Parzyszek1-0/+4
2018-03-26[LSR] Allow giving priority to post-incrementing addressing modesKrzysztof Parzyszek1-0/+14
2018-02-05[LoopStrengthReduce, x86] don't add cost for a cmp that will be macro-fused (...Sanjay Patel1-0/+4
2018-01-30Re-commit : [PowerPC] Add handling for ColdCC calling convention and a pass t...Zaara Syeda1-0/+4
2018-01-17Revert [PowerPC] This reverts commit rL322721Zaara Syeda1-4/+0
2018-01-17[PowerPC] Add handling for ColdCC calling convention and a pass to markZaara Syeda1-0/+4
2017-12-28Revert r321377, it causes regression to https://reviews.llvm.org/P8055.Guozhi Wei1-4/+0
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