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2 hours[llvm] Proofread FuzzingLLVM.rst (#161046)HEADmainKazu Hirata1-6/+6
28 hours[llvm] Proofread BuildingADistribution.rst (#160980)Kazu Hirata1-6/+6
33 hours[NFC] [docs] Fix typo in Programmer's Manual BinaryOperator description ↵Kian Kasad1-1/+1
(#160212) Fixes phrase "This subclasses represents..."
42 hours[lit] Remove support for %TAiden Grossman2-6/+1
This patch removes support for %T from llvm-lit. For now we mark the test unresolved and add an error message noting the substitution is deprecated. This is exactly the same as the error handling for other substitution failures. We intend to remove support for the nice error message once 22 branches as users should have moved over by the they are upgrading to v23. Reviewers: petrhosek, jh7370, ilovepi, pogo59, cmtice Reviewed By: cmtice, jh7370, ilovepi Pull Request: https://github.com/llvm/llvm-project/pull/160028
2 days[llvm] Proofread BugLifeCycle.rst (#160817)Kazu Hirata1-7/+7
2 days[QualGroup][docs] Reorganize QualGroup docs under Reference section (#160021)LeeYoungJoon3-4/+2
This patch makes the following updates to the `QualGroup` documentation: ✅ 1. Move to Reference section Relocated the Qualification Working Group (QualGroup) docs from the main index into the Reference section for better organization and consistency. ✅ 2. Add link in GettingInvolved Inserted a proper link to the QualGroup documentation in the GettingInvolved sync-ups table, improving discoverability for newcomers. ✅ 3. Align structure with Security Group Revised the documentation layout to follow the same structure pattern as the Security Group docs, ensuring consistency across LLVM working group references.
3 days[llvm] Proofread ExtendingLLVM.rst (#160646)Kazu Hirata1-11/+11
4 days[LangRef][VP] Clarify 'ff' mnemonic in vp.load.ff: 'first-fault' (#160649)Shih-Po Hung1-1/+1
The LangRef for llvm.vp.load.ff.* stated that 'ff' stands for 'fault-first or fault-only-first.' This patch corrects this to 'first-fault or fault-only-first.' to match established terminology. - ARM SVE uses "first-fault" [1] - RISC-V V uses "fault-only-first" [2] [1] https://arxiv.org/abs/1803.06185 [2] https://github.com/riscvarchive/riscv-v-spec/blob/master/v-spec.adoc
4 days[llvm] Proofread Docker.rst (#160448)Kazu Hirata1-6/+6
4 days[AMDGPU] Update gfx1250 documentation. NFC (#160457)Stanislav Mekhanoshin1-5/+2110
4 days[IR] Introduce `llvm.errno.tbaa` metadata for errno alias disambiguationAntonio Frighetto1-0/+22
Add a new named module-level frontend-annotated metadata that specifies the TBAA node for an integer access, for which, C/C++ `errno` accesses are guaranteed to use (under strict aliasing). This should allow LLVM to prove the involved memory location/ accesses may not alias `errno`; thus, to perform optimizations around errno-writing libcalls (store-to-load forwarding amongst others). Previous discussion: https://discourse.llvm.org/t/rfc-modelling-errno-memory-effects/82972.
4 days[IR] Forbid mixing condition and operand bundle assumes (#160460)Nikita Popov1-1/+3
Assumes either have a boolean condition, or a number of attribute based operand bundles. Currently, we also allow mixing both forms, though we don't make use of this in practice. This adds additional complexity for code dealing with assumes. Forbid mixing both forms, by requiring that assumes with operand bundles have an i1 true condition.
4 days[LangRef] Do not make align imply dereferenceability (#158062)Nikita Popov1-11/+7
We currently specify that something like `load i8, align 16384` implies that the object is actually dereferenceable up to 16384 bytes, rather than only the one byte implied by the load type. We should stop doing that, because it makes it invalid to infer alignments larger than the load/store type, which is something we do (and want to do). There is some SDAG code that does make use of this property by widening accesses and extracting part of them. However, I believe we should be justifying that based on target-specific guarantees, rather than a generic IR property. (The reasoning goes something like this: Typically, memory protection has page granularity, so widening a load to the alignment will not trap, as long as the alignment is not larger than the page size, which is true for any practically interesting access size.) Fixes https://github.com/llvm/llvm-project/issues/90446.
5 daysReapply "[Coroutines] Add llvm.coro.is_in_ramp and drop return value of ↵Weibo He1-17/+42
llvm.coro.end (#155339)" (#159278) As mentioned in #151067, current design of llvm.coro.end mixes two functionalities: querying where we are and lowering to some code. This patch separate these functionalities into independent intrinsics by introducing a new intrinsic llvm.coro.is_in_ramp. Update a test in inline/ML, Reapply #155339
5 days[NVVM][NVPTX] Add support for tcgen05.mma (#151949)Pradeep Kumar1-0/+458
This commit adds support for tcgen05.mma instructions in NVPTX with tests under CodeGen/NVPTX/tcgen05-mma*. This tcgen05.mma instructions are modeled as intrinsics with multiple flag arguments to model cta_group, mma kind, collector usage etc. The rationale for the design is documented in NVPTXUsage.rst file. For more details, please refer the [PTX ISA](https://docs.nvidia.com/cuda/parallel-thread-execution/?a#tcgen05-mma-instructions)
5 days[DataLayout][LangRef] Split non-integral and unstable pointer propertiesAlexander Richardson1-21/+118
This commit adds finer-grained versions of isNonIntegralAddressSpace() and isNonIntegralPointerType() where the current semantics prohibit introduction of both ptrtoint and inttoptr instructions. The current semantics are too strict for some targets (e.g. AMDGPU/CHERI) where ptrtoint has a stable value, but the pointer has additional metadata. Currently, marking a pointer address space as non-integral also marks it as having an unstable bitwise representation (e.g. when pointers can be changed by a copying GC). This property inhibits a lot of optimizations that are perfectly legal for other non-integral pointers such as fat pointers or CHERI capabilities that have a well-defined bitwise representation but can't be created with only an address. This change splits the properties of non-integral pointers and allows for address spaces to be marked as unstable or non-integral (or both) independently using the 'p' part of the DataLayout string. A 'u' following the p marks the address space as unstable and specifying a index width != representation width marks it as non-integral. Finally, we also add an 'e' flag to mark pointers with external state (such as the CHERI capability validity) state. These pointers require special handling of loads and stores in addition to being non-integral. This does not change the checks in any of the passes yet - we currently keep the existing non-integral behaviour. In the future I plan to audit calls to DL.isNonIntegral[PointerType]() and replace them with the DL.mustNotIntroduce{IntToPtr,PtrToInt}() checks that allow for more optimizations. RFC: https://discourse.llvm.org/t/rfc-finer-grained-non-integral-pointer-properties/83176 Reviewed By: nikic, krzysz00 Pull Request: https://github.com/llvm/llvm-project/pull/105735
5 days[llvm] Proofread GetElementPtr.rst (#160239)Kazu Hirata1-8/+8
6 days[RISCV] Add MC layer support for Andes XAndesVSIntH extension. (#159514)Rux1242-0/+4
Add MC layer support for Andes XAndesVSIntH extension. The spec is available at: https://github.com/andestech/andes-v5-isa/releases/tag/ast-v5_4_0-release
6 days[Remarks] Restructure bitstream remarks to be fully standalone (#156715)Tobias Stadler1-108/+21
Currently there are two serialization modes for bitstream Remarks: standalone and separate. The separate mode splits remark metadata (e.g. the string table) from actual remark data. The metadata is written into the object file by the AsmPrinter, while the remark data is stored in a separate remarks file. This means we can't use bitstream remarks with tools like opt that don't generate an object file. Also, it is confusing to post-process bitstream remarks files, because only the standalone files can be read by llvm-remarkutil. We always need to use dsymutil to convert the separate files to standalone files, which only works for MachO. It is not possible for clang/opt to directly emit bitstream remark files in standalone mode, because the string table can only be serialized after all remarks were emitted. Therefore, this change completely removes the separate serialization mode. Instead, the remark string table is now always written to the end of the remarks file. This requires us to tell the serializer when to finalize remark serialization. This automatically happens when the serializer goes out of scope. However, often the remark file goes out of scope before the serializer is destroyed. To diagnose this, I have added an assert to alert users that they need to explicitly call finalizeLLVMOptimizationRemarks. This change paves the way for further improvements to the remark infrastructure, including more tooling (e.g. #159784), size optimizations for bitstream remarks, and more. Pull Request: https://github.com/llvm/llvm-project/pull/156715
7 days[llvm] Proofread FAQ.rst (#160006)Kazu Hirata1-8/+8
7 daysDocument Policy on supporting newer C++ standard in LLVM codebase (#156823)Mehdi Amini2-2/+8
See RFC: https://discourse.llvm.org/t/policy-on-supporting-newer-c-standard-in-llvm-codebase/88114
8 days[llvm] Proofread DeveloperPolicy.rst (#159955)Kazu Hirata1-5/+5
8 days[llvm] Proofread GettingStarted.rst (#159904)Kazu Hirata1-14/+14
9 days[MCA] Enable customization of individual instructions (#155420)Roman Belenov1-0/+14
Currently MCA takes instruction properties from scheduling model. However, some instructions may execute differently depending on external factors - for example, latency of memory instructions may vary differently depending on whether the load comes from L1 cache, L2 or DRAM. While MCA as a static analysis tool cannot model such differences (and currently takes some static decision, e.g. all memory ops are treated as L1 accesses), it makes sense to allow manual modification of instruction properties to model different behavior (e.g. sensitivity of code performance to cache misses in particular load instruction). This patch addresses this need. The library modification is intentionally generic - arbitrary modifications to InstrDesc are allowed. The tool support is currently limited to changing instruction latencies (single number applies to all output arguments and MaxLatency) via coments in the input assembler code; the format is the like this: add (%eax), eax // LLVM-MCA-LATENCY:100 Users of MCA library can already make additional customizations; command line tool can be extended in the future. Note that InstructionView currently shows per-instruction information according to scheduling model and is not affected by this change. See https://github.com/llvm/llvm-project/issues/133429 for additional clarifications (including explanation why existing customization mechanisms do not provide required functionality) --------- Co-authored-by: Min-Yih Hsu <min@myhsu.dev>
9 days[QualGroup] Update Slides Section, Add AI Transcription Policy, Clean Up ↵Wendi4-22/+60
(#158842) This patch makes the following updates to the `QualGroup.rst` documentation: ✅ 1. Replace slide links with Google Drive URLs Replaced links to slide PDFs previously hosted in `llvm/docs/qual-wg/` with publicly accessible links to the same files stored on Google Drive. ✅ 2. Remove duplicated "Current Topics & Backlog" section Removed an accidental duplication of the "Current Topics & Backlog" section to improve clarity and structure. ✅ 3. Add "AI Transcription Policy" section Introduced a dedicated section documenting the group's practices and expectations regarding AI-based auto-transcription during sync-up meetings. Includes purpose, consent practices, retention details, and how participants can opt out or raise concerns. ✅ 4. Remove `qual-wg` subfolder from `docs` Removed the now-unused `llvm/docs/qual-wg` directory after migrating slide hosting off-repo. No longer needed for qualification group documentation. ✅ 5. Revision of the introduction Updated sentence to reflect the most current and widely relevant safety standards: adding IEC 61508 and IEC 62304 for broader applicability, and replacing EN 50128 (older standard in railways) by EN 50716 for correctness. --------- Co-authored-by: Wendi Urribarri (Woven by Toyota <wendi.urribarri@woven-planet.global>
9 days[IR] enable attaching metadata on ifuncs (#158732)Wael Yehia1-3/+4
Teach the IR parser and writer to support metadata on ifuncs, and update documentation. In PR #153049, we have a use case of attaching the `!associated` metadata to an ifunc. Since an ifunc is similar to a function declaration, it seems natural to allow metadata on ifuncs. Currently, the metadata API allows adding Metadata to llvm::GlobalObject, so the in-memory IR allows for metadata on ifuncs, but the IR reader/writer is not aware of that. --------- Co-authored-by: Wael Yehia <wyehia@ca.ibm.com>
9 days[lit] Add readfile substitutionAiden Grossman1-0/+1
This patch adds a new %{readfile:<file name>} substitution to lit. This is needed for porting a couple of tests to lit's internal shell. These tests are all using subshells to pass some option to a command are not feasible to run within the internal shell without this functionality. Reviewers: petrhosek, jh7370, ilovepi, cmtice Reviewed By: jh7370, cmtice Pull Request: https://github.com/llvm/llvm-project/pull/158441
9 days[llvm-debuginfo-analyzer] Add `--output-sort=(none|id)` option (#145761)Javier Lopez-Gomez1-0/+2
- The output for `--output-sort=id` matches `--output-sort=offset` for the available readers. Tests were updated accordingly. - For `--output-sort=none`, and per `LVReader::sortScopes()`, `LVScope::sort()` is called on the root scope. `LVScope::sort()` has no effect if `getSortFunction() == nullptr`, and thus the elements are currently traversed in the order in which they were initially added. This should change, however, after `LVScope::Children` is removed.
10 days[RISCV] Implement MC support for Zvfofp8min extension (#157014)Jim Lin2-0/+2
This patch adds MC support for Zvfofp8min https://github.com/aswaterman/riscv-misc/blob/main/isa/zvfofp8min.adoc.
10 days[llvm] Proofread GettingStartedVS.rst (#159511)Kazu Hirata1-20/+20
11 days[AMDGPU] Update documentation about DWARF registers mapping. NFC (#159447)Stanislav Mekhanoshin1-4/+4
11 days[AMDGPU] Add gfx1251 subtarget (#159430)Stanislav Mekhanoshin1-0/+16
11 days[llvm] Proofread Passes.rst (#159243)Kazu Hirata1-19/+19
11 days[LangRef] Clarify norecurse attribute definition when a function could occur ↵Usha Gupta1-3/+10
in a cycle in dynamic call-graph (#157087) Update the definition of the `norecurse` attribute to forbid marking a function as `norecurse` if any call path from its body may reach it (possibly through an external function without a visible definition). This makes it clear that `norecurse` excludes both direct and mutual recursion, even when recursion could arise through callees in separate modules. This kind of scenario only arises when norecurse is forced through a llvm user option `-mllvm -force-attribute=<fname>:norecurse` There are a few examples in https://github.com/llvm/llvm-project/issues/157081 which shows that the function attribute inference incorrectly infers norecurse when the behavior (as per new definition) is not enforced.
11 days[IR] NFC: Remove 'experimental' from partial.reduce.add intrinsic (#158637)Sander de Smalen1-6/+6
The partial reduction intrinsics are no longer experimental, because they've been used in production for a while and are unlikely to change.
12 daysRevert "Reapply "[Coroutines] Add llvm.coro.is_in_ramp and drop return value ↵Weibo He1-42/+17
of llvm.coro.end #153404"" (#159236) Reverts llvm/llvm-project#155339 because of CI fail
12 daysReapply "[Coroutines] Add llvm.coro.is_in_ramp and drop return value of ↵Weibo He1-17/+42
llvm.coro.end #153404" (#155339) As mentioned in #151067, current design of llvm.coro.end mixes two functionalities: querying where we are and lowering to some code. This patch separate these functionalities into independent intrinsics by introducing a new intrinsic llvm.coro.is_in_ramp.
12 days[llvm] Proofread GarbageCollection.rst (#158787)Kazu Hirata1-25/+25
13 days[AMDGPU] Add the support for `.cluster_dims` code object metadata (#158721)Shilei Tian1-1/+18
Co-authored-by: Ivan Kosarev <ivan.kosarev@amd.com>
13 days[AMDGPU][Attributor] Add `AAAMDGPUClusterDims` (#158076)Shilei Tian1-0/+9
13 days[docs] Refactor QualGroup.rst: add membership rules, restructure sections ↵Wendi1-20/+131
(#157804) This patch updates the LLVM Qualification Group documentation to reflect current group structure and practices: - Restructures the **Group Composition** section (previously "Participation" + "Contributors") - Adds a formal **member table** with affiliations and community handles - Introduces **participation principles** - Documents **membership criteria**, **nomination process**, and **review cycle** - Corrects references to **meeting materials** (wrong path) These changes aim to improve clarity, inclusiveness, and alignment with similar working groups (e.g., LLVM Security Response Team). --------- Co-authored-by: Wendi Urribarri (Woven by Toyota <wendi.urribarri@woven-planet.global>
13 daysDefault DEBUG_TYPE to the current filename for logging (#158494)Mehdi Amini1-14/+15
This makes it optional to define a debug type and uses the current FileName instead. This both reduced the size of the prefix printed by LDBG() and makes it possible to pass a filename to `--debug-only` to filter on.
2025-09-14[llvm] Proofread Atomics.rst (#158459)Kazu Hirata1-10/+10
2025-09-13[llvm] Proofread TestingGuide.rst (#158411)Kazu Hirata1-16/+16
2025-09-12[AMDGPU] Support lowering of cluster related instrinsics (#157978)Shilei Tian1-0/+7
Since many code are connected, this also changes how workgroup id is lowered. Co-authored-by: Jay Foad <jay.foad@amd.com> Co-authored-by: Ivan Kosarev <ivan.kosarev@amd.com>
2025-09-12[llvm] Proofread ConvergentOperations.rst (#158214)Kazu Hirata1-11/+11
2025-09-12[RISCV][MC] Add MC support of Zibi experimental extension (#127463)Boyao Wang2-0/+4
This adds the MC support of Zibi v0.1 experimental extension. References: * https://lf-riscv.atlassian.net/wiki/spaces/USXX/pages/599261201/Branch+with+Immediate+Zibi+Ratification+Plan * https://lf-riscv.atlassian.net/browse/RVS-3828 * https://github.com/riscv/zibi/releases/tag/v0.1.0
2025-09-11[PGO] Add llvm.loop.estimated_trip_count metadata (#152775)Joel E. Denny1-0/+48
This patch implements the `llvm.loop.estimated_trip_count` metadata discussed in [[RFC] Fix Loop Transformations to Preserve Block Frequencies](https://discourse.llvm.org/t/rfc-fix-loop-transformations-to-preserve-block-frequencies/85785). As the RFC explains, that metadata enables future patches, such as PR #128785, to fix block frequency issues without losing estimated trip counts.
2025-09-11[llvm] Proofread Extensions.rst (#158008)Kazu Hirata1-17/+17
2025-09-11[LangRef] Specify that load of alloca outside lifetime is poison (#157852)Nikita Popov1-0/+4
We consider (in bounds) loads from allocas to always be speculatable, without taking lifetimes into account. This means that such loads cannot be immediate UB. Specify them as returning poison instead. Due to stack coloring, such a load may end up loading from a different alloca, but that's compatible with poison. Stores are still UB, but that's a much more narrow problem (I think the only transform violating that part is store scalar promotion in LICM). Fixes https://github.com/llvm/llvm-project/issues/141892 (and probably a bunch of others...)
generated by cgit v1.1 at 2025-09-28 19:50:05 +0000