diff options
Diffstat (limited to 'llvm/utils')
26 files changed, 105 insertions, 87 deletions
diff --git a/llvm/utils/TableGen/AsmMatcherEmitter.cpp b/llvm/utils/TableGen/AsmMatcherEmitter.cpp index 9f18a11..63c9c3b 100644 --- a/llvm/utils/TableGen/AsmMatcherEmitter.cpp +++ b/llvm/utils/TableGen/AsmMatcherEmitter.cpp @@ -141,7 +141,7 @@ class AsmMatcherInfo; // RegisterSets can be seen in the outputted AsmMatcher tables occasionally, and // can even affect compiler output (at least seen in diagnostics produced when // all matches fail). So we use a type that sorts them consistently. -typedef std::set<const Record *, LessRecordByID> RegisterSet; +using RegisterSet = std::set<const Record *, LessRecordByID>; class AsmMatcherEmitter { const RecordKeeper &Records; @@ -779,8 +779,8 @@ public: std::vector<OperandMatchEntry> OperandMatchInfo; /// Map of Register records to their class information. - typedef std::map<const Record *, ClassInfo *, LessRecordByID> - RegisterClassesTy; + using RegisterClassesTy = + std::map<const Record *, ClassInfo *, LessRecordByID>; RegisterClassesTy RegisterClasses; /// Map of Predicate records to their subtarget information. @@ -1275,7 +1275,7 @@ void AsmMatcherInfo::buildRegisterClasses( const auto &Registers = Target.getRegBank().getRegisters(); auto &RegClassList = Target.getRegBank().getRegClasses(); - typedef std::set<RegisterSet, LessRegisterSet> RegisterSetSet; + using RegisterSetSet = std::set<RegisterSet, LessRegisterSet>; // The register sets used for matching. RegisterSetSet RegisterSets; @@ -1515,7 +1515,7 @@ AsmMatcherInfo::AsmMatcherInfo(const Record *asmParser, void AsmMatcherInfo::buildOperandMatchInfo() { /// Map containing a mask with all operands indices that can be found for /// that class inside a instruction. - typedef std::map<ClassInfo *, unsigned, deref<std::less<>>> OpClassMaskTy; + using OpClassMaskTy = std::map<ClassInfo *, unsigned, deref<std::less<>>>; OpClassMaskTy OpClassMask; bool CallCustomParserForAllOperands = diff --git a/llvm/utils/TableGen/AsmWriterEmitter.cpp b/llvm/utils/TableGen/AsmWriterEmitter.cpp index c8c6c23..8901ecb 100644 --- a/llvm/utils/TableGen/AsmWriterEmitter.cpp +++ b/llvm/utils/TableGen/AsmWriterEmitter.cpp @@ -814,7 +814,7 @@ static unsigned CountNumOperands(StringRef AsmString, unsigned Variant) { namespace { struct AliasPriorityComparator { - typedef std::pair<CodeGenInstAlias, int> ValueType; + using ValueType = std::pair<CodeGenInstAlias, int>; bool operator()(const ValueType &LHS, const ValueType &RHS) const { if (LHS.second == RHS.second) { // We don't actually care about the order, but for consistency it @@ -845,8 +845,8 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) { bool PassSubtarget = AsmWriter->getValueAsInt("PassSubtarget"); // Create a map from the qualified name to a list of potential matches. - typedef std::set<std::pair<CodeGenInstAlias, int>, AliasPriorityComparator> - AliasWithPriority; + using AliasWithPriority = + std::set<std::pair<CodeGenInstAlias, int>, AliasPriorityComparator>; std::map<std::string, AliasWithPriority> AliasMap; for (const Record *R : Records.getAllDerivedDefinitions("InstAlias")) { int Priority = R->getValueAsInt("EmitPriority"); diff --git a/llvm/utils/TableGen/Basic/SequenceToOffsetTable.h b/llvm/utils/TableGen/Basic/SequenceToOffsetTable.h index 8da6fbe..761ef1f 100644 --- a/llvm/utils/TableGen/Basic/SequenceToOffsetTable.h +++ b/llvm/utils/TableGen/Basic/SequenceToOffsetTable.h @@ -44,7 +44,7 @@ inline void printChar(raw_ostream &OS, char C) { /// @tparam Less A stable comparator for SeqT elements. template <typename SeqT, typename Less = std::less<typename SeqT::value_type>> class SequenceToOffsetTable { - typedef typename SeqT::value_type ElemT; + using ElemT = typename SeqT::value_type; // Define a comparator for SeqT that sorts a suffix immediately before a // sequence with that suffix. @@ -58,7 +58,7 @@ class SequenceToOffsetTable { // Keep sequences ordered according to SeqLess so suffixes are easy to find. // Map each sequence to its offset in the table. - typedef std::map<SeqT, unsigned, SeqLess> SeqMap; + using SeqMap = std::map<SeqT, unsigned, SeqLess>; // Sequences added so far, with suffixes removed. SeqMap Seqs; diff --git a/llvm/utils/TableGen/CodeGenMapTable.cpp b/llvm/utils/TableGen/CodeGenMapTable.cpp index 90f0a2a..e502578 100644 --- a/llvm/utils/TableGen/CodeGenMapTable.cpp +++ b/llvm/utils/TableGen/CodeGenMapTable.cpp @@ -84,9 +84,9 @@ #include "llvm/TableGen/Record.h" using namespace llvm; -typedef std::map<std::string, std::vector<const Record *>> InstrRelMapTy; -typedef std::map<std::vector<const Init *>, std::vector<const Record *>> - RowInstrMapTy; +using InstrRelMapTy = std::map<std::string, std::vector<const Record *>>; +using RowInstrMapTy = + std::map<std::vector<const Init *>, std::vector<const Record *>>; namespace { diff --git a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp index 8076ce2..34355d5 100644 --- a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp +++ b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp @@ -776,7 +776,7 @@ bool TypeInfer::EnforceSameSize(TypeSetByHwMode &A, TypeSetByHwMode &B) { if (B.empty()) Changed |= EnforceAny(B); - typedef SmallSet<TypeSize, 2, TypeSizeComparator> TypeSizeSet; + using TypeSizeSet = SmallSet<TypeSize, 2, TypeSizeComparator>; auto NoSize = [](const TypeSizeSet &Sizes, MVT T) -> bool { return !Sizes.contains(T.getSizeInBits()); @@ -4129,7 +4129,7 @@ void CodeGenDAGPatterns::ParseInstructions() { } } -typedef std::pair<TreePatternNode *, unsigned> NameRecord; +using NameRecord = std::pair<TreePatternNode *, unsigned>; static void FindNames(TreePatternNode &P, std::map<StringRef, NameRecord> &Names, @@ -4590,7 +4590,7 @@ void CodeGenDAGPatterns::ExpandHwModeBasedTypes() { } /// Dependent variable map for CodeGenDAGPattern variant generation -typedef StringMap<int> DepVarMap; +using DepVarMap = StringMap<int>; static void FindDepVarsOf(TreePatternNode &N, DepVarMap &DepMap) { if (N.isLeaf()) { diff --git a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.h b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.h index 2ed8d13..aa9a0a4 100644 --- a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.h +++ b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.h @@ -349,7 +349,7 @@ private: }; /// Set type used to track multiply used variables in patterns -typedef StringSet<> MultipleUseVarSet; +using MultipleUseVarSet = StringSet<>; /// SDTypeConstraint - This is a discriminated union of constraints, /// corresponding to the SDTypeConstraint tablegen class in Target.td. @@ -1217,13 +1217,13 @@ public: iterator_range<pf_iterator> ptfs() const { return PatternFragments; } // Patterns to match information. - typedef std::vector<PatternToMatch>::const_iterator ptm_iterator; + using ptm_iterator = std::vector<PatternToMatch>::const_iterator; ptm_iterator ptm_begin() const { return PatternsToMatch.begin(); } ptm_iterator ptm_end() const { return PatternsToMatch.end(); } iterator_range<ptm_iterator> ptms() const { return PatternsToMatch; } /// Parse the Pattern for an instruction, and insert the result in DAGInsts. - typedef std::map<const Record *, DAGInstruction, LessRecordByID> DAGInstMap; + using DAGInstMap = std::map<const Record *, DAGInstruction, LessRecordByID>; void parseInstructionPattern(CodeGenInstruction &CGI, const ListInit *Pattern, DAGInstMap &DAGInsts); diff --git a/llvm/utils/TableGen/Common/CodeGenHwModes.h b/llvm/utils/TableGen/Common/CodeGenHwModes.h index 5e1b31a..55062b6 100644 --- a/llvm/utils/TableGen/Common/CodeGenHwModes.h +++ b/llvm/utils/TableGen/Common/CodeGenHwModes.h @@ -36,7 +36,7 @@ struct HwMode { struct HwModeSelect { HwModeSelect(const Record *R, CodeGenHwModes &CGH); - typedef std::pair<unsigned, const Record *> PairType; + using PairType = std::pair<unsigned, const Record *>; std::vector<PairType> Items; void dump() const; }; diff --git a/llvm/utils/TableGen/Common/CodeGenInstruction.h b/llvm/utils/TableGen/Common/CodeGenInstruction.h index ed0bfa7..7295837 100644 --- a/llvm/utils/TableGen/Common/CodeGenInstruction.h +++ b/llvm/utils/TableGen/Common/CodeGenInstruction.h @@ -158,8 +158,8 @@ public: OperandInfo &back() { return OperandList.back(); } const OperandInfo &back() const { return OperandList.back(); } - typedef std::vector<OperandInfo>::iterator iterator; - typedef std::vector<OperandInfo>::const_iterator const_iterator; + using iterator = std::vector<OperandInfo>::iterator; + using const_iterator = std::vector<OperandInfo>::const_iterator; iterator begin() { return OperandList.begin(); } const_iterator begin() const { return OperandList.begin(); } iterator end() { return OperandList.end(); } diff --git a/llvm/utils/TableGen/Common/CodeGenRegisters.cpp b/llvm/utils/TableGen/Common/CodeGenRegisters.cpp index 2eb94b7e..2f0ff3f 100644 --- a/llvm/utils/TableGen/Common/CodeGenRegisters.cpp +++ b/llvm/utils/TableGen/Common/CodeGenRegisters.cpp @@ -2163,7 +2163,7 @@ void CodeGenRegBank::computeRegUnitLaneMasks() { CodeGenRegister::RegUnitLaneMaskList RegUnitLaneMasks( RegUnits.count(), LaneBitmask::getAll()); // Iterate through SubRegisters. - typedef CodeGenRegister::SubRegMap SubRegMap; + using SubRegMap = CodeGenRegister::SubRegMap; const SubRegMap &SubRegs = Register.getSubRegs(); for (auto [SubRegIndex, SubReg] : SubRegs) { // Ignore non-leaf subregisters, their lane masks are fully covered by @@ -2282,9 +2282,8 @@ void CodeGenRegBank::inferCommonSubClass(CodeGenRegisterClass *RC) { // void CodeGenRegBank::inferSubClassWithSubReg(CodeGenRegisterClass *RC) { // Map SubRegIndex to set of registers in RC supporting that SubRegIndex. - typedef std::map<const CodeGenSubRegIndex *, CodeGenRegister::Vec, - deref<std::less<>>> - SubReg2SetMap; + using SubReg2SetMap = std::map<const CodeGenSubRegIndex *, + CodeGenRegister::Vec, deref<std::less<>>>; // Compute the set of registers supporting each SubRegIndex. SubReg2SetMap SRSets; diff --git a/llvm/utils/TableGen/Common/CodeGenRegisters.h b/llvm/utils/TableGen/Common/CodeGenRegisters.h index 89dac12..c02d04b 100644 --- a/llvm/utils/TableGen/Common/CodeGenRegisters.h +++ b/llvm/utils/TableGen/Common/CodeGenRegisters.h @@ -93,9 +93,8 @@ public: std::string getQualifiedName() const; // Map of composite subreg indices. - typedef std::map<CodeGenSubRegIndex *, CodeGenSubRegIndex *, - deref<std::less<>>> - CompMap; + using CompMap = + std::map<CodeGenSubRegIndex *, CodeGenSubRegIndex *, deref<std::less<>>>; // Returns the subreg index that results from composing this with Idx. // Returns NULL if this and Idx don't compose. @@ -180,8 +179,8 @@ public: bool Constant = false; // Map SubRegIndex -> Register. - typedef std::map<CodeGenSubRegIndex *, CodeGenRegister *, deref<std::less<>>> - SubRegMap; + using SubRegMap = + std::map<CodeGenSubRegIndex *, CodeGenRegister *, deref<std::less<>>>; CodeGenRegister(const Record *R, unsigned Enum); @@ -220,7 +219,7 @@ public: return SubReg2Idx.lookup(Reg); } - typedef std::vector<const CodeGenRegister *> SuperRegList; + using SuperRegList = std::vector<const CodeGenRegister *>; // Get the list of super-registers in topological order, small to large. // This is valid after computeSubRegs visits all registers during RegBank @@ -248,8 +247,8 @@ public: } // List of register units in ascending order. - typedef SparseBitVector<> RegUnitList; - typedef SmallVector<LaneBitmask, 16> RegUnitLaneMaskList; + using RegUnitList = SparseBitVector<>; + using RegUnitLaneMaskList = SmallVector<LaneBitmask, 16>; // How many entries in RegUnitList are native? RegUnitList NativeRegUnits; @@ -281,7 +280,7 @@ public: unsigned getWeight(const CodeGenRegBank &RegBank) const; // Canonically ordered set. - typedef std::vector<const CodeGenRegister *> Vec; + using Vec = std::vector<const CodeGenRegister *>; private: bool SubRegsComplete; @@ -590,7 +589,7 @@ struct RegUnit { // Each RegUnitSet is a sorted vector with a name. struct RegUnitSet { - typedef std::vector<unsigned>::const_iterator iterator; + using iterator = std::vector<unsigned>::const_iterator; std::string Name; std::vector<unsigned> Units; @@ -602,7 +601,7 @@ struct RegUnitSet { // Base vector for identifying TopoSigs. The contents uniquely identify a // TopoSig, only computeSuperRegs needs to know how. -typedef SmallVector<unsigned, 16> TopoSigId; +using TopoSigId = SmallVector<unsigned, 16>; // CodeGenRegBank - Represent a target's registers and the relations between // them. @@ -621,8 +620,8 @@ class CodeGenRegBank { CodeGenSubRegIndex *createSubRegIndex(StringRef Name, StringRef NameSpace); - typedef std::map<SmallVector<CodeGenSubRegIndex *, 8>, CodeGenSubRegIndex *> - ConcatIdxMap; + using ConcatIdxMap = + std::map<SmallVector<CodeGenSubRegIndex *, 8>, CodeGenSubRegIndex *>; ConcatIdxMap ConcatIdx; // Registers. @@ -639,7 +638,7 @@ class CodeGenRegBank { // Register classes. std::list<CodeGenRegisterClass> RegClasses; DenseMap<const Record *, CodeGenRegisterClass *> Def2RC; - typedef std::map<CodeGenRegisterClass::Key, CodeGenRegisterClass *> RCKeyMap; + using RCKeyMap = std::map<CodeGenRegisterClass::Key, CodeGenRegisterClass *>; RCKeyMap Key2RC; // Register categories. diff --git a/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.h b/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.h index 84dfca4..d71fdb4 100644 --- a/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.h +++ b/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.h @@ -528,10 +528,10 @@ protected: ArrayRef<SMLoc> SrcLoc; - typedef std::tuple<const Record *, unsigned, unsigned> - DefinedComplexPatternSubOperand; - typedef StringMap<DefinedComplexPatternSubOperand> - DefinedComplexPatternSubOperandMap; + using DefinedComplexPatternSubOperand = + std::tuple<const Record *, unsigned, unsigned>; + using DefinedComplexPatternSubOperandMap = + StringMap<DefinedComplexPatternSubOperand>; /// A map of Symbolic Names to ComplexPattern sub-operands. DefinedComplexPatternSubOperandMap ComplexSubOperands; /// A map used to for multiple referenced error check of ComplexSubOperand. @@ -1775,7 +1775,7 @@ public: /// * Has an nsw/nuw flag or doesn't. class InstructionMatcher final : public PredicateListMatcher<PredicateMatcher> { protected: - typedef std::vector<std::unique_ptr<OperandMatcher>> OperandVec; + using OperandVec = std::vector<std::unique_ptr<OperandMatcher>>; RuleMatcher &Rule; diff --git a/llvm/utils/TableGen/Common/InfoByHwMode.cpp b/llvm/utils/TableGen/Common/InfoByHwMode.cpp index 2b3155c..a16fdbb 100644 --- a/llvm/utils/TableGen/Common/InfoByHwMode.cpp +++ b/llvm/utils/TableGen/Common/InfoByHwMode.cpp @@ -174,7 +174,7 @@ bool RegSizeInfoByHwMode::hasStricterSpillThan( } void RegSizeInfoByHwMode::writeToStream(raw_ostream &OS) const { - typedef decltype(Map)::value_type PairType; + using PairType = decltype(Map)::value_type; std::vector<const PairType *> Pairs; for (const auto &P : Map) Pairs.push_back(&P); diff --git a/llvm/utils/TableGen/Common/InfoByHwMode.h b/llvm/utils/TableGen/Common/InfoByHwMode.h index c730b73..ef688a6 100644 --- a/llvm/utils/TableGen/Common/InfoByHwMode.h +++ b/llvm/utils/TableGen/Common/InfoByHwMode.h @@ -87,10 +87,10 @@ void union_modes(const InfoByHwMode<InfoT> &A, const InfoByHwMode<InfoT> &B, } template <typename InfoT> struct InfoByHwMode { - typedef std::map<unsigned, InfoT> MapType; - typedef typename MapType::value_type PairType; - typedef typename MapType::iterator iterator; - typedef typename MapType::const_iterator const_iterator; + using MapType = std::map<unsigned, InfoT>; + using PairType = typename MapType::value_type; + using iterator = typename MapType::iterator; + using const_iterator = typename MapType::const_iterator; InfoByHwMode() = default; InfoByHwMode(const MapType &M) : Map(M) {} diff --git a/llvm/utils/TableGen/FastISelEmitter.cpp b/llvm/utils/TableGen/FastISelEmitter.cpp index c4dbb14..ed05af0 100644 --- a/llvm/utils/TableGen/FastISelEmitter.cpp +++ b/llvm/utils/TableGen/FastISelEmitter.cpp @@ -71,7 +71,7 @@ public: const TreePredicateFn &getPredicate(unsigned Idx) { return PredsByName[Idx]; } - typedef std::vector<TreePredicateFn>::const_iterator iterator; + using iterator = std::vector<TreePredicateFn>::const_iterator; iterator begin() const { return PredsByName.begin(); } iterator end() const { return PredsByName.end(); } }; @@ -366,12 +366,12 @@ struct OperandsSignature { class FastISelMap { // A multimap is needed instead of a "plain" map because the key is // the instruction's complexity (an int) and they are not unique. - typedef std::multimap<int, InstructionMemo> PredMap; - typedef std::map<MVT::SimpleValueType, PredMap> RetPredMap; - typedef std::map<MVT::SimpleValueType, RetPredMap> TypeRetPredMap; - typedef std::map<StringRef, TypeRetPredMap> OpcodeTypeRetPredMap; - typedef std::map<OperandsSignature, OpcodeTypeRetPredMap> - OperandsOpcodeTypeRetPredMap; + using PredMap = std::multimap<int, InstructionMemo>; + using RetPredMap = std::map<MVT::SimpleValueType, PredMap>; + using TypeRetPredMap = std::map<MVT::SimpleValueType, RetPredMap>; + using OpcodeTypeRetPredMap = std::map<StringRef, TypeRetPredMap>; + using OperandsOpcodeTypeRetPredMap = + std::map<OperandsSignature, OpcodeTypeRetPredMap>; OperandsOpcodeTypeRetPredMap SimplePatterns; diff --git a/llvm/utils/TableGen/InstrInfoEmitter.cpp b/llvm/utils/TableGen/InstrInfoEmitter.cpp index e725de1..ee3cd8c 100644 --- a/llvm/utils/TableGen/InstrInfoEmitter.cpp +++ b/llvm/utils/TableGen/InstrInfoEmitter.cpp @@ -68,9 +68,9 @@ private: void emitEnums(raw_ostream &OS, ArrayRef<const CodeGenInstruction *> NumberedInstructions); - typedef std::vector<std::string> OperandInfoTy; - typedef std::vector<OperandInfoTy> OperandInfoListTy; - typedef std::map<OperandInfoTy, unsigned> OperandInfoMapTy; + using OperandInfoTy = std::vector<std::string>; + using OperandInfoListTy = std::vector<OperandInfoTy>; + using OperandInfoMapTy = std::map<OperandInfoTy, unsigned>; /// Generate member functions in the target-specific GenInstrInfo class. /// diff --git a/llvm/utils/TableGen/OptionParserEmitter.cpp b/llvm/utils/TableGen/OptionParserEmitter.cpp index 48ae1a0..45edde3 100644 --- a/llvm/utils/TableGen/OptionParserEmitter.cpp +++ b/llvm/utils/TableGen/OptionParserEmitter.cpp @@ -266,8 +266,8 @@ static void emitOptionParser(const RecordKeeper &Records, raw_ostream &OS) { emitSourceFileHeader("Option Parsing Definitions", OS); // Generate prefix groups. - typedef SmallVector<SmallString<2>, 2> PrefixKeyT; - typedef std::map<PrefixKeyT, unsigned> PrefixesT; + using PrefixKeyT = SmallVector<SmallString<2>, 2>; + using PrefixesT = std::map<PrefixKeyT, unsigned>; PrefixesT Prefixes; Prefixes.try_emplace(PrefixKeyT(), 0); for (const Record &R : llvm::make_pointee_range(Opts)) { @@ -277,8 +277,8 @@ static void emitOptionParser(const RecordKeeper &Records, raw_ostream &OS) { } // Generate sub command groups. - typedef SmallVector<StringRef, 2> SubCommandKeyT; - typedef std::map<SubCommandKeyT, unsigned> SubCommandIDsT; + using SubCommandKeyT = SmallVector<StringRef, 2>; + using SubCommandIDsT = std::map<SubCommandKeyT, unsigned>; SubCommandIDsT SubCommandIDs; auto PrintSubCommandIdsOffset = [&SubCommandIDs, &OS](const Record &R) { @@ -378,9 +378,9 @@ static void emitOptionParser(const RecordKeeper &Records, raw_ostream &OS) { assert((CurIndex == 0 || !SubCommand.empty()) && "Only first subcommand set should be empty!"); for (const auto &SubCommandKey : SubCommand) { - auto It = std::find_if( - SubCommands.begin(), SubCommands.end(), - [&](const Record *R) { return R->getName() == SubCommandKey; }); + auto It = llvm::find_if(SubCommands, [&](const Record *R) { + return R->getName() == SubCommandKey; + }); assert(It != SubCommands.end() && "SubCommand not found"); OS << ", " << std::distance(SubCommands.begin(), It) << " /* '" << SubCommandKey << "' */"; diff --git a/llvm/utils/TableGen/RegisterBankEmitter.cpp b/llvm/utils/TableGen/RegisterBankEmitter.cpp index 60aa2d8..271888b 100644 --- a/llvm/utils/TableGen/RegisterBankEmitter.cpp +++ b/llvm/utils/TableGen/RegisterBankEmitter.cpp @@ -30,7 +30,7 @@ namespace { class RegisterBank { /// A vector of register classes that are included in the register bank. - typedef std::vector<const CodeGenRegisterClass *> RegisterClassesTy; + using RegisterClassesTy = std::vector<const CodeGenRegisterClass *>; private: const Record &TheDef; diff --git a/llvm/utils/TableGen/RegisterInfoEmitter.cpp b/llvm/utils/TableGen/RegisterInfoEmitter.cpp index a67a5a9..3e6e23f 100644 --- a/llvm/utils/TableGen/RegisterInfoEmitter.cpp +++ b/llvm/utils/TableGen/RegisterInfoEmitter.cpp @@ -623,8 +623,8 @@ static void printSubRegIndex(raw_ostream &OS, const CodeGenSubRegIndex *Idx) { // The initial value depends on the specific list. The list is terminated by a // 0 differential which means we can't encode repeated elements. -typedef SmallVector<int16_t, 4> DiffVec; -typedef SmallVector<LaneBitmask, 4> MaskVec; +using DiffVec = SmallVector<int16_t, 4>; +using MaskVec = SmallVector<LaneBitmask, 4>; // Fills V with differentials between every two consecutive elements of List. static DiffVec &diffEncode(DiffVec &V, SparseBitVector<> List) { @@ -912,7 +912,7 @@ void RegisterInfoEmitter::runMCDesc(raw_ostream &OS) { auto &SubRegIndices = RegBank.getSubRegIndices(); // The lists of sub-registers and super-registers go in the same array. That // allows us to share suffixes. - typedef std::vector<const CodeGenRegister *> RegVec; + using RegVec = std::vector<const CodeGenRegister *>; // Differentially encoded lists. SequenceToOffsetTable<DiffVec> DiffSeqs; @@ -926,7 +926,7 @@ void RegisterInfoEmitter::runMCDesc(raw_ostream &OS) { // Keep track of sub-register names as well. These are not differentially // encoded. - typedef SmallVector<const CodeGenSubRegIndex *, 4> SubRegIdxVec; + using SubRegIdxVec = SmallVector<const CodeGenSubRegIndex *, 4>; SequenceToOffsetTable<SubRegIdxVec, deref<std::less<>>> SubRegIdxSeqs( /*Terminator=*/std::nullopt); SmallVector<SubRegIdxVec, 4> SubRegIdxLists(Regs.size()); @@ -1348,7 +1348,7 @@ void RegisterInfoEmitter::runTargetDesc(raw_ostream &OS) { // Every bit mask present in the list has at least one bit set. // Compress the sub-reg index lists. - typedef std::vector<const CodeGenSubRegIndex *> IdxList; + using IdxList = std::vector<const CodeGenSubRegIndex *>; SmallVector<IdxList, 8> SuperRegIdxLists(RegisterClasses.size()); SequenceToOffsetTable<IdxList, deref<std::less<>>> SuperRegIdxSeqs; BitVector MaskBV(RegisterClasses.size()); diff --git a/llvm/utils/TableGen/SearchableTableEmitter.cpp b/llvm/utils/TableGen/SearchableTableEmitter.cpp index d17d90b..0dc8c92 100644 --- a/llvm/utils/TableGen/SearchableTableEmitter.cpp +++ b/llvm/utils/TableGen/SearchableTableEmitter.cpp @@ -116,7 +116,7 @@ public: void run(raw_ostream &OS); private: - typedef std::pair<const Init *, int> SearchTableEntry; + using SearchTableEntry = std::pair<const Init *, int>; enum TypeContext { TypeInStaticStruct, diff --git a/llvm/utils/TableGen/X86DisassemblerTables.cpp b/llvm/utils/TableGen/X86DisassemblerTables.cpp index b8c3c02..483fc58 100644 --- a/llvm/utils/TableGen/X86DisassemblerTables.cpp +++ b/llvm/utils/TableGen/X86DisassemblerTables.cpp @@ -864,8 +864,8 @@ void DisassemblerTables::emitInstructionInfo(raw_ostream &o, o << "static const struct OperandSpecifier x86OperandSets[][" << X86_MAX_OPERANDS << "] = {\n"; - typedef SmallVector<std::pair<OperandEncoding, OperandType>, X86_MAX_OPERANDS> - OperandListTy; + using OperandListTy = + SmallVector<std::pair<OperandEncoding, OperandType>, X86_MAX_OPERANDS>; std::map<OperandListTy, unsigned> OperandSets; unsigned OperandSetNum = 0; diff --git a/llvm/utils/TableGen/X86DisassemblerTables.h b/llvm/utils/TableGen/X86DisassemblerTables.h index 0f38274..325bb57 100644 --- a/llvm/utils/TableGen/X86DisassemblerTables.h +++ b/llvm/utils/TableGen/X86DisassemblerTables.h @@ -51,7 +51,7 @@ private: std::unique_ptr<ContextDecision> Tables[12]; // Table of ModRM encodings. - typedef std::map<std::vector<unsigned>, unsigned> ModRMMapTy; + using ModRMMapTy = std::map<std::vector<unsigned>, unsigned>; mutable ModRMMapTy ModRMTable; /// The instruction information table diff --git a/llvm/utils/TableGen/X86FoldTablesEmitter.cpp b/llvm/utils/TableGen/X86FoldTablesEmitter.cpp index 6f523b5..cbb7f89 100644 --- a/llvm/utils/TableGen/X86FoldTablesEmitter.cpp +++ b/llvm/utils/TableGen/X86FoldTablesEmitter.cpp @@ -175,9 +175,8 @@ class X86FoldTablesEmitter { } }; - typedef std::map<const CodeGenInstruction *, X86FoldTableEntry, - CompareInstrsByEnum> - FoldTable; + using FoldTable = std::map<const CodeGenInstruction *, X86FoldTableEntry, + CompareInstrsByEnum>; // Table2Addr - Holds instructions which their memory form performs // load+store. // diff --git a/llvm/utils/TableGen/X86InstrMappingEmitter.cpp b/llvm/utils/TableGen/X86InstrMappingEmitter.cpp index 2745ba7..9abb194 100644 --- a/llvm/utils/TableGen/X86InstrMappingEmitter.cpp +++ b/llvm/utils/TableGen/X86InstrMappingEmitter.cpp @@ -35,10 +35,10 @@ class X86InstrMappingEmitter { // to make the search more efficient std::map<uint64_t, std::vector<const CodeGenInstruction *>> CompressedInsts; - typedef std::pair<const CodeGenInstruction *, const CodeGenInstruction *> - Entry; - typedef std::map<StringRef, std::vector<const CodeGenInstruction *>> - PredicateInstMap; + using Entry = + std::pair<const CodeGenInstruction *, const CodeGenInstruction *>; + using PredicateInstMap = + std::map<StringRef, std::vector<const CodeGenInstruction *>>; // Hold all compressed instructions that need to check predicate PredicateInstMap PredicateInsts; diff --git a/llvm/utils/gn/secondary/llvm/test/BUILD.gn b/llvm/utils/gn/secondary/llvm/test/BUILD.gn index b297dbd..1c91cb8 100644 --- a/llvm/utils/gn/secondary/llvm/test/BUILD.gn +++ b/llvm/utils/gn/secondary/llvm/test/BUILD.gn @@ -195,6 +195,12 @@ write_lit_config("lit_site_cfg") { extra_values += [ "LLVM_ENABLE_LIBXML2=0" ] # Must be 0. } + if (llvm_enable_ondisk_cas) { + extra_values += [ "LLVM_ENABLE_ONDISK_CAS=1" ] + } else { + extra_values += [ "LLVM_ENABLE_ONDISK_CAS=0" ] # Must be 0. + } + if (llvm_enable_expensive_checks) { extra_values += [ "LLVM_ENABLE_EXPENSIVE_CHECKS=1" ] } else { @@ -265,6 +271,7 @@ group("test") { "//llvm/tools/llvm-as", "//llvm/tools/llvm-bcanalyzer", "//llvm/tools/llvm-c-test", + "//llvm/tools/llvm-cas", "//llvm/tools/llvm-cat", "//llvm/tools/llvm-cfi-verify", "//llvm/tools/llvm-cgdata", diff --git a/llvm/utils/gn/secondary/llvm/tools/llvm-cas/BUILD.gn b/llvm/utils/gn/secondary/llvm/tools/llvm-cas/BUILD.gn new file mode 100644 index 0000000..d4cd26a --- /dev/null +++ b/llvm/utils/gn/secondary/llvm/tools/llvm-cas/BUILD.gn @@ -0,0 +1,16 @@ +import("//llvm/utils/TableGen/tablegen.gni") + +tablegen("Options") { + visibility = [ ":llvm-cas" ] + args = [ "-gen-opt-parser-defs" ] +} + +executable("llvm-cas") { + deps = [ + ":Options", + "//llvm/lib/CAS", + "//llvm/lib/Option", + "//llvm/lib/Support", + ] + sources = [ "llvm-cas.cpp" ] +} diff --git a/llvm/utils/prepare-code-coverage-artifact.py b/llvm/utils/prepare-code-coverage-artifact.py index b865211..5d4f549 100755 --- a/llvm/utils/prepare-code-coverage-artifact.py +++ b/llvm/utils/prepare-code-coverage-artifact.py @@ -1,6 +1,4 @@ -#!/usr/bin/env python - -from __future__ import print_function +#!/usr/bin/env python3 """Prepare a code coverage artifact. |