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-rw-r--r--llvm/utils/TableGen/Basic/RISCVTargetDefEmitter.cpp28
-rw-r--r--llvm/utils/TableGen/Common/Types.cpp8
-rw-r--r--llvm/utils/TableGen/FastISelEmitter.cpp2
-rw-r--r--llvm/utils/TableGen/X86DisassemblerTables.cpp11
-rw-r--r--llvm/utils/TableGen/X86RecognizableInstr.cpp2
5 files changed, 29 insertions, 22 deletions
diff --git a/llvm/utils/TableGen/Basic/RISCVTargetDefEmitter.cpp b/llvm/utils/TableGen/Basic/RISCVTargetDefEmitter.cpp
index df14c77..f795937 100644
--- a/llvm/utils/TableGen/Basic/RISCVTargetDefEmitter.cpp
+++ b/llvm/utils/TableGen/Basic/RISCVTargetDefEmitter.cpp
@@ -68,13 +68,14 @@ static void emitRISCVExtensions(const RecordKeeper &Records, raw_ostream &OS) {
if (!Extensions.empty()) {
OS << "\nstatic constexpr ImpliedExtsEntry ImpliedExts[] = {\n";
for (const Record *Ext : Extensions) {
- auto ImpliesList = Ext->getValueAsListOfDefs("Implies");
+ std::vector<const Record *> ImpliesList =
+ Ext->getValueAsListOfDefs("Implies");
if (ImpliesList.empty())
continue;
StringRef Name = getExtensionName(Ext);
- for (auto *ImpliedExt : ImpliesList) {
+ for (const Record *ImpliedExt : ImpliesList) {
if (!ImpliedExt->isSubClassOf("RISCVExtension"))
continue;
@@ -150,11 +151,12 @@ static void emitRISCVProfiles(const RecordKeeper &Records, raw_ostream &OS) {
OS << "#ifdef GET_SUPPORTED_PROFILES\n";
OS << "#undef GET_SUPPORTED_PROFILES\n\n";
- auto Profiles = Records.getAllDerivedDefinitionsIfDefined("RISCVProfile");
+ ArrayRef<const Record *> Profiles =
+ Records.getAllDerivedDefinitionsIfDefined("RISCVProfile");
if (!Profiles.empty()) {
printProfileTable(OS, Profiles, /*Experimental=*/false);
- bool HasExperimentalProfiles = any_of(Profiles, [&](auto &Rec) {
+ bool HasExperimentalProfiles = any_of(Profiles, [&](const Record *Rec) {
return Rec->getValueAsBit("Experimental");
});
if (HasExperimentalProfiles)
@@ -173,15 +175,17 @@ static void emitRISCVProcs(const RecordKeeper &RK, raw_ostream &OS) {
// Iterate on all definition records.
for (const Record *Rec :
RK.getAllDerivedDefinitionsIfDefined("RISCVProcessorModel")) {
- const std::vector<const Record *> &Features =
+ std::vector<const Record *> Features =
Rec->getValueAsListOfDefs("Features");
- bool FastScalarUnalignedAccess = any_of(Features, [&](auto &Feature) {
- return Feature->getValueAsString("Name") == "unaligned-scalar-mem";
- });
-
- bool FastVectorUnalignedAccess = any_of(Features, [&](auto &Feature) {
- return Feature->getValueAsString("Name") == "unaligned-vector-mem";
- });
+ bool FastScalarUnalignedAccess =
+ any_of(Features, [&](const Record *Feature) {
+ return Feature->getValueAsString("Name") == "unaligned-scalar-mem";
+ });
+
+ bool FastVectorUnalignedAccess =
+ any_of(Features, [&](const Record *Feature) {
+ return Feature->getValueAsString("Name") == "unaligned-vector-mem";
+ });
OS << "PROC(" << Rec->getName() << ", {\"" << Rec->getValueAsString("Name")
<< "\"}, {\"";
diff --git a/llvm/utils/TableGen/Common/Types.cpp b/llvm/utils/TableGen/Common/Types.cpp
index 35b79b3..8e8d6f6 100644
--- a/llvm/utils/TableGen/Common/Types.cpp
+++ b/llvm/utils/TableGen/Common/Types.cpp
@@ -8,16 +8,12 @@
#include "Types.h"
-// For LLVM_ATTRIBUTE_UNUSED
-#include "llvm/Support/Compiler.h"
-
#include <cassert>
using namespace llvm;
-const char *
-llvm::getMinimalTypeForRange(uint64_t Range,
- unsigned MaxSize LLVM_ATTRIBUTE_UNUSED) {
+const char *llvm::getMinimalTypeForRange(uint64_t Range,
+ [[maybe_unused]] unsigned MaxSize) {
// TODO: The original callers only used 32 and 64 so these are the only
// values permitted. Rather than widen the supported values we should
// allow 64 for the callers that currently use 32 and remove the
diff --git a/llvm/utils/TableGen/FastISelEmitter.cpp b/llvm/utils/TableGen/FastISelEmitter.cpp
index dba8bde..e0be104 100644
--- a/llvm/utils/TableGen/FastISelEmitter.cpp
+++ b/llvm/utils/TableGen/FastISelEmitter.cpp
@@ -555,7 +555,7 @@ void FastISelMap::collectPatterns(const CodeGenDAGPatterns &CGP) {
raw_string_ostream SuffixOS(ManglingSuffix);
Operands.PrintManglingSuffix(SuffixOS, ImmediatePredicates, true);
if (!StringSwitch<bool>(ManglingSuffix)
- .Cases("", "r", "rr", "ri", "i", "f", true)
+ .Cases({"", "r", "rr", "ri", "i", "f"}, true)
.Default(false))
continue;
diff --git a/llvm/utils/TableGen/X86DisassemblerTables.cpp b/llvm/utils/TableGen/X86DisassemblerTables.cpp
index ed7a4fe..3414190 100644
--- a/llvm/utils/TableGen/X86DisassemblerTables.cpp
+++ b/llvm/utils/TableGen/X86DisassemblerTables.cpp
@@ -99,6 +99,7 @@ static inline bool inheritsFrom(InstructionContext child,
(noPrefix && inheritsFrom(child, IC_XS, noPrefix)));
case IC_64BIT:
return (inheritsFrom(child, IC_64BIT_REXW) ||
+ inheritsFrom(child, IC_64BIT_REX2) ||
(noPrefix && inheritsFrom(child, IC_64BIT_OPSIZE, noPrefix)) ||
(!AdSize64 && inheritsFrom(child, IC_64BIT_ADSIZE)) ||
(noPrefix && inheritsFrom(child, IC_64BIT_XD, noPrefix)) ||
@@ -151,8 +152,10 @@ static inline bool inheritsFrom(InstructionContext child,
case IC_64BIT_REXW_XS:
case IC_64BIT_REXW_OPSIZE:
case IC_64BIT_REXW_ADSIZE:
- case IC_64BIT_REX2:
+ case IC_64BIT_REX2_REXW:
return false;
+ case IC_64BIT_REX2:
+ return inheritsFrom(child, IC_64BIT_REX2_REXW);
case IC_VEX:
return (VEX_LIG && WIG && inheritsFrom(child, IC_VEX_L_W)) ||
(WIG && inheritsFrom(child, IC_VEX_W)) ||
@@ -980,9 +983,11 @@ void DisassemblerTables::emitContextTable(raw_ostream &o, unsigned &i) const {
if ((index & ATTR_EVEXB) && (index & ATTR_EVEXU))
o << "_U";
}
- } else if ((index & ATTR_64BIT) && (index & ATTR_REX2))
+ } else if ((index & ATTR_64BIT) && (index & ATTR_REX2)) {
o << "IC_64BIT_REX2";
- else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XS))
+ if (index & ATTR_REXW)
+ o << "_REXW";
+ } else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XS))
o << "IC_64BIT_REXW_XS";
else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XD))
o << "IC_64BIT_REXW_XD";
diff --git a/llvm/utils/TableGen/X86RecognizableInstr.cpp b/llvm/utils/TableGen/X86RecognizableInstr.cpp
index e87a1c9..a006888 100644
--- a/llvm/utils/TableGen/X86RecognizableInstr.cpp
+++ b/llvm/utils/TableGen/X86RecognizableInstr.cpp
@@ -365,6 +365,8 @@ InstructionContext RecognizableInstr::insnContext() const {
insnContext = IC_64BIT_XD;
else if (OpPrefix == X86Local::XS)
insnContext = IC_64BIT_XS;
+ else if (HasREX_W && ExplicitREX2Prefix)
+ insnContext = IC_64BIT_REX2_REXW;
else if (ExplicitREX2Prefix)
insnContext = IC_64BIT_REX2;
else if (HasREX_W)
generated by cgit v1.1 at 2025-10-18 20:15:31 +0000